From 19f4eca4b94300c4943bd9b1043856644435d09c Mon Sep 17 00:00:00 2001 From: Stephan Hadinger Date: Mon, 31 Jan 2022 22:20:34 +0100 Subject: [PATCH 1/2] Fix for mclk/bclk divisors #8326 Merges https://github.com/espressif/esp-idf/pull/8327 --- components/driver/i2s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/driver/i2s.c b/components/driver/i2s.c index 14ec904575..93f42b0497 100644 --- a/components/driver/i2s.c +++ b/components/driver/i2s.c @@ -1000,9 +1000,9 @@ static esp_err_t i2s_calculate_adc_dac_clock(int i2s_num, i2s_hal_clock_cfg_t *c ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->hal_cfg.mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN), ESP_ERR_INVALID_ARG, TAG, "current mode is not built-in ADC/DAC"); /* Set I2S bit clock */ - clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_AD_BCK_FACTOR * 2; + clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_AD_BCK_FACTOR; /* Set I2S bit clock default division */ - clk_cfg->bclk_div = I2S_LL_AD_BCK_FACTOR; + clk_cfg->bclk_div = I2S_LL_AD_BCK_FACTOR * 16; /* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */ clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ? p_i2s[i2s_num]->fixed_mclk : clk_cfg->bclk * clk_cfg->bclk_div; From 15e8601cfc2219cb687117df1ed9613b4d7d7750 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 23 Feb 2022 19:43:53 +0800 Subject: [PATCH 2/2] i2s: add mclk_div underflow check Closes https://github.com/espressif/esp-idf/issues/8344 --- components/driver/i2s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/driver/i2s.c b/components/driver/i2s.c index 93f42b0497..d9c5c57c8e 100644 --- a/components/driver/i2s.c +++ b/components/driver/i2s.c @@ -1002,7 +1002,7 @@ static esp_err_t i2s_calculate_adc_dac_clock(int i2s_num, i2s_hal_clock_cfg_t *c /* Set I2S bit clock */ clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_AD_BCK_FACTOR; /* Set I2S bit clock default division */ - clk_cfg->bclk_div = I2S_LL_AD_BCK_FACTOR * 16; + clk_cfg->bclk_div = p_i2s[i2s_num]->hal_cfg.chan_bits; /* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */ clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ? p_i2s[i2s_num]->fixed_mclk : clk_cfg->bclk * clk_cfg->bclk_div;