soc: update SOC_GPIO_VALID_GPIO_MASK doc

Merges https://github.com/espressif/esp-idf/pull/10165

components/soc/esp32/include/soc/soc_caps.h

@@ -160,7 +160,7 @@
 // set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to
 // control pullup/down/capability, independent with RTC registers.
 
-// 0~39 except from 24, 28~31 are valid
+// 0~39 valid except 24, 28~31
 #define SOC_GPIO_VALID_GPIO_MASK        (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
 // GPIO >= 34 are input only
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))

components/soc/esp32s2/include/soc/soc_caps.h

@@ -143,7 +143,7 @@
 // Force hold is a new function of ESP32-S2
 #define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)
 
-// 0~46 except from 22~25 are valid
+// 0~46 valid except 22~25
 #define SOC_GPIO_VALID_GPIO_MASK             (0x7FFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
 // GPIO 46 is input only
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK     (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))

components/soc/esp32s3/include/soc/soc_caps.h

@@ -150,7 +150,7 @@
 // Force hold is a new function of ESP32-S3
 #define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)
 
-// 0~48 except from 22~25 are valid
+// 0~48 valid except 22~25
 #define SOC_GPIO_VALID_GPIO_MASK         (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
 // No GPIO is input only
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK  (SOC_GPIO_VALID_GPIO_MASK)