diff --git a/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
index a93413a1cb..00888b788f 100644
--- a/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32c5/beta3/bootloader.ld
@@ -6,7 +6,7 @@
 /** Simplified memory map for the bootloader.
  *  Make sure the bootloader can load into main memory without overwriting itself.
  *
- *  TODO: [ESP32C5] IDF-8653 Check this file whether need update
+ *  TODO: [ESP32C5] IDF-9358 Check this file whether need update for MP ROM
  *  ESP32-C5 ROM static data usage is as follows:
  *  - 0x4086b2b8 - 0x4087cbc0: Shared buffers, used in UART/USB/SPI download mode only
  *  - 0x4087cbc0 - 0x4087ebc0: PRO CPU stack, can be reclaimed as heap after RTOS startup
diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index 308c5a926d..2f01b1a33d 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -15,30 +15,7 @@
 #include "esp_rom_uart.h"
 #include "sdkconfig.h"
 #if CONFIG_IDF_TARGET_ESP32
-#include "soc/dport_reg.h"
 #include "esp32/rom/cache.h"
-#elif CONFIG_IDF_TARGET_ESP32S2
-#elif CONFIG_IDF_TARGET_ESP32S3
-#elif CONFIG_IDF_TARGET_ESP32C3
-#include "esp32c3/rom/crc.h"
-#include "esp32c3/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32C2
-#include "esp32c2/rom/crc.h"
-#include "esp32c2/rom/rtc.h"
-#include "esp32c2/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32C6
-#include "esp32c6/rom/crc.h"
-#include "esp32c6/rom/rtc.h"
-#include "esp32c6/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32C5
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/crc.h"
-#include "esp32h2/rom/rtc.h"
-#include "esp32h2/rom/uart.h"
-#elif CONFIG_IDF_TARGET_ESP32P4
-
-#else // CONFIG_IDF_TARGET_*
-#error "Unsupported IDF_TARGET"
 #endif
 #include "esp_rom_spiflash.h"
 
diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c
index c91089b23f..dd099743da 100644
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -23,15 +23,6 @@
 #include "bootloader_memory_utils.h"
 #include "soc/soc_caps.h"
 #include "hal/cache_ll.h"
-#if CONFIG_IDF_TARGET_ESP32C2
-#include "esp32c2/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32C6
-#include "esp32c6/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32H2
-#include "esp32h2/rom/rtc.h"
-#elif CONFIG_IDF_TARGET_ESP32P4
-#include "esp32p4/rom/rtc.h"
-#endif
 
 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
diff --git a/components/bootloader_support/test_apps/.build-test-rules.yml b/components/bootloader_support/test_apps/.build-test-rules.yml
index 65366010f0..1dbe91f913 100644
--- a/components/bootloader_support/test_apps/.build-test-rules.yml
+++ b/components/bootloader_support/test_apps/.build-test-rules.yml
@@ -2,6 +2,5 @@
 
 components/bootloader_support/test_apps/rtc_custom_section:
   enable:
-    # TODO: [ESP32C5] IDF-8653
-    - if: SOC_RTC_MEM_SUPPORTED == 1 and IDF_TARGET != "esp32c5"
+    - if: SOC_RTC_MEM_SUPPORTED == 1
       reason: this feature is supported on chips that have RTC memory