From 357b64fd2c4d1fb8e02da9fc551b2c70d87b5e33 Mon Sep 17 00:00:00 2001
From: fuzhibo <fuzhibo@espressif.com>
Date: Mon, 12 Apr 2021 14:29:13 +0800
Subject: [PATCH] bugfix: add .rodata section for riscv ulp for esp32s2

---
 components/ulp/ld/esp32s2.ulp.riscv.ld | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/components/ulp/ld/esp32s2.ulp.riscv.ld b/components/ulp/ld/esp32s2.ulp.riscv.ld
index 983481df29..62840422fe 100644
--- a/components/ulp/ld/esp32s2.ulp.riscv.ld
+++ b/components/ulp/ld/esp32s2.ulp.riscv.ld
@@ -16,6 +16,12 @@ SECTIONS
         *(.text*)
     } >ram
 
+    .rodata ALIGN(4):
+    {
+        *(.rodata)
+        *(.rodata*)
+    } > ram
+
     .data ALIGN(4):
     {
         *(.data)