kopia lustrzana https://github.com/espressif/esp-idf
panic: dump some instruction memory on IllegalInstruction exception
rodzic
646d36c728
commit
04c511c9b5
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@ -188,6 +188,7 @@ static const char *edesc[] = {
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static void commonErrorHandler(XtExcFrame *frame);
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static void commonErrorHandler(XtExcFrame *frame);
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static inline void disableAllWdts();
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static inline void disableAllWdts();
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static void illegal_instruction_helper(XtExcFrame *frame);
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//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
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//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
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//messing up the serial output, so we stall it here.
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//messing up the serial output, so we stall it here.
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@ -357,11 +358,37 @@ void xt_unhandled_exception(XtExcFrame *frame)
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return;
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return;
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}
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}
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panicPutStr(". Exception was unhandled.\r\n");
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panicPutStr(". Exception was unhandled.\r\n");
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if (exccause == 0 /* IllegalInstruction */) {
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illegal_instruction_helper(frame);
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}
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esp_reset_reason_set_hint(ESP_RST_PANIC);
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esp_reset_reason_set_hint(ESP_RST_PANIC);
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}
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}
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commonErrorHandler(frame);
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commonErrorHandler(frame);
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}
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}
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static void illegal_instruction_helper(XtExcFrame *frame)
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{
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/* Print out memory around the instruction word */
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uint32_t epc = frame->pc;
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epc = (epc & ~0x3) - 4;
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/* check that the address was sane */
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if (epc < SOC_IROM_MASK_LOW || epc >= SOC_IROM_HIGH) {
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return;
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}
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volatile uint32_t* pepc = (uint32_t*)epc;
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panicPutStr("Memory dump at 0x");
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panicPutHex(epc);
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panicPutStr(": ");
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panicPutHex(*pepc);
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panicPutStr(" ");
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panicPutHex(*(pepc + 1));
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panicPutStr(" ");
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panicPutHex(*(pepc + 2));
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panicPutStr("\r\n");
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}
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/*
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/*
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If watchdogs are enabled, the panic handler runs the risk of getting aborted pre-emptively because
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If watchdogs are enabled, the panic handler runs the risk of getting aborted pre-emptively because
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@ -286,6 +286,8 @@
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_IROM_MASK_LOW 0x40000000
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#define SOC_IROM_MASK_HIGH 0x40070000
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#define SOC_CACHE_PRO_LOW 0x40070000
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#define SOC_CACHE_PRO_LOW 0x40070000
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#define SOC_CACHE_PRO_HIGH 0x40078000
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#define SOC_CACHE_PRO_HIGH 0x40078000
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#define SOC_CACHE_APP_LOW 0x40078000
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#define SOC_CACHE_APP_LOW 0x40078000
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