kopia lustrzana https://github.com/espressif/esp-idf
esp32c6-SHA/AES support: Added sha_ll.h and aes_ll.h files in hal layer
Aditya Patwardhan
rodzic
bcf19a275c
commit
04a9366694
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@ -8,9 +8,9 @@ set(srcs "rtc_clk_init.c"
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if(NOT BOOTLOADER_BUILD)
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# list(APPEND srcs "esp_hmac.c" // TODO: IDF-5355
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# "esp_crypto_lock.c"
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# "esp_ds.c") // TODO: IDF-5360
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list(APPEND srcs "sar_periph_ctrl.c")
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list(APPEND srcs "sar_periph_ctrl.c"
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"esp_crypto_lock.c")
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if(CONFIG_ESP_SYSTEM_MEMPROT_FEATURE)
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list(APPEND srcs "esp_memprot.c" "../esp_memprot_conv.c")
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@ -107,6 +107,10 @@ if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs "sha_hal.c")
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endif()
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if(CONFIG_SOC_AES_SUPPORTED)
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list(APPEND srcs "aes_hal.c")
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endif()
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if(CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT)
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list(APPEND srcs "${target}/modem_clock_hal.c")
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endif()
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@ -128,7 +132,6 @@ if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs
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"sdio_slave_hal.c"
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"touch_sensor_hal.c"
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"aes_hal.c"
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"esp32/brownout_hal.c"
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"esp32/touch_sensor_hal.c"
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"esp32/gpio_hal_workaround.c")
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@ -141,7 +144,6 @@ if(NOT BOOTLOADER_BUILD)
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"usb_hal.c"
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"usb_phy_hal.c"
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"xt_wdt_hal.c"
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"aes_hal.c"
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"esp32s2/brownout_hal.c"
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"esp32s2/cp_dma_hal.c"
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"esp32s2/touch_sensor_hal.c"
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@ -156,7 +158,6 @@ if(NOT BOOTLOADER_BUILD)
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"usb_hal.c"
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"usb_phy_hal.c"
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"xt_wdt_hal.c"
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"aes_hal.c"
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"esp32s3/brownout_hal.c"
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"hmac_hal.c"
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"esp32s3/touch_sensor_hal.c"
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@ -169,7 +170,6 @@ if(NOT BOOTLOADER_BUILD)
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"ds_hal.c"
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"spi_flash_hal_gpspi.c"
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"xt_wdt_hal.c"
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"aes_hal.c"
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"esp32c3/brownout_hal.c"
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"hmac_hal.c"
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"esp32c3/rtc_cntl_hal.c")
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@ -196,7 +196,8 @@ if(NOT BOOTLOADER_BUILD)
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list(APPEND srcs
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"spi_flash_hal_gpspi.c"
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"esp32c6/brownout_hal.c"
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"esp32c6/rtc_cntl_hal.c")
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"esp32c6/rtc_cntl_hal.c"
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)
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endif()
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@ -0,0 +1,225 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <string.h>
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#include "soc/hwcrypto_reg.h"
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#include "hal/aes_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief State of AES accelerator, busy, idle or done
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*
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*/
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typedef enum {
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ESP_AES_STATE_IDLE = 0, /* AES accelerator is idle */
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ESP_AES_STATE_BUSY, /* Transform in progress */
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ESP_AES_STATE_DONE, /* Transform completed */
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} esp_aes_state_t;
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/**
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* @brief Write the encryption/decryption key to hardware
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*
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* @param key Key to be written to the AES hardware
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* @param key_word_len Number of words in the key
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*
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* @return Number of bytes written to hardware, used for fault injection check
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*/
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static inline uint8_t aes_ll_write_key(const uint8_t *key, size_t key_word_len)
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{
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/* This variable is used for fault injection checks, so marked volatile to avoid optimisation */
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volatile uint8_t key_in_hardware = 0;
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/* Memcpy to avoid potential unaligned access */
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uint32_t key_word;
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for (int i = 0; i < key_word_len; i++) {
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memcpy(&key_word, key + 4 * i, 4);
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REG_WRITE(AES_KEY_0_REG + i * 4, key_word);
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key_in_hardware += 4;
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}
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return key_in_hardware;
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}
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/**
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* @brief Sets the mode
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*
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* @param mode ESP_AES_ENCRYPT = 1, or ESP_AES_DECRYPT = 0
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* @param key_bytes Number of bytes in the key
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*/
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static inline void aes_ll_set_mode(int mode, uint8_t key_bytes)
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{
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const uint32_t MODE_DECRYPT_BIT = 4;
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unsigned mode_reg_base = (mode == ESP_AES_ENCRYPT) ? 0 : MODE_DECRYPT_BIT;
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/* See TRM for the mapping between keylength and mode bit */
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REG_WRITE(AES_MODE_REG, mode_reg_base + ((key_bytes / 8) - 2));
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}
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/**
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* @brief Writes message block to AES hardware
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*
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* @param input Block to be written
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*/
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static inline void aes_ll_write_block(const void *input)
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{
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uint32_t input_word;
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for (int i = 0; i < AES_BLOCK_WORDS; i++) {
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memcpy(&input_word, (uint8_t*)input + 4 * i, 4);
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REG_WRITE(AES_TEXT_IN_0_REG + i * 4, input_word);
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}
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}
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/**
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* @brief Read the AES block
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*
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* @param output the output of the transform, length = AES_BLOCK_BYTES
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*/
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static inline void aes_ll_read_block(void *output)
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{
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uint32_t output_word;
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const size_t REG_WIDTH = sizeof(uint32_t);
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for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
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output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
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/* Memcpy to avoid potential unaligned access */
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memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
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}
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}
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/**
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* @brief Starts block transform
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*
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*/
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static inline void aes_ll_start_transform(void)
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{
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REG_WRITE(AES_TRIGGER_REG, 1);
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}
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/**
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* @brief Read state of AES accelerator
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*
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* @return esp_aes_state_t
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*/
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static inline esp_aes_state_t aes_ll_get_state(void)
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{
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return REG_READ(AES_STATE_REG);
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}
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/**
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* @brief Set mode of operation
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*
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* @note Only used for DMA transforms
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*
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* @param mode
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*/
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static inline void aes_ll_set_block_mode(esp_aes_mode_t mode)
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{
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REG_WRITE(AES_BLOCK_MODE_REG, mode);
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}
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/**
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* @brief Set AES-CTR counter to INC32
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*
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* @note Only affects AES-CTR mode
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*
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*/
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static inline void aes_ll_set_inc(void)
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{
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REG_WRITE(AES_INC_SEL_REG, 0);
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}
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/**
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* @brief Release the DMA
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*
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*/
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static inline void aes_ll_dma_exit(void)
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{
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REG_WRITE(AES_DMA_EXIT_REG, 0);
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}
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/**
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* @brief Sets the number of blocks to be transformed
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*
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* @note Only used for DMA transforms
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*
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* @param num_blocks Number of blocks to transform
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*/
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static inline void aes_ll_set_num_blocks(size_t num_blocks)
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{
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REG_WRITE(AES_BLOCK_NUM_REG, num_blocks);
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}
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/*
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* Write IV to hardware iv registers
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*/
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static inline void aes_ll_set_iv(const uint8_t *iv)
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{
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uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
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uint32_t iv_word;
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for (int i = 0; i < IV_WORDS; i++ ) {
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/* Memcpy to avoid potential unaligned access */
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memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
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REG_WRITE(®_addr_buf[i], iv_word);
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}
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}
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/*
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* Read IV from hardware iv registers
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*/
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static inline void aes_ll_read_iv(uint8_t *iv)
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{
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uint32_t iv_word;
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const size_t REG_WIDTH = sizeof(uint32_t);
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for (size_t i = 0; i < IV_WORDS; i++) {
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iv_word = REG_READ(AES_IV_MEM + (i * REG_WIDTH));
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/* Memcpy to avoid potential unaligned access */
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memcpy(iv + i * 4, &iv_word, sizeof(iv_word));
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}
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}
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/**
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* @brief Enable or disable DMA mode
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*
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* @param enable true to enable, false to disable.
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*/
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static inline void aes_ll_dma_enable(bool enable)
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{
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REG_WRITE(AES_DMA_ENABLE_REG, enable);
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}
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/**
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* @brief Enable or disable transform completed interrupt
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*
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* @param enable true to enable, false to disable.
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*/
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static inline void aes_ll_interrupt_enable(bool enable)
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{
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REG_WRITE(AES_INT_ENA_REG, enable);
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}
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/**
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* @brief Clears the interrupt
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*
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*/
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static inline void aes_ll_interrupt_clear(void)
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{
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REG_WRITE(AES_INT_CLEAR_REG, 1);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,149 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "soc/hwcrypto_reg.h"
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#include "hal/sha_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Start a new SHA block conversions (no initial hash in HW)
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_start_block(esp_sha_type sha_type)
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{
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REG_WRITE(SHA_MODE_REG, sha_type);
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REG_WRITE(SHA_START_REG, 1);
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}
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/**
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* @brief Continue a SHA block conversion (initial hash in HW)
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_continue_block(esp_sha_type sha_type)
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{
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REG_WRITE(SHA_MODE_REG, sha_type);
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REG_WRITE(SHA_CONTINUE_REG, 1);
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}
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/**
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* @brief Start a new SHA message conversion using DMA (no initial hash in HW)
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_start_dma(esp_sha_type sha_type)
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{
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REG_WRITE(SHA_MODE_REG, sha_type);
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REG_WRITE(SHA_DMA_START_REG, 1);
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}
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/**
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* @brief Continue a SHA message conversion using DMA (initial hash in HW)
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_continue_dma(esp_sha_type sha_type)
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{
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REG_WRITE(SHA_MODE_REG, sha_type);
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REG_WRITE(SHA_DMA_CONTINUE_REG, 1);
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}
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/**
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* @brief Load the current hash digest to digest register
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*
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* @note Happens automatically on ESP32C6
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*
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* @param sha_type The SHA algorithm type
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*/
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static inline void sha_ll_load(esp_sha_type sha_type)
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{
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}
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/**
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* @brief Sets the number of message blocks to be hashed
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*
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* @note DMA operation only
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*
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* @param num_blocks Number of message blocks to process
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*/
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static inline void sha_ll_set_block_num(size_t num_blocks)
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{
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REG_WRITE(SHA_DMA_BLOCK_NUM_REG, num_blocks);
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}
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/**
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* @brief Checks if the SHA engine is currently busy hashing a block
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*
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* @return true SHA engine busy
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* @return false SHA engine idle
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*/
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static inline bool sha_ll_busy(void)
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{
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return REG_READ(SHA_BUSY_REG);
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}
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/**
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* @brief Write a text (message) block to the SHA engine
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*
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* @param input_text Input buffer to be written to the SHA engine
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* @param block_word_len Number of words in block
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*/
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static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len)
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{
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uint32_t *data_words = (uint32_t *)input_text;
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_M_MEM);
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for (int i = 0; i < block_word_len; i++) {
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REG_WRITE(®_addr_buf[i], data_words[i]);
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}
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}
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/**
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* @brief Read the message digest from the SHA engine
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*
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* @param sha_type The SHA algorithm type
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* @param digest_state Buffer that message digest will be written to
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* @param digest_word_len Length of the message digest
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*/
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static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
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{
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uint32_t *digest_state_words = (uint32_t *)digest_state;
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const size_t REG_WIDTH = sizeof(uint32_t);
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for (size_t i = 0; i < digest_word_len; i++) {
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digest_state_words[i] = REG_READ(SHA_H_MEM + (i * REG_WIDTH));
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}
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}
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/**
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* @brief Write the message digest to the SHA engine
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*
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* @param sha_type The SHA algorithm type
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* @param digest_state Message digest to be written to SHA engine
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* @param digest_word_len Length of the message digest
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*/
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static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len)
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{
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uint32_t *digest_state_words = (uint32_t *)digest_state;
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uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_MEM);
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for (int i = 0; i < digest_word_len; i++) {
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REG_WRITE(®_addr_buf[i], digest_state_words[i]);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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