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support BLE with 26M xtal for esp32c2

pull/9523/head
Shen Weilong 2022-07-12 21:10:58 +08:00 zatwierdzone przez shenweilong
rodzic b66be87f88
commit 028d071e84
5 zmienionych plików z 16 dodań i 6 usunięć
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8
components/bt/controller/esp32c2/bt.c
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@ -571,12 +571,18 @@ void ble_rtc_clk_init(void)
// LP_TIMER_SEL_XTAL -> 1
// LP_TIMER_SEL_8M -> 0
// LP_TIMER_SEL_RTC_SLOW -> 0
// LP_TIMER_CLK_DIV_NUM -> 1250
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
// LP_TIMER_CLK_DIV_NUM -> 130
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#else
// LP_TIMER_CLK_DIV_NUM -> 250
SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
#endif // CONFIG_ESP32C2_XTAL_FREQ_26
// MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
// MODEM_CLKRST_ETM_CLK_SEL -> 0

2
components/bt/controller/lib_esp32c2/esp32c2-bt-lib

@ -1 +1 @@
Subproject commit d6528970622a611dc9ad4a9fc31a5a9fc1996d74
Subproject commit bdab852aa2adf459d643731b513a4431003943b6

4
components/bt/include/esp32c2/include/esp_bt.h
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@ -118,7 +118,7 @@ esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_
esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type);
#define CONFIG_VERSION 0x20220105
#define CONFIG_VERSION 0x20220729
#define CONFIG_MAGIC 0x5A5AA5A5
/**
@ -173,6 +173,7 @@ typedef struct {
uint8_t coex_phy_coded_tx_rx_time_limit;
uint8_t dis_scan_backoff;
uint8_t esp_scan_filter_en;
uint8_t main_xtal_freq;
uint32_t config_magic;
} esp_bt_controller_config_t;
@ -223,6 +224,7 @@ typedef struct {
.coex_phy_coded_tx_rx_time_limit = DEFAULT_BT_LE_COEX_PHY_CODED_TX_RX_TLIM_EFF, \
.dis_scan_backoff = NIMBLE_DISABLE_SCAN_BACKOFF, \
.esp_scan_filter_en = 0, \
.main_xtal_freq = CONFIG_ESP32C2_XTAL_FREQ, \
.config_magic = CONFIG_MAGIC, \
};

6
components/bt/include/esp32c2/include/esp_bt_cfg.h
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@ -192,7 +192,11 @@ extern "C" {
#define BLE_LL_CONN_DEF_AUTH_PYLD_TMO_N (3000)
#define RTC_FREQ_N (32000) /* in Hz */
#ifdef CONFIG_ESP32C2_XTAL_FREQ_26
#define RTC_FREQ_N (40000) /* in Hz */
#else
#define RTC_FREQ_N (32000) /* in Hz */
#endif // CONFIG_ESP32C2_XTAL_FREQ_26
#define BLE_LL_TX_PWR_DBM_N (0)

2
components/esp_rom/esp32c2/ld/esp32c2.rom.ld
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@ -1415,7 +1415,6 @@ r_ble_phy_get_packet_status = 0x40001818;
r_ble_phy_get_pyld_time_offset = 0x4000181c;
r_ble_phy_get_rx_phy_mode = 0x40001820;
r_ble_phy_get_seq_end_st = 0x40001824;
r_ble_phy_init = 0x40001828;
r_ble_phy_isr = 0x4000182c;
r_ble_phy_max_data_pdu_pyld = 0x40001830;
r_ble_phy_mode_config = 0x40001834;
@ -1498,7 +1497,6 @@ r_hal_rtc_irq_handler = 0x40001964;
r_hal_timer_deinit = 0x40001968;
r_hal_timer_disable_irq = 0x4000196c;
r_hal_timer_env_init = 0x40001970;
r_hal_timer_init = 0x40001974;
r_hal_timer_process = 0x40001978;
r_hal_timer_read = 0x4000197c;
r_hal_timer_read_tick = 0x40001980;