esp32s2beta: only support unicore

components/bootloader_support/src/bootloader_utility.c

@@ -613,7 +613,9 @@ static void load_image(const esp_image_metadata_t *image_data)
 #endif
 
     ESP_LOGI(TAG, "Disabling RNG early entropy source...");
+#if !CONFIG_IDF_ENV_FPGA
     bootloader_random_disable();
+#endif
 
     // copy loaded segments to RAM, set up caches for mapped segments, and start application
     unpack_load_app(image_data);

components/bootloader_support/src/flash_qio_mode.c

@@ -22,12 +22,10 @@
 #elif CONFIG_IDF_TARGET_ESP32S2BETA
 #include "esp32s2beta/rom/spi_flash.h"
 #include "esp32s2beta/rom/efuse.h"
+#include "soc/spi_mem_struct.h"
 #endif
 #include "soc/spi_struct.h"
 #include "soc/spi_reg.h"
-#if CONFIG_IDF_TARGET_ESP32S2BETA
-#include "soc/spi_mem_struct.h"
-#endif
 #include "soc/efuse_periph.h"
 #include "soc/io_mux_reg.h"
 #include "sdkconfig.h"

components/driver/include/driver/gpio.h

@@ -13,16 +13,20 @@
 // limitations under the License.
 
 #pragma once
+#include "sdkconfig.h"
 #include "esp_err.h"
 #include <esp_types.h>
 #include <esp_bit_defs.h>
-#include "esp32/rom/gpio.h"
 #include "esp_attr.h"
 #include "esp_intr_alloc.h"
 #include "soc/gpio_periph.h"
 #include "hal/gpio_types.h"
 
-#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/gpio.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/gpio.h"
+#endif
 
 #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
 #include "soc/rtc_io_reg.h"
@@ -413,14 +417,14 @@ void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv);
 
 #if GPIO_SUPPORTS_FORCE_HOLD
 /**
-  * @brief Force hold digital and rtc gpio pad. 
-  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. 
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
   * */
 esp_err_t gpio_force_hold_all(void);
 
 /**
-  * @brief Force unhold digital and rtc gpio pad. 
-  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. 
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
   * */
 esp_err_t gpio_force_unhold_all(void);
 #endif

components/efuse/src/esp32s2beta/esp_efuse_fields.c

@@ -17,7 +17,7 @@
 #include "esp_efuse_table.h"
 #include "stdlib.h"
 #include "esp_types.h"
-#include "esp32/rom/efuse.h"
+#include "esp32s2beta/rom/efuse.h"
 #include "assert.h"
 #include "esp_err.h"
 #include "esp_log.h"

components/efuse/src/esp_efuse_fields.c

@@ -12,12 +12,12 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+#include <stdlib.h>
+#include "sdkconfig.h"
 #include "esp_efuse.h"
 #include "esp_efuse_utility.h"
 #include "esp_efuse_table.h"
-#include "stdlib.h"
 #include "esp_types.h"
-#include "esp32/rom/efuse.h"
 #include "assert.h"
 #include "esp_err.h"
 #include "esp_log.h"
@@ -26,6 +26,12 @@
 #include "soc/apb_ctrl_reg.h"
 #include "sys/param.h"
 
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/efuse.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/efuse.h"
+#endif
+
 // Permanently update values written to the efuse write registers
 void esp_efuse_burn_new_values(void)
 {

components/esp32s2beta/clk.c

@@ -46,11 +46,8 @@
 
 static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
 
-// g_ticks_us defined in ROMs for PRO and APP CPU
+// g_ticks_us defined in ROMs for PRO CPU
 extern uint32_t g_ticks_per_us_pro;
-#if !CONFIG_FREERTOS_UNICORE
-extern uint32_t g_ticks_per_us_app;
-#endif //!CONFIG_FREERTOS_UNICORE
 
 static const char* TAG = "clk";
 
@@ -135,9 +132,6 @@ void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
 {
     /* Update scale factors used by ets_delay_us */
     g_ticks_per_us_pro = ticks_per_us;
-#if !CONFIG_FREERTOS_UNICORE
-    g_ticks_per_us_app = ticks_per_us;
-#endif //!CONFIG_FREERTOS_UNICORE
 }
 
 static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
@@ -206,25 +200,14 @@ void esp_perip_clk_init(void)
     uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
     uint32_t common_perip_clk1 = 0;
 
-#if CONFIG_FREERTOS_UNICORE
     RESET_REASON rst_reas[1];
-#else
-    RESET_REASON rst_reas[2];
-#endif
 
     rst_reas[0] = rtc_get_reset_reason(0);
 
-#if !CONFIG_FREERTOS_UNICORE
-    rst_reas[1] = rtc_get_reset_reason(1);
-#endif
-
     /* For reason that only reset CPU, do not disable the clocks
      * that have been enabled before reset.
      */
     if ((rst_reas[0] >= TG0WDT_CPU_RESET && rst_reas[0] <= TG0WDT_CPU_RESET && rst_reas[0] != RTCWDT_BROWN_OUT_RESET)
-#if !CONFIG_FREERTOS_UNICORE
-        || (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
-#endif
     ) {
         common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
         hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);

components/esp32s2beta/esp_adapter.c

@@ -38,9 +38,7 @@
 #include "esp_private/wifi_os_adapter.h"
 #include "esp_private/wifi.h"
 #include "esp_phy_init.h"
-#if CONFIG_IDF_TARGET_ESP32S2BETA
 #include "esp32s2beta/clk.h"
-#endif
 #include "driver/periph_ctrl.h"
 #include "nvs.h"
 #include "os.h"

components/esp32s2beta/panic.c

@@ -300,13 +300,6 @@ static inline void printCacheError(void)
     panicPutStr("\r\n");
 }
 
-//When interrupt watchdog happen in one core, both cores will be interrupted.
-//The core which doesn't trigger the interrupt watchdog will save the frame and return.
-//The core which triggers the interrupt watchdog will use the saved frame, and dump frames for both cores.
-#if !CONFIG_FREERTOS_UNICORE
-static volatile XtExcFrame * other_core_frame = NULL;
-#endif //!CONFIG_FREERTOS_UNICORE
-
 void panicHandler(XtExcFrame *frame)
 {
     int core_id = xPortGetCoreID();
@@ -327,25 +320,6 @@ void panicHandler(XtExcFrame *frame)
         reason = reasons[frame->exccause];
     }
 
-#if !CONFIG_FREERTOS_UNICORE
-    //Save frame for other core.
-    if ((frame->exccause == PANIC_RSN_INTWDT_CPU0 && core_id == 1) || (frame->exccause == PANIC_RSN_INTWDT_CPU1 && core_id == 0)) {
-        other_core_frame = frame;
-        while (1);
-    }
-
-    //The core which triggers the interrupt watchdog will delay 1 us, so the other core can save its frame.
-    if (frame->exccause == PANIC_RSN_INTWDT_CPU0 || frame->exccause == PANIC_RSN_INTWDT_CPU1) {
-        ets_delay_us(1);
-    }
-
-    if (frame->exccause == PANIC_RSN_CACHEERR && esp_cache_err_get_cpuid() != core_id) {
-        // Cache error interrupt will be handled by the panic handler
-        // on the other CPU.
-        while (1);
-    }
-#endif //!CONFIG_FREERTOS_UNICORE
-
     if (frame->exccause == PANIC_RSN_INTWDT_CPU0) {
         esp_reset_reason_set_hint(ESP_RST_INT_WDT);
     }
@@ -579,11 +553,7 @@ static void commonErrorHandler_dump(XtExcFrame *frame, int core_id)
             panicPutStr("\r\n");
         }
 
-        if (xPortInterruptedFromISRContext()
-#if !CONFIG_FREERTOS_UNICORE
-            && other_core_frame != frame
-#endif //!CONFIG_FREERTOS_UNICORE
-            ) {
+        if (xPortInterruptedFromISRContext()) {
             //If the core which triggers the interrupt watchdog was in ISR context, dump the epc registers.
             uint32_t __value;
             panicPutStr("Core");
@@ -642,11 +612,6 @@ static __attribute__((noreturn)) void commonErrorHandler(XtExcFrame *frame)
     reconfigureAllWdts();
 
     commonErrorHandler_dump(frame, core_id);
-#if !CONFIG_FREERTOS_UNICORE
-    if (other_core_frame != NULL) {
-        commonErrorHandler_dump((XtExcFrame *)other_core_frame, (core_id ? 0 : 1));
-    }
-#endif //!CONFIG_FREERTOS_UNICORE
 
 #if CONFIG_APPTRACE_ENABLE
     disableAllWdts();

components/esp_common/src/mac_addr.c

@@ -6,6 +6,8 @@
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/efuse.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/efuse.h"
 #endif
 
 /* esp_system.h APIs relating to MAC addresses */