kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/fix_cache_data_mem_corrupt_after_sleep' into 'master'
fix(lightsleep): Suspend cache before goto sleep to avoid cache load wrong data Closes IDFCI-1760 See merge request espressif/esp-idf!25084pull/11287/merge
commit
016cb6a19a
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@ -15,7 +15,7 @@ entries:
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rtc_clk (noflash)
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esp_gpio_reserve: esp_gpio_reserve_pins (noflash)
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esp_gpio_reserve: esp_gpio_is_pin_reserved (noflash)
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if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED = y && (PM_SLP_IRAM_OPT = y || ESP_SLEEP_POWER_DOWN_FLASH = y):
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if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED = y:
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rtc_init:rtc_vddsdio_get_config (noflash)
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rtc_init:rtc_vddsdio_set_config (noflash)
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if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n: # TODO: IDF-5645
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@ -397,8 +397,6 @@ void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
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portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
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}
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#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND && !CONFIG_IDF_TARGET_ESP32H2) \
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|| CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
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static int s_cache_suspend_cnt = 0;
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// Must be called from critical sections.
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@ -417,7 +415,6 @@ static void IRAM_ATTR resume_cache(void) {
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cache_hal_resume(CACHE_TYPE_ALL);
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}
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}
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#endif
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// [refactor-todo] provide target logic for body of uart functions below
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static void IRAM_ATTR flush_uarts(void)
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@ -745,13 +742,14 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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#endif
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#endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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} else {
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/* Cache Suspend 1: will wait cache idle in cache suspend */
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suspend_cache();
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/* On esp32c6, only the lp_aon pad hold function can only hold the GPIO state in the active mode.
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In order to avoid the leakage of the SPI cs pin, hold it here */
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#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
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#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
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if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
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/* Cache Suspend 1: will wait cache idle in cache suspend, also means SPI bus IDLE, then we can hold SPI CS pin safely*/
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suspend_cache();
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/* Cache suspend also means SPI bus IDLE, then we can hold SPI CS pin safely */
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gpio_ll_hold_en(&GPIO, SPI_CS0_GPIO_NUM);
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}
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#endif
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@ -774,21 +772,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
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if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
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gpio_ll_hold_dis(&GPIO, SPI_CS0_GPIO_NUM);
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/* Cache Resume 1: Resume cache for continue running*/
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resume_cache();
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}
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#endif
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#endif
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/* Will resume cache after flash ready. */
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}
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#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
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if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
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/* Cache Suspend 2: If previous sleep powerdowned the flash, suspend cache here so that the
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access to flash before flash ready can be explicitly exposed. */
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suspend_cache();
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}
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#endif
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#if CONFIG_ESP_SLEEP_SYSTIMER_STALL_WORKAROUND
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if (!(pd_flags & RTC_SLEEP_PD_XTAL)) {
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rtc_sleep_systimer_enable(true);
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@ -933,12 +922,8 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
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esp_rom_delay_us(flash_enable_time_us);
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}
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#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
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if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
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/* Cache Resume 2: flash is ready now, we can resume the cache and access flash safely after */
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resume_cache();
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}
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#endif
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/* Cache Resume 1: flash is ready now, we can resume the cache and access flash safely after */
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resume_cache();
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return reject;
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}
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