kopia lustrzana https://github.com/espressif/esp-idf
bootloader: Simplify multi-chip control logic of the cache
rodzic
e7b1640199
commit
001c29b077
components
bootloader_support/src
soc
esp32c3/include/soc
esp32h2/include/soc
esp32s2/include/soc
esp32s3/include/soc
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@ -198,18 +198,12 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Flush(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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uint32_t autoload = Cache_Suspend_DCache();
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Cache_Invalidate_DCache_All();
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#elif CONFIG_IDF_TARGET_ESP32C3
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#elif CONFIG_IDF_TARGET_ESP32H2
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#endif
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ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x",
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src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned );
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@ -217,34 +211,26 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
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int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
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#elif CONFIG_IDF_TARGET_ESP32S2
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int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
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#else // S3, C3, H2
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#else
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int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
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#endif
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if (e != 0) {
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ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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Cache_Resume_DCache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32C3
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32H2
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Cache_Resume_ICache(autoload);
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#endif
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return NULL;
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}
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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Cache_Resume_DCache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32C3
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32H2
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Cache_Resume_ICache(autoload);
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#endif
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mapped = true;
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@ -260,24 +246,15 @@ void bootloader_munmap(const void *mapping)
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Cache_Read_Disable(0);
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Cache_Flush(0);
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mmu_init(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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//TODO, save the autoload value.
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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Cache_MMU_Init();
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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Cache_Suspend_DCache();
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Cache_Invalidate_DCache_All();
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Cache_MMU_Init();
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#elif CONFIG_IDF_TARGET_ESP32C3
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//TODO, save the autoload value.
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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Cache_MMU_Init();
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#elif CONFIG_IDF_TARGET_ESP32H2
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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Cache_MMU_Init();
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#endif
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mapped = false;
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current_read_mapping = UINT32_MAX;
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@ -303,26 +280,18 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Flush(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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uint32_t autoload = Cache_Suspend_ICache();
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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uint32_t autoload = Cache_Suspend_DCache();
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#elif CONFIG_IDF_TARGET_ESP32C3
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uint32_t autoload = Cache_Suspend_ICache();
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#elif CONFIG_IDF_TARGET_ESP32H2
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uint32_t autoload = Cache_Suspend_ICache();
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#endif
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esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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Cache_Resume_DCache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32C3
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32H2
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Cache_Resume_ICache(autoload);
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#endif
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return spi_to_esp_err(r);
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@ -341,57 +310,39 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Flush(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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uint32_t autoload = Cache_Suspend_DCache();
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Cache_Invalidate_DCache_All();
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#elif CONFIG_IDF_TARGET_ESP32C3
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#elif CONFIG_IDF_TARGET_ESP32H2
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#endif
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ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
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#if CONFIG_IDF_TARGET_ESP32
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int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
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#elif CONFIG_IDF_TARGET_ESP32S2
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int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
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#elif CONFIG_IDF_TARGET_ESP32S3
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int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
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#elif CONFIG_IDF_TARGET_ESP32C3
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int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
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#elif CONFIG_IDF_TARGET_ESP32H2
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#else // map rodata with DBus
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int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
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#endif
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if (e != 0) {
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ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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Cache_Resume_DCache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32C3
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32H2
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Cache_Resume_ICache(autoload);
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#endif
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return ESP_FAIL;
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}
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current_read_mapping = map_at;
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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Cache_Resume_DCache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32C3
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32H2
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Cache_Resume_ICache(autoload);
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#endif
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}
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map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at));
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@ -705,18 +705,12 @@ static void set_cache_and_start_app(
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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Cache_Flush(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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uint32_t autoload = Cache_Suspend_DCache();
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Cache_Invalidate_DCache_All();
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#elif CONFIG_IDF_TARGET_ESP32C3
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#elif CONFIG_IDF_TARGET_ESP32H2
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uint32_t autoload = Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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#endif
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/* Clear the MMU entries that are already set up,
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@ -739,11 +733,7 @@ static void set_cache_and_start_app(
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rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count);
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#elif CONFIG_IDF_TARGET_ESP32S2
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32S3
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32C3
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32H2
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#else // map rodata with DBUS
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rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0);
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#endif
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ESP_LOGV(TAG, "rc=%d", rc);
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@ -757,7 +747,8 @@ static void set_cache_and_start_app(
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irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count);
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#if CONFIG_IDF_TARGET_ESP32
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rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#else // access text with IBUS
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#if CONFIG_IDF_TARGET_ESP32S2
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uint32_t iram1_used = 0;
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if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) {
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iram1_used = 1;
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@ -767,12 +758,7 @@ static void set_cache_and_start_app(
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1);
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REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1);
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}
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32S3
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32C3
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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#elif CONFIG_IDF_TARGET_ESP32H2
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#endif
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rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0);
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#endif
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ESP_LOGV(TAG, "rc=%d", rc);
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@ -794,23 +780,16 @@ static void set_cache_and_start_app(
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#if !CONFIG_FREERTOS_UNICORE
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REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS);
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#endif
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#elif CONFIG_IDF_TARGET_ESP32C3
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
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#elif CONFIG_IDF_TARGET_ESP32H2
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#else // ESP32C3, ESP32H2
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2
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#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32S3
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#else // access rodata with DCache
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Cache_Resume_DCache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32C3
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Cache_Resume_ICache(autoload);
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#elif CONFIG_IDF_TARGET_ESP32H2
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Cache_Resume_ICache(autoload);
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#endif
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// Application will need to do Cache_Flush(1) and Cache_Read_Enable(1)
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@ -5,6 +5,7 @@
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#pragma once
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_CPU_CORES_NUM 1
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#define SOC_DEDICATED_GPIO_SUPPORTED 1
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#define SOC_GDMA_SUPPORTED 1
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@ -17,13 +18,10 @@
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#define SOC_TEMP_SENSOR_SUPPORTED 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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#define SOC_XT_WDT_SUPPORTED 1
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_SUPPORTS_SECURE_DL_MODE 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
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#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_DMA (1)
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@ -5,6 +5,7 @@
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#pragma once
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_CPU_CORES_NUM 1
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#define SOC_DEDICATED_GPIO_SUPPORTED 1
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#define SOC_GDMA_SUPPORTED 1
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@ -14,10 +15,9 @@
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#define SOC_HMAC_SUPPORTED 1
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#define SOC_ASYNC_MEMCPY_SUPPORTED 1
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#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_SUPPORTS_SECURE_DL_MODE 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
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#define SOC_TEMP_SENSOR_SUPPORTED 1
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@ -44,14 +44,15 @@
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#define SOC_DIG_SIGN_SUPPORTED 1
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#define SOC_HMAC_SUPPORTED 1
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#define SOC_ASYNC_MEMCPY_SUPPORTED 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
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#define SOC_TEMP_SENSOR_SUPPORTED 1
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#define SOC_CACHE_SUPPORT_WRAP 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
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#define SOC_PSRAM_DMA_CAPABLE 1
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#define SOC_XT_WDT_SUPPORTED 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
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#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1
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#define SOC_TEMP_SENSOR_SUPPORTED 1
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#define SOC_CACHE_SUPPORT_WRAP 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
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#define SOC_PSRAM_DMA_CAPABLE 1
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#define SOC_XT_WDT_SUPPORTED 1
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/*-------------------------- ADC CAPS ----------------------------------------*/
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/*!< SAR ADC Module*/
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@ -31,11 +31,11 @@
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#define SOC_SUPPORTS_SECURE_DL_MODE 1
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#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
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#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
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#define SOC_SDMMC_HOST_SUPPORTED 1
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#define SOC_SDMMC_HOST_SUPPORTED 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
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#define SOC_PSRAM_DMA_CAPABLE 1
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#define SOC_XT_WDT_SUPPORTED 1
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#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
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#define SOC_PSRAM_DMA_CAPABLE 1
|
||||
#define SOC_XT_WDT_SUPPORTED 1
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||||
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||||
|
||||
/*-------------------------- SOC CAPS ----------------------------------------*/
|
||||
|
|
Ładowanie…
Reference in New Issue