kopia lustrzana https://github.com/espressif/esp-idf
34 wiersze
1.6 KiB
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34 wiersze
1.6 KiB
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Driver for SPI flash read/write/erase operations
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Implementation notes
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In order to perform some flash operations, we need to make sure both CPUs
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are not running any code from flash for the duration of the flash operation.
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In a single-core setup this is easy: we disable interrupts/scheduler and do
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the flash operation. In the dual-core setup this is slightly more complicated.
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We need to make sure that the other CPU doesn't run any code from flash.
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When SPI flash API is called on CPU A (can be PRO or APP), we start
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spi_flash_op_block_func function on CPU B using esp_ipc_call API. This API
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wakes up high priority task on CPU B and tells it to execute given function,
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in this case spi_flash_op_block_func. This function disables cache on CPU B and
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signals that cache is disabled by setting s_flash_op_can_start flag.
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Then the task on CPU A disables cache as well, and proceeds to execute flash
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operation.
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While flash operation is running, interrupts can still run on CPU B.
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We assume that all interrupt code is placed into RAM.
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Once flash operation is complete, function on CPU A sets another flag,
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s_flash_op_complete, to let the task on CPU B know that it can re-enable
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cache and release the CPU. Then the function on CPU A re-enables the cache on
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CPU A as well and returns control to the calling code.
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Additionally, all API functions are protected with a mutex (s_flash_op_mutex).
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In a single core environment (CONFIG_FREERTOS_UNICORE enabled), we simply
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disable both caches, no inter-CPU communication takes place.
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