2020-12-15 09:20:22 +00:00
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// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
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2019-09-09 12:56:46 +00:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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2021-01-19 12:00:01 +00:00
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#include "soc/soc_caps.h"
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2019-09-09 12:56:46 +00:00
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#include "hal/adc_hal.h"
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2020-09-10 02:37:58 +00:00
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#include "hal/adc_hal_conf.h"
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2021-01-19 12:00:01 +00:00
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#include "sdkconfig.h"
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#include <sys/param.h>
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2020-12-15 09:20:22 +00:00
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2020-12-08 06:50:32 +00:00
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2020-12-15 09:20:22 +00:00
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#if CONFIG_IDF_TARGET_ESP32C3
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2021-01-18 13:59:18 +00:00
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#include "soc/gdma_channel.h"
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2020-12-15 09:20:22 +00:00
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#include "soc/soc.h"
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#include "esp_rom_sys.h"
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2021-02-23 13:40:15 +00:00
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typedef enum {
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ADC_EVENT_ADC1_DONE = BIT(0),
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ADC_EVENT_ADC2_DONE = BIT(1),
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} adc_hal_event_t;
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2020-12-16 09:23:19 +00:00
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#endif
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2019-09-09 12:56:46 +00:00
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void adc_hal_init(void)
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{
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// Set internal FSM wait time, fixed value.
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2020-02-25 14:19:48 +00:00
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adc_ll_digi_set_fsm_time(SOC_ADC_FSM_RSTB_WAIT_DEFAULT, SOC_ADC_FSM_START_WAIT_DEFAULT,
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SOC_ADC_FSM_STANDBY_WAIT_DEFAULT);
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2020-04-08 13:56:14 +00:00
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adc_ll_set_sample_cycle(ADC_FSM_SAMPLE_CYCLE_DEFAULT);
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2020-02-25 14:19:48 +00:00
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adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
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2020-04-02 03:20:38 +00:00
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adc_ll_digi_output_invert(ADC_NUM_1, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_1));
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adc_ll_digi_output_invert(ADC_NUM_2, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_2));
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2020-12-16 09:23:19 +00:00
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adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
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2019-09-09 12:56:46 +00:00
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}
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2020-02-25 14:19:48 +00:00
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void adc_hal_deinit(void)
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2019-09-09 12:56:46 +00:00
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{
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2020-02-25 14:19:48 +00:00
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adc_ll_set_power_manage(ADC_POWER_SW_OFF);
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2019-09-09 12:56:46 +00:00
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}
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2021-01-19 12:00:01 +00:00
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/*---------------------------------------------------------------
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ADC calibration setting
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---------------------------------------------------------------*/
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#if SOC_ADC_HW_CALIBRATION_V1
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// ESP32-S2 and C3 support HW offset calibration.
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void adc_hal_calibration_init(adc_ll_num_t adc_n)
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{
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adc_ll_calibration_init(adc_n);
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}
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static uint32_t s_previous_init_code[SOC_ADC_PERIPH_NUM] = {-1, -1};
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void adc_hal_set_calibration_param(adc_ll_num_t adc_n, uint32_t param)
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{
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if (param != s_previous_init_code[adc_n]) {
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adc_ll_set_calibration_param(adc_n, param);
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s_previous_init_code[adc_n] = param;
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}
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
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{
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adc_hal_set_controller(adc_n, ADC_CTRL_RTC); //Set controller
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/* Enable/disable internal connect GND (for calibration). */
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if (internal_gnd) {
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adc_ll_rtc_disable_channel(adc_n);
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adc_ll_set_atten(adc_n, 0, atten); // Note: when disable all channel, HW auto select channel0 atten param.
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} else {
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adc_ll_rtc_enable_channel(adc_n, channel);
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adc_ll_set_atten(adc_n, channel, atten);
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}
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}
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static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
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{
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adc_ll_rtc_start_convert(adc_n, channel);
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while (adc_ll_rtc_convert_is_done(adc_n) != true);
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return (uint32_t)adc_ll_rtc_get_convert_value(adc_n);
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}
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#elif CONFIG_IDF_TARGET_ESP32C3
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static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
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{
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2021-02-23 13:40:15 +00:00
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adc_ll_onetime_sample_enable(ADC_NUM_1, false);
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adc_ll_onetime_sample_enable(ADC_NUM_2, false);
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2021-01-19 12:00:01 +00:00
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/* Enable/disable internal connect GND (for calibration). */
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if (internal_gnd) {
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const int esp32c3_invalid_chan = (adc_n == ADC_NUM_1)? 0xF: 0x1;
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adc_ll_onetime_set_channel(adc_n, esp32c3_invalid_chan);
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} else {
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adc_ll_onetime_set_channel(adc_n, channel);
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}
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adc_ll_onetime_set_atten(atten);
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2021-02-23 13:40:15 +00:00
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adc_ll_onetime_sample_enable(adc_n, true);
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2021-01-19 12:00:01 +00:00
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}
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static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
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{
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adc_ll_intr_clear(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE);
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adc_ll_onetime_start(false);
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esp_rom_delay_us(5);
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adc_ll_onetime_start(true);
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while(!adc_ll_intr_get_raw(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE));
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uint32_t read_val = -1;
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if (adc_n == ADC_NUM_1) {
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read_val = adc_ll_adc1_read();
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} else if (adc_n == ADC_NUM_2) {
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read_val = adc_ll_adc2_read();
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if (adc_ll_analysis_raw_data(adc_n, read_val)) {
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return -1;
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}
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}
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return read_val;
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}
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#endif //CONFIG_IDF_TARGET_*
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#define ADC_HAL_CAL_TIMES (10)
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#define ADC_HAL_CAL_OFFSET_RANGE (4096)
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uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd)
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{
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if (adc_n == ADC_NUM_2) {
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adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
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adc_hal_arbiter_config(&config);
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}
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cal_setup(adc_n, channel, atten, internal_gnd);
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adc_ll_calibration_prepare(adc_n, channel, internal_gnd);
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uint32_t code_list[ADC_HAL_CAL_TIMES] = {0};
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uint32_t code_sum = 0;
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uint32_t code_h = 0;
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uint32_t code_l = 0;
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uint32_t chk_code = 0;
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for (uint8_t rpt = 0 ; rpt < ADC_HAL_CAL_TIMES ; rpt ++) {
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code_h = ADC_HAL_CAL_OFFSET_RANGE;
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code_l = 0;
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chk_code = (code_h + code_l) / 2;
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adc_ll_set_calibration_param(adc_n, chk_code);
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uint32_t self_cal = read_cal_channel(adc_n, channel);
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while (code_h - code_l > 1) {
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if (self_cal == 0) {
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code_h = chk_code;
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} else {
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code_l = chk_code;
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}
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chk_code = (code_h + code_l) / 2;
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adc_ll_set_calibration_param(adc_n, chk_code);
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self_cal = read_cal_channel(adc_n, channel);
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if ((code_h - code_l == 1)) {
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chk_code += 1;
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adc_ll_set_calibration_param(adc_n, chk_code);
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self_cal = read_cal_channel(adc_n, channel);
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}
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}
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code_list[rpt] = chk_code;
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code_sum += chk_code;
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}
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code_l = code_list[0];
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code_h = code_list[0];
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for (uint8_t i = 0 ; i < ADC_HAL_CAL_TIMES ; i++) {
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code_l = MIN(code_l, code_list[i]);
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code_h = MAX(code_h, code_list[i]);
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}
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chk_code = code_h + code_l;
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uint32_t ret = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4)
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? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
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: (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
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adc_ll_calibration_finish(adc_n);
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return ret;
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}
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#endif //SOC_ADC_HW_CALIBRATION_V1
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2020-12-16 09:23:19 +00:00
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#if CONFIG_IDF_TARGET_ESP32C3
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//This feature is currently supported on ESP32C3, will be supported on other chips soon
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/*---------------------------------------------------------------
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DMA setting
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---------------------------------------------------------------*/
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2021-02-22 12:29:13 +00:00
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void adc_hal_context_config(adc_hal_context_t *hal, const adc_hal_config_t *config)
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{
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hal->dev = &GDMA;
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hal->desc_dummy_head.next = hal->rx_desc;
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hal->desc_max_num = config->desc_max_num;
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hal->dma_chan = config->dma_chan;
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hal->eof_num = config->eof_num;
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}
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void adc_hal_digi_init(adc_hal_context_t *hal)
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{
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gdma_ll_clear_interrupt_status(hal->dev, hal->dma_chan, UINT32_MAX);
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gdma_ll_enable_interrupt(hal->dev, hal->dma_chan, GDMA_LL_EVENT_RX_SUC_EOF, true);
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adc_ll_digi_dma_set_eof_num(hal->eof_num);
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2021-02-23 13:40:15 +00:00
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adc_ll_onetime_sample_enable(ADC_NUM_1, false);
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adc_ll_onetime_sample_enable(ADC_NUM_2, false);
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2021-02-22 12:29:13 +00:00
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}
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void adc_hal_fifo_reset(adc_hal_context_t *hal)
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{
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adc_ll_digi_reset();
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gdma_ll_rx_reset_channel(hal->dev, hal->dma_chan);
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}
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2021-03-25 11:04:38 +00:00
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static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *data_buf, uint32_t size, uint32_t num)
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2020-12-16 09:23:19 +00:00
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{
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assert(((uint32_t)data_buf % 4) == 0);
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assert((size % 4) == 0);
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uint32_t n = 0;
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while (num--) {
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desc[n].dw0.size = size;
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desc[n].dw0.suc_eof = 0;
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desc[n].dw0.owner = 1;
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desc[n].buffer = data_buf;
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desc[n].next = &desc[n+1];
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data_buf += size;
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n++;
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}
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desc[n-1].next = NULL;
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}
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2021-03-25 11:04:38 +00:00
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void adc_hal_digi_rxdma_start(adc_hal_context_t *hal, uint8_t *data_buf)
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2020-12-16 09:23:19 +00:00
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{
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2021-02-22 12:29:13 +00:00
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//reset the current descriptor address
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hal->cur_desc_ptr = &hal->desc_dummy_head;
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2021-03-25 11:04:38 +00:00
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adc_hal_digi_dma_link_descriptors(hal->rx_desc, data_buf, hal->eof_num * ADC_HAL_DATA_LEN_PER_CONV, hal->desc_max_num);
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2021-02-22 12:29:13 +00:00
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gdma_ll_rx_set_desc_addr(hal->dev, hal->dma_chan, (uint32_t)hal->rx_desc);
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gdma_ll_rx_start(hal->dev, hal->dma_chan);
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2020-12-16 09:23:19 +00:00
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}
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2021-02-22 12:29:13 +00:00
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void adc_hal_digi_start(adc_hal_context_t *hal)
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2020-12-16 09:23:19 +00:00
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{
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2021-03-25 11:04:38 +00:00
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//the ADC data will be sent to the DMA
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2021-02-22 12:29:13 +00:00
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adc_ll_digi_dma_enable();
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//enable sar adc timer
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adc_ll_digi_trigger_enable();
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2020-12-16 09:23:19 +00:00
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}
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2021-02-22 12:29:13 +00:00
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adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc)
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2020-12-16 09:23:19 +00:00
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{
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2021-03-25 11:04:38 +00:00
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assert(hal->cur_desc_ptr);
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2021-02-22 12:29:13 +00:00
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if (!hal->cur_desc_ptr->next) {
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2021-03-25 11:04:38 +00:00
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return ADC_HAL_DMA_DESC_NULL;
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2021-02-22 12:29:13 +00:00
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}
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if ((intptr_t)hal->cur_desc_ptr == eof_desc_addr) {
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2021-03-25 11:04:38 +00:00
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return ADC_HAL_DMA_DESC_WAITING;
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2021-02-22 12:29:13 +00:00
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}
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2020-12-16 09:23:19 +00:00
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2021-02-22 12:29:13 +00:00
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hal->cur_desc_ptr = hal->cur_desc_ptr->next;
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*cur_desc = hal->cur_desc_ptr;
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2021-03-25 11:04:38 +00:00
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return ADC_HAL_DMA_DESC_VALID;
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2020-12-16 09:23:19 +00:00
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}
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2021-02-22 12:29:13 +00:00
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void adc_hal_digi_rxdma_stop(adc_hal_context_t *hal)
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2020-12-16 09:23:19 +00:00
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{
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2021-02-22 12:29:13 +00:00
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gdma_ll_rx_stop(hal->dev, hal->dma_chan);
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2020-12-16 09:23:19 +00:00
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}
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2021-02-22 12:29:13 +00:00
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void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask)
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2020-12-16 09:23:19 +00:00
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{
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2021-02-22 12:29:13 +00:00
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gdma_ll_clear_interrupt_status(hal->dev, hal->dma_chan, mask);
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2020-12-16 09:23:19 +00:00
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|
}
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|
|
|
2021-02-22 12:29:13 +00:00
|
|
|
void adc_hal_digi_dis_intr(adc_hal_context_t *hal, uint32_t mask)
|
2020-12-16 09:23:19 +00:00
|
|
|
{
|
2021-02-22 12:29:13 +00:00
|
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|
gdma_ll_enable_interrupt(hal->dev, hal->dma_chan, mask, false);
|
2020-12-16 09:23:19 +00:00
|
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|
}
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|
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|
2021-02-22 12:29:13 +00:00
|
|
|
void adc_hal_digi_stop(adc_hal_context_t *hal)
|
2020-12-16 09:23:19 +00:00
|
|
|
{
|
|
|
|
//Set to 0: the ADC data won't be sent to the DMA
|
|
|
|
adc_ll_digi_dma_disable();
|
|
|
|
//disable sar adc timer
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|
|
|
adc_ll_digi_trigger_disable();
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|
|
|
}
|
|
|
|
|
2020-12-15 09:20:22 +00:00
|
|
|
/*---------------------------------------------------------------
|
|
|
|
Single Read
|
|
|
|
---------------------------------------------------------------*/
|
2021-02-23 13:40:15 +00:00
|
|
|
|
|
|
|
//--------------------INTR-------------------------------//
|
|
|
|
static adc_ll_intr_t get_event_intr(adc_hal_event_t event)
|
|
|
|
{
|
|
|
|
adc_ll_intr_t intr_mask = 0;
|
|
|
|
if (event & ADC_EVENT_ADC1_DONE) {
|
|
|
|
intr_mask |= ADC_LL_INTR_ADC1_DONE;
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|
|
|
}
|
|
|
|
if (event & ADC_EVENT_ADC2_DONE) {
|
|
|
|
intr_mask |= ADC_LL_INTR_ADC2_DONE;
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|
|
|
}
|
|
|
|
return intr_mask;
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|
|
|
}
|
|
|
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|
|
|
|
static void adc_hal_intr_clear(adc_hal_event_t event)
|
|
|
|
{
|
|
|
|
adc_ll_intr_clear(get_event_intr(event));
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool adc_hal_intr_get_raw(adc_hal_event_t event)
|
|
|
|
{
|
|
|
|
return adc_ll_intr_get_raw(get_event_intr(event));
|
|
|
|
}
|
|
|
|
|
|
|
|
//--------------------Single Read-------------------------------//
|
|
|
|
static void adc_hal_onetime_start(void)
|
2020-12-15 09:20:22 +00:00
|
|
|
{
|
|
|
|
/**
|
|
|
|
* There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the
|
|
|
|
* ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller
|
|
|
|
* clock cycle.
|
|
|
|
*
|
|
|
|
* This limitation will be removed in hardware future versions.
|
|
|
|
*
|
|
|
|
*/
|
2020-12-25 06:24:19 +00:00
|
|
|
uint32_t digi_clk = APB_CLK_FREQ / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1);
|
2020-12-15 09:20:22 +00:00
|
|
|
//Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough.
|
|
|
|
uint32_t delay = (1000 * 1000) / digi_clk + 1;
|
|
|
|
//3 ADC digital controller clock cycle
|
|
|
|
delay = delay * 3;
|
|
|
|
//This coefficient (8) is got from test. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
|
|
|
|
if (digi_clk >= APB_CLK_FREQ/8) {
|
|
|
|
delay = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
adc_ll_onetime_start(false);
|
|
|
|
esp_rom_delay_us(delay);
|
|
|
|
adc_ll_onetime_start(true);
|
|
|
|
//No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
|
|
|
|
}
|
|
|
|
|
2021-02-23 13:40:15 +00:00
|
|
|
static esp_err_t adc_hal_single_read(adc_ll_num_t adc_n, int *out_raw)
|
2020-12-15 09:20:22 +00:00
|
|
|
{
|
2021-02-23 13:40:15 +00:00
|
|
|
if (adc_n == ADC_NUM_1) {
|
2020-12-08 06:50:32 +00:00
|
|
|
*out_raw = adc_ll_adc1_read();
|
2021-02-23 13:40:15 +00:00
|
|
|
} else if (adc_n == ADC_NUM_2) {
|
2020-12-08 06:50:32 +00:00
|
|
|
*out_raw = adc_ll_adc2_read();
|
2021-02-23 13:40:15 +00:00
|
|
|
if (adc_ll_analysis_raw_data(adc_n, *out_raw)) {
|
2020-12-08 06:50:32 +00:00
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
2020-12-15 09:20:22 +00:00
|
|
|
}
|
|
|
|
|
2021-02-23 13:40:15 +00:00
|
|
|
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw)
|
2020-12-15 09:20:22 +00:00
|
|
|
{
|
2021-02-23 13:40:15 +00:00
|
|
|
esp_err_t ret;
|
|
|
|
adc_hal_event_t event;
|
|
|
|
|
|
|
|
if (adc_n == ADC_NUM_1) {
|
|
|
|
event = ADC_EVENT_ADC1_DONE;
|
|
|
|
} else {
|
|
|
|
event = ADC_EVENT_ADC2_DONE;
|
2020-12-15 09:20:22 +00:00
|
|
|
}
|
|
|
|
|
2021-02-23 13:40:15 +00:00
|
|
|
adc_hal_intr_clear(event);
|
2021-03-25 11:04:38 +00:00
|
|
|
adc_ll_onetime_sample_enable(ADC_NUM_1, false);
|
|
|
|
adc_ll_onetime_sample_enable(ADC_NUM_2, false);
|
2021-02-23 13:40:15 +00:00
|
|
|
adc_ll_onetime_sample_enable(adc_n, true);
|
|
|
|
adc_ll_onetime_set_channel(adc_n, channel);
|
2020-12-15 09:20:22 +00:00
|
|
|
|
2021-02-23 13:40:15 +00:00
|
|
|
//Trigger single read.
|
|
|
|
adc_hal_onetime_start();
|
|
|
|
while (!adc_hal_intr_get_raw(event));
|
|
|
|
ret = adc_hal_single_read(adc_n, out_raw);
|
2020-12-15 09:20:22 +00:00
|
|
|
|
2021-02-23 13:40:15 +00:00
|
|
|
return ret;
|
2020-12-15 09:20:22 +00:00
|
|
|
}
|
2021-02-23 13:40:15 +00:00
|
|
|
#else // !CONFIG_IDF_TARGET_ESP32C3
|
|
|
|
esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw)
|
2020-12-15 09:20:22 +00:00
|
|
|
{
|
2021-02-23 13:40:15 +00:00
|
|
|
adc_ll_rtc_enable_channel(adc_n, channel);
|
|
|
|
adc_ll_rtc_start_convert(adc_n, channel);
|
|
|
|
while (adc_ll_rtc_convert_is_done(adc_n) != true);
|
|
|
|
*out_raw = adc_ll_rtc_get_convert_value(adc_n);
|
2020-12-15 09:20:22 +00:00
|
|
|
|
2021-02-23 13:40:15 +00:00
|
|
|
if ((int)adc_ll_rtc_analysis_raw_data(adc_n, (uint16_t)(*out_raw))) {
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
}
|
2021-03-10 04:01:00 +00:00
|
|
|
|
|
|
|
return ESP_OK;
|
2020-12-15 09:20:22 +00:00
|
|
|
}
|
2021-02-23 13:40:15 +00:00
|
|
|
#endif //#if !CONFIG_IDF_TARGET_ESP32C3
|