kopia lustrzana https://github.com/espressif/esp-idf
40 wiersze
2.0 KiB
C
40 wiersze
2.0 KiB
C
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include "esp_err.h"
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/*
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* Possible errors returned from esp flash internal functions, these error codes
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* should be consistent with esp_err_t codes. But in order to make the source
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* files less dependent to esp_err_t, they use the error codes defined in this
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* replacable header. This header should ensure the consistency to esp_err_t.
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*/
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/* These should be consistent with esp_err_t errors */
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#define ESP_ERR_FLASH_SIZE_NOT_MATCH ESP_ERR_INVALID_SIZE ///< The chip doesn't have enough space for the current partition table
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#define ESP_ERR_FLASH_NO_RESPONSE ESP_ERR_INVALID_RESPONSE ///< Chip did not respond to the command, or timed out.
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#define ESP_ERR_FLASH_ERR_BASE 0x6000 ///< Starting number of Flash error codes */
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//The ROM code has already taken 1 and 2, to avoid possible conflicts, start from 3.
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#define ESP_ERR_FLASH_NOT_INITIALISED (ESP_ERR_FLASH_ERR_BASE+3) ///< esp_flash_chip_t structure not correctly initialised by esp_flash_init().
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#define ESP_ERR_FLASH_UNSUPPORTED_HOST (ESP_ERR_FLASH_ERR_BASE+4) ///< Requested operation isn't supported via this host SPI bus (chip->spi field).
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#define ESP_ERR_FLASH_UNSUPPORTED_CHIP (ESP_ERR_FLASH_ERR_BASE+5) ///< Requested operation isn't supported by this model of SPI flash chip.
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#define ESP_ERR_FLASH_PROTECTED (ESP_ERR_FLASH_ERR_BASE+6) ///< Write operation failed due to chip's write protection being enabled.
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