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esp-idf/components/hal/twai_hal_iram.c

205 wiersze
9.5 KiB
C
Czysty Zwykły widok Historia

TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stddef.h>
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
#include <string.h>
#include "sdkconfig.h"
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
#include "hal/twai_hal.h"
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
#ifdef CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT
//Errata condition occurs at 64 messages. Threshold set to 62 to prevent the chance of failing to detect errata condition.
#define TWAI_RX_FIFO_CORRUPT_THRESH 62
#endif
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
/* ----------------------------- Event Handling ----------------------------- */
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
/**
* Helper functions that can decode what events have been triggered based on
* the values of the interrupt, status, TEC and REC registers. The HAL context's
* state flags are also updated based on the events that have triggered.
*/
static inline uint32_t twai_hal_decode_interrupt(twai_hal_context_t *hal_ctx)
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
{
uint32_t events = 0;
uint32_t interrupts = twai_ll_get_and_clear_intrs(hal_ctx->dev);
uint32_t status = twai_ll_get_status(hal_ctx->dev);
uint32_t tec = twai_ll_get_tec(hal_ctx->dev);
uint32_t rec = twai_ll_get_rec(hal_ctx->dev);
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
uint32_t state_flags = hal_ctx->state_flags;
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
//Error Warning Interrupt set whenever Error or Bus Status bit changes
if (interrupts & TWAI_LL_INTR_EI) {
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
if (status & TWAI_LL_STATUS_BS) { //Currently in BUS OFF state
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
if (status & TWAI_LL_STATUS_ES) { //EWL is exceeded, thus must have entered BUS OFF
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_BUS_OFF);
TWAI_HAL_SET_BITS(state_flags, TWAI_HAL_STATE_FLAG_BUS_OFF);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
//Any TX would have been halted by entering bus off. Reset its flag
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_CLEAR_BITS(state_flags, TWAI_HAL_STATE_FLAG_RUNNING | TWAI_HAL_STATE_FLAG_TX_BUFF_OCCUPIED);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
} else {
//Below EWL. Therefore TEC is counting down in bus recovery
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_BUS_RECOV_PROGRESS);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
}
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
} else { //Not in BUS OFF
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
if (status & TWAI_LL_STATUS_ES) { //Just Exceeded EWL
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_ABOVE_EWL);
TWAI_HAL_SET_BITS(state_flags, TWAI_HAL_STATE_FLAG_ERR_WARN);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
} else if (hal_ctx->state_flags & TWAI_HAL_STATE_FLAG_RECOVERING) {
//Previously undergoing bus recovery. Thus means bus recovery complete
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_BUS_RECOV_CPLT);
TWAI_HAL_CLEAR_BITS(state_flags, TWAI_HAL_STATE_FLAG_RECOVERING | TWAI_HAL_STATE_FLAG_BUS_OFF);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
} else { //Just went below EWL
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_BELOW_EWL);
TWAI_HAL_CLEAR_BITS(state_flags, TWAI_HAL_STATE_FLAG_ERR_WARN);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
}
}
}
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
//Receive Interrupt set whenever RX FIFO is not empty
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
if (interrupts & TWAI_LL_INTR_RI) {
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_RX_BUFF_FRAME);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
}
//Transmit interrupt set whenever TX buffer becomes free
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
#ifdef CONFIG_TWAI_ERRATA_FIX_TX_INTR_LOST
if ((interrupts & TWAI_LL_INTR_TI || hal_ctx->state_flags & TWAI_HAL_STATE_FLAG_TX_BUFF_OCCUPIED) && status & TWAI_LL_STATUS_TBS) {
#else
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
if (interrupts & TWAI_LL_INTR_TI) {
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
#endif
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_TX_BUFF_FREE);
TWAI_HAL_CLEAR_BITS(state_flags, TWAI_HAL_STATE_FLAG_TX_BUFF_OCCUPIED);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
}
//Error Passive Interrupt on transition from error active to passive or vice versa
if (interrupts & TWAI_LL_INTR_EPI) {
if (tec >= TWAI_ERR_PASS_THRESH || rec >= TWAI_ERR_PASS_THRESH) {
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_ERROR_PASSIVE);
TWAI_HAL_SET_BITS(state_flags, TWAI_HAL_STATE_FLAG_ERR_PASSIVE);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
} else {
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_ERROR_ACTIVE);
TWAI_HAL_CLEAR_BITS(state_flags, TWAI_HAL_STATE_FLAG_ERR_PASSIVE);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
}
}
//Bus error interrupt triggered on a bus error (e.g. bit, ACK, stuff etc)
if (interrupts & TWAI_LL_INTR_BEI) {
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_BUS_ERR);
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
}
//Arbitration Lost Interrupt triggered on losing arbitration
if (interrupts & TWAI_LL_INTR_ALI) {
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_ARB_LOST);
}
hal_ctx->state_flags = state_flags;
return events;
}
uint32_t twai_hal_get_events(twai_hal_context_t *hal_ctx)
{
uint32_t events = twai_hal_decode_interrupt(hal_ctx);
//Handle low latency events
if (events & TWAI_HAL_EVENT_BUS_OFF) {
twai_ll_set_mode(hal_ctx->dev, TWAI_MODE_LISTEN_ONLY); //Freeze TEC/REC by entering LOM
#ifdef CONFIG_TWAI_ERRATA_FIX_BUS_OFF_REC
//Errata workaround: Force REC to 0 by re-triggering bus-off (by setting TEC to 0 then 255)
twai_ll_set_tec(hal_ctx->dev, 0);
twai_ll_set_tec(hal_ctx->dev, 255);
(void) twai_ll_get_and_clear_intrs(hal_ctx->dev); //Clear the re-triggered bus-off interrupt
#endif
}
if (events & TWAI_HAL_EVENT_BUS_RECOV_CPLT) {
twai_ll_enter_reset_mode(hal_ctx->dev); //Enter reset mode to stop the controller
}
if (events & TWAI_HAL_EVENT_BUS_ERR) {
#ifdef CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID
twai_ll_err_type_t type;
twai_ll_err_dir_t dir;
twai_ll_err_seg_t seg;
twai_ll_parse_err_code_cap(hal_ctx->dev, &type, &dir, &seg); //Decode error interrupt
//Check for errata condition (RX message has bus error at particular segments)
if (dir == TWAI_LL_ERR_DIR_RX &&
((seg == TWAI_LL_ERR_SEG_DATA || seg == TWAI_LL_ERR_SEG_CRC_SEQ) ||
(seg == TWAI_LL_ERR_SEG_ACK_DELIM && type == TWAI_LL_ERR_OTHER))) {
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_NEED_PERIPH_RESET);
}
#endif
twai_ll_clear_err_code_cap(hal_ctx->dev);
}
if (events & TWAI_HAL_EVENT_ARB_LOST) {
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
twai_ll_clear_arb_lost_cap(hal_ctx->dev);
}
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
#ifdef CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT
//Check for errata condition (rx_msg_count >= corruption_threshold)
if (events & TWAI_HAL_EVENT_RX_BUFF_FRAME && twai_ll_get_rx_msg_count(hal_ctx->dev) >= TWAI_RX_FIFO_CORRUPT_THRESH) {
TWAI_HAL_SET_BITS(events, TWAI_HAL_EVENT_NEED_PERIPH_RESET);
}
#endif
#if defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT)
if (events & TWAI_HAL_EVENT_NEED_PERIPH_RESET) {
//A peripheral reset will invalidate an RX event;
TWAI_HAL_CLEAR_BITS(events, (TWAI_HAL_EVENT_RX_BUFF_FRAME));
}
#endif
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
return events;
}
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
#if defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT)
void twai_hal_prepare_for_reset(twai_hal_context_t *hal_ctx)
{
uint32_t status = twai_ll_get_status(hal_ctx->dev);
if (!(status & TWAI_LL_STATUS_TBS)) { //Transmit buffer is NOT free, indicating an Ongoing TX will be cancelled by the HW reset
TWAI_HAL_SET_BITS(hal_ctx->state_flags, TWAI_HAL_STATE_FLAG_TX_NEED_RETRY);
//Note: Even if the TX completes right after this, we still consider it will be retried.
//Worst case the same message will get sent twice.
}
//Some register must saved before entering reset mode
hal_ctx->rx_msg_cnt_save = (uint8_t) twai_ll_get_rx_msg_count(hal_ctx->dev);
twai_ll_enter_reset_mode(hal_ctx->dev); //Enter reset mode to stop the controller
twai_ll_save_reg(hal_ctx->dev, &hal_ctx->reg_save); //Save remaining registers after entering reset mode
}
void twai_hal_recover_from_reset(twai_hal_context_t *hal_ctx)
{
twai_ll_enter_reset_mode(hal_ctx->dev);
twai_ll_enable_extended_reg_layout(hal_ctx->dev);
twai_ll_restore_reg(hal_ctx->dev, &hal_ctx->reg_save);
twai_ll_exit_reset_mode(hal_ctx->dev);
(void) twai_ll_get_and_clear_intrs(hal_ctx->dev);
if (hal_ctx->state_flags & TWAI_HAL_STATE_FLAG_TX_NEED_RETRY) {
//HW reset has cancelled a TX. Re-transmit here
twai_hal_set_tx_buffer_and_transmit(hal_ctx, &hal_ctx->tx_frame_save);
TWAI_HAL_CLEAR_BITS(hal_ctx->state_flags, TWAI_HAL_STATE_FLAG_TX_NEED_RETRY);
}
}
#endif //defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT)
TWAI: ISR runs when cache is disabled This commit adds the feature where the TWAI ISR will continue to run even if the cache is disabled. Whilst cache is disabled, any received messages will go into the RX queue, and any pending TX messages in the TX queue will be transmitted. This feature should be enabled using the CONFIG_TWAI_ISR_IN_IRAM option.
2020-08-04 04:52:10 +00:00
void twai_hal_set_tx_buffer_and_transmit(twai_hal_context_t *hal_ctx, twai_hal_frame_t *tx_frame)
{
//Copy frame into tx buffer
twai_ll_set_tx_buffer(hal_ctx->dev, tx_frame);
//Hit the send command
if (tx_frame->self_reception) {
if (tx_frame->single_shot) {
twai_ll_set_cmd_self_rx_single_shot(hal_ctx->dev);
} else {
twai_ll_set_cmd_self_rx_request(hal_ctx->dev);
}
} else if (tx_frame->single_shot){
twai_ll_set_cmd_tx_single_shot(hal_ctx->dev);
} else {
twai_ll_set_cmd_tx(hal_ctx->dev);
}
TWAI: FIFO overrun handling and errata workarounds This commit adds handling for FIFO overruns and adds workarounds for HW errats on the ESP32. Closes https://github.com/espressif/esp-idf/issues/2519 Closes https://github.com/espressif/esp-idf/issues/4276
2021-03-25 02:24:37 +00:00
TWAI_HAL_SET_BITS(hal_ctx->state_flags, TWAI_HAL_STATE_FLAG_TX_BUFF_OCCUPIED);
#if defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT)
//Save transmitted frame in case we need to retry
memcpy(&hal_ctx->tx_frame_save, tx_frame, sizeof(twai_hal_frame_t));
#endif //defined(CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID) || defined(CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT)
Whitespace: Automated whitespace fixes (large commit) Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace)
2020-11-10 07:40:01 +00:00
}