2021-11-06 09:24:45 +00:00
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2021-04-02 04:41:21 +00:00
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#include <sys/param.h>
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#include "soc/soc_caps.h"
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#include "hal/systimer_hal.h"
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#include "hal/systimer_ll.h"
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#include "hal/systimer_types.h"
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#include "hal/clk_gate_ll.h"
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2021-05-19 02:53:21 +00:00
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#include "hal/assert.h"
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2021-04-02 04:41:21 +00:00
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void systimer_hal_init(systimer_hal_context_t *hal)
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{
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hal->dev = &SYSTIMER;
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periph_ll_enable_clk_clear_rst(PERIPH_SYSTIMER_MODULE);
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systimer_ll_enable_clock(hal->dev, true);
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}
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uint64_t systimer_hal_get_counter_value(systimer_hal_context_t *hal, uint32_t counter_id)
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{
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uint32_t lo, lo_start, hi;
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/* Set the "update" bit and wait for acknowledgment */
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systimer_ll_counter_snapshot(hal->dev, counter_id);
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while (!systimer_ll_is_counter_value_valid(hal->dev, counter_id));
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/* Read LO, HI, then LO again, check that LO returns the same value.
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* This accounts for the case when an interrupt may happen between reading
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* HI and LO values, and this function may get called from the ISR.
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* In this case, the repeated read will return consistent values.
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*/
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lo_start = systimer_ll_get_counter_value_low(hal->dev, counter_id);
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do {
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lo = lo_start;
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hi = systimer_ll_get_counter_value_high(hal->dev, counter_id);
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lo_start = systimer_ll_get_counter_value_low(hal->dev, counter_id);
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} while (lo_start != lo);
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systimer_counter_value_t result = {
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.lo = lo,
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.hi = hi
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};
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return result.val;
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}
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uint64_t systimer_hal_get_time(systimer_hal_context_t *hal, uint32_t counter_id)
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{
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2021-04-25 11:38:01 +00:00
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return systimer_hal_get_counter_value(hal, counter_id) / SYSTIMER_LL_TICKS_PER_US;
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2021-04-02 04:41:21 +00:00
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}
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#if SOC_SYSTIMER_ALARM_MISS_COMPENSATE
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void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t target)
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{
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2021-04-25 11:38:01 +00:00
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systimer_counter_value_t alarm = { .val = target * SYSTIMER_LL_TICKS_PER_US};
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2021-04-02 04:41:21 +00:00
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systimer_ll_enable_alarm(hal->dev, alarm_id, false);
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systimer_ll_set_alarm_target(hal->dev, alarm_id, alarm.val);
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systimer_ll_apply_alarm_value(hal->dev, alarm_id);
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systimer_ll_enable_alarm(hal->dev, alarm_id, true);
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}
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#else
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void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t timestamp)
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{
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2021-04-25 11:38:01 +00:00
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int64_t offset = SYSTIMER_LL_TICKS_PER_US * 2;
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2021-04-02 04:41:21 +00:00
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uint64_t now_time = systimer_hal_get_counter_value(hal, 0);
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2021-04-25 11:38:01 +00:00
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systimer_counter_value_t alarm = { .val = MAX(timestamp * SYSTIMER_LL_TICKS_PER_US, now_time + offset) };
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2021-04-02 04:41:21 +00:00
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do {
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systimer_ll_enable_alarm(hal->dev, alarm_id, false);
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systimer_ll_set_alarm_target(hal->dev, alarm_id, alarm.val);
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systimer_ll_enable_alarm(hal->dev, alarm_id, true);
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now_time = systimer_hal_get_counter_value(hal, 0);
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int64_t delta = (int64_t)alarm.val - (int64_t)now_time;
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if (delta <= 0 && !systimer_ll_is_alarm_int_fired(hal->dev, alarm_id)) {
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// new alarm is less than the counter and the interrupt flag is not set
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2021-04-25 11:38:01 +00:00
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offset += -1 * delta + SYSTIMER_LL_TICKS_PER_US * 2;
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2021-04-02 04:41:21 +00:00
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alarm.val = now_time + offset;
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} else {
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// finish if either (alarm > counter) or the interrupt flag is already set.
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break;
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}
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} while (1);
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}
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#endif
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void systimer_hal_set_alarm_period(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t period)
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{
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systimer_ll_enable_alarm(hal->dev, alarm_id, false);
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2021-04-25 11:38:01 +00:00
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systimer_ll_set_alarm_period(hal->dev, alarm_id, period * SYSTIMER_LL_TICKS_PER_US);
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2021-04-02 04:41:21 +00:00
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systimer_ll_apply_alarm_value(hal->dev, alarm_id);
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systimer_ll_enable_alarm(hal->dev, alarm_id, true);
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}
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uint64_t systimer_hal_get_alarm_value(systimer_hal_context_t *hal, uint32_t alarm_id)
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{
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return systimer_ll_get_alarm_target(hal->dev, alarm_id);
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}
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void systimer_hal_enable_alarm_int(systimer_hal_context_t *hal, uint32_t alarm_id)
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{
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systimer_ll_enable_alarm_int(hal->dev, alarm_id, true);
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}
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void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t counter_id, int64_t time_us)
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{
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2021-04-25 11:38:01 +00:00
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systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(hal, counter_id) + time_us * SYSTIMER_LL_TICKS_PER_US };
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2021-04-02 04:41:21 +00:00
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systimer_ll_set_counter_value(hal->dev, counter_id, new_count.val);
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systimer_ll_apply_counter_value(hal->dev, counter_id);
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}
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void systimer_hal_enable_counter(systimer_hal_context_t *hal, uint32_t counter_id)
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{
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systimer_ll_enable_counter(hal->dev, counter_id, true);
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}
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void systimer_hal_select_alarm_mode(systimer_hal_context_t *hal, uint32_t alarm_id, systimer_alarm_mode_t mode)
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{
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switch (mode) {
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case SYSTIMER_ALARM_MODE_ONESHOT:
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systimer_ll_enable_alarm_oneshot(hal->dev, alarm_id);
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break;
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case SYSTIMER_ALARM_MODE_PERIOD:
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systimer_ll_enable_alarm_period(hal->dev, alarm_id);
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break;
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default:
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break;
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}
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}
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void systimer_hal_connect_alarm_counter(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t counter_id)
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{
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systimer_ll_connect_alarm_counter(hal->dev, alarm_id, counter_id);
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}
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void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t counter_id, uint32_t cpu_id, bool can)
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{
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systimer_ll_counter_can_stall_by_cpu(hal->dev, counter_id, cpu_id, can);
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}
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#if !SOC_SYSTIMER_FIXED_TICKS_US
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void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps)
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{
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/* Configure the counter:
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* - increment by 1 when running from PLL (80 ticks per microsecond),
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* - increment by 2 when running from XTAL (40 ticks per microsecond).
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* Note that if the APB frequency is derived from XTAL with divider != 1,
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* XTAL_STEP needs to be adjusted accordingly. For example, if
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* the APB frequency is XTAL/4 = 10 MHz, then XTAL_STEP should be set to 8.
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* This is handled in systimer_hal_on_apb_freq_update function.
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*/
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switch (clock_source) {
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case 0:
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systimer_ll_set_step_for_xtal(hal->dev, steps);
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break;
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case 1:
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systimer_ll_set_step_for_pll(hal->dev, steps);
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default:
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break;
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}
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}
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void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_ticks_per_us)
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{
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/* If this function was called when switching APB clock to PLL, don't need
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* do anything: the SYSTIMER_TIMER_PLL_STEP is already correct.
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* If this was called when switching APB clock to XTAL, need to adjust
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* XTAL_STEP value accordingly.
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*/
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2021-04-25 11:38:01 +00:00
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if (apb_ticks_per_us != SYSTIMER_LL_TICKS_PER_US) {
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2021-05-19 02:53:21 +00:00
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HAL_ASSERT((SYSTIMER_LL_TICKS_PER_US % apb_ticks_per_us) == 0 && "TICK_PER_US should be divisible by APB frequency (in MHz)");
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2021-04-25 11:38:01 +00:00
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systimer_ll_set_step_for_xtal(hal->dev, SYSTIMER_LL_TICKS_PER_US / apb_ticks_per_us);
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2021-04-02 04:41:21 +00:00
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}
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}
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#endif
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