2019-01-23 09:07:03 +00:00
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The HAL layer for SPI (common part, in iram)
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// make these functions in a seperate file to make sure all LL functions are in the IRAM.
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#include "hal/spi_hal.h"
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2020-09-23 13:01:13 +00:00
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#include "soc/soc_caps.h"
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2020-09-08 09:05:49 +00:00
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//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
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2020-09-23 13:01:13 +00:00
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#if SOC_GDMA_SUPPORTED
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#include "soc/gdma_struct.h"
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#include "hal/gdma_ll.h"
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#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL)
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#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);
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#define spi_dma_ll_rx_start(dev, addr) do {\
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gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\
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} while (0)
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#define spi_dma_ll_tx_start(dev, addr) do {\
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gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\
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} while (0)
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#endif
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2019-01-23 09:07:03 +00:00
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2020-09-09 02:21:49 +00:00
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void spi_hal_setup_device(spi_hal_context_t *hal, const spi_hal_dev_config_t *dev)
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2019-01-23 09:07:03 +00:00
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{
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//Configure clock settings
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spi_dev_t *hw = hal->hw;
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2020-09-12 09:58:30 +00:00
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#if SOC_SPI_SUPPORT_AS_CS
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2020-09-09 02:21:49 +00:00
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spi_ll_master_set_cksel(hw, dev->cs_pin_id, dev->as_cs);
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2019-06-13 06:12:54 +00:00
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#endif
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2020-09-09 02:21:49 +00:00
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spi_ll_master_set_pos_cs(hw, dev->cs_pin_id, dev->positive_cs);
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spi_ll_master_set_clock_by_reg(hw, &dev->timing_conf.clock_reg);
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2019-01-23 09:07:03 +00:00
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//Configure bit order
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2020-09-09 02:21:49 +00:00
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spi_ll_set_rx_lsbfirst(hw, dev->rx_lsbfirst);
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spi_ll_set_tx_lsbfirst(hw, dev->tx_lsbfirst);
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spi_ll_master_set_mode(hw, dev->mode);
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2019-01-23 09:07:03 +00:00
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//Configure misc stuff
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2020-09-09 02:21:49 +00:00
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spi_ll_set_half_duplex(hw, dev->half_duplex);
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spi_ll_set_sio_mode(hw, dev->sio);
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2019-01-23 09:07:03 +00:00
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//Configure CS pin and timing
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2020-09-09 02:21:49 +00:00
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spi_ll_master_set_cs_setup(hw, dev->cs_setup);
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spi_ll_master_set_cs_hold(hw, dev->cs_hold);
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spi_ll_master_select_cs(hw, dev->cs_pin_id);
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2019-01-23 09:07:03 +00:00
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}
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2020-09-09 02:21:49 +00:00
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void spi_hal_setup_trans(spi_hal_context_t *hal, const spi_hal_dev_config_t *dev, const spi_hal_trans_config_t *trans)
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2019-01-23 09:07:03 +00:00
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{
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spi_dev_t *hw = hal->hw;
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2019-04-26 17:29:48 +00:00
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//clear int bit
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2019-01-23 09:07:03 +00:00
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spi_ll_clear_int_stat(hal->hw);
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2019-04-26 17:29:48 +00:00
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//We should be done with the transmission.
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2019-01-23 09:07:03 +00:00
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assert(spi_ll_get_running_cmd(hw) == 0);
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2020-09-09 02:21:49 +00:00
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spi_ll_master_set_io_mode(hw, trans->io_mode);
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2019-01-23 09:07:03 +00:00
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int extra_dummy = 0;
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//when no_dummy is not set and in half-duplex mode, sets the dummy bit if RX phase exist
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2020-09-09 02:21:49 +00:00
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if (trans->rcv_buffer && !dev->no_compensate && dev->half_duplex) {
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extra_dummy = dev->timing_conf.timing_dummy;
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2019-01-23 09:07:03 +00:00
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}
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//SPI iface needs to be configured for a delay in some cases.
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//configure dummy bits
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2020-09-09 02:21:49 +00:00
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spi_ll_set_dummy(hw, extra_dummy + trans->dummy_bits);
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2019-01-23 09:07:03 +00:00
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uint32_t miso_delay_num = 0;
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uint32_t miso_delay_mode = 0;
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2020-09-09 02:21:49 +00:00
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if (dev->timing_conf.timing_miso_delay < 0) {
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2019-01-23 09:07:03 +00:00
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//if the data comes too late, delay half a SPI clock to improve reading
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2020-09-09 02:21:49 +00:00
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switch (dev->mode) {
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2019-01-23 09:07:03 +00:00
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case 0:
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miso_delay_mode = 2;
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break;
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case 1:
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miso_delay_mode = 1;
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break;
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case 2:
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miso_delay_mode = 1;
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break;
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case 3:
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miso_delay_mode = 2;
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break;
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}
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miso_delay_num = 0;
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} else {
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//if the data is so fast that dummy_bit is used, delay some apb clocks to meet the timing
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2020-09-09 02:21:49 +00:00
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miso_delay_num = extra_dummy ? dev->timing_conf.timing_miso_delay : 0;
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2019-01-23 09:07:03 +00:00
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miso_delay_mode = 0;
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}
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spi_ll_set_miso_delay(hw, miso_delay_mode, miso_delay_num);
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2020-09-09 02:21:49 +00:00
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spi_ll_set_mosi_bitlen(hw, trans->tx_bitlen);
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2019-01-23 09:07:03 +00:00
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2020-09-09 02:21:49 +00:00
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if (dev->half_duplex) {
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spi_ll_set_miso_bitlen(hw, trans->rx_bitlen);
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2019-01-23 09:07:03 +00:00
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} else {
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//rxlength is not used in full-duplex mode
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2020-09-09 02:21:49 +00:00
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spi_ll_set_miso_bitlen(hw, trans->tx_bitlen);
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2019-01-23 09:07:03 +00:00
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}
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//Configure bit sizes, load addr and command
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2020-09-09 02:21:49 +00:00
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int cmdlen = trans->cmd_bits;
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int addrlen = trans->addr_bits;
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if (!dev->half_duplex && dev->cs_setup != 0) {
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2019-01-23 09:07:03 +00:00
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/* The command and address phase is not compatible with cs_ena_pretrans
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* in full duplex mode.
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*/
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cmdlen = 0;
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addrlen = 0;
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}
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spi_ll_set_addr_bitlen(hw, addrlen);
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spi_ll_set_command_bitlen(hw, cmdlen);
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2020-09-09 02:21:49 +00:00
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spi_ll_set_command(hw, trans->cmd, cmdlen, dev->tx_lsbfirst);
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spi_ll_set_address(hw, trans->addr, addrlen, dev->tx_lsbfirst);
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//Save the transaction attributes for internal usage.
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memcpy(&hal->trans_config, trans, sizeof(spi_hal_trans_config_t));
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2019-01-23 09:07:03 +00:00
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}
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2020-09-09 02:21:49 +00:00
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void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *dev, const spi_hal_trans_config_t *trans)
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2019-01-23 09:07:03 +00:00
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{
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spi_dev_t *hw = hal->hw;
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2020-09-14 09:33:10 +00:00
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spi_ll_dma_fifo_reset(hal->hw);
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2019-01-23 09:07:03 +00:00
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//Fill DMA descriptors
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2020-09-09 02:21:49 +00:00
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if (trans->rcv_buffer) {
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2019-01-23 09:07:03 +00:00
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if (!hal->dma_enabled) {
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//No need to setup anything; we'll copy the result out of the work registers directly later.
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} else {
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2020-09-09 02:21:49 +00:00
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lldesc_setup_link(hal->dma_config.dmadesc_rx, trans->rcv_buffer, ((trans->rx_bitlen + 7) / 8), true);
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2020-11-10 07:40:01 +00:00
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2020-09-09 02:21:49 +00:00
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spi_dma_ll_rx_reset(hal->dma_in);
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2020-11-10 07:40:01 +00:00
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spi_ll_dma_rx_enable(hal->hw, 1);
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2020-09-09 02:21:49 +00:00
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spi_dma_ll_rx_start(hal->dma_in, hal->dma_config.dmadesc_rx);
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2019-01-23 09:07:03 +00:00
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}
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2020-09-14 09:33:10 +00:00
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2019-01-23 09:07:03 +00:00
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} else {
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//DMA temporary workaround: let RX DMA work somehow to avoid the issue in ESP32 v0/v1 silicon
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if (hal->dma_enabled) {
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2020-09-14 09:33:10 +00:00
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spi_ll_dma_rx_enable(hal->hw, 1);
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2020-09-09 02:21:49 +00:00
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spi_dma_ll_rx_start(hal->dma_in, 0);
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2019-01-23 09:07:03 +00:00
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}
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}
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2020-09-09 02:21:49 +00:00
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if (trans->send_buffer) {
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2019-01-23 09:07:03 +00:00
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if (!hal->dma_enabled) {
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//Need to copy data to registers manually
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2020-09-09 02:21:49 +00:00
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spi_ll_write_buffer(hw, trans->send_buffer, trans->tx_bitlen);
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2019-01-23 09:07:03 +00:00
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} else {
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2020-09-09 02:21:49 +00:00
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lldesc_setup_link(hal->dma_config.dmadesc_tx, trans->send_buffer, (trans->tx_bitlen + 7) / 8, false);
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2020-11-10 07:40:01 +00:00
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2020-09-09 02:21:49 +00:00
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spi_dma_ll_tx_reset(hal->dma_out);
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spi_ll_dma_tx_enable(hal->hw, 1);
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spi_dma_ll_tx_start(hal->dma_out, hal->dma_config.dmadesc_tx);
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2019-01-23 09:07:03 +00:00
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}
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}
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2020-09-14 09:33:10 +00:00
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2019-01-23 09:07:03 +00:00
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//in ESP32 these registers should be configured after the DMA is set
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2020-09-09 02:21:49 +00:00
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if ((!dev->half_duplex && trans->rcv_buffer) || trans->send_buffer) {
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2019-01-23 09:07:03 +00:00
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spi_ll_enable_mosi(hw, 1);
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} else {
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spi_ll_enable_mosi(hw, 0);
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}
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2020-09-09 02:21:49 +00:00
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spi_ll_enable_miso(hw, (trans->rcv_buffer) ? 1 : 0);
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2019-01-23 09:07:03 +00:00
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}
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void spi_hal_user_start(const spi_hal_context_t *hal)
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{
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2020-09-08 09:05:49 +00:00
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spi_ll_master_user_start(hal->hw);
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2019-01-23 09:07:03 +00:00
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}
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bool spi_hal_usr_is_done(const spi_hal_context_t *hal)
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{
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return spi_ll_usr_is_done(hal->hw);
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}
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void spi_hal_fetch_result(const spi_hal_context_t *hal)
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{
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2020-09-09 02:21:49 +00:00
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const spi_hal_trans_config_t *trans = &hal->trans_config;
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if (trans->rcv_buffer && !hal->dma_enabled) {
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2019-01-23 09:07:03 +00:00
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//Need to copy from SPI regs to result buffer.
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2020-09-09 02:21:49 +00:00
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spi_ll_read_buffer(hal->hw, trans->rcv_buffer, trans->rx_bitlen);
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2019-01-23 09:07:03 +00:00
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}
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}
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