2022-02-11 07:30:54 +00:00
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/*
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2023-07-07 09:35:29 +00:00
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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2022-02-11 07:30:54 +00:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "hal/assert.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_types.h"
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#include "hal/cache_ll.h"
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2023-02-13 11:12:44 +00:00
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#include "hal/mmu_hal.h"
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2022-10-17 04:40:05 +00:00
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#include "hal/mmu_ll.h"
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2022-02-11 07:30:54 +00:00
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#include "soc/soc_caps.h"
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2023-02-15 04:29:34 +00:00
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#include "rom/cache.h"
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2022-02-11 07:30:54 +00:00
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/*------------------------------------------------------------------------------
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* Unified Cache Control
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* See cache_hal.h for more info about these HAL APIs
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* This file is in internal RAM.
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* Now this file doesn't compile on ESP32
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*----------------------------------------------------------------------------*/
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/**
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* To know if autoload is enabled or not.
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*
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* We should have a unified flag for this aim, then we don't need to call following 2 functions
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* to know the flag.
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*
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* Suggest ROM keeping this flag value to BIT(2). Then we can replace following lines to:
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* #define DATA_AUTOLOAD_FLAG BIT(2)
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* #define INST_AUTOLOAD_FLAG BIT(2)
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*/
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2023-07-07 09:35:29 +00:00
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#if CONFIG_IDF_TARGET_ESP32P4 //TODO: IDF-7516
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2023-08-07 07:20:00 +00:00
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#define DATA_AUTOLOAD_ENABLE Cache_Disable_L2_Cache()
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#define INST_AUTOLOAD_ENABLE Cache_Disable_L2_Cache()
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2023-07-07 09:35:29 +00:00
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#else
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2023-08-07 07:20:00 +00:00
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#define DATA_AUTOLOAD_ENABLE cache_ll_is_cache_autoload_enabled(CACHE_TYPE_DATA)
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#define INST_AUTOLOAD_ENABLE cache_ll_is_cache_autoload_enabled(CACHE_TYPE_INSTRUCTION)
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2023-07-07 09:35:29 +00:00
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#endif
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2022-02-11 07:30:54 +00:00
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/**
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* Necessary hal contexts, could be maintained by upper layer in the future
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*/
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typedef struct {
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2023-08-07 07:20:00 +00:00
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bool data_autoload_en;
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bool inst_autoload_en;
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2023-06-13 03:56:14 +00:00
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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// There's no register indicating if cache is enabled on these chips, use sw flag to save this state.
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volatile bool cache_enabled;
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#endif
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2022-02-11 07:30:54 +00:00
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} cache_hal_context_t;
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static cache_hal_context_t ctx;
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void cache_hal_init(void)
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{
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2023-08-07 07:20:00 +00:00
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ctx.data_autoload_en = DATA_AUTOLOAD_ENABLE;
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ctx.inst_autoload_en = INST_AUTOLOAD_ENABLE;
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#if SOC_CACHE_L2_SUPPORTED
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Cache_Enable_L2_Cache(ctx.inst_autoload_en);
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2022-02-11 07:30:54 +00:00
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#else
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2023-08-07 07:20:00 +00:00
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cache_ll_enable_cache(CACHE_TYPE_ALL, ctx.inst_autoload_en, ctx.data_autoload_en);
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#endif //SOC_CACHE_L2_SUPPORTED
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2022-02-11 07:30:54 +00:00
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cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_DBUS_MASK);
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cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_IBUS_MASK);
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#if !CONFIG_FREERTOS_UNICORE
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cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_DBUS_MASK);
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cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_IBUS_MASK);
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#endif
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2023-06-13 03:56:14 +00:00
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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ctx.cache_enabled = 1;
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#endif
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2022-02-11 07:30:54 +00:00
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}
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void cache_hal_disable(cache_type_t type)
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{
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2023-08-07 07:20:00 +00:00
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#if SOC_CACHE_L2_SUPPORTED
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2023-07-07 09:35:29 +00:00
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Cache_Disable_L2_Cache();
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#else
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2023-08-07 07:20:00 +00:00
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cache_ll_disable_cache(type);
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#endif //SOC_CACHE_L2_SUPPORTED
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2023-06-13 03:56:14 +00:00
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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ctx.cache_enabled = 0;
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#endif
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2022-02-11 07:30:54 +00:00
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}
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void cache_hal_enable(cache_type_t type)
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{
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2023-08-07 07:20:00 +00:00
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#if SOC_CACHE_L2_SUPPORTED
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Cache_Enable_L2_Cache(ctx.inst_autoload_en);
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2022-02-11 07:30:54 +00:00
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#else
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2023-08-07 07:20:00 +00:00
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cache_ll_enable_cache(type, ctx.inst_autoload_en, ctx.data_autoload_en);
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#endif //SOC_CACHE_L2_SUPPORTED
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2023-06-13 03:56:14 +00:00
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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ctx.cache_enabled = 1;
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#endif
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}
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void cache_hal_suspend(cache_type_t type)
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{
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2023-07-07 09:35:29 +00:00
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#if SOC_CACHE_L2_SUPPORTED
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Cache_Suspend_L2_Cache();
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2023-06-13 03:56:14 +00:00
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#else
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2023-08-07 07:20:00 +00:00
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cache_ll_suspend_cache(type);
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#endif //SOC_CACHE_L2_SUPPORTED
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2023-06-13 03:56:14 +00:00
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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ctx.cache_enabled = 0;
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#endif
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}
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void cache_hal_resume(cache_type_t type)
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{
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2023-07-07 09:35:29 +00:00
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#if SOC_CACHE_L2_SUPPORTED
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Cache_Resume_L2_Cache(ctx.inst_autoload_en);
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2023-06-13 03:56:14 +00:00
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#else
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2023-08-07 07:20:00 +00:00
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cache_ll_resume_cache(type, ctx.inst_autoload_en, ctx.data_autoload_en);
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2023-06-13 03:56:14 +00:00
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#endif
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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ctx.cache_enabled = 1;
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#endif
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}
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bool cache_hal_is_cache_enabled(cache_type_t type)
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{
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bool enabled;
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2023-06-13 03:56:14 +00:00
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#if CACHE_LL_ENABLE_DISABLE_STATE_SW
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enabled = ctx.cache_enabled;
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2023-06-13 03:56:14 +00:00
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#else
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2023-08-07 07:20:00 +00:00
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enabled = cache_ll_is_cache_enabled(type);
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#endif //CACHE_LL_ENABLE_DISABLE_STATE_SW
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return enabled;
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2022-02-11 07:30:54 +00:00
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}
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2022-10-17 04:40:05 +00:00
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void cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size)
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{
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//Now only esp32 has 2 MMUs, this file doesn't build on esp32
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2023-02-13 11:12:44 +00:00
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HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(0, vaddr, size, MMU_VADDR_DATA | MMU_VADDR_INSTRUCTION));
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2023-07-07 09:35:29 +00:00
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#if CONFIG_IDF_TARGET_ESP32P4
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Cache_Invalidate_Addr(CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE, vaddr, size);
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#else
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cache_ll_invalidate_addr(vaddr, size);
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#endif
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2022-10-17 04:40:05 +00:00
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}
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2023-02-15 04:29:34 +00:00
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#if SOC_CACHE_WRITEBACK_SUPPORTED
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void cache_hal_writeback_addr(uint32_t vaddr, uint32_t size)
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{
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HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(0, vaddr, size, MMU_VADDR_DATA));
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2023-07-07 09:35:29 +00:00
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#if CONFIG_IDF_TARGET_ESP32P4
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Cache_WriteBack_Addr(CACHE_MAP_L1_DCACHE, vaddr, size);
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Cache_WriteBack_Addr(CACHE_MAP_L2_CACHE, vaddr, size);
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#else
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cache_ll_writeback_addr(vaddr, size);
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#endif
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}
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#endif //#if SOC_CACHE_WRITEBACK_SUPPORTED
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#if SOC_CACHE_FREEZE_SUPPORTED
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void cache_hal_freeze(cache_type_t type)
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{
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2023-08-07 07:20:00 +00:00
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#if SOC_CACHE_L2_SUPPORTED
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2023-07-07 09:35:29 +00:00
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Cache_Freeze_L2_Cache_Enable(CACHE_FREEZE_ACK_BUSY);
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#else
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2023-08-07 07:20:00 +00:00
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cache_ll_freeze_cache(type);
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#endif //SOC_CACHE_L2_SUPPORTED
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2023-02-15 04:29:34 +00:00
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}
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void cache_hal_unfreeze(cache_type_t type)
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{
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2023-08-07 07:20:00 +00:00
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#if SOC_CACHE_L2_SUPPORTED
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2023-07-07 09:35:29 +00:00
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Cache_Freeze_L2_Cache_Disable();
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#else
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2023-08-07 07:20:00 +00:00
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cache_ll_unfreeze_cache(type);
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#endif //SOC_CACHE_L2_SUPPORTED
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2023-02-15 04:29:34 +00:00
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}
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#endif //#if SOC_CACHE_FREEZE_SUPPORTED
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uint32_t cache_hal_get_cache_line_size(cache_type_t type)
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{
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2023-08-07 07:20:00 +00:00
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uint32_t line_size = 0;
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#if SOC_CACHE_L2_SUPPORTED
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line_size = Cache_Get_L2_Cache_Line_Size();
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2023-02-15 04:29:34 +00:00
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#else
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2023-08-07 07:20:00 +00:00
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line_size = cache_ll_get_line_size(type);
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#endif //SOC_CACHE_L2_SUPPORTED
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return line_size;
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2023-02-15 04:29:34 +00:00
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}
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