2020-12-15 09:20:22 +00:00
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// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
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2019-09-09 12:56:46 +00:00
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "hal/adc_hal.h"
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2020-09-10 02:37:58 +00:00
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#include "hal/adc_hal_conf.h"
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2020-12-15 09:20:22 +00:00
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#if CONFIG_IDF_TARGET_ESP32C3
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#include "soc/soc.h"
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#include "esp_rom_sys.h"
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2020-12-16 09:23:19 +00:00
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#endif
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2019-09-09 12:56:46 +00:00
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void adc_hal_init(void)
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{
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// Set internal FSM wait time, fixed value.
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2020-02-25 14:19:48 +00:00
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adc_ll_digi_set_fsm_time(SOC_ADC_FSM_RSTB_WAIT_DEFAULT, SOC_ADC_FSM_START_WAIT_DEFAULT,
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SOC_ADC_FSM_STANDBY_WAIT_DEFAULT);
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2020-04-08 13:56:14 +00:00
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adc_ll_set_sample_cycle(ADC_FSM_SAMPLE_CYCLE_DEFAULT);
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2020-02-25 14:19:48 +00:00
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adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
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2020-04-02 03:20:38 +00:00
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adc_ll_digi_output_invert(ADC_NUM_1, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_1));
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adc_ll_digi_output_invert(ADC_NUM_2, SOC_ADC_DIGI_DATA_INVERT_DEFAULT(ADC_NUM_2));
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2020-12-16 09:23:19 +00:00
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adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
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2019-09-09 12:56:46 +00:00
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}
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2020-02-25 14:19:48 +00:00
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void adc_hal_deinit(void)
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2019-09-09 12:56:46 +00:00
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{
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2020-02-25 14:19:48 +00:00
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adc_ll_set_power_manage(ADC_POWER_SW_OFF);
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2019-09-09 12:56:46 +00:00
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}
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2020-02-25 14:19:48 +00:00
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int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value)
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2019-09-09 12:56:46 +00:00
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{
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adc_ll_rtc_enable_channel(adc_n, channel);
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adc_ll_rtc_start_convert(adc_n, channel);
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while (adc_ll_rtc_convert_is_done(adc_n) != true);
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2020-02-25 14:19:48 +00:00
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*value = adc_ll_rtc_get_convert_value(adc_n);
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return (int)adc_ll_rtc_analysis_raw_data(adc_n, (uint16_t)(*value));
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2019-09-09 12:56:46 +00:00
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}
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2020-12-16 09:23:19 +00:00
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#if CONFIG_IDF_TARGET_ESP32C3
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//This feature is currently supported on ESP32C3, will be supported on other chips soon
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/*---------------------------------------------------------------
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DMA setting
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---------------------------------------------------------------*/
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void adc_hal_digi_dma_multi_descriptor(adc_dma_hal_config_t *dma_config, uint8_t *data_buf, uint32_t size, uint32_t num)
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{
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assert(((uint32_t)data_buf % 4) == 0);
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assert((size % 4) == 0);
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dma_descriptor_t *desc = dma_config->rx_desc;
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uint32_t n = 0;
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while (num--) {
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desc[n].dw0.size = size;
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desc[n].dw0.suc_eof = 0;
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desc[n].dw0.owner = 1;
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desc[n].buffer = data_buf;
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desc[n].next = &desc[n+1];
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data_buf += size;
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n++;
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}
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desc[n-1].next = NULL;
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}
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void adc_hal_digi_rxdma_start(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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gdma_ll_rx_reset_channel(adc_dma_ctx->dev, dma_config->dma_chan);
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gdma_ll_rx_set_desc_addr(adc_dma_ctx->dev, dma_config->dma_chan, (uint32_t)dma_config->rx_desc);
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gdma_ll_rx_start(adc_dma_ctx->dev, dma_config->dma_chan);
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}
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void adc_hal_digi_rxdma_stop(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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gdma_ll_rx_stop(adc_dma_ctx->dev, dma_config->dma_chan);
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}
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void adc_hal_digi_ena_intr(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t mask)
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{
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gdma_ll_enable_interrupt(adc_dma_ctx->dev, dma_config->dma_chan, mask, true);
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}
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void adc_hal_digi_clr_intr(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t mask)
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{
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gdma_ll_clear_interrupt_status(adc_dma_ctx->dev, dma_config->dma_chan, mask);
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}
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void adc_hal_digi_dis_intr(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t mask)
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{
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gdma_ll_enable_interrupt(adc_dma_ctx->dev, dma_config->dma_chan, mask, false);
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}
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void adc_hal_digi_set_eof_num(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config, uint32_t num)
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{
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adc_ll_digi_dma_set_eof_num(num);
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}
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void adc_hal_digi_start(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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//Set to 1: the ADC data will be sent to the DMA
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adc_ll_digi_dma_enable();
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//enable sar adc timer
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adc_ll_digi_trigger_enable();
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}
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void adc_hal_digi_stop(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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//Set to 0: the ADC data won't be sent to the DMA
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adc_ll_digi_dma_disable();
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//disable sar adc timer
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adc_ll_digi_trigger_disable();
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}
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void adc_hal_digi_init(adc_dma_hal_context_t *adc_dma_ctx, adc_dma_hal_config_t *dma_config)
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{
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adc_dma_ctx->dev = &GDMA;
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gdma_ll_enable_clock(adc_dma_ctx->dev, true);
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gdma_ll_clear_interrupt_status(adc_dma_ctx->dev, dma_config->dma_chan, UINT32_MAX);
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2020-12-09 12:29:26 +00:00
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gdma_ll_rx_connect_to_periph(adc_dma_ctx->dev, dma_config->dma_chan, SOC_GDMA_TRIG_PERIPH_ADC0);
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2020-12-16 09:23:19 +00:00
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}
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2020-12-15 09:20:22 +00:00
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/*---------------------------------------------------------------
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Single Read
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---------------------------------------------------------------*/
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void adc_hal_onetime_start(adc_digi_config_t *adc_digi_config)
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{
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/**
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* There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the
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* ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller
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* clock cycle.
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*
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* This limitation will be removed in hardware future versions.
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*
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*/
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uint32_t digi_clk = APB_CLK_FREQ / (adc_digi_config->dig_clk.div_num + adc_digi_config->dig_clk.div_a / adc_digi_config->dig_clk.div_b + 1);
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//Convert frequency to time (us). Since decimals are removed by this division operation. Add 1 here in case of the fact that delay is not enough.
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uint32_t delay = (1000 * 1000) / digi_clk + 1;
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//3 ADC digital controller clock cycle
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delay = delay * 3;
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//This coefficient (8) is got from test. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
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if (digi_clk >= APB_CLK_FREQ/8) {
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delay = 0;
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}
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adc_ll_onetime_start(false);
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esp_rom_delay_us(delay);
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adc_ll_onetime_start(true);
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//No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
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}
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void adc_hal_adc1_onetime_sample_enable(bool enable)
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{
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if (enable) {
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adc_ll_adc1_onetime_sample_ena();
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} else {
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adc_ll_adc1_onetime_sample_dis();
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}
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}
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void adc_hal_adc2_onetime_sample_enable(bool enable)
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{
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if (enable) {
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adc_ll_adc2_onetime_sample_ena();
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} else {
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adc_ll_adc2_onetime_sample_dis();
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}
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}
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void adc_hal_onetime_channel(adc_ll_num_t unit, adc_channel_t channel)
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{
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adc_ll_onetime_set_channel(unit, channel);
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}
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void adc_hal_set_onetime_atten(adc_atten_t atten)
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{
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adc_ll_onetime_set_atten(atten);
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}
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uint32_t adc_hal_adc1_read(void)
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{
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return adc_ll_adc1_read();
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}
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uint32_t adc_hal_adc2_read(void)
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{
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return adc_ll_adc2_read();
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}
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//--------------------INTR-------------------------------
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static adc_ll_intr_t get_event_intr(adc_event_t event)
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{
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adc_ll_intr_t intr_mask = 0;
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if (event & ADC_EVENT_ADC1_DONE) {
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intr_mask |= ADC_LL_INTR_ADC1_DONE;
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}
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if (event & ADC_EVENT_ADC2_DONE) {
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intr_mask |= ADC_LL_INTR_ADC2_DONE;
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}
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return intr_mask;
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}
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void adc_hal_intr_enable(adc_event_t event)
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{
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adc_ll_intr_enable(get_event_intr(event));
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}
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void adc_hal_intr_disable(adc_event_t event)
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{
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adc_ll_intr_disable(get_event_intr(event));
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}
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void adc_hal_intr_clear(adc_event_t event)
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{
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adc_ll_intr_clear(get_event_intr(event));
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}
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bool adc_hal_intr_get_raw(adc_event_t event)
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{
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return adc_ll_intr_get_raw(get_event_intr(event));
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}
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bool adc_hal_intr_get_status(adc_event_t event)
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{
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return adc_ll_intr_get_status(get_event_intr(event));
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}
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2020-12-16 09:23:19 +00:00
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#endif
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