2019-04-18 14:13:05 +00:00
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#include "hal/spi_slave_hal.h"
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#include "hal/spi_ll.h"
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2020-09-23 13:01:13 +00:00
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#include "soc/soc_caps.h"
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2020-09-08 09:05:49 +00:00
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//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros.
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2020-09-23 13:01:13 +00:00
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#if SOC_GDMA_SUPPORTED
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#include "soc/gdma_struct.h"
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#include "hal/gdma_ll.h"
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#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL)
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#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);
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#define spi_dma_ll_rx_start(dev, addr) do {\
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gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#define spi_dma_ll_tx_start(dev, addr) do {\
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gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\
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gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\
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} while (0)
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#endif
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2019-04-18 14:13:05 +00:00
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bool spi_slave_hal_usr_is_done(spi_slave_hal_context_t* hal)
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{
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return spi_ll_usr_is_done(hal->hw);
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}
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void spi_slave_hal_user_start(const spi_slave_hal_context_t *hal)
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{
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spi_ll_clear_int_stat(hal->hw); //clear int bit
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2020-09-08 09:05:49 +00:00
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spi_ll_slave_user_start(hal->hw);
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2019-04-18 14:13:05 +00:00
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}
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void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal)
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{
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if (hal->use_dma) {
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2020-09-14 09:33:10 +00:00
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spi_ll_dma_fifo_reset(hal->hw);
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2019-04-18 14:13:05 +00:00
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//Fill DMA descriptors
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2020-09-14 09:33:10 +00:00
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if (hal->rx_buffer) {
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2019-04-18 14:13:05 +00:00
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lldesc_setup_link(hal->dmadesc_rx, hal->rx_buffer, ((hal->bitlen + 7) / 8), true);
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2020-09-14 09:33:10 +00:00
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//reset dma inlink, this should be reset before spi related reset
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spi_dma_ll_rx_reset(hal->dma_in);
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spi_ll_slave_reset(hal->hw);
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spi_ll_infifo_full_clr(hal->hw);
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spi_ll_dma_rx_enable(hal->hw, 1);
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spi_dma_ll_rx_start(hal->dma_in, &hal->dmadesc_rx[0]);
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2019-04-18 14:13:05 +00:00
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}
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if (hal->tx_buffer) {
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lldesc_setup_link(hal->dmadesc_tx, hal->tx_buffer, (hal->bitlen + 7) / 8, false);
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2020-09-14 09:33:10 +00:00
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//reset dma outlink, this should be reset before spi related reset
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spi_dma_ll_tx_reset(hal->dma_out);
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spi_ll_slave_reset(hal->hw);
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spi_ll_outfifo_empty_clr(hal->hw);
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spi_ll_dma_tx_enable(hal->hw, 1);
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spi_dma_ll_tx_start(hal->dma_out, (&hal->dmadesc_tx[0]));
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2019-04-18 14:13:05 +00:00
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}
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} else {
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//No DMA. Turn off SPI and copy data to transmit buffers.
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if (hal->tx_buffer) {
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2020-09-14 09:33:10 +00:00
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spi_ll_slave_reset(hal->hw);
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2019-04-18 14:13:05 +00:00
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spi_ll_write_buffer(hal->hw, hal->tx_buffer, hal->bitlen);
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}
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2020-09-08 09:05:49 +00:00
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spi_ll_cpu_fifo_reset(hal->hw);
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2019-04-18 14:13:05 +00:00
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}
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2020-09-14 09:33:10 +00:00
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2019-04-18 14:13:05 +00:00
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spi_ll_slave_set_rx_bitlen(hal->hw, hal->bitlen);
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spi_ll_slave_set_tx_bitlen(hal->hw, hal->bitlen);
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2020-09-14 09:33:10 +00:00
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2019-04-18 14:13:05 +00:00
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spi_ll_enable_mosi(hal->hw, (hal->tx_buffer == NULL) ? 0 : 1);
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spi_ll_enable_miso(hal->hw, (hal->rx_buffer == NULL) ? 0 : 1);
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}
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void spi_slave_hal_store_result(spi_slave_hal_context_t *hal)
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{
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//when data of cur_trans->length are all sent, the slv_rdata_bit
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//will be the length sent-1 (i.e. cur_trans->length-1 ), otherwise
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//the length sent.
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hal->rcv_bitlen = spi_ll_slave_get_rcv_bitlen(hal->hw);
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if (hal->rcv_bitlen == hal->bitlen - 1) {
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hal->rcv_bitlen++;
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}
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if (!hal->use_dma && hal->rx_buffer) {
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//Copy result out
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spi_ll_read_buffer(hal->hw, hal->rx_buffer, hal->bitlen);
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}
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}
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uint32_t spi_slave_hal_get_rcv_bitlen(spi_slave_hal_context_t *hal)
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{
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return hal->rcv_bitlen;
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}
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bool spi_slave_hal_dma_need_reset(const spi_slave_hal_context_t *hal)
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{
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bool ret;
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ret = false;
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if (hal->use_dma && hal->rx_buffer) {
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int i;
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//In case CS goes high too soon, the transfer is aborted while the DMA channel still thinks it's going. This
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//leads to issues later on, so in that case we need to reset the channel. The state can be detected because
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//the DMA system doesn't give back the offending descriptor; the owner is still set to DMA.
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for (i = 0; hal->dmadesc_rx[i].eof == 0 && hal->dmadesc_rx[i].owner == 0; i++) {}
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if (hal->dmadesc_rx[i].owner) {
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ret = true;
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}
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}
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return ret;
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2020-09-08 09:05:49 +00:00
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}
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