2019-10-30 03:19:22 +00:00
|
|
|
// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
|
|
|
|
//
|
|
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
|
|
// you may not use this file except in compliance with the License.
|
|
|
|
// You may obtain a copy of the License at
|
|
|
|
//
|
|
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
//
|
|
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
|
|
// See the License for the specific language governing permissions and
|
|
|
|
// limitations under the License.
|
|
|
|
|
|
|
|
#include <string.h>
|
2019-12-26 07:25:24 +00:00
|
|
|
#include "sdkconfig.h"
|
2019-10-30 03:19:22 +00:00
|
|
|
#include "esp_system.h"
|
|
|
|
#include "esp_private/system_internal.h"
|
|
|
|
#include "esp_attr.h"
|
|
|
|
#include "esp_wifi.h"
|
|
|
|
#include "esp_log.h"
|
2020-01-17 03:47:08 +00:00
|
|
|
#include "esp32s2/rom/cache.h"
|
2020-07-13 13:33:23 +00:00
|
|
|
#include "esp_rom_uart.h"
|
2019-10-30 03:19:22 +00:00
|
|
|
#include "soc/dport_reg.h"
|
|
|
|
#include "soc/gpio_reg.h"
|
|
|
|
#include "soc/rtc_cntl_reg.h"
|
|
|
|
#include "soc/timer_group_reg.h"
|
|
|
|
#include "soc/cpu.h"
|
|
|
|
#include "soc/rtc.h"
|
|
|
|
#include "soc/syscon_reg.h"
|
2019-12-26 08:30:03 +00:00
|
|
|
#include "hal/wdt_hal.h"
|
2019-10-30 03:19:22 +00:00
|
|
|
#include "freertos/xtensa_api.h"
|
|
|
|
|
|
|
|
/* "inner" restart function for after RTOS, interrupts & anything else on this
|
|
|
|
* core are already stopped. Stalls other core, resets hardware,
|
|
|
|
* triggers restart.
|
|
|
|
*/
|
|
|
|
void IRAM_ATTR esp_restart_noos(void)
|
|
|
|
{
|
|
|
|
// Disable interrupts
|
|
|
|
xt_ints_off(0xFFFFFFFF);
|
|
|
|
|
|
|
|
// Enable RTC watchdog for 1 second
|
2019-12-26 08:30:03 +00:00
|
|
|
wdt_hal_context_t rtc_wdt_ctx;
|
|
|
|
wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
|
|
|
|
uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
|
|
|
|
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
|
|
|
|
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
|
|
|
|
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
|
|
|
|
//Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
|
|
|
|
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
|
|
|
|
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
|
2019-10-30 03:19:22 +00:00
|
|
|
|
|
|
|
// Reset and stall the other CPU.
|
|
|
|
// CPU must be reset before stalling, in case it was running a s32c1i
|
|
|
|
// instruction. This would cause memory pool to be locked by arbiter
|
|
|
|
// to the stalled CPU, preventing current CPU from accessing this pool.
|
|
|
|
const uint32_t core_id = xPortGetCoreID();
|
2019-12-26 08:30:03 +00:00
|
|
|
|
|
|
|
//Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
|
2019-10-30 03:19:22 +00:00
|
|
|
// Disable TG0/TG1 watchdogs
|
2019-12-26 08:30:03 +00:00
|
|
|
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
|
|
|
|
wdt_hal_write_protect_disable(&wdt0_context);
|
|
|
|
wdt_hal_disable(&wdt0_context);
|
|
|
|
wdt_hal_write_protect_enable(&wdt0_context);
|
|
|
|
|
|
|
|
wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
|
|
|
|
wdt_hal_write_protect_disable(&wdt1_context);
|
|
|
|
wdt_hal_disable(&wdt1_context);
|
|
|
|
wdt_hal_write_protect_enable(&wdt1_context);
|
2019-10-30 03:19:22 +00:00
|
|
|
|
|
|
|
// Flush any data left in UART FIFOs
|
2020-07-13 13:33:23 +00:00
|
|
|
esp_rom_uart_tx_wait_idle(0);
|
|
|
|
esp_rom_uart_tx_wait_idle(1);
|
2019-10-30 03:19:22 +00:00
|
|
|
// Disable cache
|
|
|
|
Cache_Disable_ICache();
|
|
|
|
Cache_Disable_DCache();
|
|
|
|
|
|
|
|
// 2nd stage bootloader reconfigures SPI flash signals.
|
|
|
|
// Reset them to the defaults expected by ROM.
|
|
|
|
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
|
|
|
|
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
|
|
|
|
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
|
|
|
|
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
|
|
|
|
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
|
|
|
|
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
|
|
|
|
|
|
|
|
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
|
2019-12-26 07:25:24 +00:00
|
|
|
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
|
|
|
|
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
|
|
|
|
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
|
|
|
|
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
|
2019-10-30 03:19:22 +00:00
|
|
|
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
|
|
|
|
|
|
|
|
// Reset timer/spi/uart
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
|
2020-07-29 05:27:53 +00:00
|
|
|
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST);
|
2019-10-30 03:19:22 +00:00
|
|
|
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
|
|
|
|
|
|
|
|
// Set CPU back to XTAL source, no PLL, same as hard reset
|
2020-02-12 12:56:59 +00:00
|
|
|
rtc_clk_cpu_freq_set_xtal();
|
2019-10-30 03:19:22 +00:00
|
|
|
|
|
|
|
// Reset CPUs
|
|
|
|
if (core_id == 0) {
|
|
|
|
esp_cpu_reset(0);
|
|
|
|
}
|
2019-12-26 07:25:24 +00:00
|
|
|
while (true) {
|
2019-10-30 03:19:22 +00:00
|
|
|
;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-12-26 07:25:24 +00:00
|
|
|
void esp_chip_info(esp_chip_info_t *out_info)
|
2019-10-30 03:19:22 +00:00
|
|
|
{
|
|
|
|
memset(out_info, 0, sizeof(*out_info));
|
|
|
|
|
2020-01-17 03:47:08 +00:00
|
|
|
out_info->model = CHIP_ESP32S2;
|
2019-10-30 03:19:22 +00:00
|
|
|
out_info->cores = 1;
|
|
|
|
out_info->features = CHIP_FEATURE_WIFI_BGN;
|
|
|
|
}
|