kopia lustrzana https://github.com/espressif/esp-idf
406 wiersze
17 KiB
C
406 wiersze
17 KiB
C
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// #define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
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#include <stdlib.h>
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#include <string.h>
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#include <sys/lock.h>
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#include "sdkconfig.h"
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#include "esp_compiler.h"
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#include "esp_heap_caps.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "soc/soc_caps.h"
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#include "soc/gpio_periph.h"
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#include "soc/io_mux_reg.h"
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#include "hal/cpu_hal.h"
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#include "hal/cpu_ll.h"
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#include "driver/periph_ctrl.h"
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#include "esp_rom_gpio.h"
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#include "freertos/FreeRTOS.h"
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#if SOC_DEDICATED_GPIO_SUPPORTED
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#include "driver/dedic_gpio.h"
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#include "soc/dedic_gpio_periph.h"
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#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
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#include "soc/dedic_gpio_struct.h"
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#include "hal/dedic_gpio_ll.h"
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#endif
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static const char *TAG = "dedic_gpio";
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#define DEDIC_CHECK(a, msg, tag, ret, ...) \
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do { \
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if (unlikely(!(a))) { \
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ESP_LOGE(TAG, "%s(%d): " msg, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
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ret_code = ret; \
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goto tag; \
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} \
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} while (0)
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typedef struct dedic_gpio_platform_t dedic_gpio_platform_t;
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typedef struct dedic_gpio_bundle_t dedic_gpio_bundle_t;
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// Dedicated GPIO driver platform, GPIO bundles will be installed onto it
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static dedic_gpio_platform_t *s_platform[SOC_CPU_CORES_NUM];
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// platform level mutex lock
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static _lock_t s_platform_mutexlock[SOC_CPU_CORES_NUM];
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struct dedic_gpio_platform_t {
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portMUX_TYPE spinlock; // Spinlock, stop GPIO channels from accessing common resource concurrently
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uint32_t out_occupied_mask; // mask of output channels that already occupied
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uint32_t in_occupied_mask; // mask of input channels that already occupied
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#if SOC_DEDIC_GPIO_HAS_INTERRUPT
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intr_handle_t intr_hdl; // interrupt handle
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dedic_gpio_isr_callback_t cbs[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; // array of callback function for input channel
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void *cb_args[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; // array of callback arguments for input channel
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dedic_gpio_bundle_t *in_bundles[SOC_DEDIC_GPIO_IN_CHANNELS_NUM]; // which bundle belongs to for input channel
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#endif
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#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
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dedic_dev_t *dev;
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#endif
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};
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struct dedic_gpio_bundle_t {
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uint32_t core_id; // CPU core ID, a GPIO bundle must be installed to a specific CPU core
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uint32_t out_mask; // mask of output channels in the bank
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uint32_t in_mask; // mask of input channels in the bank
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uint32_t out_offset; // offset in the bank (seen from output channel)
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uint32_t in_offset; // offset in the bank (seen from input channel)
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size_t nr_gpio; // number of GPIOs in the gpio_array
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int gpio_array[0]; // array of GPIO numbers (configured by user)
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};
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static esp_err_t dedic_gpio_build_platform(uint32_t core_id)
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{
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esp_err_t ret_code = ESP_OK;
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if (!s_platform[core_id]) {
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// prevent building platform concurrently
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_lock_acquire(&s_platform_mutexlock[core_id]);
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if (!s_platform[core_id]) {
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s_platform[core_id] = calloc(1, sizeof(dedic_gpio_platform_t));
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if (s_platform[core_id]) {
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// initialize platfrom members
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s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
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s_platform[core_id]->dev = &DEDIC_GPIO;
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#endif
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periph_module_enable(dedic_gpio_periph_signals.module); // enable APB clock to peripheral
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}
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}
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_lock_release(&s_platform_mutexlock[core_id]);
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DEDIC_CHECK(s_platform[core_id], "no mem for s_platform[%d]", err, ESP_ERR_NO_MEM, core_id);
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ESP_LOGD(TAG, "build platform on core[%d] at %p", core_id, s_platform);
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}
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err:
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return ret_code;
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}
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static void dedic_gpio_break_platform(uint32_t core_id)
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{
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if (s_platform[core_id]) {
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// prevent breaking platform concurrently
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_lock_acquire(&s_platform_mutexlock[core_id]);
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if (s_platform[core_id]) {
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free(s_platform[core_id]);
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s_platform[core_id] = NULL;
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periph_module_disable(dedic_gpio_periph_signals.module); // disable module if no GPIO channel is being used
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}
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_lock_release(&s_platform_mutexlock[core_id]);
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}
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}
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#if SOC_DEDIC_GPIO_HAS_INTERRUPT
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static void dedic_gpio_default_isr(void *arg)
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{
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bool need_yield = false;
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dedic_gpio_platform_t *platform = (dedic_gpio_platform_t *)arg;
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// get and clear interrupt status
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portENTER_CRITICAL_ISR(&platform->spinlock);
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uint32_t status = dedic_gpio_ll_get_interrupt_status(platform->dev);
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dedic_gpio_ll_clear_interrupt_status(platform->dev, status);
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portEXIT_CRITICAL_ISR(&platform->spinlock);
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// handle dedicated channel one by one
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while (status) {
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uint32_t channel = __builtin_ffs(status) - 1; // get dedicated channel number which triggered the interrupt
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if (platform->cbs[channel]) {
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if (platform->cbs[channel](platform->in_bundles[channel], channel - platform->in_bundles[channel]->in_offset, platform->cb_args[channel])) {
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need_yield = true; // note that we need to yield at the end of isr
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}
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}
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status = status & (status - 1); // clear the right most bit '1'
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}
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if (need_yield) {
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portYIELD_FROM_ISR();
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}
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}
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static esp_err_t dedic_gpio_install_interrupt(uint32_t core_id)
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{
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esp_err_t ret_code = ESP_OK;
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if (!s_platform[core_id]->intr_hdl) {
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// prevent install interrupt concurrently
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_lock_acquire(&s_platform_mutexlock[core_id]);
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if (!s_platform[core_id]->intr_hdl) {
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int isr_flags = 0;
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ret_code = esp_intr_alloc(dedic_gpio_periph_signals.irq, isr_flags, dedic_gpio_default_isr, s_platform[core_id], &s_platform[core_id]->intr_hdl);
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// clear pending interrupt
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uint32_t status = dedic_gpio_ll_get_interrupt_status(s_platform[core_id]->dev);
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dedic_gpio_ll_clear_interrupt_status(s_platform[core_id]->dev, status);
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}
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_lock_release(&s_platform_mutexlock[core_id]);
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DEDIC_CHECK(ret_code == ESP_OK, "alloc interrupt failed", err, ret_code);
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}
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err:
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return ret_code;
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}
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static void dedic_gpio_uninstall_interrupt(uint32_t core_id)
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{
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if (s_platform[core_id]->intr_hdl) {
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// prevent uninstall interrupt concurrently
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_lock_acquire(&s_platform_mutexlock[core_id]);
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if (s_platform[core_id]->intr_hdl) {
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esp_intr_free(s_platform[core_id]->intr_hdl);
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s_platform[core_id]->intr_hdl = NULL;
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// disable all interrupt
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dedic_gpio_ll_enable_interrupt(s_platform[core_id]->dev, ~0UL, false);
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}
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_lock_release(&s_platform_mutexlock[core_id]);
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}
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}
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static void dedic_gpio_set_interrupt(uint32_t core_id, uint32_t channel, dedic_gpio_intr_type_t type)
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{
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dedic_gpio_ll_set_interrupt_type(s_platform[core_id]->dev, channel, type);
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if (type != DEDIC_GPIO_INTR_NONE) {
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dedic_gpio_ll_enable_interrupt(s_platform[core_id]->dev, 1 << channel, true);
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} else {
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dedic_gpio_ll_enable_interrupt(s_platform[core_id]->dev, 1 << channel, false);
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}
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}
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#endif // SOC_DEDIC_GPIO_HAS_INTERRUPT
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esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_gpio_bundle_handle_t *ret_bundle)
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{
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esp_err_t ret_code = ESP_OK;
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dedic_gpio_bundle_t *bundle = NULL;
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uint32_t out_mask = 0;
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uint32_t in_mask = 0;
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uint32_t core_id = cpu_hal_get_core_id(); // dedicated GPIO will be binded to the CPU who invokes this API
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DEDIC_CHECK(config && ret_bundle, "invalid argument", err, ESP_ERR_INVALID_ARG);
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DEDIC_CHECK(config->gpio_array && config->array_size > 0, "invalid GPIO array or size", err, ESP_ERR_INVALID_ARG);
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DEDIC_CHECK(config->flags.in_en || config->flags.out_en, "no input/output mode specified", err, ESP_ERR_INVALID_ARG);
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// lazy install s_platform[core_id]
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DEDIC_CHECK(dedic_gpio_build_platform(core_id) == ESP_OK, "build platform %d failed", err, ESP_FAIL, core_id);
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size_t bundle_size = sizeof(dedic_gpio_bundle_t) + config->array_size * sizeof(config->gpio_array[0]);
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bundle = calloc(1, bundle_size);
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DEDIC_CHECK(bundle, "no mem for bundle", err, ESP_ERR_NO_MEM);
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// for performance reasons, we only search for continuous channels
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uint32_t pattern = (1 << config->array_size) - 1;
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// configure outwards channels
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uint32_t out_offset = 0;
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if (config->flags.out_en) {
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DEDIC_CHECK(SOC_DEDIC_GPIO_OUT_CHANNELS_NUM >= config->array_size, "array size(%d) exceeds maximum supported out channels(%d)",
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err, ESP_ERR_INVALID_ARG, config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM);
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// prevent install bundle concurrently
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portENTER_CRITICAL(&s_platform[core_id]->spinlock);
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for (size_t i = 0; i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size; i++) {
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if ((s_platform[core_id]->out_occupied_mask & (pattern << i)) == 0) {
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out_mask = pattern << i;
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out_offset = i;
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break;
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}
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}
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if (out_mask) {
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s_platform[core_id]->out_occupied_mask |= out_mask;
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#if SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
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// always enable instruction to access output GPIO, which has better performance than register access
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dedic_gpio_ll_enable_instruction_access_out(s_platform[core_id]->dev, out_mask, true);
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#endif
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}
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portEXIT_CRITICAL(&s_platform[core_id]->spinlock);
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DEDIC_CHECK(out_mask, "no free outward channels on core[%d]", err, ESP_ERR_NOT_FOUND, core_id);
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ESP_LOGD(TAG, "new outward bundle(%p) on core[%d], offset=%d, mask(%x)", bundle, core_id, out_offset, out_mask);
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}
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// configure inwards channels
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uint32_t in_offset = 0;
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if (config->flags.in_en) {
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DEDIC_CHECK(SOC_DEDIC_GPIO_IN_CHANNELS_NUM >= config->array_size, "array size(%d) exceeds maximum supported in channels(%d)",
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err, ESP_ERR_INVALID_ARG, config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM);
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// prevent install bundle concurrently
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portENTER_CRITICAL(&s_platform[core_id]->spinlock);
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for (size_t i = 0; i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size; i++) {
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if ((s_platform[core_id]->in_occupied_mask & (pattern << i)) == 0) {
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in_mask = pattern << i;
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in_offset = i;
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break;
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}
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}
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if (in_mask) {
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s_platform[core_id]->in_occupied_mask |= in_mask;
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}
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portEXIT_CRITICAL(&s_platform[core_id]->spinlock);
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DEDIC_CHECK(in_mask, "no free inward channels on core[%d]", err, ESP_ERR_NOT_FOUND, core_id);
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ESP_LOGD(TAG, "new inward bundle(%p) on core[%d], offset=%d, mask(%x)", bundle, core_id, in_offset, in_mask);
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}
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// route dedicated GPIO channel signals to GPIO matrix
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if (config->flags.in_en) {
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for (size_t i = 0; i < config->array_size; i++) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO);
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esp_rom_gpio_connect_in_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].in_sig_per_channel[in_offset + i], config->flags.in_invert);
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}
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}
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if (config->flags.out_en) {
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for (size_t i = 0; i < config->array_size; i++) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[config->gpio_array[i]], PIN_FUNC_GPIO);
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esp_rom_gpio_connect_out_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].out_sig_per_channel[out_offset + i], config->flags.out_invert, false);
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}
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}
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// it's safe to initialize bundle members without locks here
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bundle->core_id = core_id;
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bundle->out_mask = out_mask;
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bundle->in_mask = in_mask;
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bundle->out_offset = out_offset;
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bundle->in_offset = in_offset;
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bundle->nr_gpio = config->array_size;
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memcpy(bundle->gpio_array, config->gpio_array, config->array_size * sizeof(config->gpio_array[0]));
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*ret_bundle = bundle; // return bundle instance
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return ESP_OK;
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err:
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if (s_platform[core_id] && (out_mask || in_mask)) {
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portENTER_CRITICAL(&s_platform[core_id]->spinlock);
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s_platform[core_id]->out_occupied_mask &= ~out_mask;
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s_platform[core_id]->in_occupied_mask &= ~in_mask;
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portEXIT_CRITICAL(&s_platform[core_id]->spinlock);
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}
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if (bundle) {
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free(bundle);
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}
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return ret_code;
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}
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esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
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{
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esp_err_t ret_code = ESP_OK;
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bool recycle_all = false;
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DEDIC_CHECK(bundle, "invalid argument", err, ESP_ERR_INVALID_ARG);
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uint32_t core_id = cpu_hal_get_core_id();
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DEDIC_CHECK(core_id == bundle->core_id, "del bundle on wrong CPU", err, ESP_FAIL);
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portENTER_CRITICAL(&s_platform[core_id]->spinlock);
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s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask);
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s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask);
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if (!s_platform[core_id]->in_occupied_mask && !s_platform[core_id]->out_occupied_mask) {
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recycle_all = true;
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}
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portEXIT_CRITICAL(&s_platform[core_id]->spinlock);
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free(bundle);
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if (recycle_all) {
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#if SOC_DEDIC_GPIO_HAS_INTERRUPT
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dedic_gpio_uninstall_interrupt(core_id);
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#endif
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dedic_gpio_break_platform(core_id);
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}
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err:
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return ret_code;
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}
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esp_err_t dedic_gpio_get_out_mask(dedic_gpio_bundle_handle_t bundle, uint32_t *mask)
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{
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esp_err_t ret_code = ESP_OK;
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DEDIC_CHECK(bundle && mask, "invalid argument", err, ESP_ERR_INVALID_ARG);
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*mask = bundle->out_mask;
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err:
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return ret_code;
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}
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esp_err_t dedic_gpio_get_in_mask(dedic_gpio_bundle_handle_t bundle, uint32_t *mask)
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{
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esp_err_t ret_code = ESP_OK;
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DEDIC_CHECK(bundle && mask, "invalid argument", err, ESP_ERR_INVALID_ARG);
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*mask = bundle->in_mask;
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err:
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return ret_code;
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}
|
||
|
|
||
|
void dedic_gpio_bundle_write(dedic_gpio_bundle_handle_t bundle, uint32_t mask, uint32_t value)
|
||
|
{
|
||
|
// For performace reasons, we don't want to check the validation of parameters here
|
||
|
// Even didn't check if we're working on the correct CPU core (i.e. bundle->core_id == current core_id)
|
||
|
cpu_ll_write_dedic_gpio_mask(bundle->out_mask & (mask << bundle->out_offset), value << bundle->out_offset);
|
||
|
}
|
||
|
|
||
|
uint32_t dedic_gpio_bundle_read_out(dedic_gpio_bundle_handle_t bundle)
|
||
|
{
|
||
|
// For performace reasons, we don't want to check the validation of parameters here
|
||
|
// Even didn't check if we're working on the correct CPU core (i.e. bundle->core_id == current core_id)
|
||
|
uint32_t value = cpu_ll_read_dedic_gpio_out();
|
||
|
return (value & bundle->out_mask) >> (bundle->out_offset);
|
||
|
}
|
||
|
|
||
|
uint32_t dedic_gpio_bundle_read_in(dedic_gpio_bundle_handle_t bundle)
|
||
|
{
|
||
|
// For performace reasons, we don't want to check the validation of parameters here
|
||
|
// Even didn't check if we're working on the correct CPU core (i.e. bundle->core_id == current core_id)
|
||
|
uint32_t value = cpu_ll_read_dedic_gpio_in();
|
||
|
return (value & bundle->in_mask) >> (bundle->in_offset);
|
||
|
}
|
||
|
|
||
|
#if SOC_DEDIC_GPIO_HAS_INTERRUPT
|
||
|
esp_err_t dedic_gpio_bundle_set_interrupt_and_callback(dedic_gpio_bundle_handle_t bundle, uint32_t mask, dedic_gpio_intr_type_t intr_type, dedic_gpio_isr_callback_t cb_isr, void *cb_args)
|
||
|
{
|
||
|
esp_err_t ret_code = ESP_OK;
|
||
|
DEDIC_CHECK(bundle, "invalid argument", err, ESP_ERR_INVALID_ARG);
|
||
|
uint32_t core_id = cpu_hal_get_core_id();
|
||
|
// lazy alloc interrupt
|
||
|
DEDIC_CHECK(dedic_gpio_install_interrupt(core_id) == ESP_OK, "allocate interrupt on core %d failed", err, ESP_FAIL, core_id);
|
||
|
|
||
|
uint32_t channel_mask = bundle->in_mask & (mask << bundle->in_offset);
|
||
|
uint32_t channel = 0;
|
||
|
while (channel_mask) {
|
||
|
channel = __builtin_ffs(channel_mask) - 1;
|
||
|
portENTER_CRITICAL(&s_platform[core_id]->spinlock);
|
||
|
dedic_gpio_set_interrupt(core_id, channel, intr_type);
|
||
|
portEXIT_CRITICAL(&s_platform[core_id]->spinlock);
|
||
|
|
||
|
s_platform[core_id]->cbs[channel] = cb_isr;
|
||
|
s_platform[core_id]->cb_args[channel] = cb_args;
|
||
|
s_platform[core_id]->in_bundles[channel] = bundle;
|
||
|
channel_mask = channel_mask & (channel_mask - 1); // clear the right most bit '1'
|
||
|
}
|
||
|
|
||
|
err:
|
||
|
return ret_code;
|
||
|
}
|
||
|
#endif // SOC_DEDIC_GPIO_HAS_INTERRUPT
|
||
|
#endif // SOC_DEDICATED_GPIO_SUPPORTED
|