2021-05-24 07:08:00 +00:00
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.. This file gets included from other .rst files in this folder.
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.. It contains target-specific snippets.
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.. Comments and '---' lines act as delimiters.
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..
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.. This is necessary mainly because RST doesn't support substitutions
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.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
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.. These code blocks can be moved back to the main .rst files, with target-specific
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.. file names being replaced by substitutions.
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.. run-openocd
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::
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2021-10-11 19:15:31 +00:00
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openocd -f board/esp32s3-builtin.cfg
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2021-05-24 07:08:00 +00:00
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.. |run-openocd-device-name| replace:: ESP32-S3
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---
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.. run-openocd-output
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::
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2021-10-11 19:15:31 +00:00
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user-name@computer-name:~/esp/esp-idf$ openocd -f board/esp32s3-builtin.cfg
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Open On-Chip Debugger v0.10.0-esp32-20210902 (2021-10-05-23:44)
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2021-05-24 07:08:00 +00:00
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Licensed under GNU GPL v2
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For bug reports, read
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2022-04-28 06:34:20 +00:00
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https://openocd.org/doc/doxygen/bugs.html
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2021-10-11 19:15:31 +00:00
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debug_level: 2
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Info : only one transport option; autoselect 'jtag'
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Warn : Transport "jtag" was already selected
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Info : Listening on port 6666 for tcl connections
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Info : Listening on port 4444 for telnet connections
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Info : esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255
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Info : clock speed 40000 kHz
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2021-05-24 07:08:00 +00:00
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Info : JTAG tap: esp32s3.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
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2021-10-11 19:15:31 +00:00
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Info : JTAG tap: esp32s3.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
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Info : esp32s3.cpu0: Debug controller was reset.
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Info : esp32s3.cpu0: Core was reset.
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Info : esp32s3.cpu1: Debug controller was reset.
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Info : esp32s3.cpu1: Core was reset.
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Info : Listening on port 3333 for gdb connections
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2021-05-24 07:08:00 +00:00
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2021-10-11 19:15:31 +00:00
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.. |run-openocd-cfg-file-err| replace:: ``Can't find board/esp32s3-builtin.cfg``
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2021-05-24 07:08:00 +00:00
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---
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.. run-openocd-upload
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::
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2021-10-11 19:15:31 +00:00
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openocd -f board/esp32s3-builtin.cfg -c "program_esp filename.bin 0x10000 verify exit"
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2021-05-24 07:08:00 +00:00
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---
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.. run-openocd-src-linux
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.. code-block:: bash
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2021-10-11 19:15:31 +00:00
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src/openocd -f board/esp32s3-builtin.cfg
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2021-05-24 07:08:00 +00:00
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---
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.. run-openocd-src-win
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.. code-block:: batch
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2021-10-11 19:15:31 +00:00
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src\openocd -f board/esp32s3-builtin.cfg
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2021-05-24 07:08:00 +00:00
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---
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.. idf-py-openocd-default-cfg
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2021-10-11 19:15:31 +00:00
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.. |idf-py-def-cfg| replace:: ``-f board/esp32s3-builtin.cfg``
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2021-05-24 07:08:00 +00:00
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---
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.. run-openocd-appimage-offset
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::
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2021-10-11 19:15:31 +00:00
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openocd -f board/esp32s3-builtin.cfg -c "init; halt; esp appimage_offset 0x210000"
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2021-05-24 07:08:00 +00:00
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---
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.. openocd-cfg-files
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.. list-table:: OpenOCD configuration files for ESP32-S3
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:widths: 25 75
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:header-rows: 1
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* - Name
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- Description
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2021-10-11 19:15:31 +00:00
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* - ``board/esp32s3-builtin.cfg``
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- Board configuration file for ESP32-S3 for debugging via builtin USB JTAG, includes target and adapter configuration.
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* - ``board/esp32s3-ftdi.cfg``
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- Board configuration file for ESP32-S3 for via externally connected FTDI-based probe like ESP-Prog, includes target and adapter configuration.
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2021-05-24 07:08:00 +00:00
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* - ``target/esp32s3.cfg``
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- ESP32-S3 target configuration file. Can be used together with one of the ``interface/`` configuration files.
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2021-10-11 19:15:31 +00:00
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* - ``interface/ftdi/esp_usb_jtag.cfg``
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- JTAG adapter configuration file for ESP32-S3 builtin USB JTAG.
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2021-05-24 07:08:00 +00:00
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* - ``interface/ftdi/esp32_devkitj_v1.cfg``
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2021-10-11 19:15:31 +00:00
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- JTAG adapter configuration file for ESP-Prog debug adapter board.
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2021-05-24 07:08:00 +00:00
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---
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.. openocd-target-specific-config-vars
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---
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---
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.. jtag-pins
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.. list-table:: ESP32-S3 pins and JTAG signals
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:widths: 25 75
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:header-rows: 1
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* - ESP32-S3 Pin
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- JTAG Signal
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2021-08-27 12:01:53 +00:00
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* - MTDO / GPIO40
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2021-05-24 07:08:00 +00:00
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- TDO
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2021-08-27 12:01:53 +00:00
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* - MTDI / GPIO41
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2021-05-24 07:08:00 +00:00
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- TDI
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2021-08-27 12:01:53 +00:00
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* - MTCK / GPIO39
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2021-05-24 07:08:00 +00:00
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- TCK
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2021-08-27 12:01:53 +00:00
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* - MTMS / GPIO42
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2021-05-24 07:08:00 +00:00
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- TMS
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2021-08-27 12:01:53 +00:00
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.. |jtag-sel-gpio| replace:: GPIO3
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.. |jtag-gpio-list| replace:: GPIO39-GPIO42
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2021-05-24 07:08:00 +00:00
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---
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.. run-openocd-d3
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::
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2021-10-11 19:15:31 +00:00
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openocd -l openocd_log.txt -d3 -f board/esp32s3-builtin.cfg
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2021-05-24 07:08:00 +00:00
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---
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.. run-openocd-d3-tee
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::
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2021-10-11 19:15:31 +00:00
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openocd -d3 -f board/esp32s3-builtin.cfg 2>&1 | tee openocd.log
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2021-05-24 07:08:00 +00:00
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---
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.. run-gdb-remotelog
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::
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xtensa-esp32s3-elf-gdb -ex "set remotelogfile gdb_log.txt" <all other options>
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---
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.. devkit-defs
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.. |devkit-name| replace:: ESP32-S3
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.. |devkit-name-with-link| replace:: :doc:`ESP32-S3 <../../hw-reference/index>`
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---
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.. devkit-hw-config
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* Out of the box, ESP32-S3 doesn't need any additional hardware configuration for JTAG debugging. However if you are experiencing issues, check that switches 2-5 of the "JTAG" DIP switch block are in "ON" position.
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---
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