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esp-idf/components/espcoredump/component.mk

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coredump: improvements refactoring Move existing core dump files into espcoredump component folder Add KConfig, linker.lf, make and CMakeList.txt for new component Existing functionality separated into core_dump_common, core_dump_flash, core_dump_uart Update test_core_dump.c and make files to link it as unit test Update according to review: Move target and RTOS related functionality into separated file (core_dump_port.c).
2019-01-29 14:49:56 +00:00
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_SRCDIRS := src
COMPONENT_PRIV_INCLUDEDIRS := include_core_dump
Whitespace: Automated whitespace fixes (large commit) Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace)
2020-11-10 07:40:01 +00:00
COMPONENT_ADD_LDFRAGMENTS += linker.lf
espcoredump: code refactoring and add support for RISC-V implemetation This commit includes the refactoring of the core dump feature. Thanks to this refactoring, it is easier to integrate the support of RISC-V architecture for this feature. Fixes ESP-1758
2020-12-14 03:10:29 +00:00
ifdef CONFIG_IDF_TARGET_ARCH_XTENSA
espcoredump: Fix bugs related to (fake) stacks Add support to tasks stacks in RTC DRAM. Before this fix, any stack in RTC DRAM would have been considered as corrupted, whichi is not the case. Fix a bug related to wrong parameters passed to esp_core_dump_get_stack. Fix a bug reading fake stack memory, triggering a memory violation. * Closes https://github.com/espressif/esp-idf/issues/6751 * Merges https://github.com/espressif/esp-idf/pull/6750
2021-03-02 06:17:24 +00:00
COMPONENT_SRCDIRS += src/port/xtensa
espcoredump: On device core dump parsing to generate summary
2021-03-01 10:30:35 +00:00
COMPONENT_ADD_INCLUDEDIRS += include/port/xtensa
espcoredump: code refactoring and add support for RISC-V implemetation This commit includes the refactoring of the core dump feature. Thanks to this refactoring, it is easier to integrate the support of RISC-V architecture for this feature. Fixes ESP-1758
2020-12-14 03:10:29 +00:00
COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/xtensa
endif
ifdef CONFIG_IDF_TARGET_ARCH_RISCV
espcoredump: Fix bugs related to (fake) stacks Add support to tasks stacks in RTC DRAM. Before this fix, any stack in RTC DRAM would have been considered as corrupted, whichi is not the case. Fix a bug related to wrong parameters passed to esp_core_dump_get_stack. Fix a bug reading fake stack memory, triggering a memory violation. * Closes https://github.com/espressif/esp-idf/issues/6751 * Merges https://github.com/espressif/esp-idf/pull/6750
2021-03-02 06:17:24 +00:00
COMPONENT_SRCDIRS += src/port/riscv
espcoredump: On device core dump parsing to generate summary
2021-03-01 10:30:35 +00:00
COMPONENT_ADD_INCLUDEDIRS += include/port/riscv
espcoredump: code refactoring and add support for RISC-V implemetation This commit includes the refactoring of the core dump feature. Thanks to this refactoring, it is easier to integrate the support of RISC-V architecture for this feature. Fixes ESP-1758
2020-12-14 03:10:29 +00:00
COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/riscv
endif