2021-10-22 09:50:20 +00:00
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/*
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2021-12-15 15:30:29 +00:00
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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2021-10-22 09:50:20 +00:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2021-05-07 09:38:36 +00:00
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "hal/emac_hal.h"
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#include "hal/emac_ll.h"
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#include "hal/gpio_ll.h"
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#define ETH_CRC_LENGTH (4)
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void emac_hal_iomux_init_mii(void)
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{
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/* TX_CLK to GPIO0 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
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/* TX_EN to GPIO21 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO21_U, FUNC_GPIO21_EMAC_TX_EN);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[21]);
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/* TXD0 to GPIO19 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[19]);
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/* TXD1 to GPIO22 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO22_U, FUNC_GPIO22_EMAC_TXD1);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[22]);
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/* TXD2 to MTMS */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTMS_U, FUNC_MTMS_EMAC_TXD2);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[14]);
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/* TXD3 to MTDI */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTDI_U, FUNC_MTDI_EMAC_TXD3);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[12]);
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/* RX_CLK to GPIO5 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, FUNC_GPIO5_EMAC_RX_CLK);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[5]);
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/* RX_DV to GPIO27 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[27]);
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/* RXD0 to GPIO25 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO25_U, FUNC_GPIO25_EMAC_RXD0);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[25]);
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/* RXD1 to GPIO26 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, FUNC_GPIO26_EMAC_RXD1);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[26]);
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/* RXD2 to U0TXD */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_EMAC_RXD2);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[1]);
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/* RXD3 to MTDO */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTDO_U, FUNC_MTDO_EMAC_RXD3);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[15]);
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}
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void emac_hal_iomux_rmii_clk_input(void)
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{
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/* REF_CLK(RMII mode) to GPIO0 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
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}
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void emac_hal_iomux_rmii_clk_ouput(int num)
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{
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switch (num) {
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case 0:
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/* APLL clock output to GPIO0 (must be configured to 50MHz!) */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);
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break;
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case 16:
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/* RMII CLK (50MHz) output to GPIO16 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);
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break;
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case 17:
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/* RMII CLK (50MHz) output to GPIO17 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);
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break;
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default:
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break;
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}
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}
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void emac_hal_iomux_init_rmii(void)
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{
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/* TX_EN to GPIO21 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO21_U, FUNC_GPIO21_EMAC_TX_EN);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[21]);
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/* TXD0 to GPIO19 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[19]);
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/* TXD1 to GPIO22 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO22_U, FUNC_GPIO22_EMAC_TXD1);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[22]);
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/* CRS_DV to GPIO27 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[27]);
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/* RXD0 to GPIO25 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO25_U, FUNC_GPIO25_EMAC_RXD0);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[25]);
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/* RXD1 to GPIO26 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, FUNC_GPIO26_EMAC_RXD1);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[26]);
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}
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void emac_hal_iomux_init_tx_er(void)
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{
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/* TX_ER to GPIO4 */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_GPIO4_U, FUNC_GPIO4_EMAC_TX_ER);
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PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[4]);
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}
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void emac_hal_iomux_init_rx_er(void)
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{
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/* RX_ER to MTCK */
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gpio_ll_iomux_func_sel(PERIPHS_IO_MUX_MTCK_U, FUNC_MTCK_EMAC_RX_ER);
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[13]);
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}
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void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
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uint8_t **rx_buf, uint8_t **tx_buf)
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{
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hal->dma_regs = &EMAC_DMA;
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hal->mac_regs = &EMAC_MAC;
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hal->ext_regs = &EMAC_EXT;
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hal->descriptors = descriptors;
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hal->rx_buf = rx_buf;
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hal->tx_buf = tx_buf;
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}
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void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq)
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{
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2021-07-14 12:03:54 +00:00
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/* Tell MAC system clock Frequency in MHz, which will determine the frequency range of MDC(1MHz~2.5MHz) */
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2021-08-25 05:31:34 +00:00
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if (freq >= 20000000 && freq < 35000000) {
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2021-05-07 09:38:36 +00:00
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emac_ll_set_csr_clock_division(hal->mac_regs, 2); // CSR clock/16
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2021-08-25 05:31:34 +00:00
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} else if (freq >= 35000000 && freq < 60000000) {
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2021-05-07 09:38:36 +00:00
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emac_ll_set_csr_clock_division(hal->mac_regs, 3); // CSR clock/26
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2021-08-25 05:31:34 +00:00
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} else if (freq >= 60000000 && freq < 100000000) {
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2021-05-07 09:38:36 +00:00
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emac_ll_set_csr_clock_division(hal->mac_regs, 0); // CSR clock/42
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2021-08-25 05:31:34 +00:00
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} else if (freq >= 100000000 && freq < 150000000) {
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2021-05-07 09:38:36 +00:00
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emac_ll_set_csr_clock_division(hal->mac_regs, 1); // CSR clock/62
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2021-08-25 05:31:34 +00:00
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} else if (freq >= 150000000 && freq < 250000000) {
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2021-05-07 09:38:36 +00:00
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emac_ll_set_csr_clock_division(hal->mac_regs, 4); // CSR clock/102
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} else {
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emac_ll_set_csr_clock_division(hal->mac_regs, 5); // CSR clock/124
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}
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}
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void emac_hal_reset_desc_chain(emac_hal_context_t *hal)
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{
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/* reset DMA descriptors */
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hal->rx_desc = (eth_dma_rx_descriptor_t *)(hal->descriptors);
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hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->descriptors +
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sizeof(eth_dma_rx_descriptor_t) * CONFIG_ETH_DMA_RX_BUFFER_NUM);
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/* init rx chain */
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for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) {
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/* Set Own bit of the Rx descriptor Status: DMA */
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2021-10-22 09:50:20 +00:00
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hal->rx_desc[i].RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
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2021-05-07 09:38:36 +00:00
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/* Set Buffer1 size and Second Address Chained bit */
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hal->rx_desc[i].RDES1.SecondAddressChained = 1;
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hal->rx_desc[i].RDES1.ReceiveBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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/* Enable Ethernet DMA Rx Descriptor interrupt */
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hal->rx_desc[i].RDES1.DisableInterruptOnComplete = 0;
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/* point to the buffer */
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hal->rx_desc[i].Buffer1Addr = (uint32_t)(hal->rx_buf[i]);
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/* point to next descriptor */
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hal->rx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc + i + 1);
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}
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/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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hal->rx_desc[CONFIG_ETH_DMA_RX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc);
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/* init tx chain */
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for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
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2021-10-22 09:50:20 +00:00
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/* Set Own bit of the Tx descriptor Status: CPU */
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hal->tx_desc[i].TDES0.Own = EMAC_LL_DMADESC_OWNER_CPU;
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2021-05-07 09:38:36 +00:00
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hal->tx_desc[i].TDES0.SecondAddressChained = 1;
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hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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/* Enable Ethernet DMA Tx Descriptor interrupt */
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hal->tx_desc[1].TDES0.InterruptOnComplete = 1;
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/* Enable Transmit Timestamp */
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hal->tx_desc[i].TDES0.TransmitTimestampEnable = 1;
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/* point to the buffer */
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hal->tx_desc[i].Buffer1Addr = (uint32_t)(hal->tx_buf[i]);
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/* point to next descriptor */
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hal->tx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc + i + 1);
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}
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/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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hal->tx_desc[CONFIG_ETH_DMA_TX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc);
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/* set base address of the first descriptor */
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emac_ll_set_rx_desc_addr(hal->dma_regs, (uint32_t)hal->rx_desc);
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emac_ll_set_tx_desc_addr(hal->dma_regs, (uint32_t)hal->tx_desc);
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}
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void emac_hal_init_mac_default(emac_hal_context_t *hal)
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{
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/* MACCR Configuration */
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/* Enable the watchdog on the receiver, frame longer than 2048 Bytes is not allowed */
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emac_ll_watchdog_enable(hal->mac_regs, true);
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/* Enable the jabber timer on the transmitter, frame longer than 2048 Bytes is not allowed */
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emac_ll_jabber_enable(hal->mac_regs, true);
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/* minimum IFG between frames during transmission is 96 bit times */
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emac_ll_set_inter_frame_gap(hal->mac_regs, EMAC_LL_INTERFRAME_GAP_96BIT);
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/* Enable Carrier Sense During Transmission */
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emac_ll_carrier_sense_enable(hal->mac_regs, true);
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/* Select speed: port: 10/100 Mbps, here set default 100M, afterwards, will reset by auto-negotiation */
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emac_ll_set_port_speed(hal->mac_regs, ETH_SPEED_100M);;
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/* Allow the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
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emac_ll_recv_own_enable(hal->mac_regs, true);
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/* Disable internal loopback mode */
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emac_ll_loopback_enable(hal->mac_regs, false);
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/* Select duplex mode: here set default full duplex, afterwards, will reset by auto-negotiation */
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emac_ll_set_duplex(hal->mac_regs, ETH_DUPLEX_FULL);
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/* Select the checksum mode for received frame payload's TCP/UDP/ICMP headers */
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emac_ll_checksum_offload_mode(hal->mac_regs, ETH_CHECKSUM_HW);
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/* Enable MAC retry transmission when a colision occurs in half duplex mode */
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emac_ll_retry_enable(hal->mac_regs, true);
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/* MAC passes all incoming frames to host, without modifying them */
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emac_ll_auto_pad_crc_strip_enable(hal->mac_regs, false);
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/* Set Back-Off limit time before retry a transmittion after a collision */
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emac_ll_set_back_off_limit(hal->mac_regs, EMAC_LL_BACKOFF_LIMIT_10);
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/* Disable deferral check, MAC defers until the CRS signal goes inactive */
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emac_ll_deferral_check_enable(hal->mac_regs, false);
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/* Set preamble length 7 Bytes */
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emac_ll_set_preamble_length(hal->mac_regs, EMAC_LL_PREAMBLE_LENGTH_7);
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/* MACFFR Configuration */
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/* Receiver module passes only those frames to the Application that pass the SA or DA address filter */
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emac_ll_receive_all_enable(hal->mac_regs, false);
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/* Disable source address filter */
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emac_ll_set_src_addr_filter(hal->mac_regs, EMAC_LL_SOURCE_ADDR_FILTER_DISABLE);
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emac_ll_sa_inverse_filter_enable(hal->mac_regs, false);
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/* MAC blocks all control frames */
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emac_ll_set_pass_ctrl_frame_mode(hal->mac_regs, EMAC_LL_CONTROL_FRAME_BLOCKALL);
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/* AFM module passes all received broadcast frames and multicast frames */
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emac_ll_broadcast_frame_enable(hal->mac_regs, true);
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emac_ll_pass_all_multicast_enable(hal->mac_regs, true);
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/* Address Check block operates in normal filtering mode for the DA address */
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emac_ll_da_inverse_filter_enable(hal->mac_regs, false);
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/* Disable Promiscuous Mode */
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emac_ll_promiscuous_mode_enable(hal->mac_regs, false);
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}
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void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable)
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{
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/* MACFCR Configuration */
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if (enable) {
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/* Pause time */
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emac_ll_set_pause_time(hal->mac_regs, EMAC_LL_PAUSE_TIME);
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/* Enable generation of Zero-Quanta Pause Control frames */
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emac_ll_zero_quanta_pause_enable(hal->mac_regs, true);
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/* Threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
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emac_ll_set_pause_low_threshold(hal->mac_regs, EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_28);
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/* Don't allow MAC detect Pause frames with MAC address0 unicast address and unique multicast address */
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emac_ll_unicast_pause_frame_detect_enable(hal->mac_regs, false);
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/* Enable MAC to decode the received Pause frame and disable its transmitter for a specific time */
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emac_ll_receive_flow_ctrl_enable(hal->mac_regs, true);
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/* Enable MAC to transmit Pause frames in full duplex mode or the MAC back-pressure operation in half duplex mode */
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emac_ll_transmit_flow_ctrl_enable(hal->mac_regs, true);
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} else {
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emac_ll_clear(hal->mac_regs);
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}
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}
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2022-01-24 14:40:11 +00:00
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void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *hal_config)
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2021-05-07 09:38:36 +00:00
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{
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/* DMAOMR Configuration */
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/* Enable Dropping of TCP/IP Checksum Error Frames */
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emac_ll_drop_tcp_err_frame_enable(hal->dma_regs, true);
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/* Enable Receive Store Forward */
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emac_ll_recv_store_forward_enable(hal->dma_regs, true);
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/* Enable Flushing of Received Frames because of the unavailability of receive descriptors or buffers */
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emac_ll_flush_recv_frame_enable(hal->dma_regs, true);
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2021-07-14 12:03:54 +00:00
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/* Disable Transmit Store Forward */
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emac_ll_trans_store_forward_enable(hal->dma_regs, false);
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2021-05-07 09:38:36 +00:00
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/* Flush Transmit FIFO */
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emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
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/* Transmit Threshold Control */
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emac_ll_set_transmit_threshold(hal->dma_regs, EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_64);
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/* Disable Forward Error Frame */
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emac_ll_forward_err_frame_enable(hal->dma_regs, false);
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/* Disable forward undersized good frame */
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emac_ll_forward_undersized_good_frame_enable(hal->dma_regs, false);
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/* Receive Threshold Control */
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emac_ll_set_recv_threshold(hal->dma_regs, EMAC_LL_RECEIVE_THRESHOLD_CONTROL_64);
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/* Allow the DMA to process a second frame of Transmit data even before obtaining the status for the first frame */
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emac_ll_opt_second_frame_enable(hal->dma_regs, true);;
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/* DMABMR Configuration */
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/* Enable Mixed Burst */
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emac_ll_mixed_burst_enable(hal->dma_regs, true);
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/* Enable Address Aligned Beates */
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emac_ll_addr_align_enable(hal->dma_regs, true);
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2022-01-24 14:40:11 +00:00
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/* Don't use Separate PBL */
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2022-01-14 08:29:08 +00:00
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emac_ll_use_separate_pbl_enable(hal->dma_regs, false);
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2021-05-07 09:38:36 +00:00
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/* Set Rx/Tx DMA Burst Length */
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2022-01-24 14:40:11 +00:00
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emac_ll_set_prog_burst_len(hal->dma_regs, hal_config->dma_burst_len);
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2021-05-07 09:38:36 +00:00
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/* Enable Enhanced Descriptor,8 Words(32 Bytes) */
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emac_ll_enhance_desc_enable(hal->dma_regs, true);
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/* Specifies the number of word to skip between two unchained descriptors (Ring mode) */
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emac_ll_set_desc_skip_len(hal->dma_regs, 0);
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/* DMA Arbitration Scheme */
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emac_ll_fixed_arbitration_enable(hal->dma_regs, false);
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/* Set priority ratio in the weighted round-robin arbitration between Rx DMA and Tx DMA */
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emac_ll_set_priority_ratio(hal->dma_regs, EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1);
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}
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void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write)
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{
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/* Write the result value into the MII Address register */
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emac_ll_set_phy_addr(hal->mac_regs, phy_addr);
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/* Set the PHY register address */
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emac_ll_set_phy_reg(hal->mac_regs, phy_reg);
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/* Set as write mode */
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emac_ll_write_enable(hal->mac_regs, write);
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/* Set MII busy bit */
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emac_ll_set_busy(hal->mac_regs, true);
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}
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void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr)
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{
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/* Make sure mac address is unicast type */
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|
if (!(mac_addr[0] & 0x01)) {
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emac_ll_set_addr(hal->mac_regs, mac_addr);
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}
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}
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void emac_hal_start(emac_hal_context_t *hal)
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{
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/* Enable Ethernet MAC and DMA Interrupt */
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emac_ll_enable_corresponding_intr(hal->dma_regs, EMAC_LL_CONFIG_ENABLE_INTR_MASK);
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|
2021-12-20 11:45:24 +00:00
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/* Flush Transmit FIFO */
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emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);
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|
2021-05-07 09:38:36 +00:00
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/* Start DMA transmission */
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emac_ll_start_stop_dma_transmit(hal->dma_regs, true);
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/* Start DMA reception */
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emac_ll_start_stop_dma_receive(hal->dma_regs, true);
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|
2022-01-26 08:55:36 +00:00
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/* Enable transmit state machine of the MAC for transmission on the MII */
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emac_ll_transmit_enable(hal->mac_regs, true);
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/* Enable receive state machine of the MAC for reception from the MII */
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emac_ll_receive_enable(hal->mac_regs, true);
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|
2021-05-07 09:38:36 +00:00
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/* Clear all pending interrupts */
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emac_ll_clear_all_pending_intr(hal->dma_regs);
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}
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|
2021-12-20 11:45:24 +00:00
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esp_err_t emac_hal_stop(emac_hal_context_t *hal)
|
2021-05-07 09:38:36 +00:00
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{
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/* Stop DMA transmission */
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emac_ll_start_stop_dma_transmit(hal->dma_regs, false);
|
2021-12-20 11:45:24 +00:00
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if (emac_ll_transmit_frame_ctrl_status(hal->mac_regs) != 0x0) {
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/* Previous transmit in progress */
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return ESP_ERR_INVALID_STATE;
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}
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|
2021-05-07 09:38:36 +00:00
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/* Disable transmit state machine of the MAC for transmission on the MII */
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emac_ll_receive_enable(hal->mac_regs, false);
|
2022-01-26 08:55:36 +00:00
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/* Disable receive state machine of the MAC for reception from the MII */
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emac_ll_transmit_enable(hal->mac_regs, false);
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if (emac_ll_receive_read_ctrl_state(hal->mac_regs) != 0x0) {
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/* Previous receive copy in progress */
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return ESP_ERR_INVALID_STATE;
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}
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/* Stop DMA reception */
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emac_ll_start_stop_dma_receive(hal->dma_regs, false);
|
2021-05-07 09:38:36 +00:00
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/* Disable Ethernet MAC and DMA Interrupt */
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emac_ll_disable_all_intr(hal->dma_regs);
|
2021-12-20 11:45:24 +00:00
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return ESP_OK;
|
2021-05-07 09:38:36 +00:00
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}
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uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal)
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{
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return hal->tx_desc->TDES0.Own;
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}
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uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length)
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{
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/* Get the number of Tx buffers to use for the frame */
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uint32_t bufcount = 0;
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uint32_t lastlen = length;
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uint32_t sentout = 0;
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while (lastlen > CONFIG_ETH_DMA_BUFFER_SIZE) {
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lastlen -= CONFIG_ETH_DMA_BUFFER_SIZE;
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bufcount++;
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}
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if (lastlen) {
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bufcount++;
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}
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if (bufcount > CONFIG_ETH_DMA_TX_BUFFER_NUM) {
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goto err;
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}
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eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc;
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/* A frame is transmitted in multiple descriptor */
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for (size_t i = 0; i < bufcount; i++) {
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/* Check if the descriptor is owned by the Ethernet DMA (when 1) or CPU (when 0) */
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if (desc_iter->TDES0.Own != EMAC_LL_DMADESC_OWNER_CPU) {
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|
goto err;
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}
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/* Clear FIRST and LAST segment bits */
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desc_iter->TDES0.FirstSegment = 0;
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desc_iter->TDES0.LastSegment = 0;
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desc_iter->TDES0.InterruptOnComplete = 0;
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if (i == 0) {
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|
|
/* Setting the first segment bit */
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desc_iter->TDES0.FirstSegment = 1;
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}
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if (i == (bufcount - 1)) {
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/* Setting the last segment bit */
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desc_iter->TDES0.LastSegment = 1;
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/* Enable transmit interrupt */
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desc_iter->TDES0.InterruptOnComplete = 1;
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/* Program size */
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desc_iter->TDES1.TransmitBuffer1Size = lastlen;
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/* copy data from uplayer stack buffer */
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memcpy((void *)(desc_iter->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, lastlen);
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sentout += lastlen;
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} else {
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/* Program size */
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desc_iter->TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
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|
/* copy data from uplayer stack buffer */
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memcpy((void *)(desc_iter->Buffer1Addr), buf + i * CONFIG_ETH_DMA_BUFFER_SIZE, CONFIG_ETH_DMA_BUFFER_SIZE);
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sentout += CONFIG_ETH_DMA_BUFFER_SIZE;
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|
}
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/* Point to next descriptor */
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desc_iter = (eth_dma_tx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
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}
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|
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
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for (size_t i = 0; i < bufcount; i++) {
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hal->tx_desc->TDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
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hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr);
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}
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emac_ll_transmit_poll_demand(hal->dma_regs, 0);
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return sentout;
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err:
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return 0;
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|
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}
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uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain, uint32_t *free_desc)
|
|
|
|
{
|
|
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|
eth_dma_rx_descriptor_t *desc_iter = NULL;
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eth_dma_rx_descriptor_t *first_desc = NULL;
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|
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uint32_t used_descs = 0;
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uint32_t seg_count = 0;
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uint32_t ret_len = 0;
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uint32_t copy_len = 0;
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uint32_t write_len = 0;
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|
|
uint32_t frame_count = 0;
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first_desc = hal->rx_desc;
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|
desc_iter = hal->rx_desc;
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|
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/* Traverse descriptors owned by CPU */
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while ((desc_iter->RDES0.Own != EMAC_LL_DMADESC_OWNER_DMA) && (used_descs < CONFIG_ETH_DMA_RX_BUFFER_NUM) && !frame_count) {
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|
used_descs++;
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|
seg_count++;
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|
|
/* Last segment in frame */
|
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|
|
if (desc_iter->RDES0.LastDescriptor) {
|
|
|
|
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
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|
|
ret_len = desc_iter->RDES0.FrameLength - ETH_CRC_LENGTH;
|
|
|
|
/* packets larger than expected will be truncated */
|
|
|
|
copy_len = ret_len > size ? size : ret_len;
|
|
|
|
/* update unhandled frame count */
|
|
|
|
frame_count++;
|
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|
|
}
|
|
|
|
/* First segment in frame */
|
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|
|
if (desc_iter->RDES0.FirstDescriptor) {
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|
|
first_desc = desc_iter;
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|
|
|
}
|
|
|
|
/* point to next descriptor */
|
|
|
|
desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
|
|
|
|
}
|
|
|
|
/* there's at least one frame to process */
|
|
|
|
if (frame_count) {
|
|
|
|
/* check how many frames left to handle */
|
|
|
|
while ((desc_iter->RDES0.Own != EMAC_LL_DMADESC_OWNER_DMA) && (used_descs < CONFIG_ETH_DMA_RX_BUFFER_NUM)) {
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|
|
|
used_descs++;
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|
|
|
if (desc_iter->RDES0.LastDescriptor) {
|
|
|
|
frame_count++;
|
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|
|
}
|
|
|
|
/* point to next descriptor */
|
|
|
|
desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
|
|
|
|
}
|
|
|
|
desc_iter = first_desc;
|
|
|
|
for (size_t i = 0; i < seg_count - 1; i++) {
|
|
|
|
used_descs--;
|
|
|
|
write_len = copy_len < CONFIG_ETH_DMA_BUFFER_SIZE ? copy_len : CONFIG_ETH_DMA_BUFFER_SIZE;
|
|
|
|
/* copy data to buffer */
|
|
|
|
memcpy(buf, (void *)(desc_iter->Buffer1Addr), write_len);
|
|
|
|
buf += write_len;
|
|
|
|
copy_len -= write_len;
|
|
|
|
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
|
|
|
|
desc_iter->RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
|
|
|
|
desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
|
|
|
|
}
|
|
|
|
memcpy(buf, (void *)(desc_iter->Buffer1Addr), copy_len);
|
|
|
|
desc_iter->RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
|
|
|
|
/* update rxdesc */
|
|
|
|
hal->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
|
|
|
|
/* poll rx demand */
|
|
|
|
emac_ll_receive_poll_demand(hal->dma_regs, 0);
|
|
|
|
frame_count--;
|
|
|
|
used_descs--;
|
|
|
|
}
|
|
|
|
*frames_remain = frame_count;
|
|
|
|
*free_desc = CONFIG_ETH_DMA_RX_BUFFER_NUM - used_descs;
|
|
|
|
return ret_len;
|
|
|
|
}
|