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esp-idf/components/soc/esp32/include/soc/soc.h

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global: move the soc component out of the common list This MR removes the common dependency from every IDF components to the SOC component. Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components. But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components. In CMAKE, we have two kinds of header visibilities (set by include path visibility): (Assume component A --(depends on)--> B, B is the current component) 1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B) 2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only) and we have two kinds of depending ways: (Assume component A --(depends on)--> B --(depends on)--> C, B is the current component) 1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B) 2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B) 1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default. 2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it. 3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers 4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link) This is a breaking change. Previous code may depends on the long include chain. You may need to include the following headers for some files after this commit: - soc/soc.h - soc/soc_memory_layout.h - driver/gpio.h - esp_sleep.h The major broken include chain includes: 1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h. 2. ets_sys.h no longer includes soc/soc.h 3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h BREAKING CHANGE
2019-04-03 05:17:38 +00:00
// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
Initial public version
2016-08-17 15:08:22 +00:00
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
soc: allow REG_SET_FIELD to be used with single-bit fields
2017-04-18 04:09:19 +00:00
//
Initial public version
2016-08-17 15:08:22 +00:00
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
Updates for riscv support * Target components pull in xtensa component directly * Use CPU HAL where applicable * Remove unnecessary xtensa headers * Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no longer signed/unsigned int). Changes come from internal branch commit a6723fc
2020-11-06 04:00:07 +00:00
#pragma once
Initial public version
2016-08-17 15:08:22 +00:00
esp32: make soc header compatible with assembler
2017-03-18 09:27:19 +00:00
#ifndef __ASSEMBLER__
Initial public version
2016-08-17 15:08:22 +00:00
#include <stdint.h>
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#include "esp_assert.h"
esp32: make soc header compatible with assembler
2017-03-18 09:27:19 +00:00
#endif
Initial public version
2016-08-17 15:08:22 +00:00
global: move the soc component out of the common list This MR removes the common dependency from every IDF components to the SOC component. Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components. But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components. In CMAKE, we have two kinds of header visibilities (set by include path visibility): (Assume component A --(depends on)--> B, B is the current component) 1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B) 2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only) and we have two kinds of depending ways: (Assume component A --(depends on)--> B --(depends on)--> C, B is the current component) 1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B) 2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B) 1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default. 2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it. 3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers 4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link) This is a breaking change. Previous code may depends on the long include chain. You may need to include the following headers for some files after this commit: - soc/soc.h - soc/soc_memory_layout.h - driver/gpio.h - esp_sleep.h The major broken include chain includes: 1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h. 2. ets_sys.h no longer includes soc/soc.h 3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h BREAKING CHANGE
2019-04-03 05:17:38 +00:00
#include <esp_bit_defs.h>
Initial public version
2016-08-17 15:08:22 +00:00
Only modify headers in soc/ . Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-13 15:02:03 +00:00
#define PRO_CPU_NUM (0)
#define APP_CPU_NUM (1)
Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.
2017-07-20 08:26:35 +00:00
heap: Add integer overflow checks on MALLOC_CAP_32BIT & MALLOC_CAP_EXEC
2019-03-10 23:49:51 +00:00
#define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_DPORT_BASE 0x3ff00000
esp32 hwcrypto: Use AES registers directly
2017-08-15 22:58:33 +00:00
#define DR_REG_AES_BASE 0x3ff01000
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_RSA_BASE 0x3ff02000
#define DR_REG_SHA_BASE 0x3ff03000
bug fix of assert happen in PSRAM
2018-01-03 11:47:42 +00:00
#define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000
#define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000
#define DR_REG_DPORT_END 0x3ff13FFC
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
#define DR_REG_GPIO_BASE 0x3ff44000
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_FRC_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SENS_BASE 0x3ff48800
soc,ulp: add register definitions of RTC_I2C peripheral
2018-01-08 13:27:28 +00:00
#define DR_REG_RTC_I2C_BASE 0x3ff48C00
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
#define DR_REG_I2S_BASE 0x3ff4F000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
#define DR_REG_I2C_EXT_BASE 0x3ff53000
#define DR_REG_UHCI0_BASE 0x3ff54000
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_RMT_BASE 0x3ff56000
#define DR_REG_PCNT_BASE 0x3ff57000
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5A000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_NRX_BASE 0x3ff5CC00
#define DR_REG_BB_BASE 0x3ff5D000
mcpwm: fix wrong meta information
2021-01-07 09:31:18 +00:00
#define DR_REG_PWM0_BASE 0x3ff5E000
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
soc,ulp: add register definitions of RTC_I2C peripheral
2018-01-08 13:27:28 +00:00
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_SPI2_BASE 0x3ff64000
#define DR_REG_SPI3_BASE 0x3ff65000
soc,ulp: add register definitions of RTC_I2C peripheral
2018-01-08 13:27:28 +00:00
#define DR_REG_SYSCON_BASE 0x3ff66000
#define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
#define DR_REG_SDMMC_BASE 0x3ff68000
#define DR_REG_EMAC_BASE 0x3ff69000
CAN Driver The following commit contains the first version of the ESP32 CAN Driver. closes #544
2017-12-18 12:32:29 +00:00
#define DR_REG_CAN_BASE 0x3ff6B000
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define DR_REG_PWM1_BASE 0x3ff6C000
#define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART2_BASE 0x3ff6E000
Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.
2017-07-20 08:26:35 +00:00
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
Initial public version
2016-08-17 15:08:22 +00:00
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
test: fix the IRAM type conflict issue using heap_caps_malloc
2018-10-19 04:00:16 +00:00
#define ETS_CACHED_ADDR(addr) (addr)
Initial public version
2016-08-17 15:08:22 +00:00
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
#ifndef __ASSEMBLER__
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
efuse: update the scheme of getting chip revision
2019-07-29 03:35:00 +00:00
#if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM )
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
#else
#define ASSERT_IF_DPORT_REG(_r, OP)
#endif
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//write value to register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_WRITE(_r, _v) ({ \
fix reg operation missing
2017-07-07 11:10:02 +00:00
ASSERT_IF_DPORT_REG((_r), REG_WRITE); \
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
(*(volatile uint32_t *)(_r)) = (_v); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//read value from register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_READ(_r) ({ \
ASSERT_IF_DPORT_REG((_r), REG_READ); \
fix reg operation missing
2017-07-07 11:10:02 +00:00
(*(volatile uint32_t *)(_r)); \
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
})
Initial public version
2016-08-17 15:08:22 +00:00
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get bit or get bits from register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_GET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \
(*(volatile uint32_t*)(_r) & (_b)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set bit or set bits to register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_SET_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \
(*(volatile uint32_t*)(_r) |= (_b)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//clear bit or clear bits of register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_CLR_BIT(_r, _b) ({ \
ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \
(*(volatile uint32_t*)(_r) &= ~(_b)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_SET_BITS(_r, _b, _m) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
})
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
Flash encryption: Support enabling flash encryption in bootloader, app support * App access functions are all flash encryption-aware * Documentation for flash encryption * Partition read/write is flash aware * New encrypted write function
2016-11-11 06:00:34 +00:00
//get field from register, uses field _S & _V to determine mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_GET_FIELD(_r, _f) ({ \
ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
soc: allow REG_SET_FIELD to be used with single-bit fields
2017-04-18 04:09:19 +00:00
//set field of a register from variable, uses field _S & _V to determine mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define REG_SET_FIELD(_r, _f, _v) ({ \
ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get field value from a variable, used when _f is not left shifted by _f##_S
Initial public version
2016-08-17 15:08:22 +00:00
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get field value from a variable, used when _f is left shifted by _f##_S
Initial public version
2016-08-17 15:08:22 +00:00
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set field value to a variable, used when _f is not left shifted by _f##_S
Initial public version
2016-08-17 15:08:22 +00:00
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set field value to a variable, used when _f is left shifted by _f##_S
Initial public version
2016-08-17 15:08:22 +00:00
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//generate a value from a field value, used when _f is not left shifted by _f##_S
Initial public version
2016-08-17 15:08:22 +00:00
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//generate a value from a field value, used when _f is left shifted by _f##_S
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
Initial public version
2016-08-17 15:08:22 +00:00
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//read value from register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define READ_PERI_REG(addr) ({ \
ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//write value to register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define WRITE_PERI_REG(addr, val) ({ \
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//clear bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define SET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get bits of register controlled by mask
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define GET_PERI_REG_MASK(reg, mask) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \
(READ_PERI_REG(reg) & (mask)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get bits of register controlled by highest bit and lowest bit
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//set bits of register controlled by mask and shift
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
})
add comments to register read/write operations
2016-09-06 12:21:47 +00:00
//get field of register
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \
((READ_PERI_REG(reg)>>(shift))&(mask)); \
})
Initial public version
2016-08-17 15:08:22 +00:00
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
#endif /* !__ASSEMBLER__ */
component/esp32 : do more fix of dualcore bug 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function
2017-05-10 07:45:04 +00:00
//}}
add detection of invalid cache access - fix level 4 interrupt vectors to produce correct backtrace - initialize invalid cache access interrupt on startup - handle invalid cache access in panic handler
2017-03-09 12:50:39 +00:00
Initial public version
2016-08-17 15:08:22 +00:00
//Periheral Clock {{
Add API for random number generator
2016-11-21 14:59:46 +00:00
#define APB_CLK_FREQ_ROM ( 26*1000000 )
Initial public version
2016-08-17 15:08:22 +00:00
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
spi: re-enable the unit tests for esp32s2beta
2019-10-11 08:07:43 +00:00
#define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP32_DEFAULT_CPU_FREQ_MHZ
Add API for random number generator
2016-11-21 14:59:46 +00:00
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
uart: add support for REF_TICK
2017-08-21 14:30:23 +00:00
#define REF_CLK_FREQ ( 1000000 )
Initial public version
2016-08-17 15:08:22 +00:00
#define UART_CLK_FREQ APB_CLK_FREQ
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define WDT_CLK_FREQ APB_CLK_FREQ
Initial public version
2016-08-17 15:08:22 +00:00
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
#define SPI_CLK_DIV 4
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
spi_master: refactor and add HAL support
2019-01-23 09:07:03 +00:00
#define GPIO_MATRIX_DELAY_NS 25
Initial public version
2016-08-17 15:08:22 +00:00
//}}
heap: Add new multi_heap heap implementation to replace FreeRTOS-based tagged heaps
2017-04-28 04:08:58 +00:00
/* Overall memory map */
add esp32s2beta in soc component
2019-04-03 09:08:02 +00:00
#define SOC_DROM_LOW 0x3F400000
#define SOC_DROM_HIGH 0x3F800000
#define SOC_DRAM_LOW 0x3FFAE000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_IROM_LOW 0x400D0000
#define SOC_IROM_HIGH 0x40400000
#define SOC_IROM_MASK_LOW 0x40000000
soc: fix backtraces containing ROM functions esp_ptr_executable would return false for pointers to ROM, which would interrupt the backtrace. This makes ROM ranges recognized as executable.
2019-11-15 13:59:14 +00:00
#define SOC_IROM_MASK_HIGH 0x40064F00
add esp32s2beta in soc component
2019-04-03 09:08:02 +00:00
#define SOC_CACHE_PRO_LOW 0x40070000
#define SOC_CACHE_PRO_HIGH 0x40078000
#define SOC_CACHE_APP_LOW 0x40078000
#define SOC_CACHE_APP_HIGH 0x40080000
#define SOC_IRAM_LOW 0x40080000
#define SOC_IRAM_HIGH 0x400A0000
#define SOC_RTC_IRAM_LOW 0x400C0000
#define SOC_RTC_IRAM_HIGH 0x400C2000
#define SOC_RTC_DRAM_LOW 0x3FF80000
#define SOC_RTC_DRAM_HIGH 0x3FF82000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3F800000
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
heap: Add new multi_heap heap implementation to replace FreeRTOS-based tagged heaps
2017-04-28 04:08:58 +00:00
spiram: Add soc macro for SPIRAM address space size, use it where applicable Reference https://github.com/espressif/esp-idf/pull/5373
2020-06-16 04:51:31 +00:00
#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
heap: Refactor heap regions/capabilities out of FreeRTOS Remove tagged heap API, rename caps_xxx to heap_caps_xxx Also includes additional heap_caps_xxx inspection functions.
2017-05-03 08:03:28 +00:00
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x400A0000
1. Fix backtrace is incomplete 2. Optimization code style
2019-08-14 08:07:24 +00:00
#define SOC_DIRAM_IRAM_HIGH 0x400C0000
heap: Refactor heap regions/capabilities out of FreeRTOS Remove tagged heap API, rename caps_xxx to heap_caps_xxx Also includes additional heap_caps_xxx inspection functions.
2017-05-03 08:03:28 +00:00
#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
1. Fix backtrace is incomplete 2. Optimization code style
2019-08-14 08:07:24 +00:00
#define SOC_DIRAM_DRAM_HIGH 0x40000000
heap: make compatible with non-OS builds, remove target dependence
2019-12-18 16:04:49 +00:00
// Byte order of D/IRAM regions is reversed between accessing as DRAM or IRAM
#define SOC_DIRAM_INVERTED 1
heap: Refactor heap regions/capabilities out of FreeRTOS Remove tagged heap API, rename caps_xxx to heap_caps_xxx Also includes additional heap_caps_xxx inspection functions.
2017-05-03 08:03:28 +00:00
soc: Move esp_ptr_dma_capable() function to soc_memory_layout.h
2017-05-05 04:16:02 +00:00
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SOC_DMA_LOW 0x3FFAE000
#define SOC_DMA_HIGH 0x40000000
Add logic to make external RAM usable with malloc()
2017-09-22 08:02:39 +00:00
// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
soc: correct values of SOC_BYTE_ACCESSIBLE_LOW, SOC_MEM_INTERNAL_LOW Internal byte accessible memory starts with Internal ROM 1 at 0x3FF90000. Region of RTC fast memory starting at 0x3FF80000 is not used in IDF as it is mapped to PRO CPU only.
2017-10-18 04:18:38 +00:00
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000
feat(log): add new function to log buffer with level and hex dump.
2017-08-21 14:03:53 +00:00
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
soc: correct values of SOC_BYTE_ACCESSIBLE_LOW, SOC_MEM_INTERNAL_LOW Internal byte accessible memory starts with Internal ROM 1 at 0x3FF90000. Region of RTC fast memory starting at 0x3FF80000 is not used in IDF as it is mapped to PRO CPU only.
2017-10-18 04:18:38 +00:00
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x3FF90000
Add logic to make external RAM usable with malloc()
2017-09-22 08:02:39 +00:00
#define SOC_MEM_INTERNAL_HIGH 0x400C2000
bootloader: Add fault injection resistance to Secure Boot bootloader verification Goal is that multiple faults would be required to bypass a boot-time signature check. - Also strengthens some address range checks for safe app memory addresses - Change pre-enable logic to also check the bootloader signature before enabling SBV2 on ESP32 Add some additional checks for invalid sections: - Sections only partially in DRAM or IRAM are invalid - If a section is in D/IRAM, allow the possibility only some is in D/IRAM - Only pass sections that are entirely in the same type of RTC memory region
2020-02-16 05:51:42 +00:00
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3ffe3f20
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/
#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/
#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/
#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/
#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/
#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/
#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/
#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/
#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/
#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/
#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
Merge branch 'master' into feature/btdm_bluedroid 1.update esptool submodule 2.new esp32 lib and new phy lib 3.new bt lib 4.soc.h add comment
2016-11-01 09:53:59 +00:00
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt
2021-08-03 06:35:29 +00:00
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/
#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/
#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/
#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/
#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/
#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/
#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/
#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/
#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/
#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/
#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/
#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/
TWAI: Add ESP32-S2 support This commit adds TWAI driver support for the ESP32-S2. The following features were added: - Expanded BRP support - Expanded CLKOUT Divider Support - Updated example READMEs
2020-03-11 16:45:02 +00:00
#define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/
#define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/
#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/
#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/
#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/
#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/
#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/
#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/
#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/
#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/
#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/
#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/
#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/
#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/
#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
add esp32s2beta in soc component
2019-04-03 09:08:02 +00:00
#define ETS_MAX_INTR_SOURCE 69/**< total number of interrupt sources*/
Initial public version
2016-08-17 15:08:22 +00:00
components/os: add config option to choose system check intterupt level.
2021-09-02 13:10:29 +00:00
#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
component/bt : change VHCI interrupt type to software interrupt(int no 7)
2017-04-28 09:17:39 +00:00
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
Mark some interrupts that are now allocated dynamically as free, add int handle param documentation, add local ints test
2016-12-08 04:38:22 +00:00
* 2 1 extern level
* 3 1 extern level
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 4 1 extern level WBB
components/bt: High level interrupt in bluetooth components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h
2021-09-01 13:55:50 +00:00
* 5 1 extern level
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
component/bt : change VHCI interrupt type to software interrupt(int no 7)
2017-04-28 09:17:39 +00:00
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
Mark some interrupts that are now allocated dynamically as free, add int handle param documentation, add local ints test
2016-12-08 04:38:22 +00:00
* 9 1 extern level
soc: release interrupts which are not reserved by timers any more
2017-08-21 14:29:50 +00:00
* 10 1 extern edge
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
soc: release interrupts which are not reserved by timers any more
2017-08-21 14:29:50 +00:00
* 22 3 extern edge
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 23 3 extern level
components/bt: High level interrupt in bluetooth components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h
2021-09-01 13:55:50 +00:00
* 24 4 extern level
* 25 4 extern level BT/BLE Controller BT/BLE Controller
* 26 5 extern level TG1_WDT & CACHEERR
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 27 3 extern level Reserved Reserved
components/bt: High level interrupt in bluetooth components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h
2021-09-01 13:55:50 +00:00
* 28 4 extern edge
* 29 3 software BT/BLE hli BT/BLE hli
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
* 30 4 extern edge Reserved Reserved
components/bt: High level interrupt in bluetooth components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h
2021-09-01 13:55:50 +00:00
* 31 5 extern level IPC_ISR IPC_ISR
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
*************************************************************************************************************
*/
Initial public version
2016-08-17 15:08:22 +00:00
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
newlib: implement time syscalls
2016-11-02 09:17:28 +00:00
#define ETS_FRC1_INUM 22
components/bt: High level interrupt in bluetooth components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h
2021-09-01 13:55:50 +00:00
#define ETS_T1_WDT_CACHEERR_INUM 26
#define ETS_T1_WDT_INUM ETS_T1_WDT_CACHEERR_INUM
#define ETS_MEMACCESS_ERR_INUM ETS_T1_WDT_CACHEERR_INUM
esp32s2: IRAM/DRAM memory protection * new mem_prot API * mem_prot on & locked by default (see Kconfig) * feature activated in start_cpu0_default() JIRA IDF-1355
2020-03-10 15:46:10 +00:00
/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
components/bt: High level interrupt in bluetooth components/os: Move ETS_T1_WDT_INUM, ETS_CACHEERR_INUM and ETS_DPORT_INUM to l5 interrupt components/os: high level interrupt(5) components/os: hli_api: meta queue: fix out of bounds access, check for overflow components/os: hli: don't spill registers, instead save them to a separate region Level 4 interrupt has a chance of preempting a window overflow or underflow exception. Therefore it is not possible to use standard context save functions, as the SP on entry to Level 4 interrupt may be invalid (e.g. in WindowUnderflow4). Instead, mask window overflows and save the entire general purpose register file, plus some of the special registers. Then clear WindowStart, allowing the C handler to execute without spilling the old windows. On exit from the interrupt handler, do everything in reverse. components/bt: using high level interrupt in lc components/os: Add DRAM_ATTR to avoid feature `Allow .bss segment placed in external memory` components/bt: optimize code structure components/os: Modify the BT assert process to adapt to coredump and HLI components/os: Disable exception mode after saving special registers To store some registers first, avoid stuck due to live lock after disabling exception mode components/os: using dport instead of AHB in BT to fix live lock components/bt: Fix hli queue send error components/bt: Fix CI fail # Conflicts: # components/bt/CMakeLists.txt # components/bt/component.mk # components/bt/controller/bt.c # components/bt/controller/lib # components/esp_common/src/int_wdt.c # components/esp_system/port/soc/esp32/dport_panic_highint_hdl.S # components/soc/esp32/include/soc/soc.h
2021-09-01 13:55:50 +00:00
#define ETS_IPC_ISR_INUM 31
Initial public version
2016-08-17 15:08:22 +00:00
newlib: implement time syscalls
2016-11-02 09:17:28 +00:00
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
header files: modify rom code and soc header files 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
2016-08-31 13:53:23 +00:00
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
Only modify headers in soc/ . Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-13 15:02:03 +00:00
//Other interrupt number should be managed by the user
Initial public version
2016-08-17 15:08:22 +00:00
component/bt : fix interrupt number conflict 1. the typical problem is when push keyboard on serial tool, the bluetooth may stop.
2017-06-15 09:20:25 +00:00
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
components/os: add config option to choose system check intterupt level.
2021-09-02 13:10:29 +00:00
#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software BT/BLE VHCI BT/BLE VHCI
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge IPC_ISR IPC_ISR
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
*************************************************************************************************************
*/
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_MEMACCESS_ERR_INUM 25
/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
#define ETS_IPC_ISR_INUM 28
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
//Other interrupt number should be managed by the user
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 6
#endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */