2022-07-15 04:52:44 +00:00
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "unity.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "driver/gptimer.h"
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#include "esp_rom_sys.h"
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#include "test_common_adc.h"
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#include "esp_adc/adc_oneshot.h"
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const __attribute__((unused)) static char *TAG = "TEST_ADC";
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/*---------------------------------------------------------------
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ADC General Macros
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---------------------------------------------------------------*/
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//ADC Channels
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#if CONFIG_IDF_TARGET_ESP32
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#define ADC1_TEST_CHAN0 ADC_CHANNEL_4
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#else
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#define ADC1_TEST_CHAN0 ADC_CHANNEL_2
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#endif
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typedef struct {
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void *adc_handle; //ADC handle, could be oneshot / continuous handle
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bool level; //ADC level
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int adc_raw_high; //ADC reading raw when IO tie high
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int cb_exe_times_high; //Callback running times when IO tie high and $ disabled
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int adc_raw_low; //ADC reading raw when IO tie low
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int cb_exe_times_low; //Callback running times when IO tie low and $ disabled
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bool cache_disable_flag; //Indicating cache is disabled
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} test_adc_iram_ctx_t;
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extern void spi_flash_disable_interrupts_caches_and_other_cpu(void);
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extern void spi_flash_enable_interrupts_caches_and_other_cpu(void);
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__attribute__((unused))
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static void s_test_cache_disable_period_us(test_adc_iram_ctx_t *ctx, uint32_t period_us);
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#if CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM && CONFIG_GPTIMER_ISR_IRAM_SAFE
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/*---------------------------------------------------------------
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ADC oneshot work with cache safe ISR
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---------------------------------------------------------------*/
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static bool IRAM_ATTR NOINLINE_ATTR s_alarm_cb(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_data)
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{
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test_adc_iram_ctx_t *test_ctx = (test_adc_iram_ctx_t *)user_data;
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adc_oneshot_unit_handle_t oneshot_handle = *(adc_oneshot_unit_handle_t *)(test_ctx->adc_handle);
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if (test_ctx->cache_disable_flag) {
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if (test_ctx->level) {
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adc_oneshot_read_isr(oneshot_handle, ADC1_TEST_CHAN0, &test_ctx->adc_raw_high);
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esp_rom_printf(DRAM_STR("adc raw: %d\n"), test_ctx->adc_raw_high);
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test_ctx->cb_exe_times_high++;
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} else {
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adc_oneshot_read_isr(oneshot_handle, ADC1_TEST_CHAN0, &test_ctx->adc_raw_low);
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esp_rom_printf(DRAM_STR("adc raw: %d\n"), test_ctx->adc_raw_low);
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test_ctx->cb_exe_times_low++;
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}
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}
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return false;
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}
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TEST_CASE("ADC oneshot fast work with ISR and Flash", "[adc_oneshot]")
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{
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adc_oneshot_unit_handle_t oneshot_handle;
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static DRAM_ATTR test_adc_iram_ctx_t isr_test_ctx = {};
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isr_test_ctx.adc_handle = &oneshot_handle;
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//-------------ADC1 Init---------------//
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adc_oneshot_unit_init_cfg_t init_config1 = {
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.unit_id = ADC_UNIT_1,
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.ulp_mode = false,
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};
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TEST_ESP_OK(adc_oneshot_new_unit(&init_config1, &oneshot_handle));
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//-------------ADC1 TEST Channel 0 Config---------------//
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adc_oneshot_chan_cfg_t config = {
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.bitwidth = ADC_BITWIDTH_DEFAULT,
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.atten = ADC_ATTEN_DB_11,
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};
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TEST_ESP_OK(adc_oneshot_config_channel(oneshot_handle, ADC1_TEST_CHAN0, &config));
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//-------------GPTimer Init & Config---------------//
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gptimer_handle_t timer = NULL;
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gptimer_config_t timer_config = {
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.resolution_hz = 1 * 1000 * 1000,
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.clk_src = GPTIMER_CLK_SRC_DEFAULT,
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.direction = GPTIMER_COUNT_UP,
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};
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TEST_ESP_OK(gptimer_new_timer(&timer_config, &timer));
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gptimer_event_callbacks_t cbs = {
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.on_alarm = s_alarm_cb,
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};
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gptimer_alarm_config_t alarm_config = {
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.reload_count = 0,
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.alarm_count = 100000, // 100ms
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.flags.auto_reload_on_alarm = true,
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};
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TEST_ESP_OK(gptimer_set_alarm_action(timer, &alarm_config));
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TEST_ESP_OK(gptimer_register_event_callbacks(timer, &cbs, &isr_test_ctx));
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//ADC IO tile low
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 0);
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isr_test_ctx.level = 0;
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printf("start timer\r\n");
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TEST_ESP_OK(gptimer_enable(timer));
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TEST_ESP_OK(gptimer_start(timer));
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s_test_cache_disable_period_us(&isr_test_ctx, 100 * 1000);
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TEST_ESP_OK(gptimer_stop(timer));
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//Checks
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TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, isr_test_ctx.adc_raw_low);
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esp_rom_printf("callback runs %d times when $ disabled\n", isr_test_ctx.cb_exe_times_low);
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TEST_ASSERT_GREATER_OR_EQUAL(1, isr_test_ctx.cb_exe_times_low);
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//ADC IO tile high
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 1);
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isr_test_ctx.level = 1;
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//Reset counter value to zero
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TEST_ESP_OK(gptimer_set_raw_count(timer, 0));
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printf("start timer\r\n");
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TEST_ESP_OK(gptimer_start(timer));
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s_test_cache_disable_period_us(&isr_test_ctx, 100 * 1000);
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TEST_ESP_OK(gptimer_stop(timer));
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//Checks
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TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL, isr_test_ctx.adc_raw_high);
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esp_rom_printf("callback runs %d times when $ disabled\n", isr_test_ctx.cb_exe_times_high);
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TEST_ASSERT_GREATER_OR_EQUAL(1, isr_test_ctx.cb_exe_times_high);
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//Tear Down
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TEST_ESP_OK(gptimer_disable(timer));
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TEST_ESP_OK(gptimer_del_timer(timer));
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TEST_ESP_OK(adc_oneshot_del_unit(oneshot_handle));
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}
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#endif //#if CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM && CONFIG_GPTIMER_ISR_IRAM_SAFE
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#if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
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#include "esp_adc/adc_continuous.h"
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/*---------------------------------------------------------------
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ADC continuous work with cache safe ISR
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---------------------------------------------------------------*/
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#if (SOC_ADC_DIGI_RESULT_BYTES == 2)
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#define ADC_TEST_OUTPUT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE1
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#else
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#define ADC_TEST_OUTPUT_TYPE ADC_DIGI_OUTPUT_FORMAT_TYPE2
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#endif
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#define ADC_TEST_FREQ_HZ (50 * 1000)
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#define ADC_TEST_PKG_SIZE 100
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static bool IRAM_ATTR NOINLINE_ATTR s_conv_done_cb(adc_continuous_handle_t handle, const adc_continuous_evt_data_t *edata, void *user_data)
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{
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test_adc_iram_ctx_t *test_ctx = (test_adc_iram_ctx_t *)user_data;
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if (test_ctx->cache_disable_flag) {
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int raw = 0;
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for (int i = 0; i < edata->size; i += SOC_ADC_DIGI_RESULT_BYTES) {
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adc_digi_output_data_t *p = (void*)&(edata->conv_frame_buffer[i]);
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#if (SOC_ADC_DIGI_RESULT_BYTES == 2)
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raw += p->type1.data;
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#else
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raw += p->type2.data;
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#endif
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}
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if (test_ctx->level) {
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test_ctx->adc_raw_high = raw / (edata->size / SOC_ADC_DIGI_RESULT_BYTES);
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test_ctx->cb_exe_times_high++;
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} else {
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test_ctx->adc_raw_low = raw / (edata->size / SOC_ADC_DIGI_RESULT_BYTES);
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test_ctx->cb_exe_times_low++;
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}
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}
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return false;
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}
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TEST_CASE("ADC continuous work with ISR and Flash", "[adc_oneshot]")
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{
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adc_continuous_handle_t handle = NULL;
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adc_continuous_handle_cfg_t adc_config = {
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.max_store_buf_size = 1024,
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.conv_frame_size = ADC_TEST_PKG_SIZE,
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};
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TEST_ESP_OK(adc_continuous_new_handle(&adc_config, &handle));
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adc_continuous_config_t dig_cfg = {
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.sample_freq_hz = ADC_TEST_FREQ_HZ,
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.conv_mode = ADC_CONV_SINGLE_UNIT_1,
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.format = ADC_TEST_OUTPUT_TYPE,
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};
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adc_digi_pattern_config_t adc_pattern[SOC_ADC_PATT_LEN_MAX] = {0};
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adc_pattern[0].atten = ADC_ATTEN_DB_0;
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adc_pattern[0].channel = ADC1_TEST_CHAN0;
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adc_pattern[0].unit = ADC_UNIT_1;
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adc_pattern[0].bit_width = SOC_ADC_DIGI_MAX_BITWIDTH;
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dig_cfg.adc_pattern = adc_pattern;
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dig_cfg.pattern_num = 1;
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TEST_ESP_OK(adc_continuous_config(handle, &dig_cfg));
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static DRAM_ATTR test_adc_iram_ctx_t isr_test_ctx = {};
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isr_test_ctx.adc_handle = &handle;
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adc_continuous_evt_cbs_t cbs = {
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.on_conv_done = s_conv_done_cb,
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};
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TEST_ESP_OK(adc_continuous_register_event_callbacks(handle, &cbs, &isr_test_ctx));
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#if CONFIG_IDF_TARGET_ESP32
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//This may need to be bigger, when the sampling freq is low
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uint32_t overhead_us = 150;
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#else
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2022-07-25 02:40:52 +00:00
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uint32_t overhead_us = 50;
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2022-07-15 04:52:44 +00:00
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#endif
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uint32_t wait_time_us = (1000 * 1000 / ADC_TEST_FREQ_HZ * ADC_TEST_PKG_SIZE / SOC_ADC_DIGI_RESULT_BYTES) + overhead_us;
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printf("period is %d us\n", wait_time_us);
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//ADC IO tile low
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 0);
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isr_test_ctx.level = 0;
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TEST_ESP_OK(adc_continuous_start(handle));
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s_test_cache_disable_period_us(&isr_test_ctx, wait_time_us);
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TEST_ESP_OK(adc_continuous_stop(handle));
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//Checks
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TEST_ASSERT_INT_WITHIN(ADC_TEST_LOW_THRESH, ADC_TEST_LOW_VAL, isr_test_ctx.adc_raw_low);
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esp_rom_printf("callback runs %d times when $ disabled\n", isr_test_ctx.cb_exe_times_low);
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TEST_ASSERT_GREATER_OR_EQUAL(1, isr_test_ctx.cb_exe_times_low);
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vTaskDelay(10);
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printf("to set high\n");
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//ADC IO tile high
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test_adc_set_io_level(ADC_UNIT_1, ADC1_TEST_CHAN0, 1);
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isr_test_ctx.level = 1;
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TEST_ESP_OK(adc_continuous_start(handle));
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s_test_cache_disable_period_us(&isr_test_ctx, wait_time_us);
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TEST_ESP_OK(adc_continuous_stop(handle));
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//Checks
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// TEST_ASSERT_INT_WITHIN(ADC_TEST_HIGH_THRESH, ADC_TEST_HIGH_VAL_DMA, isr_test_ctx.adc_raw_high);
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esp_rom_printf("callback runs %d times when $ disabled\n", isr_test_ctx.cb_exe_times_high);
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TEST_ASSERT_GREATER_OR_EQUAL(1, isr_test_ctx.cb_exe_times_high);
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TEST_ESP_OK(adc_continuous_deinit(handle));
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}
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#endif //#if CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE
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static void IRAM_ATTR NOINLINE_ATTR s_test_cache_disable_period_us(test_adc_iram_ctx_t *ctx, uint32_t period_us)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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ctx->cache_disable_flag = 1;
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esp_rom_delay_us(period_us);
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ctx->cache_disable_flag = 0;
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spi_flash_enable_interrupts_caches_and_other_cpu();
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}
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