kopia lustrzana https://github.com/espressif/esp-idf
308 wiersze
6.6 KiB
ArmAsm
308 wiersze
6.6 KiB
ArmAsm
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "soc/soc.h"
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#include "soc/interrupt_reg.h"
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.equ SAVE_REGS, 32
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.equ CONTEXT_SIZE, (SAVE_REGS * 4)
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.equ PANIC_REGS, 38
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.equ PANIC_REGS_SIZE, (PANIC_REGS * 4)
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.altmacro
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.macro lwsp a, b
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lw \a, ((\b)*4)(sp)
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.endm
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.macro swsp a, b
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sw \a, ((\b)*4)(sp)
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.endm
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.macro save_regs
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addi sp, sp, -CONTEXT_SIZE
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swsp ra, 1
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swsp a0, 2
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swsp a1, 3
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swsp a2, 4
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swsp a3, 5
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swsp a4, 6
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swsp a5, 7
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swsp a6, 8
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swsp a7, 9
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swsp t0, 10
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swsp t1, 11
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swsp t2, 12
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swsp t3, 13
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swsp t4, 14
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swsp t5, 15
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swsp t6, 16
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//swsp sp, 17
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//swsp gp, 18
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swsp tp, 19
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swsp s0, 20
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swsp s1, 21
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swsp s2, 22
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swsp s3, 23
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swsp s4, 24
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swsp s5, 25
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swsp s6, 26
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swsp s7, 27
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swsp s8, 28
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swsp s9, 29
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swsp s10, 30
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swsp s11, 31
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.endm
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.macro save_mepc
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csrr t0, mepc
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swsp t0, 0
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.endm
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.macro restore_regs
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lwsp ra, 1
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lwsp a0, 2
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lwsp a1, 3
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lwsp a2, 4
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lwsp a3, 5
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lwsp a4, 6
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lwsp a5, 7
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lwsp a6, 8
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lwsp a7, 9
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lwsp t0, 10
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lwsp t1, 11
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lwsp t2, 12
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lwsp t3, 13
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lwsp t4, 14
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lwsp t5, 15
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lwsp t6, 16
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//lwsp sp, 17
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//lwsp gp, 18
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lwsp tp, 19
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lwsp s0, 20
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lwsp s1, 21
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lwsp s2, 22
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lwsp s3, 23
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lwsp s4, 24
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lwsp s5, 25
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lwsp s6, 26
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lwsp s7, 27
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lwsp s8, 28
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lwsp s9, 29
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lwsp s10, 30
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lwsp s11, 31
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addi sp, sp, CONTEXT_SIZE
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.endm
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.macro restore_mepc
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lwsp t0, 0
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csrw mepc, t0
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.endm
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.global vPortYieldFromISR
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.global uxInterruptNesting
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.global uxSchedulerRunning
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.global xIsrStackTop
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.global pxCurrentTCB
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.global _global_interrupt_handler
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.section .exception_vectors.text
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/* This is the vector table. MTVEC points here.
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*
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* Use 4-byte intructions here. 1 instruction = 1 entry of the table.
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* The CPU jumps to MTVEC (i.e. the first entry) in case of an exception,
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* and (MTVEC & 0xfffffffc) + (mcause & 0x7fffffff) * 4, in case of an interrupt.
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*
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* Note: for our CPU, we need to place this on a 256-byte boundary, as CPU
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* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
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*/
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.balign 0x100
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.global _vector_table
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.type _vector_table, @function
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_vector_table:
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.option push
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.option norvc
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j _panic_handler /* exception handler, entry 0 */
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.rept 31
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j _interrupt_handler /* 31 identical entries, all pointing to the interrupt handler */
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.endr
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.option pop
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.size _vector_table, .-_vector_table
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/* Exception handler.*/
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.global panicHandler
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.type _panic_handler, @function
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_panic_handler:
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addi sp, sp, -PANIC_REGS_SIZE
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swsp x0, 0
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swsp x1, 1
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/* x2 is sp - it will be placed on stack later (after we can use the other registers for computation) */
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swsp x3, 3
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swsp x4, 4
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swsp x5, 5
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swsp x6, 6
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swsp x7, 7
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swsp x8, 8
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swsp x9, 9
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swsp x10, 10
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swsp x11, 11
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swsp x12, 12
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swsp x13, 13
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swsp x14, 14
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swsp x15, 15
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swsp x16, 16
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swsp x17, 17
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swsp x18, 18
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swsp x19, 19
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swsp x20, 20
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swsp x21, 21
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swsp x22, 22
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swsp x23, 23
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swsp x24, 24
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swsp x25, 25
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swsp x26, 26
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swsp x27, 27
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swsp x28, 28
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swsp x29, 29
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swsp x30, 30
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swsp x31, 31
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/* "Undo" the modification already done to the sp (x2) by the panic handler */
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addi a1, x2, PANIC_REGS_SIZE
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swsp a1, 2
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csrr a1, mcause
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swsp a1, 32
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csrr a1, mepc
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swsp a1, 33
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csrr a1, mhartid
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swsp a1, 34
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csrr a1, mstatus
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swsp a1, 35
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csrr a1, mtval
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swsp a1, 36
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csrr a1, mtvec
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swsp a1, 37
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mv a0, sp
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csrr a1, mcause
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jal zero, panicHandler
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/* panicHandler never returns */
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.size _panic_handler, .-_panic_handler
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/* This is the interrupt handler.
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* It saves the registers on the stack,
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* prepares for interrupt nesting,
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* re-enables the interrupts,
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* then jumps to the C dispatcher in interrupt.c.
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*/
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.global _interrupt_handler
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.type _interrupt_handler, @function
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_interrupt_handler:
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/* entry */
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save_regs
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save_mepc
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/* scheduler not enabled, jump directly to ISR handler */
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lw t0, uxSchedulerRunning
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beq t0,zero,already_on_handler
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/* increments the ISR nesting count */
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/* This will work properly when we have nested interrupts */
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la t0, uxInterruptNesting
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lw t1, 0x0(t0)
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addi t2,t1,1
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sw t2, 0x0(t0)
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/* If reached here from another low-prio ISR, skip stack pushing to TCB */
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bne t1,zero, already_on_handler
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/* Otherwise, save current sp, and use the isr stack from here */
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lw t0, pxCurrentTCB
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sw sp, 0x0(t0)
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lw sp, xIsrStackTop
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already_on_handler:
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/* Before dispatch c handler, restore interrupt to enable nested intr */
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csrr s1, mcause
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csrr s2, mstatus
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/* Save the interrupt threshold level */
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la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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lw s3, 0(t0)
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/* Increase interrupt threshold level */
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la t2, 0x7fffffff
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and t1, s1, t2 /* t1 = mcause & mask */
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slli t1, t1, 2 /* t1 = mcause * 4 */
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la t2, INTC_INT_PRIO_REG(0)
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add t1, t2, t1 /* t1 = INTC_INT_PRIO_REG + 4 * mcause */
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lw t2, 0(t1) /* t2 = INTC_INT_PRIO_REG[mcause] */
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addi t2, t2, 1 /* t2 = t2 +1 */
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sw t2, 0(t0) /* INTERRUPT_CORE0_CPU_INT_THRESH_REG = t2 */
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fence
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la t0, 0x8
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csrrs t0, mstatus, t0
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/* call the C dispatcher */
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mv a0, sp /* argument 1, stack pointer */
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csrr a1, mcause /* argument 2, interrupt number */
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/* mask off the interrupt flag of mcause */
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la t0, 0x7fffffff
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and a1, a1, t0
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jal _global_interrupt_handler
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/* After dispatch c handler, disable interrupt to make freertos make context switch */
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la t0, 0x8
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csrrc t0, mstatus, t0
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/* restore the interrupt threshold level */
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la t0, INTERRUPT_CORE0_CPU_INT_THRESH_REG
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sw s3, 0(t0)
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fence
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/* may skip RTOS aware interrupt since scheduler was not started */
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lw t1, uxSchedulerRunning
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beq t1,zero, isr_exit
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/* update nesting interrupts counter */
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la t0, uxInterruptNesting
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lw t1, 0x0(t0)
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/* Already zero, protect againts underflow */
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beq t1, zero, isr_skip_decrement
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addi t1,t1, -1
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sw t1, 0x0(t0)
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isr_skip_decrement:
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/* may still have interrupts pending, skip section below and exit */
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bne t1,zero,isr_exit
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/* handlered all the ISRs and scheduled the next task, take its stack */
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/* load on sp, then exit. */
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lw sp, pxCurrentTCB
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lw sp, 0x0(sp)
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isr_exit:
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/* restore the rest of the registers */
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csrw mcause, s1
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csrw mstatus, s2
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restore_mepc
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restore_regs
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/* exit, this will also re-enable the interrupts */
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mret
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.size _interrupt_handler, .-_interrupt_handler
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