esp-idf/tools/unit-test-app/configs/release_c3

CONFIG_IDF_TARGET="esp32c3"
TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs sdmmc
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
tools: merge C3 changes into master 2020-12-29 02:00:45 +00:00			`CONFIG_IDF_TARGET="esp32c3"`
sdspi: enable UT & ExampleTest for C3/S2 Closes https://github.com/espressif/esp-idf/issues/7389 (1) "MMC_RSP_BITS" [sd] [Y] (2) "probe SD in SPI mode" [sd][test_env=UT_T1_SPIMODE] [Y] (3) "probe SD in SPI mode, slot 0" [sd][ignore] [N] (4) "SDMMC performance (SPI mode)" [sdspi][test_env=UT_T1_SPIMODE] [Y] (5) "SDMMC test read/write with offset (SPI mode)" [sdspi][test_env=UT_T1_SPIMODE] [Y] (6) "CD input works in SPI mode" [sd][test_env=UT_T1_SPIMODE] [Y] (7) "WP input works in SPI mode" [sd][test_env=UT_T1_SPIMODE] [Y] 2021-09-23 02:57:05 +00:00			`TEST_COMPONENTS=freertos esp_hw_support esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs sdmmc`
tools: merge C3 changes into master 2020-12-29 02:00:45 +00:00			`CONFIG_COMPILER_OPTIMIZATION_SIZE=y`
			`CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y`
sdspi: enable UT & ExampleTest for C3/S2 Closes https://github.com/espressif/esp-idf/issues/7389 (1) "MMC_RSP_BITS" [sd] [Y] (2) "probe SD in SPI mode" [sd][test_env=UT_T1_SPIMODE] [Y] (3) "probe SD in SPI mode, slot 0" [sd][ignore] [N] (4) "SDMMC performance (SPI mode)" [sdspi][test_env=UT_T1_SPIMODE] [Y] (5) "SDMMC test read/write with offset (SPI mode)" [sdspi][test_env=UT_T1_SPIMODE] [Y] (6) "CD input works in SPI mode" [sd][test_env=UT_T1_SPIMODE] [Y] (7) "WP input works in SPI mode" [sd][test_env=UT_T1_SPIMODE] [Y] 2021-09-23 02:57:05 +00:00			`CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y`