2021-12-23 06:12:47 +00:00
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/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2020-04-17 19:34:56 +00:00
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#include <stdio.h>
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#include <string.h>
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#include "esp_sleep.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "soc/rtc_periph.h"
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2021-12-23 06:12:47 +00:00
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#if CONFIG_IDF_TARGET_ESP32S2
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2020-04-17 19:34:56 +00:00
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#include "esp32s2/ulp.h"
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#include "esp32s2/ulp_riscv.h"
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2021-12-23 06:12:47 +00:00
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/ulp.h"
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#include "esp32s3/ulp_riscv.h"
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#endif
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2020-04-17 19:34:56 +00:00
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#include "ulp_test_app.h"
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#include "unity.h"
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#include <sys/time.h>
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2022-01-19 02:57:31 +00:00
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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2020-04-17 19:34:56 +00:00
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typedef enum{
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RISCV_READ_WRITE_TEST = 1,
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RISCV_DEEP_SLEEP_WAKEUP_TEST,
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RISCV_LIGHT_SLEEP_WAKEUP_TEST,
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RISCV_STOP_TEST,
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RISCV_NO_COMMAND,
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} riscv_test_commands_t;
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typedef enum {
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RISCV_COMMAND_OK = 1,
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RISCV_COMMAND_NOK,
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RISCV_COMMAND_INVALID,
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} riscv_test_command_reply_t;
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#define XOR_MASK 0xDEADBEEF
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#define ULP_WAKEUP_PERIOD 1000000 // 1 second
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2020-04-17 19:34:56 +00:00
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extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_test_app_bin_start");
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extern const uint8_t ulp_main_bin_end[] asm("_binary_ulp_test_app_bin_end");
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static bool firmware_loaded = false;
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static void load_and_start_ulp_firmware(void)
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{
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if (!firmware_loaded) {
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2020-11-10 07:40:01 +00:00
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TEST_ASSERT(ulp_riscv_load_binary(ulp_main_bin_start,
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2020-04-17 19:34:56 +00:00
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(ulp_main_bin_end - ulp_main_bin_start)) == ESP_OK);
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TEST_ASSERT(ulp_set_wakeup_period(0, ULP_WAKEUP_PERIOD) == ESP_OK);
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2020-04-17 19:34:56 +00:00
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TEST_ASSERT(ulp_riscv_run() == ESP_OK);
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firmware_loaded = true;
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}
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}
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2022-01-19 02:57:31 +00:00
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TEST_CASE("ULP-RISC-V and main CPU are able to exchange data", "[ulp]")
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{
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const uint32_t test_data = 0x12345678;
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struct timeval start, end;
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware();
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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/* Setup test data */
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ulp_riscv_test_data_in = test_data ^ XOR_MASK;
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ulp_main_cpu_command = RISCV_READ_WRITE_TEST;
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/* Enter Light Sleep */
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TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
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/* Wait for wakeup from ULP RISC-V Coprocessor */
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TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
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2020-11-10 07:40:01 +00:00
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/* Wait till we receive the correct command response */
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gettimeofday(&start, NULL);
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while (ulp_command_resp != RISCV_READ_WRITE_TEST)
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;
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gettimeofday(&end, NULL);
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printf("Response time %ld ms\n", (end.tv_sec - start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000);
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/* Verify test data */
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TEST_ASSERT(ulp_command_resp == RISCV_READ_WRITE_TEST);
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TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
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printf("data out: 0x%X, expected: 0x%X \n", ulp_riscv_test_data_out, test_data);
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TEST_ASSERT(test_data == ulp_riscv_test_data_out);
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/* Clear test data */
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ulp_main_cpu_command = RISCV_NO_COMMAND;
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2020-04-17 19:34:56 +00:00
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}
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TEST_CASE("ULP-RISC-V is able to wakeup main CPU from light sleep", "[ulp]")
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{
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struct timeval start, end;
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware();
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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/* Setup test data */
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ulp_main_cpu_command = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
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/* Enter Light Sleep */
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TEST_ASSERT(esp_light_sleep_start() == ESP_OK);
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/* Wait for wakeup from ULP RISC-V Coprocessor */
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TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_ULP);
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/* Wait till we receive the correct command response */
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gettimeofday(&start, NULL);
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while (ulp_command_resp != RISCV_LIGHT_SLEEP_WAKEUP_TEST)
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;
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gettimeofday(&end, NULL);
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printf("Response time %ld ms\n", (end.tv_sec - start.tv_sec) * 1000 + (end.tv_usec - start.tv_usec) / 1000);
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/* Verify test data */
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TEST_ASSERT(ulp_command_resp == RISCV_LIGHT_SLEEP_WAKEUP_TEST);
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TEST_ASSERT(ulp_main_cpu_reply == RISCV_COMMAND_OK);
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/* Clear test data */
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ulp_main_cpu_command = RISCV_NO_COMMAND;
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}
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TEST_CASE("ULP-RISC-V is able to wakeup main CPU from deep sleep", "[ulp][reset=SW_CPU_RESET][ignore]")
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{
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware();
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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/* Setup test data */
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ulp_main_cpu_command = RISCV_DEEP_SLEEP_WAKEUP_TEST;
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/* Enter Deep Sleep */
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esp_deep_sleep_start();
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UNITY_TEST_FAIL(__LINE__, "Should not get here!");
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2020-11-10 07:40:01 +00:00
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}
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static bool ulp_riscv_is_running(void)
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{
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uint32_t start_cnt = ulp_riscv_counter;
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/* Wait a few ULP wakeup cycles to ensure ULP has run */
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vTaskDelay((5 * ULP_WAKEUP_PERIOD / 1000) / portTICK_PERIOD_MS);
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uint32_t end_cnt = ulp_riscv_counter;
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printf("start run count: %d, end run count %d\n", start_cnt, end_cnt);
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/* If the ulp is running the counter should have been incremented */
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return (start_cnt != end_cnt);
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}
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TEST_CASE("ULP-RISC-V can be stopped and resumed from main CPU", "[ulp]")
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{
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware();
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TEST_ASSERT(ulp_riscv_is_running());
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printf("Stopping the ULP\n");
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ulp_riscv_timer_stop();
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ulp_riscv_halt();
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TEST_ASSERT(!ulp_riscv_is_running());
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printf("Resuming the ULP\n");
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ulp_riscv_timer_resume();
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TEST_ASSERT(ulp_riscv_is_running());
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}
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TEST_CASE("ULP-RISC-V can stop itself and be resumed from the main CPU", "[ulp]")
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{
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volatile riscv_test_commands_t *command_resp = &ulp_command_resp;
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/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
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load_and_start_ulp_firmware();
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TEST_ASSERT(ulp_riscv_is_running());
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printf("Stopping the ULP\n");
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/* Setup test data */
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ulp_main_cpu_command = RISCV_STOP_TEST;
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while (*command_resp != RISCV_STOP_TEST) {
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}
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/* Wait a bit to ensure ULP finished shutting down */
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vTaskDelay(100 / portTICK_PERIOD_MS);
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TEST_ASSERT(!ulp_riscv_is_running());
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printf("Resuming the ULP\n");
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ulp_main_cpu_command = RISCV_NO_COMMAND;
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ulp_riscv_timer_resume();
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TEST_ASSERT(ulp_riscv_is_running());
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}
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