From 0215694d80222bf03441842b7ae099245d3f7c55 Mon Sep 17 00:00:00 2001 From: Martin Date: Sun, 4 Nov 2018 02:05:47 +0100 Subject: [PATCH] Included sensor board KiCad files. --- electronics/encoder/custom_symbols.dcm | 3 + electronics/encoder/custom_symbols.lib | 60 +++ electronics/encoder/encoder-cache.lib | 144 +++++++ electronics/encoder/encoder.kicad_pcb | 495 +++++++++++++++++++++++++ electronics/encoder/encoder.net | 167 +++++++++ electronics/encoder/encoder.pro | 61 +++ electronics/encoder/encoder.sch | 244 ++++++++++++ 7 files changed, 1174 insertions(+) create mode 100644 electronics/encoder/custom_symbols.dcm create mode 100644 electronics/encoder/custom_symbols.lib create mode 100644 electronics/encoder/encoder-cache.lib create mode 100644 electronics/encoder/encoder.kicad_pcb create mode 100644 electronics/encoder/encoder.net create mode 100644 electronics/encoder/encoder.pro create mode 100644 electronics/encoder/encoder.sch diff --git a/electronics/encoder/custom_symbols.dcm b/electronics/encoder/custom_symbols.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/electronics/encoder/custom_symbols.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/electronics/encoder/custom_symbols.lib b/electronics/encoder/custom_symbols.lib new file mode 100644 index 0000000..db51e55 --- /dev/null +++ b/electronics/encoder/custom_symbols.lib @@ -0,0 +1,60 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# OPTO_NPN +# +DEF OPTO_NPN Q 0 0 Y Y 1 F N +F0 "Q" 150 50 50 H V L CNN +F1 "OPTO_NPN" 150 -100 50 H V L CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 2 0 1 0 0 0 75 -75 N +P 2 0 1 0 0 0 100 100 N +P 2 0 1 0 0 100 0 -100 N +P 5 0 1 0 -30 -50 -30 -30 -50 -50 -30 -50 -30 -50 N +P 5 0 1 0 50 -100 100 -100 100 -50 50 -100 50 -100 N +P 6 0 1 0 -110 10 -70 -30 -70 -10 -30 -50 -30 -50 -30 -50 N +P 6 0 1 0 -110 80 -70 40 -70 60 -30 20 -30 20 -30 20 N +P 6 0 1 0 -30 20 -30 40 -50 20 -30 20 -30 20 -30 20 N +X E 1 100 -200 100 U 40 40 1 1 P +X C 2 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# OPTO_NPNx2CC +# +DEF OPTO_NPNx2CC Q 0 0 Y Y 1 F N +F0 "Q" -250 0 50 H V L CNN +F1 "OPTO_NPNx2CC" 0 250 50 H V L CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +S -150 200 650 -150 0 1 0 N +P 2 0 1 0 0 0 75 -75 N +P 2 0 1 0 0 0 100 100 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 100 -100 100 -150 N +P 2 0 1 0 250 -150 250 150 N +P 2 0 1 0 400 -100 400 -150 N +P 2 0 1 0 500 0 400 100 N +P 2 0 1 0 500 0 425 -75 N +P 2 0 1 0 500 100 500 -100 N +P 4 0 1 0 400 100 400 150 100 150 100 100 N +P 5 0 1 0 -30 -50 -30 -30 -50 -50 -30 -50 -30 -50 N +P 5 0 1 0 50 -100 100 -100 100 -50 50 -100 50 -100 N +P 5 0 1 0 450 -100 400 -100 400 -50 450 -100 450 -100 N +P 5 0 1 0 530 -50 530 -30 550 -50 530 -50 530 -50 N +P 6 0 1 0 -110 10 -70 -30 -70 -10 -30 -50 -30 -50 -30 -50 N +P 6 0 1 0 -110 80 -70 40 -70 60 -30 20 -30 20 -30 20 N +P 6 0 1 0 -30 20 -30 40 -50 20 -30 20 -30 20 -30 20 N +P 6 0 1 0 530 20 530 40 550 20 530 20 530 20 530 20 N +P 6 0 1 0 610 10 570 -30 570 -10 530 -50 530 -50 530 -50 N +P 6 0 1 0 610 80 570 40 570 60 530 20 530 20 530 20 N +X E1 1 100 -250 100 U 40 40 1 1 P +X C 2 250 -250 100 U 40 40 1 1 P +X E2 3 400 -250 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/electronics/encoder/encoder-cache.lib b/electronics/encoder/encoder-cache.lib new file mode 100644 index 0000000..5754570 --- /dev/null +++ b/electronics/encoder/encoder-cache.lib @@ -0,0 +1,144 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CONN_01X04 +# +DEF CONN_01X04 P 0 40 Y N 1 F N +F0 "P" 0 250 50 H V C CNN +F1 "CONN_01X04" 100 0 50 V V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + Pin_Header_Straight_1X04 + Pin_Header_Angled_1X04 + Socket_Strip_Straight_1X04 + Socket_Strip_Angled_1X04 +$ENDFPLIST +DRAW +S -50 -145 10 -155 0 1 0 N +S -50 -45 10 -55 0 1 0 N +S -50 55 10 45 0 1 0 N +S -50 155 10 145 0 1 0 N +S -50 200 50 -200 0 1 0 N +X P1 1 -200 150 150 R 50 50 1 1 P +X P2 2 -200 50 150 R 50 50 1 1 P +X P3 3 -200 -50 150 R 50 50 1 1 P +X P4 4 -200 -150 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# LED +# +DEF LED D 0 40 Y N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "LED" 0 -100 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + LED-3MM + LED-5MM + LED-10MM + LED-0603 + LED-0805 + LED-1206 + LEDV +$ENDFPLIST +DRAW +P 2 0 1 0 -50 50 -50 -50 N +P 3 0 1 0 -80 -25 -125 -65 -120 -40 N +P 3 0 1 0 -65 -40 -110 -80 -105 -55 N +P 3 0 1 0 50 50 -50 0 50 -50 F +X K 1 -200 0 150 R 40 40 1 1 P +X A 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# OPTO_NPN +# +DEF OPTO_NPN Q 0 0 Y Y 1 F N +F0 "Q" 150 50 50 H V L CNN +F1 "OPTO_NPN" 150 -100 50 H V L CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 2 0 1 0 0 0 75 -75 N +P 2 0 1 0 0 0 100 100 N +P 2 0 1 0 0 100 0 -100 N +P 5 0 1 0 -30 -50 -30 -30 -50 -50 -30 -50 -30 -50 N +P 5 0 1 0 50 -100 100 -100 100 -50 50 -100 50 -100 N +P 6 0 1 0 -110 10 -70 -30 -70 -10 -30 -50 -30 -50 -30 -50 N +P 6 0 1 0 -110 80 -70 40 -70 60 -30 20 -30 20 -30 20 N +P 6 0 1 0 -30 20 -30 40 -50 20 -30 20 -30 20 -30 20 N +X E 1 100 -200 100 U 40 40 1 1 P +X C 2 100 200 100 D 40 40 1 1 P +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# VCC +# +DEF VCC #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VCC" 0 150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VCC 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/electronics/encoder/encoder.kicad_pcb b/electronics/encoder/encoder.kicad_pcb new file mode 100644 index 0000000..a6ab5cb --- /dev/null +++ b/electronics/encoder/encoder.kicad_pcb @@ -0,0 +1,495 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-stable) + + (general + (links 15) + (no_connects 1) + (area 144.751667 94.125 182.121525 119.085) + (thickness 1.6) + (drawings 7) + (tracks 51) + (zones 0) + (modules 11) + (nets 6) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (user_trace_width 1) + (user_trace_width 1.5) + (trace_clearance 0.2) + (zone_clearance 1) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x00030_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 VCC) + (net 3 "Net-(C1-Pad2)") + (net 4 "Net-(D1-Pad1)") + (net 5 "Net-(C2-Pad2)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net GND) + (add_net "Net-(C1-Pad2)") + (add_net "Net-(C2-Pad2)") + (add_net "Net-(D1-Pad1)") + (add_net VCC) + ) + + (module Capacitors_ThroughHole:C_Rect_L4_W2.5_P2.5 (layer F.Cu) (tedit 5BD9B96D) (tstamp 5BD8E105) + (at 176.53 105.156 270) + (descr "Film Capacitor Length 4mm x Width 2.5mm, Pitch 2.5mm") + (tags Capacitor) + (path /5BD8CD2E) + (fp_text reference D1 (at 5.08 0 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value LED (at 1.25 2.5 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1 -1.5) (end 3.5 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.5 -1.5) (end 3.5 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.5 1.5) (end -1 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 1.5) (end -1 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.75 -1.25) (end 3.25 -1.25) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.75 1.25) (end 3.25 1.25) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 270) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask F.SilkS) + (net 4 "Net-(D1-Pad1)")) + (pad 2 thru_hole circle (at 2.5 0 270) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask F.SilkS) + (net 2 VCC)) + ) + + (module Pin_Headers:Pin_Header_Straight_1x04 (layer F.Cu) (tedit 5BD9B98A) (tstamp 5BD8E10D) + (at 149.86 102.87) + (descr "Through hole pin header") + (tags "pin header") + (path /5BD8CDB1) + (fp_text reference P1 (at 2.54 3.81) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X04 (at 0 -3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.75 -1.75) (end 1.75 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 9.4) (end 1.75 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.27 1.27) (end -1.27 8.89) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 8.89) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 8.89) (end 1.27 8.89) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 2 VCC)) + (pad 2 thru_hole oval (at 0 2.54) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 3 thru_hole oval (at 0 5.08) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 "Net-(C1-Pad2)")) + (pad 4 thru_hole oval (at 0 7.62) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 5 "Net-(C2-Pad2)")) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x04.wrl + (at (xyz 0 -0.15 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Resistors_ThroughHole:Resistor_Horizontal_RM7mm (layer F.Cu) (tedit 5BD9BBEB) (tstamp 5BD8E11A) + (at 160.02 110.49 90) + (descr "Resistor, Axial, RM 7.62mm, 1/3W,") + (tags "Resistor Axial RM 7.62mm 1/3W R3") + (path /5BD8D7EA) + (fp_text reference R1 (at -2.54 0 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 10K (at 3.81 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.25 -1.5) (end 8.85 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.25 1.5) (end -1.25 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.85 -1.5) (end 8.85 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.25 1.5) (end 8.85 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 6.35 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 6.35 -1.27) (end 6.35 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 6.35 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at 0 0 90) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 5 "Net-(C2-Pad2)")) + (pad 2 thru_hole circle (at 7.62 0 90) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 1 GND)) + ) + + (module Resistors_ThroughHole:Resistor_Horizontal_RM7mm (layer F.Cu) (tedit 5BD9B980) (tstamp 5BD8E120) + (at 157.48 110.49 90) + (descr "Resistor, Axial, RM 7.62mm, 1/3W,") + (tags "Resistor Axial RM 7.62mm 1/3W R3") + (path /5BD8DF5F) + (fp_text reference R2 (at -2.54 0 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 10K (at 3.81 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.25 -1.5) (end 8.85 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.25 1.5) (end -1.25 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.85 -1.5) (end 8.85 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.25 1.5) (end 8.85 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 6.35 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 6.35 -1.27) (end 6.35 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 6.35 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at 0 0 90) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 3 "Net-(C1-Pad2)")) + (pad 2 thru_hole circle (at 7.62 0 90) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 1 GND)) + ) + + (module Resistors_ThroughHole:Resistor_Horizontal_RM7mm (layer F.Cu) (tedit 5BD9B97C) (tstamp 5BD8E126) + (at 162.56 110.49 90) + (descr "Resistor, Axial, RM 7.62mm, 1/3W,") + (tags "Resistor Axial RM 7.62mm 1/3W R3") + (path /5BD8D87B) + (fp_text reference R3 (at -2.54 0 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 550R (at 3.81 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.25 -1.5) (end 8.85 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.25 1.5) (end -1.25 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.85 -1.5) (end 8.85 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.25 1.5) (end 8.85 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 6.35 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 6.35 -1.27) (end 6.35 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 6.35 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at 0 0 90) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 4 "Net-(D1-Pad1)")) + (pad 2 thru_hole circle (at 7.62 0 90) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 1 GND)) + ) + + (module Capacitors_ThroughHole:C_Disc_D3_P2.5 (layer F.Cu) (tedit 5BDE4303) (tstamp 5BD9B176) + (at 166.37 105.918 90) + (descr "Capacitor 3mm Disc, Pitch 2.5mm") + (tags Capacitor) + (path /5BD8EEC4) + (fp_text reference C1 (at 4.572 0 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 100n (at 1.25 2.5 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.9 -1.5) (end 3.4 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 -1.5) (end 3.4 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 1.5) (end -0.9 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.9 1.5) (end -0.9 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.25 -1.25) (end 2.75 -1.25) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.75 1.25) (end -0.25 1.25) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 2 VCC)) + (pad 2 thru_hole circle (at 2.5 0 90) (size 1.3 1.3) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 3 "Net-(C1-Pad2)")) + (model Capacitors_ThroughHole.3dshapes/C_Disc_D3_P2.5.wrl + (at (xyz 0.0492126 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_ThroughHole:C_Disc_D3_P2.5 (layer F.Cu) (tedit 5BDE42F6) (tstamp 5BDC84AA) + (at 170.18 105.41 90) + (descr "Capacitor 3mm Disc, Pitch 2.5mm") + (tags Capacitor) + (path /5BDC923E) + (fp_text reference Q2 (at 1.27 2.286 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value OPTO_NPN (at 1.25 2.5 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.9 -1.5) (end 3.4 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 -1.5) (end 3.4 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 1.5) (end -0.9 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.9 1.5) (end -0.9 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.25 -1.25) (end 2.75 -1.25) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.75 1.25) (end -0.25 1.25) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 3 "Net-(C1-Pad2)")) + (pad 2 thru_hole circle (at 2.5 0 90) (size 1.3 1.3) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 2 VCC)) + (model Capacitors_ThroughHole.3dshapes/C_Disc_D3_P2.5.wrl + (at (xyz 0.0492126 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_ThroughHole:C_Disc_D3_P2.5 (layer F.Cu) (tedit 5BDE42FB) (tstamp 5BDC84E6) + (at 170.18 109.855 90) + (descr "Capacitor 3mm Disc, Pitch 2.5mm") + (tags Capacitor) + (path /5BDC9202) + (fp_text reference Q1 (at 1.397 2.032 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value OPTO_NPN (at 1.25 2.5 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.9 -1.5) (end 3.4 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 -1.5) (end 3.4 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 1.5) (end -0.9 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.9 1.5) (end -0.9 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.25 -1.25) (end 2.75 -1.25) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.75 1.25) (end -0.25 1.25) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 5 "Net-(C2-Pad2)")) + (pad 2 thru_hole circle (at 2.5 0 90) (size 1.3 1.3) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 2 VCC)) + (model Capacitors_ThroughHole.3dshapes/C_Disc_D3_P2.5.wrl + (at (xyz 0.0492126 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_ThroughHole:C_Disc_D3_P2.5 (layer F.Cu) (tedit 5BDE4308) (tstamp 5BDC8C0E) + (at 166.37 107.188 270) + (descr "Capacitor 3mm Disc, Pitch 2.5mm") + (tags Capacitor) + (path /5BDC9426) + (fp_text reference C2 (at 4.572 -0.254 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 100n (at 1.25 2.5 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.9 -1.5) (end 3.4 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 -1.5) (end 3.4 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.4 1.5) (end -0.9 1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.9 1.5) (end -0.9 -1.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.25 -1.25) (end 2.75 -1.25) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.75 1.25) (end -0.25 1.25) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 2 VCC)) + (pad 2 thru_hole circle (at 2.5 0 270) (size 1.3 1.3) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 5 "Net-(C2-Pad2)")) + (model Capacitors_ThroughHole.3dshapes/C_Disc_D3_P2.5.wrl + (at (xyz 0.0492126 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Wire_Pads:SolderWirePad_single_1-5mmDrill (layer F.Cu) (tedit 5BDE4324) (tstamp 5BDC8D4C) + (at 169.672 99.06) + (fp_text reference REF** (at 0.254 0) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value SolderWirePad_single_1-5mmDrill (at -0.635 3.81) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole circle (at 0 0) (size 4.0005 4.0005) (drill 1.50114) (layers *.Cu *.Mask F.SilkS)) + ) + + (module Wire_Pads:SolderWirePad_single_1-5mmDrill (layer F.Cu) (tedit 5BDE4321) (tstamp 5BDC8D56) + (at 169.672 114.3) + (fp_text reference REF** (at 0.762 0) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value SolderWirePad_single_1-5mmDrill (at -0.635 3.81) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole circle (at 0 0) (size 4.0005 4.0005) (drill 1.50114) (layers *.Cu *.Mask F.SilkS)) + ) + + (gr_line (start 148.59 115.57) (end 148.59 115.316) (angle 90) (layer F.SilkS) (width 0.2)) + (gr_line (start 179.578 115.57) (end 148.59 115.57) (angle 90) (layer F.SilkS) (width 0.2)) + (gr_line (start 179.578 97.79) (end 148.59 97.79) (angle 90) (layer F.SilkS) (width 0.2)) + (gr_line (start 148.59 115.57) (end 148.59 97.79) (angle 90) (layer F.SilkS) (width 0.2)) + (gr_line (start 179.578 97.79) (end 179.578 115.57) (angle 90) (layer F.SilkS) (width 0.2)) + (gr_circle (center 169.672 99.06) (end 169.672 100.33) (layer F.SilkS) (width 0.2)) + (gr_circle (center 169.672 114.3) (end 170.942 114.3) (layer F.SilkS) (width 0.2)) + + (segment (start 149.86 105.41) (end 154.94 105.41) (width 1.5) (layer B.Cu) (net 1)) + (segment (start 154.94 105.41) (end 157.48 102.87) (width 1.5) (layer B.Cu) (net 1) (tstamp 5BDC6BAC)) + (segment (start 162.56 102.87) (end 160.02 102.87) (width 1.5) (layer B.Cu) (net 1)) + (segment (start 160.02 102.87) (end 157.48 102.87) (width 1.5) (layer B.Cu) (net 1) (tstamp 5BDC6B15)) + (segment (start 153.416 102.87) (end 149.86 102.87) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A8D)) + (segment (start 170.18 101.346) (end 164.338 101.346) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8AA5)) + (segment (start 164.338 101.346) (end 163.576 100.584) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A79)) + (segment (start 163.576 100.584) (end 155.702 100.584) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A7F)) + (segment (start 155.702 100.584) (end 153.416 102.87) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A86)) + (segment (start 166.37 105.918) (end 166.37 107.188) (width 1) (layer B.Cu) (net 2)) + (segment (start 170.18 107.355) (end 166.537 107.355) (width 1.5) (layer B.Cu) (net 2)) + (segment (start 166.537 107.355) (end 166.37 107.188) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8C59)) + (segment (start 170.18 102.91) (end 170.18 101.346) (width 1.5) (layer B.Cu) (net 2)) + (segment (start 170.18 101.346) (end 170.18 101.6) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8AA2)) + (segment (start 170.18 101.6) (end 170.18 101.346) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8AA4)) + (segment (start 176.53 107.656) (end 174.712 107.656) (width 1.5) (layer B.Cu) (net 2)) + (segment (start 171.45 101.346) (end 170.18 101.346) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A76)) + (segment (start 172.72 102.616) (end 171.45 101.346) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A71)) + (segment (start 172.72 105.664) (end 172.72 102.616) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A6E)) + (segment (start 174.712 107.656) (end 172.72 105.664) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC8A66)) + (segment (start 170.18 107.355) (end 171.537 107.355) (width 1.5) (layer B.Cu) (net 2)) + (segment (start 171.537 107.355) (end 172.974 105.918) (width 1.5) (layer B.Cu) (net 2) (tstamp 5BDC89D7)) + (segment (start 166.37 103.418) (end 167.426 103.418) (width 1) (layer B.Cu) (net 3)) + (segment (start 169.418 105.41) (end 170.18 105.41) (width 1) (layer B.Cu) (net 3) (tstamp 5BDC8CB4)) + (segment (start 167.426 103.418) (end 169.418 105.41) (width 1) (layer B.Cu) (net 3) (tstamp 5BDC8CB1)) + (segment (start 166.37 103.418) (end 165.822 103.418) (width 1.5) (layer B.Cu) (net 3)) + (segment (start 165.822 103.418) (end 165.1 104.14) (width 1.5) (layer B.Cu) (net 3) (tstamp 5BDC8C87)) + (segment (start 165.1 104.14) (end 163.83 105.41) (width 1.5) (layer B.Cu) (net 3) (tstamp 5BD9B92E)) + (segment (start 157.48 107.95) (end 160.02 105.41) (width 1.5) (layer B.Cu) (net 3) (tstamp 5BDC6AE0)) + (segment (start 160.02 105.41) (end 163.83 105.41) (width 1.5) (layer B.Cu) (net 3) (tstamp 5BDC6AE2)) + (segment (start 149.86 107.95) (end 157.48 107.95) (width 1.5) (layer B.Cu) (net 3)) + (segment (start 157.48 110.49) (end 157.48 107.95) (width 1.5) (layer B.Cu) (net 3)) + (segment (start 162.56 110.49) (end 163.576 110.49) (width 1.5) (layer B.Cu) (net 4)) + (segment (start 177.292 105.156) (end 176.53 105.156) (width 1.5) (layer B.Cu) (net 4) (tstamp 5BDC8A5F)) + (segment (start 178.562 106.426) (end 177.292 105.156) (width 1.5) (layer B.Cu) (net 4) (tstamp 5BDC8A5C)) + (segment (start 178.562 110.49) (end 178.562 106.426) (width 1.5) (layer B.Cu) (net 4) (tstamp 5BDC8A57)) + (segment (start 177.038 112.014) (end 178.562 110.49) (width 1.5) (layer B.Cu) (net 4) (tstamp 5BDC8A52)) + (segment (start 165.1 112.014) (end 177.038 112.014) (width 1.5) (layer B.Cu) (net 4) (tstamp 5BDC8A4B)) + (segment (start 163.576 110.49) (end 165.1 112.014) (width 1.5) (layer B.Cu) (net 4) (tstamp 5BDC8A46)) + (segment (start 166.37 109.688) (end 167.6 109.688) (width 0.25) (layer F.Cu) (net 5)) + (segment (start 167.6 109.688) (end 167.64 109.728) (width 0.25) (layer F.Cu) (net 5) (tstamp 5BDE4351)) + (segment (start 170.18 109.855) (end 165.735 109.855) (width 1) (layer B.Cu) (net 5)) + (segment (start 160.02 108.712) (end 160.02 110.49) (width 1) (layer B.Cu) (net 5) (tstamp 5BDC8A0E)) + (segment (start 161.036 107.696) (end 160.02 108.712) (width 1) (layer B.Cu) (net 5) (tstamp 5BDC8A0B)) + (segment (start 163.576 107.696) (end 161.036 107.696) (width 1) (layer B.Cu) (net 5) (tstamp 5BDC8A09)) + (segment (start 165.735 109.855) (end 163.576 107.696) (width 1) (layer B.Cu) (net 5) (tstamp 5BDC8A03)) + (segment (start 149.86 110.49) (end 153.67 110.49) (width 1.5) (layer B.Cu) (net 5)) + (segment (start 160.02 111.76) (end 160.02 110.49) (width 1.5) (layer B.Cu) (net 5) (tstamp 5BDC6BBD)) + (segment (start 158.75 113.03) (end 160.02 111.76) (width 1.5) (layer B.Cu) (net 5) (tstamp 5BDC6BBB)) + (segment (start 156.21 113.03) (end 158.75 113.03) (width 1.5) (layer B.Cu) (net 5) (tstamp 5BDC6BB9)) + (segment (start 153.67 110.49) (end 156.21 113.03) (width 1.5) (layer B.Cu) (net 5) (tstamp 5BDC6BB5)) + + (zone (net 5) (net_name "Net-(C2-Pad2)") (layer B.Cu) (tstamp 5BD9BB89) (hatch edge 0.508) + (connect_pads yes (clearance 1)) + (min_thickness 0.254) + (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 162.56 116.84) (xy 148.59 116.84) (xy 148.59 110.49) (xy 162.56 110.49) (xy 162.56 114.3) + ) + ) + (filled_polygon + (pts + (xy 155.353142 110.911129) (xy 155.676199 111.692986) (xy 156.273868 112.291699) (xy 157.055159 112.61612) (xy 157.901129 112.616858) + (xy 158.682986 112.293801) (xy 159.281699 111.696132) (xy 159.60612 110.914841) (xy 159.60638 110.617) (xy 160.433399 110.617) + (xy 160.433142 110.911129) (xy 160.756199 111.692986) (xy 161.353868 112.291699) (xy 162.135159 112.61612) (xy 162.433 112.61638) + (xy 162.433 116.713) (xy 148.717 116.713) (xy 148.717 110.617) (xy 155.353399 110.617) + ) + ) + ) + (zone (net 2) (net_name VCC) (layer B.Cu) (tstamp 5BD9B9CD) (hatch edge 0.508) + (connect_pads yes (clearance 1)) + (min_thickness 0.254) + (fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 179.578 116.84) (xy 172.466 116.84) (xy 172.466 106.68) (xy 172.466 102.87) (xy 170.18 101.6) + (xy 163.83 101.6) (xy 162.56 100.33) (xy 156.379333 100.33) (xy 154.686 102.87) (xy 148.59 102.87) + (xy 148.59 96.52) (xy 179.578 96.52) (xy 179.578 109.22) + ) + ) + (filled_polygon + (pts + (xy 179.451 104.660521) (xy 178.619239 103.828761) (xy 178.010297 103.421878) (xy 177.990801 103.418) (xy 177.292 103.279) + (xy 176.53 103.279) (xy 175.811703 103.421878) (xy 175.796491 103.432043) (xy 175.512359 103.485506) (xy 175.128781 103.732331) + (xy 174.871452 104.108944) (xy 174.80879 104.418379) (xy 174.795878 104.437703) (xy 174.653 105.156) (xy 174.795878 105.874297) + (xy 174.806043 105.889509) (xy 174.859506 106.173641) (xy 175.106331 106.557219) (xy 175.482944 106.814548) (xy 175.792379 106.87721) + (xy 175.811703 106.890122) (xy 176.510678 107.029157) (xy 176.685 107.203479) (xy 176.685 109.712521) (xy 176.260522 110.137) + (xy 172.593 110.137) (xy 172.593 102.87) (xy 172.582994 102.82059) (xy 172.554553 102.778965) (xy 172.527677 102.758982) + (xy 170.984204 101.901497) (xy 171.44113 101.712699) (xy 172.321607 100.833757) (xy 172.798706 99.684777) (xy 172.799791 98.440681) + (xy 172.324699 97.29087) (xy 171.681952 96.647) (xy 179.451 96.647) + ) + ) + (filled_polygon + (pts + (xy 167.022393 97.286243) (xy 166.545294 98.435223) (xy 166.544209 99.679319) (xy 167.019301 100.82913) (xy 167.662048 101.473) + (xy 164.170125 101.473) (xy 163.766132 101.068301) (xy 163.27324 100.863634) (xy 162.649803 100.240197) (xy 162.607789 100.212334) + (xy 162.56 100.203) (xy 156.379333 100.203) (xy 156.329923 100.213006) (xy 156.273663 100.259553) (xy 154.618032 102.743) + (xy 148.717 102.743) (xy 148.717 96.647) (xy 167.662752 96.647) + ) + ) + ) +) diff --git a/electronics/encoder/encoder.net b/electronics/encoder/encoder.net new file mode 100644 index 0000000..22207e0 --- /dev/null +++ b/electronics/encoder/encoder.net @@ -0,0 +1,167 @@ +(export (version D) + (design + (source ./encoder.sch) + (date "4 nov 2018, 00:52:40") + (tool "Eeschema 4.0.2+dfsg1-stable") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title Encoder_board) + (company) + (rev 1) + (date) + (source encoder.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref D1) + (value IR_LED) + (footprint Capacitors_ThroughHole:C_Rect_L4_W2.5_P2.5) + (libsource (lib device) (part LED)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BD8CD2E)) + (comp (ref P1) + (value CONN_01X04) + (footprint Pin_Headers:Pin_Header_Straight_1x04) + (libsource (lib conn) (part CONN_01X04)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BD8CDB1)) + (comp (ref R1) + (value 2-10K) + (footprint Resistors_ThroughHole:Resistor_Horizontal_RM7mm) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BD8D7EA)) + (comp (ref R3) + (value 150-550R) + (footprint Resistors_ThroughHole:Resistor_Horizontal_RM7mm) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BD8D87B)) + (comp (ref R2) + (value 2-10K) + (footprint Resistors_ThroughHole:Resistor_Horizontal_RM7mm) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BD8DF5F)) + (comp (ref C1) + (value 100n) + (footprint Capacitors_ThroughHole:C_Disc_D3_P2.5) + (libsource (lib device) (part C)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BD8EEC4)) + (comp (ref Q1) + (value OPTO_NPN) + (footprint Capacitors_ThroughHole:C_Disc_D3_P2.5) + (libsource (lib custom_symbols) (part OPTO_NPN)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BDC9202)) + (comp (ref Q2) + (value OPTO_NPN) + (footprint Capacitors_ThroughHole:C_Disc_D3_P2.5) + (libsource (lib custom_symbols) (part OPTO_NPN)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BDC923E)) + (comp (ref C2) + (value 100n) + (footprint Capacitors_ThroughHole:C_Disc_D3_P2.5) + (libsource (lib device) (part C)) + (sheetpath (names /) (tstamps /)) + (tstamp 5BDC9426))) + (libparts + (libpart (lib device) (part C) + (description "Unpolarized capacitor") + (footprints + (fp C?) + (fp C_????_*) + (fp C_????) + (fp SMD*_c) + (fp Capacitor*)) + (fields + (field (name Reference) C) + (field (name Value) C)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive)))) + (libpart (lib conn) (part CONN_01X04) + (description "Connector 01x04") + (footprints + (fp Pin_Header_Straight_1X04) + (fp Pin_Header_Angled_1X04) + (fp Socket_Strip_Straight_1X04) + (fp Socket_Strip_Angled_1X04)) + (fields + (field (name Reference) P) + (field (name Value) CONN_01X04)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)))) + (libpart (lib device) (part LED) + (footprints + (fp LED-3MM) + (fp LED-5MM) + (fp LED-10MM) + (fp LED-0603) + (fp LED-0805) + (fp LED-1206) + (fp LEDV)) + (fields + (field (name Reference) D) + (field (name Value) LED)) + (pins + (pin (num 1) (name K) (type passive)) + (pin (num 2) (name A) (type passive)))) + (libpart (lib custom_symbols) (part OPTO_NPN) + (fields + (field (name Reference) Q) + (field (name Value) OPTO_NPN)) + (pins + (pin (num 1) (name E) (type passive)) + (pin (num 2) (name C) (type passive)))) + (libpart (lib device) (part R) + (description Resistor) + (footprints + (fp R_*) + (fp Resistor_*)) + (fields + (field (name Reference) R) + (field (name Value) R)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive))))) + (libraries + (library (logical conn) + (uri /usr/share/kicad/library/conn.lib)) + (library (logical device) + (uri /usr/share/kicad/library/device.lib)) + (library (logical custom_symbols) + (uri custom_symbols.lib))) + (nets + (net (code 1) (name VCC) + (node (ref D1) (pin 2)) + (node (ref P1) (pin 1)) + (node (ref C2) (pin 1)) + (node (ref Q2) (pin 2)) + (node (ref Q1) (pin 2)) + (node (ref C1) (pin 1))) + (net (code 2) (name "Net-(C1-Pad2)") + (node (ref R2) (pin 1)) + (node (ref P1) (pin 3)) + (node (ref C1) (pin 2)) + (node (ref Q2) (pin 1))) + (net (code 3) (name "Net-(C2-Pad2)") + (node (ref C2) (pin 2)) + (node (ref P1) (pin 4)) + (node (ref R1) (pin 1)) + (node (ref Q1) (pin 1))) + (net (code 4) (name "Net-(D1-Pad1)") + (node (ref R3) (pin 1)) + (node (ref D1) (pin 1))) + (net (code 5) (name GND) + (node (ref R2) (pin 2)) + (node (ref R3) (pin 2)) + (node (ref R1) (pin 2)) + (node (ref P1) (pin 2))))) diff --git a/electronics/encoder/encoder.pro b/electronics/encoder/encoder.pro new file mode 100644 index 0000000..58ecbb8 --- /dev/null +++ b/electronics/encoder/encoder.pro @@ -0,0 +1,61 @@ +update=2 nov 2018, 18:12:50 +version=1 +last_client=kicad +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[general] +version=1 +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=custom_symbols +LibName2=power +LibName3=device +LibName4=transistors +LibName5=conn +LibName6=linear +LibName7=regul +LibName8=74xx +LibName9=cmos4000 +LibName10=adc-dac +LibName11=memory +LibName12=xilinx +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves diff --git a/electronics/encoder/encoder.sch b/electronics/encoder/encoder.sch new file mode 100644 index 0000000..cb91bb7 --- /dev/null +++ b/electronics/encoder/encoder.sch @@ -0,0 +1,244 @@ +EESchema Schematic File Version 2 +LIBS:custom_symbols +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:encoder-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "Encoder_board" +Date "" +Rev "1" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L LED D1 +U 1 1 5BD8CD2E +P 6400 3500 +F 0 "D1" H 6400 3600 50 0000 C CNN +F 1 "IR_LED" H 6400 3400 50 0000 C CNN +F 2 "Capacitors_ThroughHole:C_Rect_L4_W2.5_P2.5" H 6400 3500 50 0001 C CNN +F 3 "" H 6400 3500 50 0000 C CNN + 1 6400 3500 + 0 -1 -1 0 +$EndComp +$Comp +L CONN_01X04 P1 +U 1 1 5BD8CDB1 +P 4300 4200 +F 0 "P1" H 4300 4450 50 0000 C CNN +F 1 "CONN_01X04" V 4400 4200 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x04" H 4300 4200 50 0001 C CNN +F 3 "" H 4300 4200 50 0000 C CNN + 1 4300 4200 + -1 0 0 1 +$EndComp +$Comp +L R R1 +U 1 1 5BD8D7EA +P 5050 4400 +F 0 "R1" V 5130 4400 50 0000 C CNN +F 1 "2-10K" V 4950 4400 50 0000 C CNN +F 2 "Resistors_ThroughHole:Resistor_Horizontal_RM7mm" V 4980 4400 50 0001 C CNN +F 3 "" H 5050 4400 50 0000 C CNN + 1 5050 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R3 +U 1 1 5BD8D87B +P 6400 3850 +F 0 "R3" V 6480 3850 50 0000 C CNN +F 1 "150-550R" V 6300 3850 50 0000 C CNN +F 2 "Resistors_ThroughHole:Resistor_Horizontal_RM7mm" V 6330 3850 50 0001 C CNN +F 3 "" H 6400 3850 50 0000 C CNN + 1 6400 3850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5BD8DBD5 +P 6400 4000 +F 0 "#PWR01" H 6400 3750 50 0001 C CNN +F 1 "GND" H 6400 3850 50 0000 C CNN +F 2 "" H 6400 4000 50 0000 C CNN +F 3 "" H 6400 4000 50 0000 C CNN + 1 6400 4000 + 1 0 0 -1 +$EndComp +$Comp +L VCC #PWR02 +U 1 1 5BD8DDCA +P 6400 3300 +F 0 "#PWR02" H 6400 3150 50 0001 C CNN +F 1 "VCC" H 6400 3450 50 0000 C CNN +F 2 "" H 6400 3300 50 0000 C CNN +F 3 "" H 6400 3300 50 0000 C CNN + 1 6400 3300 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 5BD8DF5F +P 5550 4400 +F 0 "R2" V 5630 4400 50 0000 C CNN +F 1 "2-10K" V 5450 4400 50 0000 C CNN +F 2 "Resistors_ThroughHole:Resistor_Horizontal_RM7mm" V 5480 4400 50 0001 C CNN +F 3 "" H 5550 4400 50 0000 C CNN + 1 5550 4400 + 1 0 0 -1 +$EndComp +$Comp +L VCC #PWR03 +U 1 1 5BD8E190 +P 4750 3300 +F 0 "#PWR03" H 4750 3150 50 0001 C CNN +F 1 "VCC" H 4750 3450 50 0000 C CNN +F 2 "" H 4750 3300 50 0000 C CNN +F 3 "" H 4750 3300 50 0000 C CNN + 1 4750 3300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 5BD8E62D +P 5050 4650 +F 0 "#PWR04" H 5050 4400 50 0001 C CNN +F 1 "GND" H 5050 4500 50 0000 C CNN +F 2 "" H 5050 4650 50 0000 C CNN +F 3 "" H 5050 4650 50 0000 C CNN + 1 5050 4650 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 5BD8EEC4 +P 5950 3450 +F 0 "C1" H 5975 3550 50 0000 L CNN +F 1 "100n" H 5975 3350 50 0000 L CNN +F 2 "Capacitors_ThroughHole:C_Disc_D3_P2.5" H 5988 3300 50 0001 C CNN +F 3 "" H 5950 3450 50 0000 C CNN + 1 5950 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5550 3800 5550 4250 +Wire Wire Line + 5050 3800 5050 4250 +Wire Wire Line + 5050 4550 5050 4650 +Wire Wire Line + 5550 4650 5550 4550 +Wire Wire Line + 4500 4150 5950 4150 +Connection ~ 5050 4650 +Wire Wire Line + 4500 4250 4850 4250 +Wire Wire Line + 4850 4250 4850 4650 +Wire Wire Line + 5300 3300 5300 3950 +Wire Wire Line + 4850 4650 5550 4650 +Wire Wire Line + 5300 3950 4750 3950 +Wire Wire Line + 4750 3300 4750 4350 +Wire Wire Line + 4750 4350 4500 4350 +Connection ~ 4750 3950 +Wire Wire Line + 5950 4150 5950 3600 +$Comp +L VCC #PWR05 +U 1 1 5BD9B2BD +P 5950 3300 +F 0 "#PWR05" H 5950 3150 50 0001 C CNN +F 1 "VCC" H 5950 3450 50 0000 C CNN +F 2 "" H 5950 3300 50 0000 C CNN +F 3 "" H 5950 3300 50 0000 C CNN + 1 5950 3300 + 1 0 0 -1 +$EndComp +Connection ~ 5550 4150 +Wire Wire Line + 5050 4050 4500 4050 +Connection ~ 5050 4050 +Wire Wire Line + 5050 3400 5050 3300 +Wire Wire Line + 5050 3300 5550 3300 +Wire Wire Line + 5550 3300 5550 3400 +Connection ~ 5300 3300 +$Comp +L OPTO_NPN Q1 +U 1 1 5BDC9202 +P 4950 3600 +F 0 "Q1" H 5100 3650 50 0000 L CNN +F 1 "OPTO_NPN" H 5050 3400 50 0000 L CNN +F 2 "Capacitors_ThroughHole:C_Disc_D3_P2.5" H 4950 3600 50 0001 C CNN +F 3 "" H 4950 3600 50 0000 C CNN + 1 4950 3600 + 1 0 0 -1 +$EndComp +$Comp +L OPTO_NPN Q2 +U 1 1 5BDC923E +P 5450 3600 +F 0 "Q2" H 5600 3650 50 0000 L CNN +F 1 "OPTO_NPN" H 5550 3400 50 0000 L CNN +F 2 "Capacitors_ThroughHole:C_Disc_D3_P2.5" H 5450 3600 50 0001 C CNN +F 3 "" H 5450 3600 50 0000 C CNN + 1 5450 3600 + 1 0 0 -1 +$EndComp +$Comp +L C C2 +U 1 1 5BDC9426 +P 4500 3450 +F 0 "C2" H 4525 3550 50 0000 L CNN +F 1 "100n" H 4525 3350 50 0000 L CNN +F 2 "Capacitors_ThroughHole:C_Disc_D3_P2.5" H 4538 3300 50 0001 C CNN +F 3 "" H 4500 3450 50 0000 C CNN + 1 4500 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 4050 4500 3600 +Wire Wire Line + 4500 3300 4750 3300 +$EndSCHEMATC