kopia lustrzana https://github.com/softcomplex/digirig
rev 1.5
- smaller footprint crystals - full re-layout... again - back to 40mm long PCB - non-inverting open collector drivers for RST/DTS linesusb-c
rodzic
edc93dd217
commit
5597985c42
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@ -37,7 +37,7 @@ F1 "CM108" -500 -50 50 H V L CNN
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F2 "" -400 50 50 H I C CNN
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F3 "" -400 50 50 H I C CNN
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DRAW
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S -500 -100 1400 -2100 0 1 0 N
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S -500 -100 1400 -2100 0 1 0 f
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X SPDIFO 1 750 0 100 D 50 50 0 0 O
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X MODE 10 -600 -1700 100 R 50 50 0 0 I
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X GPIO2 11 1500 -1000 100 L 50 50 0 0 B
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@ -153,7 +153,7 @@ F1 "USB2412-DZK-TR" 100 1500 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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P 5 0 1 0 -1000 1450 0 1450 0 -600 -1000 -600 -1000 1450 N
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P 5 0 1 0 -1000 1450 0 1450 0 -600 -1000 -600 -1000 1450 f
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X USBDN1_DP 1 100 900 100 L 50 50 1 1 B
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X VDD3V4 10 -600 1550 100 D 50 50 1 1 W
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X PRTPWR2 11 100 250 100 L 50 50 1 1 O
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@ -1,31 +0,0 @@
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Reference, Quantity, Value, Footprint, Datasheet
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C1 C5 C14 C15 C17 ,5,"100nF","Capacitor_SMD:C_0402_1005Metric","~"
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C2 C3 C7 C8 ,4,"27pF","Capacitor_SMD:C_0402_1005Metric","~"
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C4 C6 C9 C10 C11 C12 C13 C16 ,8,"10uF","Capacitor_SMD:C_0402_1005Metric","~"
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J1 ,1,"USB_C_Receptacle_USB2.0","Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12","https://www.usb.org/sites/default/files/documents/usb_type-c.zip"
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J2 ,1,"Audio","footprints:jack_3.5_pj313d-smt","~"
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J3 ,1,"Serial","footprints:jack_3.5_pj313d-smt","~"
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JP1 JP2 ,2,"SolderJumper_3_Bridged12","footprints:SolderJumper-BCu","~"
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L1 ,1,"LOGO","footprints:digirig-logo-6mm",""
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R1 R4 R5 R6 ,4,"100K","Resistor_SMD:R_0402_1005Metric","~"
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R11 ,1,"27K","Resistor_SMD:R_0402_1005Metric","~"
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R7 R12 ,2,"1M","Resistor_SMD:R_0402_1005Metric","~"
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R13 R14 ,2,"33","Resistor_SMD:R_0402_1005Metric","~"
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R2 R3 ,2,"5K1","Resistor_SMD:R_0402_1005Metric","~"
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R8 R10 ,2,"12K","Resistor_SMD:R_0402_1005Metric","~"
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R9 ,1,"1K5","Resistor_SMD:R_0402_1005Metric","~"
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TP1 ,1,"5V","footprints:TP","~"
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TP10 ,1,"GND","footprints:TP","~"
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TP2 ,1,"ROUT","footprints:TP","~"
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TP3 ,1,"PTT","footprints:TP","~"
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TP4 ,1,"COS","footprints:TP","~"
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TP5 ,1,"CTCSS","footprints:TP","~"
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TP6 ,1,"IO3","footprints:TP","~"
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TP7 ,1,"IO2","footprints:TP","~"
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TP8 ,1,"IO1","footprints:TP","~"
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TP9 ,1,"IO0","footprints:TP","~"
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U1 ,1,"USB2412-DZK-TR","Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm",""
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U2 ,1,"CM108","Package_QFP:LQFP-48_7x7mm_P0.5mm",""
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U3 ,1,"CP2102N-A02-GQFN24","Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm","https://www.silabs.com/documents/public/data-sheets/cp2102n-datasheet.pdf"
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Y1 ,1,"24MHz","Crystal:Crystal_SMD_HC49-SD","~"
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Y2 ,1,"12MHz","Crystal:Crystal_SMD_HC49-SD","~"
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Plik diff jest za duży
Load Diff
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@ -1,4 +1,4 @@
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update=2/8/2021 10:02:21 AM
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update=4/9/2021 4:56:57 PM
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version=1
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last_client=kicad
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[general]
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@ -24,14 +24,13 @@ RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.127
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MinViaDiameter=0.2
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MinViaDrill=0.3
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MinViaDrill=0.2
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.15
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TrackWidth2=0.25
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ViaDiameter1=0.5
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ViaDrill1=0.3
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TrackWidth1=0.127
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ViaDiameter1=0.4
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ViaDrill1=0.2
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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@ -228,10 +227,10 @@ Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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Name=Default
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Clearance=0.15
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TrackWidth=0.15
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ViaDiameter=0.5
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ViaDrill=0.3
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Clearance=0.127
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TrackWidth=0.127
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ViaDiameter=0.4
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ViaDrill=0.2
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uViaDiameter=0.2
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uViaDrill=0.1
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dPairWidth=0.2
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@ -239,9 +238,9 @@ dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/1]
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Name=Power
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Clearance=0.15
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Clearance=0.127
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TrackWidth=0.25
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ViaDiameter=0.8
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ViaDiameter=0.6
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ViaDrill=0.4
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uViaDiameter=0.3
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uViaDrill=0.1
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Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
83183
electric/fp-info-cache
83183
electric/fp-info-cache
Plik diff jest za duży
Load Diff
Ładowanie…
Reference in New Issue