revision 1.3

- uses two port embedded hub USB2412 - reduced size to fit into 23x40mm for aluminum extrusion case
2021-01-26 14:26:39 -07:00 · 2021-01-26 14:26:39 -07:00 · 3babb622ee
commit 3babb622ee
--- a/electric/components.lib
+++ b/electric/components.lib
@ -133,4 +133,45 @@ X PWRON1 9 950 400 100 L 50 50 0 0 O V
 ENDDRAW
 ENDDEF
 #
+# USB2412-DZK-TR
+#
+DEF USB2412-DZK-TR U 0 40 Y Y 1 F N
+F0 "U" -1000 1500 50 H V C CNN
+F1 "USB2412-DZK-TR" 100 1500 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 5 0 1 0 -1000 1450 0 1450 0 -600 -1000 -600 -1000 1450 N
+X USBDN1_DP 1 100 900 100 L 50 50 1 1 B
+X VDD3V4 10 -600 1550 100 D 50 50 1 1 W
+X PRTPWR2 11 100 250 100 L 50 50 1 1 O
+X ~OSC2 12 100 150 100 L 50 50 1 1 I
+X NON_REM1 13 -1100 0 100 R 50 50 1 1 I
+X VDD3V3 14 -500 1550 100 D 50 50 1 1 W
+X TEST1 15 -100 -700 100 U 50 50 1 1 I
+X HS_IND 16 -1100 100 100 R 50 50 1 1 I
+X ~RST 17 -1100 600 100 R 50 50 1 1 I
+X VBUS_DET 18 -1100 1000 100 R 50 50 1 1 I
+X SUSP_IND 19 -1100 -100 100 R 50 50 1 1 I
+X USBDN2_DM 2 100 450 100 L 50 50 1 1 B
+X VDD3V3 20 -400 1550 100 D 50 50 1 1 W
+X USBUP_DP 21 -1100 800 100 R 50 50 1 1 B
+X USBUP_DM 22 -1100 900 100 R 50 50 1 1 B
+X XTAL_OUT 23 -850 -700 100 U 50 50 1 1 O
+X XTAL_IN 24 -750 -700 100 U 50 50 1 1 I
+X PLLFILT 25 100 -250 100 L 50 50 1 1 O
+X RBIAS 26 100 -50 100 L 50 50 1 1 I
+X VDD3V3 27 -300 1550 100 D 50 50 1 1 W
+X USBDN1_DM 28 100 1000 100 L 50 50 1 1 B
+X GND 29 -500 -700 100 U 50 50 1 1 W
+X USBDN2_DP 3 100 350 100 L 50 50 1 1 B
+X VDD3V3 4 -700 1550 100 D 50 50 1 1 W
+X NC 5 -300 -700 100 U 50 50 1 1 N
+X TEST 6 -200 -700 100 U 50 50 1 1 I
+X PRTPWR1 7 100 800 100 L 50 50 1 1 O
+X ~OSC1 8 100 700 100 L 50 50 1 1 I
+X CFILT 9 100 -150 100 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
 #End Library
--- a/electric/digirig-mobile.kicad_pcb
+++ b/electric/digirig-mobile.kicad_pcb
--- a/electric/digirig-mobile.pro
+++ b/electric/digirig-mobile.pro
@ -1,29 +1,10 @@
-update=22/05/2015 07:44:53
+update=1/25/2021 7:07:29 PM
 version=1
 last_client=kicad
 [general]
 version=1
 RootSch=
 BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
 [cvpcb]
 version=1
 NetIExt=net
@ -31,3 +12,240 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.127
+MinViaDiameter=0.2
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.15
+TrackWidth2=0.127
+TrackWidth3=0.25
+ViaDiameter1=0.4
+ViaDrill1=0.3
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.15
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.09999999999999999
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0
+SolderMaskMinWidth=0
+SolderPasteClearance=0
+SolderPasteRatio=-0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.15
+TrackWidth=0.15
+ViaDiameter=0.4
+ViaDrill=0.3
+uViaDiameter=0.2
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=Power
+Clearance=0.15
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
--- a/electric/digirig-mobile.sch
+++ b/electric/digirig-mobile.sch