kopia lustrzana https://github.com/cariboulabs/cariboulite
101 wiersze
2.5 KiB
Verilog
101 wiersze
2.5 KiB
Verilog
module lvds_rx (
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input i_rst_b,
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input i_ddr_clk,
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input [1:0] i_ddr_data,
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input i_fifo_full,
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output o_fifo_write_clk,
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output o_fifo_push,
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output [15:0] o_fifo_data,
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input i_sync_input,
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output [ 1:0] o_debug_state
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);
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// Internal FSM States
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localparam state_idle = 2'b00, state_i_phase = 2'b01, state_q_sync = 2'b10, state_q_phase = 2'b11;
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// Modem sync symbols
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localparam modem_i_sync = 2'b10, modem_q_sync = 2'b01;
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// Internal Registers
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reg [1:0] r_state_if;
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reg [2:0] r_phase_count;
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reg r_sync_input;
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reg r_fifo_push;
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assign o_fifo_push = r_fifo_push;
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// Initial conditions
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initial begin
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r_state_if = state_idle;
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r_phase_count = 3'b111;
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end
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// Global Assignments
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assign o_fifo_write_clk = i_ddr_clk;
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assign o_debug_state = r_state_if;
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reg [35:0] r_fifo_data;
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always @(posedge i_ddr_clk) begin
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r_fifo_data <= {r_fifo_data[33:0], i_ddr_data};;
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end
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assign o_fifo_data = r_fifo_data[19:4];
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reg fifo_push2;
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// Main Process
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always @(posedge i_ddr_clk or negedge i_rst_b) begin
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if (i_rst_b == 1'b0) begin
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r_state_if <= state_idle;
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r_fifo_push <= 1'b0;
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r_phase_count <= 3'b000;
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r_sync_input <= 1'b0;
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fifo_push2 <= 1'b0;
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end else begin
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r_phase_count <= r_phase_count + 1;
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case (r_state_if)
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state_idle: begin
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if (r_fifo_data[1:0] == modem_i_sync) begin
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r_state_if <= state_i_phase;
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r_sync_input <= i_sync_input; // mark the sync input for this sample
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end
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r_phase_count <= 3'b001;
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r_fifo_push <= 1'b0;
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if(fifo_push2) begin
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r_fifo_push <= 1'b1;
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fifo_push2 <= 1'b0;
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end
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end
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state_i_phase: begin
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if (r_phase_count == 3'b111) begin
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r_state_if <= state_q_sync;
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end
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r_fifo_push <= 1'b0;
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end
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state_q_sync: begin
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if (r_fifo_data[1:0] == modem_q_sync) begin
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r_state_if <= state_q_phase;
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r_fifo_push <= ~i_fifo_full;
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fifo_push2 <= ~i_fifo_full;
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end else begin
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r_state_if <= state_idle;
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end
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end
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state_q_phase: begin
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if (r_phase_count == 3'b111) begin
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r_state_if <= state_idle;
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end
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r_fifo_push <= 1'b0;
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end
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endcase
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end
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end
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endmodule
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