kopia lustrzana https://github.com/cariboulabs/cariboulite
80 wiersze
2.1 KiB
Verilog
80 wiersze
2.1 KiB
Verilog
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/*
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* Contribution by matteo serva
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* https://github.com/matteoserva
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*
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*/
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module lvds_clock_sync (
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input i_rst_b,
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input i_ddr_clk,
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input i_sys_clk, // FPGA Clock
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output reg o_data_sbe_ddr,
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output o_lvds_ready_ddr,
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output o_lvds_ready_sys
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);
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reg [3:0] r_phase_count;
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always @(posedge i_ddr_clk) begin
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r_phase_count <= r_phase_count + 1;
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if(r_phase_count == 4'd0) begin
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o_data_sbe_ddr <= 1'b1;
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end else begin
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o_data_sbe_ddr <= 1'b0;
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end
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end
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reg [2:0] lvds_heartbeat_synchronizer;
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always @(posedge i_sys_clk) begin
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lvds_heartbeat_synchronizer = {r_phase_count[3] , lvds_heartbeat_synchronizer[2:1]};
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end
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wire lvds_heartbeat_sbe;
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assign lvds_heartbeat_sbe = lvds_heartbeat_synchronizer[1] ^ lvds_heartbeat_synchronizer[0];
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reg [6:0] lvds_timeout_counter;
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wire lvds_heartbeat_lost;
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assign lvds_heartbeat_lost = lvds_timeout_counter[6];
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always @(posedge i_sys_clk) begin
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if (i_rst_b == 1'b0) begin
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lvds_timeout_counter <= 0;
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end else begin
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if (lvds_heartbeat_sbe) begin
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lvds_timeout_counter <= 0;
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end else if(!lvds_heartbeat_lost) begin
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lvds_timeout_counter <= lvds_timeout_counter + 1;
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end
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end
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end
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reg [9:0] lvds_start_delay_counter;
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assign lvds_ready = lvds_start_delay_counter[9];
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wire lvds_ready;
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always @(posedge i_ddr_clk or posedge lvds_heartbeat_lost) begin
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if (lvds_heartbeat_lost == 1'b1) begin
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lvds_start_delay_counter <= 0;
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end else begin
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if (!lvds_ready) begin
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lvds_start_delay_counter <= lvds_start_delay_counter + 1;
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end
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end
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end
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assign o_lvds_ready_ddr = lvds_ready;
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reg [1:0] lvds_ready_synchronizer;
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always @(posedge i_sys_clk) begin
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lvds_ready_synchronizer = {lvds_ready , lvds_ready_synchronizer[1]};
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end
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assign o_lvds_ready_sys = lvds_ready_synchronizer[0];
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endmodule
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