kopia lustrzana https://github.com/cariboulabs/cariboulite
12703 wiersze
576 KiB
Plaintext
12703 wiersze
576 KiB
Plaintext
.comment from next-pnr
|
|
.device 1k
|
|
.io_tile 1 0
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 2 0
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 3 0
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 4 0
|
|
000000000000000010
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000111010100001
|
|
000000000011110000
|
|
001101011000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000001111000001100
|
|
000000001000001000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 5 0
|
|
000000000000000010
|
|
000100000000000000
|
|
000001010000000000
|
|
000000001000000001
|
|
000000000000110001
|
|
000000000011110000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000001010001111110
|
|
000000001011011100
|
|
000011010001000000
|
|
000011111000000001
|
|
000000111000000001
|
|
000000000000000000
|
|
|
|
.io_tile 6 0
|
|
000000000000000010
|
|
000100000000000000
|
|
000010111000000000
|
|
000010111000000001
|
|
000000000010101101
|
|
000000000011010000
|
|
001101010000000000
|
|
000000001000000000
|
|
000001111000000000
|
|
101000001000000000
|
|
010000000011110110
|
|
000000000011111000
|
|
000000000000000000
|
|
000000000000000001
|
|
000011010000000001
|
|
000000011000000000
|
|
|
|
.io_tile 7 0
|
|
000000000000000010
|
|
000000000000000000
|
|
000001011000000000
|
|
000010110000000001
|
|
000010000000011101
|
|
000001110011011000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000010000000000100
|
|
000000010000001000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 8 0
|
|
000000000000011000
|
|
000000000000000000
|
|
000000000001100000
|
|
000000000000011001
|
|
000000000000000000
|
|
000000000000000000
|
|
001100000000000000
|
|
000000000000001000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 9 0
|
|
000010000000000010
|
|
000110110000000000
|
|
000001010000000000
|
|
000000001000000001
|
|
000000000000000001
|
|
000000000011010000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000001100
|
|
000000000000001100
|
|
000001010001000000
|
|
000000001000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 10 0
|
|
000000000000000000
|
|
000100000000000000
|
|
010010000000000000
|
|
000010110000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000011110110
|
|
000000000011011000
|
|
000010000000000000
|
|
000000110000000001
|
|
000001010000000001
|
|
000000001000000000
|
|
|
|
.io_tile 11 0
|
|
000001011000000010
|
|
000100000000000000
|
|
000010000000000000
|
|
000000110000000001
|
|
000000000000000001
|
|
000000000001110000
|
|
001000000000000000
|
|
000000000000000000
|
|
000000000000000010
|
|
000100000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 12 0
|
|
000000000000000000
|
|
001100000000000000
|
|
000000000000000000
|
|
100000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
001000000000001000
|
|
000000000000000000
|
|
010000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
100000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 1
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 1
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000100000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 2 1
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
111000000000000000000010110001100000100000010100000000
|
|
000000000000000000000111010000101110100000010000000000
|
|
010000000000000111100110000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000001000000000000000011000110000000100000000
|
|
000000000000001011000000000000011100110000000000000000
|
|
000000000000000001100000000101101100110100010000000000
|
|
000000000000000000000000000000001010110100010000000000
|
|
000000000000000000000000000001101010101000000100000100
|
|
000000000000000000000000000000110000101000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000111000000000000000000000000000000000000
|
|
010000000000000000000000001101000001100000010000000000
|
|
000000000000000000000000000101101001111001110000000000
|
|
|
|
.ramb_tile 3 1
|
|
000000000000000000000000000000000001000000
|
|
000000000000000000000000000101001010000000
|
|
111000000000001101100111001011100000000000
|
|
000000000000001011100100000101101111000000
|
|
110000000000000111000000000000000000000000
|
|
010000000000000000000000000011000000000000
|
|
000000000000000011100000001000000000000000
|
|
000000000000000111100000000001000000000000
|
|
000000000000000000000010100000000000000000
|
|
000000000000000111000011111111000000000000
|
|
000000000000000000000000001111100000000000
|
|
000000000000000000000010111001000000000000
|
|
000000000000000000000011111000000000000000
|
|
000000000000000000000011001111000000000000
|
|
010000000000000101000010000000000000000000
|
|
010000000000000000100100001011000000000000
|
|
|
|
.logic_tile 4 1
|
|
100000000000000111100000000011000000000000000100000000
|
|
000000000000000000100000000000000000000001000000000000
|
|
011000000000000101100000000101000000000000000100000000
|
|
100000000000000000000000000000000000000001000000000000
|
|
110000000100000101100000000101000000000000000100000000
|
|
100000000000100000000011100000100000000001000000000000
|
|
000000000000000000000000001011001100001101000000000000
|
|
000000000000001111000000000011011000000100000000000000
|
|
000000000100001101000000010000000000000000000000000000
|
|
000000000000001011100010000000000000000000000000000000
|
|
000000000000000001100000000000011110000100000100000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000001100000000001011010000100000000000000
|
|
000000000000000000000000000111001100010100100000000000
|
|
010000000000000101000000001000000000000000000100000100
|
|
100000000000000000100000000001000000000010000000000000
|
|
|
|
.logic_tile 5 1
|
|
100000000000000000000110110000000000000000000000000000
|
|
000000000000000111000011110000000000000000000000000000
|
|
011000000000100000000000010001011011001001000000000000
|
|
100000000001010000000010100101011110000101000000000000
|
|
010000000000001000000000000000000000000000000000000000
|
|
010000000000000101000000000000000000000000000000000000
|
|
000000000000000000000010000000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000001000000000001000000000111001110100000000
|
|
000000000110000011000000001001001100110110110010000000
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011000000000000000000000000000000
|
|
000000000000000000000000001000001000111101010100000000
|
|
000000000000000000000000001011010000111110100000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000001111000000000000000000000000000000000000
|
|
|
|
.logic_tile 6 1
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000111000000000000000000000000000000000000
|
|
011000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
110000001100000101100000000000000000001111000000000000
|
|
010000000000000000000000000000001000001111000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000011100000000000000000000000000000000000
|
|
000000000000000000100010010000000000000000000000000000
|
|
000000000000000000000000000101000000111001110100000000
|
|
000000000000000000000000000000001100111001110010000000
|
|
000000000001000000000000000000000000000000000000000000
|
|
000000001010000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 7 1
|
|
000000000000000000000000000000000001000000001000000000
|
|
000000000000000000000000000000001110000000000000001000
|
|
000000000000010000000000000000011111001100111000000000
|
|
000000000000100000000000000000001101110011000010000000
|
|
000100000000000000000000000011101000001100111010000000
|
|
000000000000000000000000000000000000110011000000000000
|
|
000000001110000000000010100000001001001100111000000000
|
|
000000000000000000000100000000001110110011000000000000
|
|
000000000000000101000000000011001000001100111000000000
|
|
000000000000000000100010110000000000110011000000000000
|
|
000000000000000011100010100011101000001100111000000000
|
|
000000000000000000100110110000100000110011000000000000
|
|
000000000000000000000000000000001001001100111000000010
|
|
000000000000000000000000000000001011110011000000000000
|
|
000000000000000101000000000011001000001100111000000010
|
|
000000000000001101100000000000100000110011000000000000
|
|
|
|
.logic_tile 8 1
|
|
100000000000000011100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
111000000000000001100000000111000000000000000100000000
|
|
000000000000000101000000000000000000000001000000000100
|
|
000000000000000000000110100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000100000000000000000000001000000100100000000
|
|
000000000001010000000000000000001101000000000000100100
|
|
000000000000000101000000001000000000100000010000000001
|
|
000000000110000000000000000001001011010000100010000000
|
|
000000000000000000000110100000000000000000000100000000
|
|
000000000000000000000000000011000000000010000000000000
|
|
000000000000000101100000000000011000000100000100000000
|
|
000000000000000000000000000000000000000000000000000100
|
|
000010000000000000000000000101000000101001010010000000
|
|
000001000000000000000000000001100000000000000000000000
|
|
|
|
.logic_tile 9 1
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000001101000000000000000000000000000000000000
|
|
111000000000000000000010100000000001000000100100000000
|
|
000000000000000000000100000000001001000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000010000000000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000001000000000000000100000000
|
|
000000000000000000000000000000000000000001000000000000
|
|
|
|
.ramb_tile 10 1
|
|
000000000000000000000000000000000000000000
|
|
000010110000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000001110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 1
|
|
100000000001010000000110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
101000000000001001100000000000011001100000000100000000
|
|
001000000000000001000000000011001100010000000000000000
|
|
000000000000000001100000000001011100111000000000000000
|
|
000000000000000011000000000000101010111000000000000000
|
|
000000000000000111100110001101000000000000000100000000
|
|
000000000000000000000000000011001100100000010000000000
|
|
000000000000000011100000010000011000101011110100000000
|
|
000000000000000001100010001011000000010111110000000000
|
|
000000000000000001000000001001111010000000110000000000
|
|
000000000000000000000000000011011100000000100000000000
|
|
000000000000000000000000001000001101000111110000000000
|
|
000000000000000000000000001101001000001011110001000000
|
|
000000000000000000000000000000011010000000010100000000
|
|
000000000000000000000000001001001010000000100000000000
|
|
|
|
.logic_tile 12 1
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000010000000000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 1
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 2
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 2
|
|
000000000000001000000011100000000000000000000000000000
|
|
000000000000001101000000000000000000000000000000000000
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010100000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000001000101000000100000000
|
|
000010000000000000000000000001010000010100000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000001100000010100000000
|
|
000000000000000000000000000001001111010000100000000000
|
|
010000000000001000000110000001000001100000010100000000
|
|
000000000000000001000000000000001110100000010000000000
|
|
|
|
.logic_tile 2 2
|
|
000000000000000000000000010000001111110000000100000000
|
|
000000001000000000000011100000001001110000000000000000
|
|
111000000000001111100000010011011000101000000100000000
|
|
000000000000000101100011010000010000101000000000000000
|
|
010000100000000001100111101000000001100000010100000000
|
|
110001000000010000000100001111001001010000100000000100
|
|
000000000000000000000110100001101000101000000100000000
|
|
000000000000000000000000000000110000101000000000000100
|
|
000000000010001000000000000000000001100000010100000000
|
|
000000000000000001000000000101001001010000100010000000
|
|
000000000000000000000000001101101100101000000000000000
|
|
000000000000000111000000000001100000111101010000000000
|
|
000000000000000000000000000001101111111000100000000000
|
|
000000000000000111000000000000001000111000100000000000
|
|
110000000000000000000110000001111100101000000100000000
|
|
000000000000000000000000000000100000101000000000000000
|
|
|
|
.ramt_tile 3 2
|
|
000010010001000000000111100000000000000000
|
|
000000000100100000000111100101001111000000
|
|
001000010001010111100111110011100001000000
|
|
100000000000100000000011111001001000000000
|
|
010000000000000111100000000000000000000000
|
|
010000000110000000100000000111000000000000
|
|
000000000000000000000000001000000000000000
|
|
000000000000000000000000000011000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000011101011000000000000
|
|
000000000000001011100000001111100000000000
|
|
000000000000001001100000001001100000000000
|
|
000000100000000011100011101000000000000000
|
|
000001000000000000100100001001000000000000
|
|
110010100000000001000110001000000000000000
|
|
110001000000000000100110011111000000000000
|
|
|
|
.logic_tile 4 2
|
|
000000000000001000000000001000011110101000000100000000
|
|
000000000000000001000000001111010000010100000000000000
|
|
111000000000000000000000001011000000101001010100000000
|
|
000000000000000000000000001111000000000000000001000000
|
|
110000000000000001000000000000011110110000000100000000
|
|
110000000000000000000000000000011000110000000000000000
|
|
000000000000000000000000011000000000000000000000000000
|
|
000000000000000000000010000111000000000010000000000000
|
|
000000000000001000000000000111111010101000000100000000
|
|
000000000010000111000000000000110000101000000000000000
|
|
000000000000000000000000001000000000100000010100000000
|
|
000000000000000000000000001111001111010000100000000000
|
|
000000000000000000000111110000011111110000000100000000
|
|
000000000000000001000110000000011110110000000000000000
|
|
110000000000000001100011100101000000100000010000000000
|
|
000000000000001011000110000111001111110110110010000000
|
|
|
|
.logic_tile 5 2
|
|
000000000000000000000000000011111011110001010000000000
|
|
000000000010000111000000000000101010110001010001000000
|
|
111000000000001000000000010000000001100000010100000000
|
|
000000000000000101000010100101001101010000100000000000
|
|
010000000001000001100000000000000000000000000000000000
|
|
100000000000100011000000000000000000000000000000000000
|
|
000001000000000101100000000011100000101001010100000000
|
|
000000100000001111000000000101000000000000000000000001
|
|
000000000000000000000000001101100000111001110000000000
|
|
000000000000000000000000001001001010010000100000000001
|
|
000000000000001000000110011011111000101000000000000000
|
|
000000000001001011000010000101100000111101010000000001
|
|
000000000000000000000000000000001010110000000100000000
|
|
000000000000000000000000000000001010110000000000000000
|
|
010000000000000000000000000001000000101001010100000000
|
|
000000000000000000000000000101000000000000000000000000
|
|
|
|
.logic_tile 6 2
|
|
100000000000000000000110000101101000010101010000000000
|
|
000000000000000000000110000000010000010101010000000000
|
|
111001001010100001100000001000000000000000000100000000
|
|
000000101111010000100000000101000000000010000000000001
|
|
010000000000010001100000011000000000000000000100000000
|
|
010000000000100000100010011101000000000010000000000001
|
|
000000001110001000000110000000000000011001100000000000
|
|
000000000000001001000100001101001001100110010000000000
|
|
000000000000000000000000000000001000000100000100000000
|
|
000000000000000000000000000000010000000000000000000001
|
|
000001000000000000000000000000011110000011110100000000
|
|
000000100000000000000000000000000000000011110000000000
|
|
000000000000000000000000000001100000000000000100000000
|
|
000000000000000000000000000000000000000001000000000000
|
|
010000000000100001100000000000001010000100000100000001
|
|
100000000001000000000000000000000000000000000010000010
|
|
|
|
.logic_tile 7 2
|
|
100001000000000001100000010101101000001100111000000000
|
|
000000000000000000100011100000100000110011000000110000
|
|
111000000000000101000010100000001000001100110010000000
|
|
000000000000000101000010100000001010110011000000100000
|
|
110000000000000101000000000001011001100101100000000000
|
|
010000000000001111000010100000011001100101100000000000
|
|
000000000000000000000000001000001000100101100000000000
|
|
000000000000000000000011101001011110011010010000000000
|
|
000000000000000000000000010101000000011001100000000100
|
|
000000000000000000000011000000101010011001100000000010
|
|
000000000000000000000000000001100001011001100010000100
|
|
000000000000000000000000000000101000011001100000000000
|
|
000000000010001000000000001001100000000000000000000010
|
|
000000000000000001000000000001000000111111110000000000
|
|
010000000000000000000000000001100000000000000100000000
|
|
100000000000000000000000000000100000000001000000000001
|
|
|
|
.logic_tile 8 2
|
|
000000000000000000000000000000000001000000001000000000
|
|
000000000000000000000000000000001101000000000000001000
|
|
000000000000100000000000000011011100001100111010000000
|
|
000000000001000000000000000000110000110011000000000100
|
|
000000000000000000000000000011001000001100111000000000
|
|
000000000000000000000000000000100000110011000000000001
|
|
000000000001010000000000000000001001001100111000000000
|
|
000000000000000000000000000000001100110011000000000000
|
|
000000000000000000000010100000001001001100111000000000
|
|
000000000000000000000010100000001100110011000000000000
|
|
000000000000001101100000000000001001001100111000000000
|
|
000000000110000101000010100000001111110011000000000000
|
|
000000000000000000000110110111001000001100111000000000
|
|
000000000000000000000010100000100000110011000000000000
|
|
000000000000000000000000010111001000001100111000000000
|
|
000000000000000000000010100000100000110011000000000001
|
|
|
|
.logic_tile 9 2
|
|
000000000000000000000000000000000000010110100100000000
|
|
000000000000000000000010111001000000101001010000000000
|
|
001000000000000101100000011000000001011001100100000000
|
|
100000000000000000000010100101001000100110010000000000
|
|
110000000000000000000110101000000000000000000100000000
|
|
110000000000000000000000001001000000000010000010000000
|
|
000000001110001000000110100000011010000100000100000000
|
|
000001000000000101000000000000010000000000000010000000
|
|
000000000000000000000000000000011010000100000100000000
|
|
000000000000000000000000000000000000000000000010000000
|
|
000000000000100000000000000101000000000000000100000000
|
|
000000000011010000000000000000100000000001000010000000
|
|
000000000000000000000110100000011000000100000100000000
|
|
000000000000000000000100000000000000000000000010000000
|
|
010000000000000000000000000101111000010101010100000000
|
|
100000000000000000000000000000110000010101010000000000
|
|
|
|
.ramt_tile 10 2
|
|
000001000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000010000000000000000000000000000
|
|
000000000000100000000000000000000000000000
|
|
000000000001010000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 2
|
|
000000000000001000000011100000000000000000001000000000
|
|
000000000000001111000000000000001000000000000000001000
|
|
000000000000000000000000000000011011001100111000000000
|
|
000000000000000000000000000000001111110011000000000000
|
|
000000000000000000000000000000001000001100111000000000
|
|
000000000000000000000000000000001101110011000000000000
|
|
000000000000000111100000000011001000001100111000000000
|
|
000000000000000000000000000000000000110011000000000000
|
|
000000000000001000000000010000001001001100111000000000
|
|
000000000000000111000011100000001100110011000000000000
|
|
000000000000001000000000000000001001001100111000000000
|
|
000000001000000111000011110000001110110011000000000000
|
|
000000000000000000000000000000001001001100111000000000
|
|
000000000000000000000000000000001101110011000000000000
|
|
000000000000000000000000000000001000001100111000000100
|
|
000000000000001111000010000000001001110011000000000000
|
|
|
|
.logic_tile 12 2
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 2
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 3
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 3
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
111000000000000000000000010000000000000000000000000000
|
|
000000000000000000000010000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000100000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000011001000011000101000000100000000
|
|
000000000000000000000100001011010000010100000010000000
|
|
000000000000100000000000000011111010101000000100000000
|
|
000000000000000000000000000000110000101000000000000000
|
|
010000000000000001100000000000011111110000000100000000
|
|
000000000000000000000000000000001101110000000000000000
|
|
|
|
.logic_tile 2 3
|
|
000000000100100000000111100011111000101000000110000000
|
|
000000000000000000000010100000000000101000000000000000
|
|
111000000000000001100110110000000001100000010100000000
|
|
000000000000000101000010101101001100010000100000000000
|
|
010011100000000101000010100011100000101001010100000000
|
|
100000000000000000000011100111000000000000000010000000
|
|
000000000000001000000000000000001011111000100000000000
|
|
000000000000001111000000001001011001110100010010000000
|
|
000000000000000000000000011101100001111001110000000000
|
|
000000000000000000000010000001001001010000100000000000
|
|
000000000000000011100000010000001101110000000100000000
|
|
000000000000000000100010010000011100110000000010000000
|
|
000000000000000001100000000101100001111001110000000000
|
|
000000000000000000000000000101001101010000100000000000
|
|
010000000000000000000000001000001000111000100000000000
|
|
000000000000000000000000000101011011110100010000000000
|
|
|
|
.ramb_tile 3 3
|
|
010000000000010001000000011000000001000000
|
|
001000000000000111000011110111001011000000
|
|
111000000000001000000011111001100001000000
|
|
000000000000000101000110101101101001000000
|
|
010000000000000000000011100000000000000000
|
|
011000000000000000000000000001000000000000
|
|
000000000000001000000111111000000000000000
|
|
001000000000000111000011100101000000000000
|
|
000001000010000000000000000000000000000000
|
|
001000000110000000000000001101000000000000
|
|
000000000000001000000000001001100000000000
|
|
001000000000001011000000001111000000000000
|
|
000000000000000000000000001000000000000000
|
|
001000000000000000000000001111000000000000
|
|
110000000000000111000010000000000000000000
|
|
011000000000000000000011100001000000000000
|
|
|
|
.logic_tile 4 3
|
|
100000000000000101100111111011100000100000010000000000
|
|
000000000000000000000010000111101010111001110010000000
|
|
011000000000000111100000000000011010000100000100000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
110000000000000101000111100001000000000000000100000000
|
|
100000000000000101000100000000000000000001000000000000
|
|
000000000000000101100000000111000000000000000100000000
|
|
000000000000000000000000000000000000000001000000000000
|
|
000000000000010000000000011101001110111101010010000000
|
|
000000000000000000000011010111010000101000000000000000
|
|
000000000000000101000111100001001101101001000000000000
|
|
000000000000000000100100001001111000010000000000000000
|
|
000100000000000101000000010000011100000100000100000000
|
|
000000000000000000100011100000000000000000000000000000
|
|
010000000000000001000000001111101010101000000000000000
|
|
100000000000001111100000000111010000111110100000000010
|
|
|
|
.logic_tile 5 3
|
|
100000000000000011000000000101011001110000010000100000
|
|
000000000000000000000000001101111001010000000000000000
|
|
011000000000000000000110010111000000000000000100000000
|
|
100000000000001111000011110000100000000001000000000000
|
|
110000000100010101100011110000000000000000000000000000
|
|
100010000000100000100011110000000000000000000000000000
|
|
000000000000000000000000000001111000101001000000100000
|
|
000000000000000000000000000011101011100000000000000000
|
|
000000000000000001100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000100000000
|
|
000000000000000000000000000001000000000010000000000000
|
|
000000000000010000000010000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
010000000000000000000000000101000000000000000100000000
|
|
100000100000000000000000000000000000000001000000000000
|
|
|
|
.logic_tile 6 3
|
|
100000000000000000000110011000011001000001100000000000
|
|
000000100001010101000110010011011001000010010000000000
|
|
111000000000000000000010110001000000000000000100000000
|
|
000000000000000000000010000000000000000001000000000000
|
|
110000000000100000000010100000000000000000100100000000
|
|
010000100000010000000000000000001011000000000000000000
|
|
000000000000000000000000000111001001000000100000000000
|
|
000000000000000000000010011001111101000000000000000100
|
|
000000000000000011100000010000000000000000000000000000
|
|
000000000110000000100011010000000000000000000000000000
|
|
000000001110000000000110001001001011110011110000000100
|
|
000000000000001001000000001101011110100001010000000000
|
|
000000100000000000000110100000001100000100000100000000
|
|
000001000000000000000000000000000000000000000000000010
|
|
010000000000100000000000001001001011110110100000000000
|
|
100000000000011001000000000111011011110100010000000000
|
|
|
|
.logic_tile 7 3
|
|
000000000000000000000000010000011000110011000000000000
|
|
000000000000000000000010010000011101110011000000000000
|
|
111001000000000000000010100011011000111000010000000000
|
|
000010100000001111000010100111001111010010110000000000
|
|
110000000010001101000110001011011010010100100000000000
|
|
110010000000001111100100001011001010100001010000000000
|
|
000010100001000000000000000001100001011001100000000000
|
|
000000000000100001000000000000101010011001100000000000
|
|
000000000000000001100000000000000000000000000000000000
|
|
000000000000000111100010000000000000000000000000000000
|
|
000000000001000000000000010101011101110100000000000000
|
|
000000000000100000000010010011011010011100000000000000
|
|
000000000110011000000011110000000000011001100000000000
|
|
000000000100000001000110011101001001100110010000000010
|
|
010000000000000000000000000000000000010110100100000000
|
|
100000000000000000000000000101000000101001010000000000
|
|
|
|
.logic_tile 8 3
|
|
000000000000001111100011100111101000001100111000000000
|
|
000000000000000001000010100000000000110011000000010000
|
|
001000000000000101000010100000001000001100110000000001
|
|
100000000000000101000000000001000000110011000010000000
|
|
000001000000000000000010100000001000000100000100000000
|
|
000010000000000000000000000000010000000000000010000000
|
|
000000000000000000000110110101100000000000000100000000
|
|
000000000000000000000010000000100000000001000000100000
|
|
000000000000000000000000001001111010000011000000000000
|
|
000000000000000000000000001011111000000000110000000000
|
|
000000001100000000000000010000000000000000000100000000
|
|
000000000000000000000011011111000000000010000010000000
|
|
000000000000000000000000011000011001100101100000000000
|
|
000000000000000000000011000111001000011010010000000000
|
|
000000000000101001100000011101001000101000000000000000
|
|
000000000001000101000011001111110000000010100000000000
|
|
|
|
.logic_tile 9 3
|
|
000000000000001000000000000000001100101011110000000100
|
|
000000000000000101000010011011010000010111110001100001
|
|
001000000000000000000000010011100001110000110000000000
|
|
100000000000000000000010001101101101001111000000000000
|
|
010000000000000000000000010011000000000000000100000101
|
|
010000000000000000000010100000000000000001000000000001
|
|
000000000000000000000000000000000000000000100110000001
|
|
000000001010000000000000000000001111000000000000000000
|
|
000000000000000001100011100000000000000000100110000000
|
|
000000000000000000100111110000001000000000000000000000
|
|
000000000000000000000110010000011111001100110000000000
|
|
000000000000000000000110010000001111001100110000000000
|
|
000000000000000000000110011000000000010110100100000000
|
|
000000000000000000000110011001000000101001010000000000
|
|
010001000000001001100000011000001110010101010000000000
|
|
100010100000001001100010010111010000101010100000000000
|
|
|
|
.ramb_tile 10 3
|
|
010000001010000000000000001000000000000000
|
|
001000000001000000000011110111001010000000
|
|
111000000000000000000000001111000001010000
|
|
000000000000001001000011101101101101000000
|
|
010000000000000111000111101000000000000000
|
|
111000000000000000100000001101000000000000
|
|
000000000001000011000111001000000000000000
|
|
001000000000000000000111110111000000000000
|
|
000001000000000111000000001000000000000000
|
|
001010000000000000000000001001000000000000
|
|
000000000000100000000111100001000000000000
|
|
001000000001010000000100000011100000001000
|
|
000000000000100000000011101000000000000000
|
|
001010000000000000000100000101000000000000
|
|
010000000000001111000000001000000000000000
|
|
011000000000001011000010001111000000000000
|
|
|
|
.logic_tile 11 3
|
|
000000000000000101000010100111101000001100110000000000
|
|
000000000000000001000010100000100000110011000000010000
|
|
001000000000100101000010101000011001011010010000000000
|
|
100000000001000101000010100101001000100101100000000000
|
|
010000000000000001100111101011111000001000010000000000
|
|
110000000000000000000000001001001110100001000000000000
|
|
000000000000001000000000000001001000011010010000000000
|
|
000000000000001111000000000000011000011010010000000000
|
|
000010100000000011100000000001101101001000010000000000
|
|
000001000000000000100000000101101001010010000000000000
|
|
000000000000000001100111100001011110000011110000000000
|
|
000000000000000000000100001001100000111100000000000000
|
|
000010100000100111100110001000000000000000000100000000
|
|
000001000000010000100000001111000000000010000001000000
|
|
010000000000000001000111110001101111001100000000000000
|
|
100000000000000000000010001001011101110000000000000000
|
|
|
|
.logic_tile 12 3
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000010100000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000110000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000010000000000000000000000000000000000000000
|
|
000000001010000000000000000000000000000000000000000000
|
|
000000000000010000000000000000000000000000000000000000
|
|
000000000000110000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 3
|
|
000000000000000000
|
|
000100000000000000
|
|
000000111000000000
|
|
000000001000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000010
|
|
000000000000110000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000010
|
|
000000000000000000
|
|
|
|
.io_tile 0 4
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000100000100000000
|
|
000000000100000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 4
|
|
010000000000000000000000010000000000000000000000000000
|
|
001000000000000000000011100000000000000000000000000000
|
|
111000000000000001100010100000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000001000011000101000000100000000
|
|
101000000000001101000000000011000000010100000000000010
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000010101000011100101000000100000000
|
|
001000000000001011000000001011000000010100000000000000
|
|
000100000000000000000000001001100000101001010100000000
|
|
001000000000000000000000000011100000000000000000000000
|
|
010000000000000000000000001001000000100000010000000000
|
|
001000000000000000000000000001101010110110110010000000
|
|
|
|
.logic_tile 2 4
|
|
010000000000000001100000010000011010110000000100000000
|
|
001000000000000000000010110000011001110000000000000000
|
|
111000000000001000000111110001001100101000000100000000
|
|
000000000000001011000110100000100000101000000000000000
|
|
110000000000000101000000000001101100101000000000000000
|
|
111000000000000000000000000101110000111110100000000000
|
|
000000000000000000000000010001101000101000000100000000
|
|
001000000000000000000011010000010000101000000000000000
|
|
000000000000001000000110001001100000100000010000000000
|
|
001000000000000001000000001001101100110110110000000000
|
|
000000000000000000000110000000001000101000000100000000
|
|
001000000000000000000000001011010000010100000000000101
|
|
000001000000100000000111000011100000100000010100000000
|
|
001000000000000000000100000000101001100000010010000000
|
|
110000000000000000000000000001000000100000010100000000
|
|
001000000000000000000000000000101000100000010000000010
|
|
|
|
.ramt_tile 3 4
|
|
000000010000000000000000011000000001000000
|
|
000000000000000000000010101101001001000000
|
|
001000010000000011100000001111100001000000
|
|
100000000000000000100011101101101010000000
|
|
110000000001000000000111100000000000000000
|
|
110000000000100000000100000011000000000000
|
|
000000000000000000000111111000000000000000
|
|
000000000000000111000011010001000000000000
|
|
000010000000000000000000000000000000000000
|
|
000000000000001111000011111101000000000000
|
|
000000000000000000000010001001000000000000
|
|
000000000000000000000000001011100000000000
|
|
000010100000000000000010000000000000000000
|
|
000000000000000000000100001011000000000000
|
|
110000000000000001000110001000000000000000
|
|
110000000000000000000110001111000000000000
|
|
|
|
.logic_tile 4 4
|
|
110000000100001111000111000111111100000001110000000000
|
|
001000000000001111100111100001001100000000010000000000
|
|
011000000000000000000000000101100001111001110100000000
|
|
100000000000001101000010100000001010111001110001000000
|
|
010000000000000101000010101011101000010000000000000000
|
|
011000000000001101100000000001011000010110000000000000
|
|
000000000000000101000000010000001100111100110100100000
|
|
001000000000000111000011110000011111111100110000000000
|
|
000000000000000000000000010000011101111100110100000000
|
|
001000000000000011000010000000011111111100110000000010
|
|
000000000001000011100011100001011001110000010000000000
|
|
001000000000000000100000000101011100010000000000000000
|
|
000000000000000000000000011001000000101001010100000000
|
|
001000000110000000000010100111000000111111110010000000
|
|
000000000000001001100110001101001011110000010000000000
|
|
001000000000000011000000001101011100100000000000000000
|
|
|
|
.logic_tile 5 4
|
|
110000000000101000000000000000000000000000000000000000
|
|
001000000001000101000011100000000000000000000000000000
|
|
011001000000100000000000000111001110100000010000000000
|
|
100000100001000000000000001111101101010100000000000000
|
|
010000000110000000000000000011101111111000000000000000
|
|
011000000000010000000000001111011010100000000000000000
|
|
000000000000000101000000000001000000111001110100000000
|
|
001000000000001111000000000000001100111001110000100000
|
|
000000100000001001110010100111000000010000100100000000
|
|
001001000000001011000100000000101111010000100000000001
|
|
000000000000000111000010000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000001100111100000000000000000000000000000
|
|
001000000000000000100011100000000000000000000000000000
|
|
000010101000000000000000001000001101101000110000000000
|
|
001001000000000000000000000101001101010100110000000001
|
|
|
|
.logic_tile 6 4
|
|
010001000010100101000000000011011010000100010000000000
|
|
001000000000010000000010101011111111100010000000000000
|
|
001000000000100000000000000000000000000000000100000000
|
|
100000000001000000000010110001000000000010000000000000
|
|
000000000000000000000000000101111111100000100000000000
|
|
001000001111010000000000000000111011100000100000000000
|
|
000000000000000000000010001111011000011100000000000000
|
|
001000000000000000000010101101011111110100000000000000
|
|
000000001110000001100010000000000000000000000000000000
|
|
001001000000000000000010100000000000000000000000000000
|
|
000001000000000000000000000000000000000000100110000000
|
|
001000100000000000000000000000001100000000000010000000
|
|
000000000000000001000010100000000000000000000000000000
|
|
001000000000010000000010100000000000000000000000000000
|
|
000000000000000000000000000000001000000100000110000000
|
|
001000000000000000000010100000010000000000000000000000
|
|
|
|
.logic_tile 7 4
|
|
010000000001010101000111000000000000000000000000000000
|
|
001000001100000101000110100000000000000000000000000000
|
|
001000000000000011100111000001111110010101010000000000
|
|
100000000000001101100100000000010000010101010000000000
|
|
000000000000100111000010000000000000000000100100000000
|
|
001000000000000000000000000000001110000000000010000000
|
|
000000000000100101000000000101101001000000000000000000
|
|
001000000001010000000000000001011101000000100000000000
|
|
000000000010001101000000000000000000000000000000000000
|
|
001000000000001001100000000000000000000000000000000000
|
|
000000000000000000000110001001000001000110000000000000
|
|
001000000000000000000000000001001111001111000000000000
|
|
000000000000000101100000000001001110010100000000000000
|
|
001000000000000000000010000101110000000001010000000000
|
|
010000000000100000000010011101001100000000110000000000
|
|
101000000001000000000010001001101100000000000000000000
|
|
|
|
.logic_tile 8 4
|
|
110001000000000001100000001111011000110110100000000000
|
|
001000100001000101100000001011111011111000100000000000
|
|
101000000001000001100110000000000001001111000100000000
|
|
101000000000100111000100000000001101001111000000000000
|
|
000000000000000101000010110011101010010101010000000000
|
|
001000000000001101000111010000010000010101010000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
001000000000000101000000000000000000000000000000000000
|
|
000000100000001000000000010000001010100101100000000000
|
|
001001000000000001000011100101001000011010010000000000
|
|
000000000000001001000011110011011011000010000000000000
|
|
001001000000000001000110010001111001000001010000000000
|
|
000000000000000001000000010000000000000000000000000000
|
|
001000000000000000100011100000000000000000000000000000
|
|
010000000000000000000000001011011101000000010000000000
|
|
011000000000000000000000000001001010000000000000000010
|
|
|
|
.logic_tile 9 4
|
|
010001001010000000000000000000001110001100110100000000
|
|
001010100000000000000000000000001110001100110000000000
|
|
001000000000000101000010101011011110110011000000000000
|
|
100000000000000000000000000001001011000000000010000000
|
|
010000000000000000000111111000000000000000000100000000
|
|
111000000000000000000010100101000000000010000000000000
|
|
000000000000000111100011100000000000000000100100000000
|
|
001010100000000000000000000000001011000000000000000000
|
|
000001000000101000000000001111000000000000000100000000
|
|
001000000000000011000000001101000000111111110000000000
|
|
000000000000000000000000001000000000000000000100000000
|
|
001000000000000000000000001001000000000010000000000000
|
|
000000001010101001100000000000000000000000000000000000
|
|
001000000001011001100000000000000000000000000000000000
|
|
010000001100000101000000000000000001000000100100000000
|
|
101000000000000000100000000000001000000000000000000000
|
|
|
|
.ramt_tile 10 4
|
|
000000010000110111100000000000000001000000
|
|
000000000001110000000011101101001101000000
|
|
001000010000001000000000000101100000000000
|
|
100000000000000111000000001111101000010000
|
|
110000001110001000000011101000000000000000
|
|
010000000000000111000000000001000000000000
|
|
000000000000000111100111101000000000000000
|
|
000000000000000000100111100011000000000000
|
|
000000000000000000000000010000000000000000
|
|
000000000001010111000011111001000000000000
|
|
000000000000000001000000000011000000000000
|
|
000010100000000000000010000101000000100000
|
|
000000000001010000000000001000000000000000
|
|
000010100000100000000010000101000000000000
|
|
110000000000000001000000001000000000000000
|
|
110000000000100000000000001101000000000000
|
|
|
|
.logic_tile 11 4
|
|
110000000000000000000110000101101001000000010000000000
|
|
001000000000000000000010100111011101000000000000000000
|
|
111000000000000101000010100111111100000000000000000000
|
|
000000000000000000100010100111101010111111000000000000
|
|
000000000000000111100000001111011110010010000000000000
|
|
001000000000000101100010111101001100110011000000000000
|
|
000000000000000000000111101111011100111100000000000000
|
|
001000001000000101000011101101101010001111000000000000
|
|
000000000000000000000000001000000000000000000100000001
|
|
001000000000001111000011111001000000000010000000000000
|
|
000000000000001000000000011000001000101000000000000000
|
|
001000000000001011000010001001010000010100000000000000
|
|
000000000001011001100010010111111000011000000000000000
|
|
001000000000100011000010000000101010011000000000000000
|
|
000000000000001000000111000011000000100000010000000000
|
|
001000000000001011000011111111101011000000000000000000
|
|
|
|
.logic_tile 12 4
|
|
010000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000100000000000000000000000000000000000000000000000
|
|
000001000110000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000010000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000011010000000000000000000000000000000000000000
|
|
001000000000100000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 4
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100011001
|
|
000000000100000000
|
|
000000000100000000
|
|
001100000100000000
|
|
000000000100000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000001000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 5
|
|
000000111100001010
|
|
000100000100000000
|
|
000000000100000000
|
|
000000000100000001
|
|
000000000100010010
|
|
000000000100110000
|
|
001110000100000000
|
|
000010010100000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000010
|
|
000000000000010000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000010
|
|
000000000000000000
|
|
|
|
.logic_tile 1 5
|
|
010000000000001000000000000111111100101000000100000000
|
|
001000000000000001000000000000110000101000000000000000
|
|
111000000000001000000000001001000000101001010100000000
|
|
000000000000000111000000001111000000000000000000000000
|
|
010000100000000000000111000111100001100000010100000000
|
|
111001000000000000000000000000101010100000010000000010
|
|
000000000000000001100000001000000001100000010100000000
|
|
001000000000000000000000001111001110010000100000000100
|
|
000000000000000001100110000111101100101000000100000000
|
|
001000000000000000000010100000100000101000000000000010
|
|
000000000000000000000110000000000001100000010100000000
|
|
001000000000000000000000001011001111010000100000000000
|
|
000000000000000000000000001000000000010110100000000000
|
|
001000000000000000000000000001000000101001010000000000
|
|
110000000000000000000000000000001101110000000100000000
|
|
001000000000000101000011010000011111110000000000000000
|
|
|
|
.logic_tile 2 5
|
|
010000000000000101000000001111000000100000010000000000
|
|
001000000000000000000000000101101010111001110000000010
|
|
111000000000000011100000001000000000100000010100000000
|
|
000000000000000000100000000001001101010000100000000000
|
|
010000000000000101100000001011001010101000000000000000
|
|
101000000000010000000010110101010000111101010010000000
|
|
000000000000000111000110100101111011111000100000000000
|
|
001000000000000000000000000000011101111000100010000000
|
|
000000000000000001100010100001011101101100010000000000
|
|
001000000000000000000100000000001010101100010000000000
|
|
000000000000000001100110010011100001100000010100000000
|
|
001000000000000000000010010000101000100000010000000000
|
|
000000000000100000000000010001111100101000000100000000
|
|
001010000000000000000010010000000000101000000010000000
|
|
010000000000000000000000001000000000100000010100000000
|
|
001000000000000000000000000001001100010000100000000000
|
|
|
|
.ramb_tile 3 5
|
|
010000000000001000000011100000000000000000
|
|
001001000000001111000010000001001010000000
|
|
111010000000011000000000000011100000000000
|
|
000001000000100101000000001001001111000000
|
|
010000100000000111000000001000000000000000
|
|
011000000000000000000000001111000000000000
|
|
000000000000000111100000000000000000000000
|
|
001000001010000000000011100111000000000000
|
|
000000000000100000000000001000000000000000
|
|
001000000011010000000000000111000000000000
|
|
000010000000001001000000001001100000000000
|
|
001001000000001001100000001101000000000000
|
|
000000100001000000000010010000000000000000
|
|
001000000000000001000111001111000000000000
|
|
010000000000000011100111001000000000000000
|
|
111000000000000000100100000011000000000000
|
|
|
|
.logic_tile 4 5
|
|
110000000001000101100000000011100000000000000100000000
|
|
001000000110000000000000000000000000000001000000000000
|
|
011000000000000101100000000111000000000000000100000000
|
|
100000000000000000000000000000000000000001000000000000
|
|
110000000000000111000011110000000000000000100100100000
|
|
101000000000000000100011110000001010000000000000000000
|
|
000010100000000000000000001000000000000000000100000000
|
|
001001000000000000000000000001000000000010000000000000
|
|
000000000001000000000000000101000000000000000100000000
|
|
001000001010000000000000000000100000000001000000000000
|
|
000000000000000101000000000000000000000000100100000000
|
|
001000001100000000100000000000001000000000000000100000
|
|
000000100001000101000000000000000000000000000000000000
|
|
001001000000100000100000000000000000000000000000000000
|
|
010000000000000000000000000000001010000100000100000000
|
|
101000000000000000000000000000010000000000000000000010
|
|
|
|
.logic_tile 5 5
|
|
010000000100000101000010100001111010111101010000000000
|
|
001000001100000000100110110011000000010100000000000001
|
|
001000000001010111000000000000000000000000000110000001
|
|
100000000000100000000000001001000000000010000001000010
|
|
010000000110000000000011100000000001000000100110000001
|
|
111000000000000000000000000000001011000000000000100001
|
|
000000000000000101000010100001000000000000000100000001
|
|
001000001110001111100110110000100000000001000001100001
|
|
000000000000001000000000001000000000000000000110000000
|
|
001000000100000111000000000101000000000010000010000001
|
|
000000000000000000000000001000000000000000000110000100
|
|
001000000000000000000000001101000000000010000011000001
|
|
000000000000000000000000000111100000010110100110000000
|
|
001000000000000000000000000000100000010110100000100011
|
|
010000000000000000000000010000000000000000100110000000
|
|
101000000000000000000010000000001000000000000000100011
|
|
|
|
.logic_tile 6 5
|
|
110001000000000111000010100000000000000000000000000000
|
|
001010100001010000000010100000000000000000000000000000
|
|
111001000000000001100110000111101100001001000000000000
|
|
000000100000001101100000001111101000000010000000000000
|
|
000000001000000000000110001001111010111000110100000000
|
|
001000000000000101000111100001111111110000111000000000
|
|
000000000000000000000000010011101011100000000000000000
|
|
001000000000000000000011011001011000000000000000000000
|
|
000001001000000000000010100011001010000011010000000000
|
|
001010000100000101000010010011101110000010110000000000
|
|
000000100000001000000110100000001100110011110010000000
|
|
001001000000000001000010100000011000110011110000100011
|
|
000000001110000101100110010011011100010010100000000000
|
|
001000100001000000000010001001111110001001010000000000
|
|
010000000000000000000110100111011100101000000000000000
|
|
101000000000000000000000001101010000000010100000000000
|
|
|
|
.logic_tile 7 5
|
|
110000000110001000000000010000011010000100000100000000
|
|
001000100000000111000011100000010000000000000000100000
|
|
111000000000000000000111010000011000000100000100000000
|
|
000000000000001111000011100000010000000000000000000000
|
|
000000000000000000000000000000011010000100000100000000
|
|
001000000000000000000000000000000000000000000000100000
|
|
000000000000001011100000000000001000000100000100100000
|
|
001000000000000111000011110000010000000000000000000010
|
|
000000000000000000000000001000000000000000000100000000
|
|
001000000000000000000000000001000000000010000000000000
|
|
000000001000000000000000011101111101100010000000000000
|
|
001000000110000001000010000111011001001000100000000000
|
|
000001000000000000000000000000000000000000100100000000
|
|
001010000110000000000000000000001000000000000000100000
|
|
000000000000011000000000000011100000000000000100000000
|
|
001000000000100001000000000000000000000001000000000000
|
|
|
|
.logic_tile 8 5
|
|
010000000000000000000000010000000000000000000100000000
|
|
001000000000000000000010001001000000000010000010000000
|
|
001000000110000000000000000000001100000100000100100000
|
|
100000000000001101000000000000010000000000000000000000
|
|
000000000000000101000000001000000000000000000100000000
|
|
001000000000000000100000000001000000000010000000000000
|
|
000001000000000000000000010000001110000100000100100000
|
|
001000100000000000000010000000010000000000000010000000
|
|
000000000000000000000000001000000000000000000100000000
|
|
001000000000000000000010110011000000000010000000000000
|
|
000000000000000000000000000000000001000000100100000000
|
|
001000000010001101000000000000001011000000000000000001
|
|
000000000001010000000011100000000000000000100100000000
|
|
001010000000000000000000000000001010000000000000000000
|
|
000000000000001000000000000000000001000000100100000000
|
|
001000000000000001000000000000001110000000000010100000
|
|
|
|
.logic_tile 9 5
|
|
110000001000100000000010100000001000000100000100000000
|
|
001000000001000101000000000000010000000000000001000000
|
|
111000000000000000000000000101100000000000000100000000
|
|
000000000000000101000000000000000000000001000001000000
|
|
000100000000000000000000000101000000000000000100000000
|
|
001100000000000000000010100000100000000001000001000000
|
|
000000000000000101000010100001000000000000000100000000
|
|
001000000000000000000000000000000000000001000001000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000001000000100110000000
|
|
001000000000000000000000000000001011000000000000000000
|
|
000000000000000000000000000000011000000100000110000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
|
|
.ramb_tile 10 5
|
|
010000000000100111000000001000000000000000
|
|
001000000000010000000011110101001100000000
|
|
111000000000001000000000001001000000100000
|
|
000001000000100111000000001111101110000000
|
|
110000000000000111100011101000000000000000
|
|
111000000000000000000000001101000000000000
|
|
000000000000001111000111001000000000000000
|
|
001000000000001011000100000101000000000000
|
|
000010000000001111100000000000000000000000
|
|
001001001100001011000000001101000000000000
|
|
000000000000000000000000000101000000100000
|
|
001000000000000001000000000001000000000000
|
|
000000000001011000000111001000000000000000
|
|
001000101010000011000100000001000000000000
|
|
110000100001000000000000000000000000000000
|
|
011000001000000000000010000011000000000000
|
|
|
|
.logic_tile 11 5
|
|
010010000000000000000000000000000000000000000000000000
|
|
001001000000000101000000000000000000000000000000000000
|
|
001000000000001101000000000000000000000000000000000000
|
|
100001000000001101000000000000000000000000000000000000
|
|
000010100000000000000000001101000001101001010000000000
|
|
001001000110001101000000000011001000010000100000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000100000010000000000000001101111111001010100000000
|
|
001001001110000000000000000001011011110000000010000000
|
|
000000000000001000000110001111011100000000000000000000
|
|
001000000000000001000000001011000000000001010000000100
|
|
000010100000000111000000000000000000000000000000000000
|
|
001001000000000000000011110000000000000000000000000000
|
|
010000000000100000000000000000001110000100000100000000
|
|
101000000000010000000000000000000000000000000000000000
|
|
|
|
.logic_tile 12 5
|
|
010010100000000000000000000000000000000000000000000000
|
|
001001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000010100000000000000000000000000000000000000000000000
|
|
001001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 5
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 6
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 6
|
|
000000000000000001100000000111000000101001010100000000
|
|
000000000110010000000000000101000000000000000000000000
|
|
111000000000000101000000000101100000101001010100000000
|
|
000000000000000000000000000111000000000000000000000000
|
|
010000000000000001100000000011001110101000000100000000
|
|
100000000000000000000011110000000000101000000000000000
|
|
000000000000000001100110000000000000100000010100000000
|
|
000000000000001111000000000111001011010000100000000000
|
|
000000000000001011000000011001011010101001010000000000
|
|
000000000000000001100010000011000000010101010000000001
|
|
000000000000001000000000000000001100110000000100000000
|
|
000000000000000101010000000000011110110000000000000000
|
|
000000000000000000000000000101111001111000100000000000
|
|
000000000000001011000000000000001011111000100000100000
|
|
010000000000000000000000000000001100101000000100000000
|
|
000000000000000000000000000111000000010100000000100000
|
|
|
|
.logic_tile 2 6
|
|
000010100000000000000110110101011100101000000100000000
|
|
000000000000010000000010100000100000101000000000000000
|
|
111000000000000101100000000101001000111101010000000000
|
|
000000000000000000000000000101010000010100000000000010
|
|
010000000010001111100111001101000000101001010100000000
|
|
110000000000000001100111100101100000000000000000000000
|
|
000000000000000001100000000101011010111000100000000001
|
|
000000000000000000000000000000001001111000100000000000
|
|
000000000101000000000000001000001010101000000100000000
|
|
000010000000010000000000001011010000010100000000000000
|
|
000000000000000111000000010111100000101001010100000000
|
|
000000000000000000000010001101000000000000000000000000
|
|
000000000001000000000000000101001010101000000100000000
|
|
000000000000100000000000000000010000101000000000000000
|
|
110000000000000101000000000101011101111000100000000100
|
|
000000000000000000100000000000011000111000100000000000
|
|
|
|
.ramt_tile 3 6
|
|
000010110000001000000000011000000000000000
|
|
000000001000001111000011001101001100000000
|
|
001000010000000001000000001101000001000000
|
|
100000000000000111100000001101001111000000
|
|
110000000000000011100000000000000000000000
|
|
110010000100000000100000000111000000000000
|
|
000000000000011000000111111000000000000000
|
|
000000000000100111000111110011000000000000
|
|
000010100001011000000000001000000000000000
|
|
000000000000000111000000001111000000000000
|
|
000000000000000011100000001001000000000000
|
|
000000000000000000100000000101100000000000
|
|
000000000001000011100010000000000000000000
|
|
000000000000100000000000000001000000000000
|
|
010000000001010000000111001000000000000000
|
|
010000000000000000000111110001000000000000
|
|
|
|
.logic_tile 4 6
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
011000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
110000000000010000000000000000011100000100000100100000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000101000000000000000000000000000000000000
|
|
000000000000000000100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 5 6
|
|
000000000100000101000000000000000001000000001000000000
|
|
000000000000000000000010100000001001000000000000001000
|
|
000000000000000000000000000101111000001100111000000000
|
|
000000000000000000000010100000110000110011000010000001
|
|
000001000000000000000010100000001000001100111000000000
|
|
000010100000000000000000000000001011110011000010000000
|
|
000010001011010101000010100000001000001100111000000000
|
|
000000000000000101000000000000001000110011000000100001
|
|
000000101110000000000000000111001000001100111000000100
|
|
000000000000100000000000000000000000110011000000000000
|
|
000000100001010000000000000000001001001100111000000000
|
|
000011000000110000000000000000001010110011000000000000
|
|
000001000000001000000000000000001001001100111000000000
|
|
000010100000000011000000000000001010110011000000000001
|
|
000000000000010000000000000001001000001100111000000110
|
|
000000001110000000000000000000100000110011000000000000
|
|
|
|
.logic_tile 6 6
|
|
100001000000000011100000010000000000000000000000000000
|
|
000010100001000000000010000000000000000000000000000000
|
|
111000000011010000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000001000000000000010000101000000010110100100100000
|
|
110000000000000000000010100000100000010110100000000000
|
|
000000000001100001100110000101101000111100000000000000
|
|
000000100111110000100100000001110000010100000000000000
|
|
000000001000000000000110001000001100100000000000000000
|
|
000000100001000000000000000101011110010000000000000000
|
|
000010100001010000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000001001100110101100000000000000001001111000000000000
|
|
000000000000000000000000000000001111001111000001000001
|
|
010000000100000000000010000000000000000000000000000000
|
|
100000000000010000000000000000000000000000000000000000
|
|
|
|
.logic_tile 7 6
|
|
100000000000000000000000000000011010000100000100100000
|
|
000000000000000000000000000000010000000000000000000000
|
|
111000001110000000000010110001111011010100010000000000
|
|
000000000000000000000011010101111001100010100000000000
|
|
110010100000000000000000001000000000000000000100000000
|
|
010001000000000111000000000011000000000010000000000000
|
|
000000000000000111000010010000011010000100000100000000
|
|
000000000001000000000011010000000000000000000000100000
|
|
000000000100000000000110100000011101001100110100000000
|
|
000000000000000000000111100000001010001100110000000000
|
|
000000000000001101110000000000000001011001100100000000
|
|
000000000000001101100000001011001100100110010000000000
|
|
000000000100000000000000000000011011001100110000000000
|
|
000000000001010000000000000000011010001100110000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 8 6
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000001000100000000000000000000000000000000000000000
|
|
111000000000000000000000000000011010000100000100000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
110000000000000000000010000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
000000000000000011100010010000000000000000000000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000000000000000000000000101100000000000000100000000
|
|
000000000000000000000011100000100000000001000000000000
|
|
000000000000000000000000000000011010000100000100000000
|
|
000010100000000000000000000000010000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000101000000010110100100000000
|
|
100000000000000000000000000000100000010110100000000000
|
|
|
|
.logic_tile 9 6
|
|
000000000000010000000010100000001000000100000100100001
|
|
000000000000000000000100000000010000000000000000000000
|
|
001000000000000000000110100000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000001010000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000001001000000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000000000000000
|
|
000000000000100000000000001000000000000000000100000000
|
|
000000000001010000000000001001000000000010000010000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000110000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.ramt_tile 10 6
|
|
000000010111111000000111100000000000000000
|
|
000000101110111111000111110101001000000000
|
|
001000010000000000000000000011100000100000
|
|
100001000000000000000000000101001011000000
|
|
110000000000000111000000011000000000000000
|
|
010000001101011111100011110101000000000000
|
|
000001000000000111000000001000000000000000
|
|
000000101000000000100000000011000000000000
|
|
000010000001010000000000000000000000000000
|
|
000001000000100000000010001111000000000000
|
|
000000000000000001000000000111100000000000
|
|
000000000000000111100000001001100000010000
|
|
000000000001010000000111000000000000000000
|
|
000000000000000000000100001001000000000000
|
|
110000000000000001000111011000000000000000
|
|
110000000000000000100111011111000000000000
|
|
|
|
.logic_tile 11 6
|
|
000000000000000000000000000111000000000000000100100000
|
|
000000001110000000000011100000100000000001000000000000
|
|
001000000000000000000000001111011100010110100000000001
|
|
100000000000000000000000000101110000010101010000000000
|
|
000000000000000000000000000111100000000000000100000000
|
|
000000000000000000000000000000100000000001000000100000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000001010101000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000011100000000000000000000000000000
|
|
000000000000010000000010010000000000000000100100000000
|
|
000000001100100000000111100000001001000000000000100000
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
|
|
.logic_tile 12 6
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000100000000000000000000000000000000000000000000
|
|
101000000000000000000010110000000000000000000000000000
|
|
110000000000000111000000000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
000000000000000011100000000000000000000000000000000000
|
|
000000000000000000100000000000000000000000000000000000
|
|
000000000000000000000110100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000000000000000000000000000001111000000000000
|
|
000000000000000000000000000000001101001111000000000100
|
|
000000000000000000000011001000000000000000000100000000
|
|
000000000000000000000000001001000000000010000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 6
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
001000000000000000
|
|
000000000000000000
|
|
100000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 7
|
|
000000000000000000
|
|
000000000001000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 7
|
|
000000001100000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000000000000000
|
|
111000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011010000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
010000000000000101000000000000000000000000000000000000
|
|
000000000000000000000011100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011000000000000000000000000000000
|
|
000000000000001000000000000000011100000011110100000000
|
|
000000000000000111000000000000000000000011110000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000101111000111000100000000000
|
|
000000000000000000000000000000111010111000100010000000
|
|
|
|
.logic_tile 2 7
|
|
000000000001010000000000001000000000000000000100000000
|
|
000000001010000000000000000111000000000010000000100000
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000100000000000000000000000000000000000000000000000
|
|
000001000000010000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000110000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000100000000000000000000000000000000000000000000
|
|
000000000000010000000000000000000000000000000000000000
|
|
000000000000000011100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.ramb_tile 3 7
|
|
000000000001000000000000001000000001000000
|
|
000000000000100000000000000111001001000000
|
|
111000000000000000000111110011100000000000
|
|
000000000000001111000111110101101011000000
|
|
010000000000001000000111111000000000000000
|
|
110000000000001111000111001101000000000000
|
|
000000000000000011100111001000000000000000
|
|
000000000000000000100100001001000000000000
|
|
000000000000000000000000001000000000000000
|
|
000000000000000000000000000101000000000000
|
|
000010100000000001000111011111000000000000
|
|
000000000000000000000111101011000000000000
|
|
000000100000000111000010000000000000000000
|
|
000000000000100000100000001111000000000000
|
|
010000000000000011100000001000000000000000
|
|
010000000000000000100000000011000000000000
|
|
|
|
.logic_tile 4 7
|
|
100000100000010101100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
011010100000000101000010100111000000000000000100000000
|
|
100001000000000000100100000000000000000001000000000000
|
|
110000000000000000000011110011100000000000000100000000
|
|
100000000000000000000110000000000000000001000000000000
|
|
000000000000000000000011100000000000000000000000000000
|
|
000000000000000000000110110000000000000000000000000000
|
|
000000000001000001100000000001000000000000000100000000
|
|
000001000000000000000000000000000000000001000000000000
|
|
000010000000000101000000001101011010000000010000000000
|
|
000001000000000000100000001101111100000010110000100000
|
|
000000000000000101000000001101011000000100000000000000
|
|
000000000000000000100000001101101011101000010000100000
|
|
010000000001011000000000001101101011000000100000000000
|
|
100000000000100001000000000111111001010100100000000100
|
|
|
|
.logic_tile 5 7
|
|
100000000000000101000000000001001000001100111010000000
|
|
000000000000000000100000000000000000110011000010010100
|
|
011010000000000000000111100000001000001100110000100000
|
|
100001000000000111000000000011000000110011000000000100
|
|
110001000000000101100000000000000001000000100100100000
|
|
100010000000000000100000000000001100000000000000000000
|
|
000000000001000101000000001101100000000000000000000000
|
|
000000000000100101000000000101000000111111110000000000
|
|
000001000000000011100000000000011000000100000100000000
|
|
000000000010000000100000000000010000000000000000100000
|
|
000000001000000000000000000000011000000100000100000000
|
|
000000000000000001000000000000000000000000000000000000
|
|
000000000000000000000000000111000000000000000100000000
|
|
000000001010000001000000000000000000000001000000000000
|
|
010000000000010000000000000000001010000100000100000000
|
|
100000000000000000000000000000000000000000000000100000
|
|
|
|
.logic_tile 6 7
|
|
000000000000100000000111100000000001000000100100000000
|
|
000000000110010000000100000000001000000000000000000000
|
|
001000000000001101100000010000001100000100000100000000
|
|
100000000000000011000010100000000000000000000000000000
|
|
000000001110100001100000000111111100010101010000000000
|
|
000000000000000000000000000000100000010101010000000000
|
|
000100000000000000000000001111111000101001000000100000
|
|
000100000000000000000000000001011101100000000000000000
|
|
000000001010101000000110100000000000000000000000000000
|
|
000010100000010001000000000000000000000000000000000000
|
|
000000000000000001100000000000000000000000000000000000
|
|
000010100000000000100000000000000000000000000000000000
|
|
000001000010000000000000000000000000000000000000000000
|
|
000000100000100000000000000000000000000000000000000000
|
|
010000000000000101100000010011001010000000000010000000
|
|
100000000000000000000010011001000000000001010001100011
|
|
|
|
.logic_tile 7 7
|
|
100000000000000000000110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
011000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000001001011110101011110000000001
|
|
000000000000000000000000000111100000000011110000000000
|
|
000000001110000000000000000000000000010110100110100000
|
|
000000000000000000000000001001000000101001010001100010
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000011110010101010110000000
|
|
000000000000000000000000001001000000101010100001000110
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000001100000000000000000000000000000000000
|
|
100000000000001011000000000000000000000000000000000000
|
|
|
|
.logic_tile 8 7
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000001000000000000000000000000000000000000000000
|
|
000000000010000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000001100000000000000000000000000000000000
|
|
000000001100000000100000000000000000000000000000000000
|
|
000000000000001000000000000000001110000100000100000000
|
|
000000000000001001000000000000000000000000000010000000
|
|
000000000000000000000000001000000000000000000100000000
|
|
000000000000000000000000000011000000000010000000100000
|
|
|
|
.logic_tile 9 7
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000111000000000000000100000000
|
|
100000000000000000000000000000000000000001000000000000
|
|
000010100000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000111100000000000000100000000
|
|
000000000000000000000000000000000000000001000000000000
|
|
000001000000000001100000000011000000000000000000000001
|
|
000010000000000000000000000111000000010110100000000000
|
|
000000001100000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000111100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000001100000000000000000000000000000000000
|
|
000000000000000000100000000000000000000000000000000000
|
|
|
|
.ramb_tile 10 7
|
|
000010100001010111100000010000000001000000
|
|
000010100000001111000011101011001011000000
|
|
111000000000000000000000000101100001010000
|
|
000000000000000000000000000101001010000000
|
|
010000000100001111000111100000000000000000
|
|
010000000001010111000100001101000000000000
|
|
000000000000000111000011100000000000000000
|
|
000000000000001111100100000001000000000000
|
|
000000001001010111000000000000000000000000
|
|
000000000001100000000011100101000000000000
|
|
000000000000000000000000000001000000000000
|
|
000000000000001111000000000011000000010000
|
|
000001001001010000000000001000000000000000
|
|
000010000000100001000000001111000000000000
|
|
110000000000000000000010000000000000000000
|
|
010000000000000000000000000111000000000000
|
|
|
|
.logic_tile 11 7
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
101000000000000001100000000000000000000000100100000000
|
|
001000000000000000100000000000001110000000000000000000
|
|
010000000000000000000110000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000001000000000000000000000000000
|
|
000000000000000000000000000001000000000010000000000000
|
|
000000000000000001100000000000001100000100000100000000
|
|
000000001110000001000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000001000000000000000000000000000000000000000
|
|
000000000000001101000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 12 7
|
|
000000000000000000000000000000000001000000001000000000
|
|
000000000000000111000000000000001010000000000000001000
|
|
001000000000000000000000000101011010001100111100000000
|
|
001000000000000111000000000000000000110011000000000000
|
|
000000000000000001100000000111001000001100110100000000
|
|
000000000000000000000000000000100000110011000000000000
|
|
000000000000000001100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000001111001110111100110000000010
|
|
000000000000000000000000000101101010111100000000000000
|
|
000000000100000000000000000000011010000011110100000000
|
|
000000000000000000000000000000000000000011110000000000
|
|
000000000100001000000000011111000000100000010000000000
|
|
000000000000001101000010000101101010000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 7
|
|
000000000000000010
|
|
000100000000000000
|
|
000010000000000000
|
|
001010110000000001
|
|
000000000000000010
|
|
000000000000110000
|
|
001000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 8
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000100
|
|
000000000000001100
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000011010000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 8
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011100000000000000000000000000100
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000011100001011001100000000000
|
|
010000000000000001000000000000101011011001100000000100
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000000000000000001000000000000000000111000001
|
|
000000000000000000000000000011000000000010000000000010
|
|
000000000000000000000111100000000000000000100110000101
|
|
000000000000001001000100000000001010000000000000000010
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 2 8
|
|
000010000000000000000111100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
001000000000001000000000000001100000000000000100000000
|
|
100000000000000111000000000000000000000001000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000001110000100000100000001
|
|
000000000000000000000000000000000000000000000010000000
|
|
000000000000000000000000000111001001110001010000000001
|
|
000000000000000000000000000000011110110001010000000000
|
|
000000000001000000000000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
000000000000000001100000000000000000000000000000000000
|
|
000000000000000111000000000000000000000000000000000000
|
|
000000001110000001100000000000000000000000000000000000
|
|
000000000000000000100000000000000000000000000000000000
|
|
|
|
.ramt_tile 3 8
|
|
000010010000011000000000011000000000000000
|
|
000001000010100111000011101101001011000000
|
|
001000010001010011100000010011000001000000
|
|
100000000000100000100011111111001010000000
|
|
110000000000001111000011100000000000000000
|
|
110000000000001111000000000001000000000000
|
|
000000000001001000000111101000000000000000
|
|
000000000000000111000000000001000000000000
|
|
000010100000000000000000001000000000000000
|
|
000001000000000001000000001001000000000000
|
|
000000000000000000000000000101000000000000
|
|
000000000010000001000000000101000000000000
|
|
000000000000000000000010000000000000000000
|
|
000000000000000000000110001001000000000000
|
|
110000000000000000000000001000000000000000
|
|
010000000000000101000000000111000000000000
|
|
|
|
.logic_tile 4 8
|
|
100010000001010001000000000011100000000000000100000100
|
|
000000000000000000000000000000000000000001000000000000
|
|
011000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
110000000000010000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000100000000000
|
|
000000000000000000000000000000001000000000000000000000
|
|
000010000000000101000111000000000000000000000000000000
|
|
000000000000000000100000000000000000000000000000000000
|
|
000000000000000101000000000111000000000000000100000000
|
|
000000001100000000100000000000100000000001000000000000
|
|
000000000000000000000111000000001100000100000100000000
|
|
000000000000000000000100000000010000000000000000000000
|
|
010000000000000000000000000000000000000000100100000000
|
|
100000000000000000000000000000001100000000000000000000
|
|
|
|
.logic_tile 5 8
|
|
000000001110000101000010110000001010000100000110100000
|
|
000000000000000101000010010000000000000000000001000001
|
|
001000001100000000000000000001000000000000000110100000
|
|
100000000000000000000000000000000000000001000011000001
|
|
010001000000000000000110100000001001110011000000000000
|
|
110000000000000111000010110000011111110011000000000000
|
|
000000000000000001100110000001001110010101010000000000
|
|
000000000000000000000100000000100000010101010000000000
|
|
000000000100000000000110010000001000000100000100000001
|
|
000000000000000000000010000000010000000000000000000000
|
|
000000000000000000000000000111011010100000000000000000
|
|
000010100000000000000000000111111000000100000000000000
|
|
000000000000001011100111100000000000000000100100000010
|
|
000000000000000101100100000000001001000000000000000000
|
|
010000001100000000000111000011011010000000000000000000
|
|
100000000000000000000100001011101011100000000000000000
|
|
|
|
.logic_tile 6 8
|
|
000001000000001000000011110101101010010101010000000000
|
|
000000101000000101000011110000110000010101010000000000
|
|
001000000010101000000111110001000001010000100000000000
|
|
100000001110001111000111100101101010001001000000000000
|
|
110001001100001000000111010001000000100110010000000000
|
|
010000100000100101000111010000101000100110010000000000
|
|
000000000000001000000000000000000001000000100100000000
|
|
000000000000010011000011110000001001000000000000100000
|
|
000000000000100001100000000000000000000000000000000000
|
|
000000000001000000000011100000000000000000000000000000
|
|
000000000000000000000010101000000000000000000100000010
|
|
000000000000000000000100001111000000000010000000000000
|
|
000000001100000000000000011111001101000000000000000000
|
|
000000000000000000000010001001101111000000110000000000
|
|
010000000000000000000110001101000001110000110000000000
|
|
010000000000010000000010001101101101000000000000000000
|
|
|
|
.logic_tile 7 8
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
110000000010110000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
000000000000000001000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000111100000000000000100000010
|
|
000000000000000000000010010000000000000001001000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
110000000000000001000000000000000000000000000000000000
|
|
|
|
.logic_tile 8 8
|
|
000000001010100000000000000000000000000000000000000000
|
|
000000000001010000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000001000000000000010000000000000000000000000000
|
|
000000000000100000000011000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000100110000000
|
|
000000000000000000000000000000001011000000000000000000
|
|
|
|
.logic_tile 9 8
|
|
000000001000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000100000000111100000000000000000000000000000
|
|
000000000000010000000100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000001010000000000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000100000000
|
|
000000000100000000000000001101000000000010000000000000
|
|
000001001100000000000000000000000000000000000000000000
|
|
000010100000000000000000000000000000000000000000000000
|
|
|
|
.ramt_tile 10 8
|
|
000000010111011000000000001000000000000000
|
|
000000000000101111000000001001001010000000
|
|
001000010110001000000011100101100000000000
|
|
100000000000000111000111100111101011100000
|
|
010000000000001111000011110000000000000000
|
|
110000100010000111100111000111000000000000
|
|
000000000000100011100011111000000000000000
|
|
000000000000010000100011011001000000000000
|
|
000000000110000000000000001000000000000000
|
|
000000000001010000000000000001000000000000
|
|
000000000110000000000000000101100000000000
|
|
000000000000000000000000000101000000100000
|
|
000000000000001111000000000000000000000000
|
|
000000000000000011100000000001000000000000
|
|
110000000000000001000000001000000000000000
|
|
110000000000000000000000001101000000000000
|
|
|
|
.logic_tile 11 8
|
|
000000000000000101000000000000000000000000000100000000
|
|
000000000000000000000000000011000000000010000000000000
|
|
001000000000000000000000000111100000000000000100000000
|
|
101000001100000000000000000000100000000001000000000000
|
|
010000000000010001000110100000011010000100000100000000
|
|
110000000000100000000100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000100100000000
|
|
000000000000000101000000000000001101000000000000000000
|
|
000000000000001000000110101000000000000000000100000000
|
|
000000000000000101000000000011000000000010000000000000
|
|
000000000000001101100110101000000000000000000100000000
|
|
000000000000000101000100001011000000000010000000000000
|
|
001000000000000000000000000011100000000000000100000000
|
|
000000001110000000000000000000000000000001000000000000
|
|
000000000000000000000110100000000000000000000100000000
|
|
000000000000000000000000000001000000000010000000000000
|
|
|
|
.logic_tile 12 8
|
|
000000000000001000000000010000000001000000100100000000
|
|
000000000000000001000011000000001010000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
101000000000000000000010100000000000000000000000000000
|
|
010000000000101011100000000000000000000000000000000000
|
|
010000000000010011000000000000000000000000000000000000
|
|
000000000000000001100000001000000000000000000100000000
|
|
000000000000000000000000001011000000000010000000000000
|
|
000000000000000000000110000011000000000000000100000000
|
|
000000000000000000000000000000100000000001000000000000
|
|
000000000000001000000110000011100000000000000100000000
|
|
000010000000001001000000000000000000000001000000000000
|
|
000000000000000000000000001101000000000000000001000000
|
|
000000000000000000000000001001000000010110100000000000
|
|
000000000000000000000000000001000000000000000100000000
|
|
000000000000000000000000000000000000000001000000000000
|
|
|
|
.io_tile 13 8
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000111000000100
|
|
000000000000000100
|
|
000000000000000000
|
|
000000000000000000
|
|
010000000000000000
|
|
010100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000001001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 9
|
|
000000000000000000
|
|
000000000000001000
|
|
000000000000100000
|
|
000000000000000000
|
|
000001111000000100
|
|
000000001000000100
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 9
|
|
000010100001000000000000000000000000000000001000000000
|
|
000000000000000000000000000000001010000000000000001000
|
|
000000000000000101000000010000001011001100111000000000
|
|
000000000000000101100011110000001010110011000000000000
|
|
000000000000000101000010100101101000001100111000000000
|
|
000000000000000000100100000000100000110011000000000000
|
|
000000000000000101000000000101101000001100111000000000
|
|
000000000000001101000010110000000000110011000000000000
|
|
000000000000000000000000000000001000001100111000000000
|
|
000000000000000000000000000000001011110011000000000000
|
|
000000000000100000000000000001101000001100111000000000
|
|
000000000001010000000000000000000000110011000000000000
|
|
000000000000000000000000000001101000001100111000000000
|
|
000010000000000000000000000000000000110011000000000000
|
|
000000000000000000000000000001101000001100111000000000
|
|
000000000000000000000000000000100000110011000000000000
|
|
|
|
.logic_tile 2 9
|
|
000010100010000111000110100000000001011001100000000000
|
|
000000000000000111100011110001001000100110010000000000
|
|
111000000000001000000111001000011100110001010000000000
|
|
000000000000000101000111001001011000110010100000000000
|
|
110000000001001101100011110000001001011010010000000000
|
|
110000000000001111000010101101011000100101100000000000
|
|
000000000000000111100110110011101000001000010000000000
|
|
000000000000000000100010101001011011100001000000000000
|
|
000000000000010000000110010101000001001111000000000000
|
|
000000000000000001000010000101101010110000110000000000
|
|
000000001000001000000110000011011000110001010100000000
|
|
000000000000000001000010000000011110110001010110000000
|
|
000000000000000000000111000011101100100000000000000000
|
|
000000000000000001000000000000111101100000000000000100
|
|
010010100000000000000000000000011011011010010000000000
|
|
100001001100000000000000000101011011100101100000000000
|
|
|
|
.ramb_tile 3 9
|
|
000000000000000000000000000000000001000000
|
|
000000000000000000000010001101001100000000
|
|
111000000000000000000111000101000000000000
|
|
000000001110000000000111101111001101000000
|
|
010000001110000101100011100000000000000000
|
|
010000000000000000000000001011000000000000
|
|
000000100001000111000000000000000000000000
|
|
000001000000100000100000000111000000000000
|
|
000000000001000000000111000000000000000000
|
|
000000000000000111000111100011000000000000
|
|
000000000000000001000000001001100000000000
|
|
000000000000000001100000001001100000000000
|
|
000000000000000000000010000000000000000000
|
|
000000000000000001000110001111000000000000
|
|
010000000000000000000000001000000000000000
|
|
110000000000000000000000000011000000000000
|
|
|
|
.logic_tile 4 9
|
|
000000000000001001100111000000000001001111000100000000
|
|
000000000010001001100010110000001101001111000001000000
|
|
001000000000000000000000000011001100010101010110000000
|
|
100000000000001101000000000000010000010101010000000000
|
|
110000000000010111100010000001011011111100110000000000
|
|
110000000100000000100010001001101010001111110000000000
|
|
000000000000000001100010100101001011111100110000000000
|
|
000000000000000001000100000001101110001111110000000000
|
|
000000000000000000000110000000000000000000000110000100
|
|
000000000000000001000010001011000000000010000000100010
|
|
000000000000000000000000000000011000001100110000000000
|
|
000000000000000000000010000000001011001100110000000000
|
|
000000000010000000000110100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
010000000000101000000000000001011010000111000000000000
|
|
100000000001000001000000001101011101001110000000000000
|
|
|
|
.logic_tile 5 9
|
|
000000000000000101000011110001000000001111000000000000
|
|
000000001010000111000010101111001000110000110000000000
|
|
001000000000000000000110100000011010001100110000000000
|
|
100000000000000000000011100000001011001100110000000001
|
|
000010000000001101000111000011101101110110100000000000
|
|
000000000000000001100110001011001100111000100000000000
|
|
000000000000100011100010110001101110000000110000000000
|
|
000000000001011101000010011001101010110000000000000000
|
|
000000000000000001100110000000000000011001100000000100
|
|
000000001010000001000010111101001100100110010000000000
|
|
000000000000101101000010001001111100000000110000000000
|
|
000000000001000001100010111011111101110000000000000000
|
|
000000000000000111000010100101111001000000000000000000
|
|
000000000000000000000100001001111110100000000000000000
|
|
010000000000000001100000011101101011101001010100000000
|
|
100000000000000000000010001111101010110110101010000100
|
|
|
|
.logic_tile 6 9
|
|
000000100000000001100000001000011001010000000000000000
|
|
000000000000000000000010110101001101100000000000000000
|
|
001000000001100111000110001000011010111001000100000000
|
|
100000000011110000100000001001011110110110000000000000
|
|
010001000000000000000000000000000000000000000100000000
|
|
010010000000000000000000000011000000000010000000000001
|
|
000000000000010001100111100000000000000000100100000000
|
|
000010100000100000000100000000001110000000000000000000
|
|
000000000000001000000110010001001100111101010000000000
|
|
000000001000000011000010000000010000111101010000000001
|
|
000000001000000000000000010011000000000000000000000000
|
|
000000000000000000000010101011101000010000100010000000
|
|
000000000000001000000000000001001100000001000000000100
|
|
000000000000000001000000000000011101000001000000000000
|
|
010000000000000000000000000000001100000001000000000000
|
|
100000000000000000000000001011011000000010000000000100
|
|
|
|
.logic_tile 7 9
|
|
000000000000000000000000010101100000000000001000000000
|
|
000000000000001101000010000000000000000000000000001000
|
|
001000000000001000000010100101100000000010101010000100
|
|
100000000000000101000100000000001100000001010010100111
|
|
110000000000000000000000010000001000001100110100000000
|
|
010000000000000000000010101001001110110011001000000000
|
|
000001000000101001100000001001001001111010100000000000
|
|
000000100000010001000010111101011001111001010000000000
|
|
000000000000100001100000000000011010000011110100000000
|
|
000000000001000000000010000000000000000011110000000000
|
|
000100000000000000000000001101101110001100110100000001
|
|
000000000000000000000000000101000000110011001000000000
|
|
000000000000000001100000001000001010101011110000000000
|
|
000000000000000000000000000001010000010111110000000000
|
|
110000000000000101000000001001011010000010100000000000
|
|
110000000000000000000000000101100000000000000000000000
|
|
|
|
.logic_tile 8 9
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011100000000000000000000000000000
|
|
001000000000000101000000000000000000000000000000000000
|
|
100000000000000000100000000000000000000000000000000000
|
|
010000000000100000000110101000011000101011000110000000
|
|
010000001110000000000000000101001011010111000000000000
|
|
000000000000000111000000000000000000000000000000000000
|
|
000000000000000000100000000000000000000000000000000000
|
|
000001000000001000000000000000000000000000000000000000
|
|
000010000000000101000000000000000000000000000000000000
|
|
000000000000000000000000011011101100101001010000000000
|
|
000000000000010000000010100001100000010111110010100100
|
|
000010100000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 9 9
|
|
000000000000000000000000000111100000000000000100000000
|
|
000000000000000000000000000000100000000001000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
000000000000000001000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000000000000000000000000000000000000000000100000001
|
|
000000000000000000000000000101000000000010000001000100
|
|
000010100000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000011010000100000100000000
|
|
000000000000000000000000000000010000000000000000000000
|
|
000000001010000000000000010000000000000000000000000000
|
|
000000000000000000000010000000000000000000000000000000
|
|
|
|
.ramb_tile 10 9
|
|
000000000000000000000000000000000000000000
|
|
000000010000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000
|
|
000000000001010000000000000000000000000000
|
|
000000000000100000000000000000000000000000
|
|
000000001110000000000000000000000000000000
|
|
000000001100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000
|
|
000001001000000000000000000000000000000000
|
|
|
|
.logic_tile 11 9
|
|
000000000000000101000000010001000000000000000100000000
|
|
000000000000000101000011110000000000000001000000000100
|
|
001000000000000000000010100101000000000000000100000000
|
|
100000000000000101000010100000100000000001000000000100
|
|
010010101010000000000010100000001010000100000110000000
|
|
010001000000000000000010100000010000000000000000000001
|
|
000000000000000101000000000000000001000000100110000000
|
|
000000000000000000000000000000001001000000000000000001
|
|
000000000001010000000000000000000000000000100110000001
|
|
000000000000100000000000000000001000000000000000000000
|
|
000000000000000000000000000000011000000100000110000000
|
|
000000000000000000000000000000000000000000000000000100
|
|
000000000001010000000000001000000000000000000100000000
|
|
000000000000000000000000000101000000000010000000000100
|
|
000000000000000000000000000000011000000100000100000001
|
|
000000000000000000000000000000010000000000000000000000
|
|
|
|
.logic_tile 12 9
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 9
|
|
000001110000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000100
|
|
000000000000000000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 10
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000001110000000000
|
|
000001111000110010
|
|
000000001000010000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000010000000
|
|
000100000001000000
|
|
000000000000110100
|
|
000000000000111000
|
|
000001111000000000
|
|
000000001000000000
|
|
000010000000101010
|
|
000010110011000100
|
|
|
|
.logic_tile 1 10
|
|
000000000000001000000000001000001000001100110000000000
|
|
000000000000001001000011111101000000110011000000010000
|
|
111000000000000101000000000000000000000000100110000001
|
|
000000000000000000000011110000001100000000000001000001
|
|
010000000001010000000000000101111001010001110000000000
|
|
010000000000000000000000000001101010001011100000000000
|
|
000000000000000001000111100111100000000000000110000101
|
|
000000000000000000100010100000000000000001000000000010
|
|
000000000000000101100000010000000000000000100111000000
|
|
000000000000000000000010100000001101000000000010000011
|
|
000000000000100000000110101000000000000000000110000000
|
|
000000000000000000000000001011000000000010000000000010
|
|
000010100000000000000110100000000000000000100110000000
|
|
000000000000000000000000000000001111000000000010000010
|
|
010000000000000101100000001001100001100000010000000001
|
|
100000000000000000000000000001101011000110000000000000
|
|
|
|
.logic_tile 2 10
|
|
000000000001010101100111000000000001000000001000000000
|
|
000000000000000000000000000000001010000000000000001000
|
|
000000000000000101100000000000011010001100111000000000
|
|
000000000000000000000000000000001000110011000000000100
|
|
000000000001000011100110100101101000001100111010000000
|
|
000000001010100000000000000000000000110011000000000100
|
|
000000000000001101000000010000001001001100111010000001
|
|
000000000000000101100010100000001011110011000000000001
|
|
000000000000010000000000000001001000001100111010000000
|
|
000001000000000000000000000000100000110011000000000100
|
|
000000000000000000000000000101001000001100111000000000
|
|
000000000000000000000000000000100000110011000000000000
|
|
000000000000000000000000000000001000001100111000000000
|
|
000000000000000000000000000000001010110011000000100000
|
|
000000000000000000000000000000001001001100111000000000
|
|
000000000000000000000000000000001000110011000000000000
|
|
|
|
.ramt_tile 3 10
|
|
000010010000011111100000001000000000000000
|
|
000001000000101111100000001001001000000000
|
|
001000010000000111100000010101000001000000
|
|
100000000000001111100011111101001000000001
|
|
110000100000000011100011110000000000000000
|
|
110000001110000000000011111011000000000000
|
|
000001000000001000000010001000000000000000
|
|
000010000000001001000100001111000000000000
|
|
000010100001010000000000010000000000000000
|
|
000001000000100111000011000011000000000000
|
|
000010101000000000000000000101000000000000
|
|
000001001100000000000000000001100000000001
|
|
000000000000000000000010001000000000000000
|
|
000000001110000000000000001101000000000000
|
|
010000000000000000000000011000000000000000
|
|
010000000000000000000011010101000000000000
|
|
|
|
.logic_tile 4 10
|
|
000000000000001101000000001000000000101111010000000101
|
|
000000001110001111100000000101001000011111100000000010
|
|
001000000000100000000000001111101110001100000000000000
|
|
100000000001010111000011111101111110110000000000000000
|
|
000000000001010000000000000011100000000000000100000000
|
|
000000000000101101000000000000100000000001000000000000
|
|
000000000001000011100000000000000000000000000100000000
|
|
000000000000000000100011100101000000000010000000000000
|
|
000000000000000000000000001000000000000000000100000000
|
|
000010001110000000000000000001000000000010000000000010
|
|
000000000000000000000011100000011000000100000100000001
|
|
000000000000000000000000000000010000000000000000000000
|
|
000000000000000000000110100001000000000000000100000000
|
|
000000000000000001000000000000000000000001000000000000
|
|
000000000000000111000111000111100000000000000100000001
|
|
000000000000000000000100000000000000000001000000000010
|
|
|
|
.logic_tile 5 10
|
|
000000000000001101000000010101000000011001100000000000
|
|
000000000000001011000010100000101000011001100000000000
|
|
111000000000100101100000000011101011100100000000000000
|
|
000000000001000101000011100000101011100100000000000000
|
|
110000000000000101100110110001011001101110000000000000
|
|
110000000000000000000011011001001000011110100000000000
|
|
000000000000000011100000010111101100101010100000000000
|
|
000000000000000000100010100000100000101010100000000000
|
|
000000000000001000000000000011101110100100000000000000
|
|
000000000000000001000000000000111011100100000000000000
|
|
000001000000001000000110010000011101001100000100000000
|
|
000010100000101011000010000000001110001100000100000000
|
|
000000000000000000000010110000001011001100110000000000
|
|
000000000000000000000010000000011001001100110000000000
|
|
010000000000000000000011011000011010010101010000000000
|
|
100001000000100001000110111111000000101010100000000000
|
|
|
|
.logic_tile 6 10
|
|
000000000000000000000000000101100000000000000100000000
|
|
000000000000000000000010100000100000000001000010000000
|
|
001000000000001001100010101011001111101000000000000000
|
|
100000000000001011000010101111011001010000100010000000
|
|
010000000000000000000010001111101011011111100000000000
|
|
110000000000001101000000001001101111010111100000000000
|
|
000000000100100101000010101001000001001111000000000000
|
|
000000000000000101000010100011101010001001000000000000
|
|
000000000000000000000000000001111011000001000000000001
|
|
000000000000000111000000000000011111000001000000000000
|
|
000001000010100001000000000101100001010000100000000000
|
|
000010100000000000000000000000101111010000100000000000
|
|
000000000000000000000110000101111000011100000000000000
|
|
000000000000000000000000001001001100001100000001000000
|
|
010010100000000000000110001011011010000001010000000000
|
|
010000000000010000000010010101000000000000000000000000
|
|
|
|
.logic_tile 7 10
|
|
000000001110000101000000001101101101000010100000000000
|
|
000000000000000000100010111011001010000110000000000000
|
|
001000000000000000000010100111100000000000000100000000
|
|
100010000000001101000000000000100000000001000000000000
|
|
011010100000100000000110000001011011110001010000000000
|
|
110001000000000000000000000000001011110001010000000000
|
|
000000000110100101000010101000011111110000010000000000
|
|
000000000001000101100110111001001101110000100000000000
|
|
000000000000000001100000010000000000000000100100000000
|
|
000000000000000000000010000000001110000000000000000000
|
|
000000000100000001100010001001000001100000010000000000
|
|
000000000000000001000010000101101011111001110000000000
|
|
000000000000000111000000000000011101111001000000000000
|
|
000000000000000000000000001011001101110110000000000000
|
|
110000001000001101100111001001111101010000100000000000
|
|
010000000000000001000100000111011010100000100000000000
|
|
|
|
.logic_tile 8 10
|
|
000000000000000000000000000000000001001111000000000010
|
|
000000000000000000000000000000001000001111000010000000
|
|
001000000001011000000000000000000000000000000000000000
|
|
100000000000101001000000000000000000000000000000000000
|
|
110000000001000000000000000000000000000000000000000000
|
|
010000000000000000000011100000000000000000000000000000
|
|
000000000001010011100000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
000000000000000000000000001000000000000000000100000000
|
|
000000000000000000000011111011000000000010000010000011
|
|
000000000000000000000000010000000000111001110000000000
|
|
000000000000000000000010011101001110110110110000000000
|
|
000000000000000000000000000111001010000010100000000000
|
|
000000001010001111000000000000010000000010100000100000
|
|
010000000000010000000000000000000000000000000000000000
|
|
110000000000100000000000000000000000000000000000000000
|
|
|
|
.logic_tile 9 10
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000100000000000000000000000011000000100000100100001
|
|
100001000000001111000000000000000000000000000101100110
|
|
110000000000000000000000000101111101100000000010000000
|
|
010000000000000000000000000000001111100000000000100000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000001100000101000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000011000000000000000000000000000000
|
|
000000000000000111000000000000000000000000000000000000
|
|
000000000000000000100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000010000000000000000000000000000000
|
|
100000000000000000000100000000000000000000000000000000
|
|
|
|
.ramt_tile 10 10
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000001100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000001100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 10
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
010000000000000000000010000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
000000000000000101000000000000000000000000000000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000011010000100000110000010
|
|
000000000000000000000000000000010000000000000000000111
|
|
000000000000000000000000000101100000000000000100000000
|
|
000000000000000000000000000000000000000001000001100000
|
|
|
|
.logic_tile 12 10
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000010100000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 10
|
|
000000000000000000
|
|
000100000000100000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
001000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 0 11
|
|
000000000000000000
|
|
000100000000001000
|
|
000000000000000000
|
|
100000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
001100000000000000
|
|
100000000000000000
|
|
001000000000101000
|
|
000100000000000100
|
|
000010000000000100
|
|
000000110000001100
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 11
|
|
000000000000000111100000001000001111100100000000000000
|
|
000000000000001101000010101001001011011000000000000000
|
|
111000100000000101000010110000011011001100110000000001
|
|
000000000000000000100110010000011011001100110000000000
|
|
000000000000000011100110010101000001011001100000000000
|
|
000000000000000101000010010000101111011001100010000001
|
|
000000000000000111000110011101101001000000010000000000
|
|
000000000000100001100110011011011010000000000000000000
|
|
000000000000000000000000001101011001001100110000000000
|
|
000000000000000000000000001011011111000100100010000000
|
|
000000000000000111000110000001000001010000100000000000
|
|
000000000000000000100010000000001100010000100000000100
|
|
000000000000000000000010100001011000101001010100000000
|
|
000000000000000001000010001101001111110110100011000000
|
|
010000000000000000000010000101011100000010100000000000
|
|
100000000000000000000000001111011010100000010000000000
|
|
|
|
.logic_tile 2 11
|
|
000000000000000000000010100111101000001100111000000001
|
|
000000000000000000000011000000100000110011000000010000
|
|
111000000000000001100010100000001001001100110000000001
|
|
000000000000000101000010100000001010110011000000000000
|
|
010000100100010000000111101000000001011001100000000000
|
|
010001000000000000000110100101001001100110010000000001
|
|
000000000000001101000000001000001100010101010000000001
|
|
000000000000001011000000001001000000101010100010000000
|
|
000000000000001000000000001000000001011001100010000000
|
|
000000000000000001000000000001001010100110010010000000
|
|
000000000000000000000000000000000001001111000100000000
|
|
000000000000000000000000000000001000001111000010000010
|
|
000000000001010000000000000000001001001100110000000000
|
|
000000100000000000000000000000011000001100110010000010
|
|
010000000000000000000000000000001010000001100000000000
|
|
100000000000000000000010001101011001000010010000000000
|
|
|
|
.ramb_tile 3 11
|
|
010000000000000000000000000000000000000000
|
|
001000010000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000010100000000000000000000000000000000000
|
|
001001000001000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000001100000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000010100000000000000000000000000000000000
|
|
001001000000000000000000000000000000000000
|
|
|
|
.logic_tile 4 11
|
|
000000000001000000000000000000000001000000100100000000
|
|
000000000000000000000000000000001010000000000000000000
|
|
001000000000100001100111100000011010000100000100000000
|
|
100000001000010000000100000000010000000000000000000000
|
|
000000000000001111000000000001100000010000100010000000
|
|
000000000000001111000000001011101100001001000000000000
|
|
000000000001000101000010100000000000110110110001000001
|
|
000000000000000000100100000101001111111001110000000111
|
|
000000000000100000000000001011101111001000000000000000
|
|
000000000000000111000010101011011110100000000001000000
|
|
000000000000000111100000000000011100000000110000000000
|
|
000000000000001001100010010000001110000000110000000000
|
|
000000100000001000000000010111111001000011000000000000
|
|
000001000000000111000010100101101111000000000001000000
|
|
000000000000001001000110000011000001001001000000000000
|
|
000000000000000111100011110000101110001001000000000000
|
|
|
|
.logic_tile 5 11
|
|
000000000000000000000000010000001010000100000100000000
|
|
000000000000000101000011100000000000000000000000000000
|
|
001000000000000101000011100111000000111111110000000000
|
|
100000000000000000000100000011100000010110100000000000
|
|
010000000000000000000000000001111001110001010010000100
|
|
010000000000000111000000000000011010110001010000100010
|
|
000000000000000111100010100000000001000000100100000000
|
|
000000001000000000100010100000001011000000000000000001
|
|
000000000000000111100010000000001100000100000100000000
|
|
000000000000000000100000000000010000000000000000000000
|
|
000001000000000000000000000001000000000000000100000100
|
|
000010100000000000000000000000000000000001000000000000
|
|
000000001110000000000011100000000001000000100100000010
|
|
000000000000000000000000000000001011000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 6 11
|
|
000000000000000101100000010101011010000010100000100000
|
|
000000001000000000000011010000010000000010100000000000
|
|
001000000000001000000000000000000000000000000000000000
|
|
100000000000001111000000000000000000000000000000000000
|
|
010000000000001001000000000000000000001001000100000001
|
|
010000000000001111000000000101001100000110000010000001
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011000001000000000010000000000000
|
|
000000000000000000000000000000000000010000100100000000
|
|
000000000010000001000000000101001100100000010010000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000010001000000000000000000000000000000000000000000000
|
|
000001000010000000000000000000000000000000000000000000
|
|
010000000000000000000000000011001010101000000100000000
|
|
010000000000000000000000000000000000101000000000000000
|
|
|
|
.logic_tile 7 11
|
|
000000100000000111000000011001011111010000000011000000
|
|
000000000010000000000010100101001000000000000001000000
|
|
001000000000001000000110100000000000000000000100000000
|
|
100000000000000111000000001111000000000010000000000000
|
|
010000000000000000000010101000000000000000000100000000
|
|
110000000000000000000000001111000000000010000000000000
|
|
000000000000111011100000001001001101000000000000000000
|
|
000010001111110101100000000101101001000010000000000000
|
|
000000000001001001000000000111100000000000000100000000
|
|
000000000000000101100000000000100000000001000000000000
|
|
000010100000001000000000010000000000000000000100000000
|
|
000001000000000111000011000011000000000010000000000000
|
|
000000000000101000000000010111000000000000000100000000
|
|
000000000000000011000011010000000000000001000000000000
|
|
110000000000000000000111010000011100000100000100000000
|
|
010000000000000011000111010000010000000000000000000000
|
|
|
|
.logic_tile 8 11
|
|
000000000000000000000110000000001000000100000110000000
|
|
000000000000000000000000000000010000000000000000000000
|
|
001000000100000111100000010000000000000000000000000000
|
|
100000000000000000100011110000000000000000000000000000
|
|
010000000000000111100011000000000000000000000000000000
|
|
110000000000000000100000000000000000000000000000000000
|
|
000010100000010000000000011000000001000110000000000000
|
|
000001000000100101000011100001001011001001000001000000
|
|
000000000000001000000000000000000000000000000000000000
|
|
000000000000000101000000000000000000000000000000000000
|
|
000000000000000000000000001111101100000000010010000100
|
|
000000001110000000000000001111001110000000000000000000
|
|
000000000000001000000000000000011011110000000000000000
|
|
000000000000000111000000000000001001110000000000000001
|
|
000010100000100101100000010101000000000000000100000000
|
|
000001000000000000000010000000000000000001000000000011
|
|
|
|
.logic_tile 9 11
|
|
000000000000000000000110001000000000000000000110000000
|
|
000000000000000000000010010101000000000010000000000100
|
|
001000000001011111100000000000000000000000000000000000
|
|
100000001100100001000000000000000000000000000000000000
|
|
010001000000000000000111100000000000000000000000000000
|
|
110010100000000000000000000000000000000000000000000000
|
|
000000000000000001000000000011100000000000000100000000
|
|
000000001110010000100000000000100000000001000000000000
|
|
000001000000000000000000000001100000000000000100000000
|
|
000010000000000000000000000000000000000001000000000000
|
|
000000000100000000000000010111111000000010100000000100
|
|
000000000000000000000011001001100000000000000000000000
|
|
000000000000100000000000001000001001000001000000000100
|
|
000000000000010000000000001111011000000010000000000000
|
|
000001000001010000000110000000001000000100000100000000
|
|
000010000000100000000000000000010000000000000000000000
|
|
|
|
.ramb_tile 10 11
|
|
010000000000000000000000000000000000000000
|
|
001000010000000000000000000000000000000000
|
|
000000000100000000000000000000000000000000
|
|
000000001100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000001110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000
|
|
001000001100100000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000100000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 11
|
|
000000000000001000000000000011100000000000000100000000
|
|
000000000000001011000000000000000000000001000011100100
|
|
001010000000010000000000001000000000000000000110000000
|
|
100001100000100000000000001011000000000010000011000100
|
|
110000000000000001000000010000000000000000000100000000
|
|
110000000000000000000011010001000000000010000001000001
|
|
000010000100000000000010000101000000000000000100000000
|
|
000010000000000000000000000000000000000001000001000100
|
|
000000000000000000000000000000001010000100000100000100
|
|
000000000000000000000000000000010000000000000000000000
|
|
000000000010100001000010000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000011100000000001000000100100000000
|
|
000000000000000000000100000000001011000000000011000001
|
|
000000001010000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 12 11
|
|
000000000000001101100000000000000000000000000000000000
|
|
000000000000000101000000000000000000000000000000000000
|
|
001010000000000000000000000001000000000000000100000000
|
|
100010000000000000000000000000000000000001000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000010000000000000000100100000000
|
|
000000000000000000000010100000001000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000001000000000000000000100000000
|
|
000000000000000000000000001101000000000010000000100000
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 11
|
|
000000000000000010
|
|
000100000000000000
|
|
000000011000000000
|
|
100000001000000001
|
|
000000000000100010
|
|
000000000000010000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000011000000000
|
|
001000001000000000
|
|
000000000000000010
|
|
000000000000110000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000010
|
|
000000000000000000
|
|
|
|
.io_tile 0 12
|
|
000000000100000000
|
|
000100000100000000
|
|
100000000100000000
|
|
000000000100000001
|
|
000000000100000000
|
|
000000000100000000
|
|
001100000100000000
|
|
000000000100000000
|
|
001000000000000000
|
|
000100000000000000
|
|
000000000000001100
|
|
000000000000001100
|
|
000001010000000000
|
|
000000001000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 12
|
|
010000000000000111100000001111101111000011110000000000
|
|
001000000000000000000000000111001101000010110000000000
|
|
111000000000000000000000000011000000000000000100000000
|
|
000000000000000000000010100000000000000001000000000010
|
|
000000000000000001100000001111011111000100000000000000
|
|
001000000000000000100000000111001101000000000000000001
|
|
000000000000000000000000010000000000000000000000000000
|
|
001000000000000000000010110000000000000000000000000000
|
|
000000000000000001100010001011001100000000000000000000
|
|
001000000000000001000000001111101010111111000000000000
|
|
000000000000001000000000010011100001100000010000000000
|
|
001000000000000001000011001111001111000000000000000000
|
|
000000000000001000000000001001001100000000000000000000
|
|
001000000000000011000010101001001010010010100000000000
|
|
000000000000001001100110011000000000000000000100000000
|
|
001000000000001001100010001101000000000010000000000000
|
|
|
|
.logic_tile 2 12
|
|
010001000000000101000000000011100000000000000000000000
|
|
001010100010000101000010101001000000111111110000000000
|
|
111000000000000111000010111001001100010010100000000000
|
|
000000000000000000100010001001011000001001010000000000
|
|
000000000000000111100000001000000000000000000100100000
|
|
001000000000100000000000001001000000000010000000000000
|
|
000000000000000000000111001111101100000000010000000000
|
|
001000000000000101000100000111101100000000000000000000
|
|
000000000000001001100000011001111010101110000000000000
|
|
001000000000000001000010001101001110101101010000000000
|
|
000000000000000001100000000000001010000100000100000000
|
|
001000000000000001000000000000000000000000000000000100
|
|
000000000000001001100000000000000001000000100100000000
|
|
001000000000001001100000000000001100000000000000000000
|
|
000000000000001000000110000001001100001111000000000000
|
|
001000000000000001000000000001011110001100000000000000
|
|
|
|
.ramt_tile 3 12
|
|
000001000000000000000000000000000000000000
|
|
000000100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000001110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000
|
|
000000100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000001110000000000000000000000000000000
|
|
000000000000100000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 4 12
|
|
010000000000000111100111100000001000000100000110100100
|
|
001000000000001001100100000000010000000000000001100110
|
|
111000000000000000000000000000001100000100000100000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000010100000001001001100110100000000
|
|
111000000100000000000000000000011011001100110000000000
|
|
000000000000000111100111100101100000000000000110100101
|
|
001000000000000000000100000000100000000001000000100000
|
|
000000000000000001000000001000000000000000000100000000
|
|
001000000000000111100000000101000000000010000000000000
|
|
000000000000000000000000000000000000000000000100000000
|
|
001000000000000000000000000001000000000010000000000000
|
|
000000000000000000000000000111000000000000000100000000
|
|
001000000000001111000000000000000000000001000000000000
|
|
010000000000000000000000000001000000011001100100000000
|
|
101000000000000000000000000000001100011001100000000000
|
|
|
|
.logic_tile 5 12
|
|
010000000000000000000000000000000000000000000000000000
|
|
001000000000000101000000000000000000000000000000000000
|
|
111000000000000000000000000001000000000000000100000000
|
|
000000000000000101000000000000000000000001000000000000
|
|
000000000000000001100000000000000001000000100100000001
|
|
001000001010000000000000000000001110000000000000000000
|
|
000000000000000000000000000011100000000000000101000000
|
|
001000000000000000000000000000000000000001000000000000
|
|
000000000000000000000000000000000000000000100100000000
|
|
001000000000000000000000000000001010000000000001000100
|
|
000000000000000000000000000000011000000100000100000000
|
|
001000000000000001000000000000000000000000000000000000
|
|
000000000000000000000000000111100000000000000100000000
|
|
001000000000000000000000000000000000000001000001000000
|
|
000001000000001001100000000000000000000000000000000000
|
|
001000000000001101000000000000000000000000000000000000
|
|
|
|
.logic_tile 6 12
|
|
010000000000000111100000000111001101000110100000000000
|
|
001000000000000101000011101101111110001111110000000000
|
|
111000000001010000000000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
010000000000000011100110000111100000000000000000000000
|
|
011000000000000000100100000000000000000001000000000000
|
|
000000000000000000000111001011011110101000000100000000
|
|
001000001010000000000110011101110000111101010100100000
|
|
000000000000000101100110110111100000100000010000000000
|
|
001000000000000000000010100101101000000000000010000000
|
|
000010100000000000000000001000000000001001000000000000
|
|
001000000000000000000000001111001100000110000000100000
|
|
000000000000000000000000011001001100010111100000000000
|
|
001000000000000000000010111101011011000111010000000000
|
|
010000000000001001000011000000000000000000000000000000
|
|
101000000000000001000010000000000000000000000000000000
|
|
|
|
.logic_tile 7 12
|
|
010000000000000000000000001111001011000000100000000000
|
|
001000000000000111000000000011101111000000000000000000
|
|
001010100000000111000000000011111110111001010000000000
|
|
100001000000000000100000000101011111111100110000000000
|
|
110000001100011111100010100000011000000100000100000000
|
|
011000000000101001000000000000000000000000000100000000
|
|
000010100000000000000000000111111100000000000000000000
|
|
001001000000000000000010001111101010000010000000000000
|
|
000000001110101000000110000111001100000110100000000000
|
|
001000000001000001000010001101011000001111110000000000
|
|
000000000000001000000000000000001101000011100000000000
|
|
001000000000001001000000001011001011000011010000000000
|
|
000000000000011000000000011111001011000010100000000000
|
|
001000000000101101000010010011101111000011000000000000
|
|
010000000000000000000110000000001010000100000100000000
|
|
101000000000000000000100000000000000000000000100100000
|
|
|
|
.logic_tile 8 12
|
|
010000000000000000000000010000000000000000000100000000
|
|
001000000000000101000011110101000000000010000000000100
|
|
001000000000000111100010110000011011101111110000100000
|
|
100000000000000000100010010101001001011111110000000010
|
|
010000000000001111100000000000000000000000000000000000
|
|
011000000000001001100000000000000000000000000000000000
|
|
000000000000000001100010100000000000000000000000000000
|
|
001000000000000000100010100000000000000000000000000000
|
|
000000100000000000000000000000001110001000000000000000
|
|
001001000000000000000000000001001110000100000000000000
|
|
000000000000000000000000010001111011100000000000000000
|
|
001000000000000011000010000101111110000000000000100000
|
|
000000000000001001000000000101000001010000100000000000
|
|
001000000000000001000000000000001001010000100010000000
|
|
110000000000001000000000001101111101100000010000000000
|
|
011000000000000001000000001101011000010000000000100001
|
|
|
|
.logic_tile 9 12
|
|
010000000000000111000111111001001010000000000000000000
|
|
001000000000000101000111100111001111010000000000000010
|
|
001000000000001011100110100001111100000001010000000000
|
|
100000000000000001100000000000010000000001010010000000
|
|
010000000000001101100110100011111010000000000000000000
|
|
011000000000000101000110111101110000010100000000000000
|
|
000000000000000101000000010011111110000000000000000100
|
|
001000000000000000000010100001101010100000000000000000
|
|
000000000000100000000000001011111010000010100000000000
|
|
001000000001010000000000000101110000000011110000000000
|
|
000000000001011000000110001001000001100000010000000000
|
|
001000000000101011000110111001001101010110100010000000
|
|
000000000000000000000111000001101010001011110100000000
|
|
001000000000000000000100000000011010001011110001000000
|
|
010000000000000001000110000011111111100000010000000000
|
|
011000000000000000100100001001011011010000010000000000
|
|
|
|
.ramt_tile 10 12
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000001110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 12
|
|
010000001000001111000000010000000000000000000000000000
|
|
001000000000001111100011110000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
011000000000000000000000000000000000000000000000000000
|
|
000000000000101000000000000001001100000001010000000000
|
|
001000000000000011000000000001000000000000000000000000
|
|
000000000000001000000000000000000000000000000000000000
|
|
001000000000000111000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001010000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000001000000000000000000110000010
|
|
101010000000000000000000000101000000000010000100100000
|
|
|
|
.logic_tile 12 12
|
|
010000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
010000000000000000000110100000000000000000000000000000
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000111000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
001010100000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000011010000100000100000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 12
|
|
000000000100000010
|
|
000000000100000000
|
|
000000000100000001
|
|
000000000100000001
|
|
000000000100110010
|
|
000000000100110000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000010001
|
|
000000011000000000
|
|
000000001000000000
|
|
|
|
.io_tile 0 13
|
|
000000000100001000
|
|
000100000100000000
|
|
010000000100000000
|
|
000011110100000000
|
|
000000000100000000
|
|
100000000100000000
|
|
001100000100000000
|
|
000000000100000000
|
|
001000000000101000
|
|
000100000000000100
|
|
000000000000000100
|
|
000000000000001000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 13
|
|
010000000000000000000000001001101111000000000001000000
|
|
001000000000001101000000000101111000000010000000000000
|
|
111000000000001000000010001011000000111001110100000101
|
|
000000000000000101000100001111101110100000010000000000
|
|
010000000000000000000000000000011011001100000000100001
|
|
101000000000000101000000000000001011001100000000100000
|
|
000000000000001101100110000101111000010100000000000000
|
|
001000000000000111000000000000000000010100000000000100
|
|
000000000000000000000000001000001010000011010000000000
|
|
001000000000000000000010001011001000000011100000000000
|
|
000000000000000000000000000000011110000000110000000000
|
|
001000001100000000000010100000001110000000110000000000
|
|
000000000000001000000000010000000001000000100100000001
|
|
001000000000000011000011000000001110000000000000100000
|
|
000000000000000011100000010001111011010010100000000000
|
|
001000000000000000000010101111001001101001010000000000
|
|
|
|
.logic_tile 2 13
|
|
010000000001000000000111110101011000111100000000000000
|
|
001000000000000000000010100101100000000000000000000000
|
|
111000000000001111000000000000000000000000000000000000
|
|
000000000000010101100010110000000000000000000000000000
|
|
010000000000001011100010001101001000000010000000000000
|
|
011000000000000001000110000101011011000100000000000000
|
|
000000000000000011100000000001100000000000000000000000
|
|
001000000000001111100000000000000000000001000000000000
|
|
000000000000000000000010101111011011110110100100000000
|
|
001000000000000000000100001111101100010110000000100000
|
|
000000000000001000000000000000000000000000000000000000
|
|
001000000000001011000000000000000000000000000000000000
|
|
000000000000000000000000000111001101100000000000000000
|
|
001000000000001101000011110000011001100000000010000000
|
|
000000000000000000000111000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
|
|
.ramb_tile 3 13
|
|
010000000000000000000000000000000000000000
|
|
001000010000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
|
|
.logic_tile 4 13
|
|
010000000000000000000000000000000000000000000000000000
|
|
001000000000000000000010100000000000000000000000000000
|
|
001000000000000000000000000000000000000000100100100000
|
|
100000000000000101000010100000001111000000000000000010
|
|
000000000000000101000000000000000000000000100100000000
|
|
001000001010000000000000000000001001000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000001101000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000100000000
|
|
001000000000000000000000000101000000000010000000100000
|
|
000000000000000000000000000000011000000100000100000000
|
|
001000000000000000000000000000010000000000000000100000
|
|
000000000000000000000000011000000000000000000100000000
|
|
001000000000000000000010000001000000000010000000100000
|
|
000000000000000000000000001000000000000000000100000000
|
|
001000000000000000000000000101000000000010000000000100
|
|
|
|
.logic_tile 5 13
|
|
010000000000000000000110000000000000000000000000000000
|
|
001000001100000000000000000000000000000000000000000000
|
|
111000000000000000000000001000000000000000000100000000
|
|
000000000000000000000000000111000000000010000000000000
|
|
000000000000000000000000000000011100000100000100000000
|
|
001000001010000000000011100000010000000000000000000000
|
|
000000000000000000000000000000000000000000100100000000
|
|
001000000000000000000000000000001011000000000000000000
|
|
000000000000000000000000000000001110000100000100000000
|
|
001000000000000000000000000000010000000000000001100100
|
|
000000001010000000000010000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000001000001100000010000000000000000000100000000
|
|
001000000000100000000010000111000000000010000001100010
|
|
000000000000000000000000000000000000000000000100000000
|
|
001000000000000001000000001001000000000010000001100000
|
|
|
|
.logic_tile 6 13
|
|
010000000000000101000110000001100001011111100100000000
|
|
001000000000000101100110110001001001101001010000000000
|
|
101010000000001101000011111101011000100001010100000000
|
|
101001000000001001100110010101111001010001110000000000
|
|
110000000000001000000010101001000001011111100100000000
|
|
111000000000001001000100000101001001101001010000000000
|
|
000000000010001001100010100001101101111000100100000000
|
|
001000000000000111100110101001101110010100100000000000
|
|
000000000000001000000000001111100001010110100100000000
|
|
001000001100001011000000001001101100110110110000000000
|
|
000000000000000000000000000001111011111111010100000000
|
|
001000000000000001000000000101111011011111100000000000
|
|
000000000000000111000011101001101000111000100100000000
|
|
001000000000001001000000001001111001101000010000000000
|
|
000000000000000000000000010001111000110011110100000000
|
|
001000000000000001000010100111101010110111110000000000
|
|
|
|
.logic_tile 7 13
|
|
010100000010000001000010101000000000000000000100100000
|
|
001000000000000101100000001001000000000010000000000000
|
|
001000000000001000000000010101000000000000000100100000
|
|
100000000000000101000010100000000000000001000000000000
|
|
110000000001001101100110110101000000000000000100100000
|
|
011000000000000101000010100000100000000001000000000010
|
|
000000000000000000000110100000000000000000100100100000
|
|
001000000000000000000000000000001010000000000000000000
|
|
000000000000000000000000010000000000000000000100000000
|
|
001000000000100000000010011101000000000010000000000010
|
|
000000000000000000000000000101100000000000000100000000
|
|
001000000000000000000000000000100000000001000000100000
|
|
000000000001000000000000000001001000010110100000000000
|
|
001000000000100000000000000001010000000001010000000000
|
|
000000000000000000000000000000011000000100000100000000
|
|
001000000000000000000000000000000000000000000000100000
|
|
|
|
.logic_tile 8 13
|
|
010000000000000111000010100101100001100000010000000000
|
|
001000000000000000100100000000001000100000010010000001
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000101000010100000000000000000000000000000
|
|
010000000000000101000111001111101100111110100100000000
|
|
111000000000000000100000001101110000101001010001000000
|
|
000000000000001000000110000001111110101000000010000000
|
|
001000000000000001000000000000110000101000000000000001
|
|
000000000000000000000010001111100000000000000010000000
|
|
001000000000000001000000001111001100100000010000000000
|
|
000010100000000000000000011011011110010001110000000000
|
|
001001000000000000000010000111011111010000110000000000
|
|
000000000000000000000000000111000001001001000000000000
|
|
001000000000000000000010000011101111000000000000000000
|
|
000000000000000000000010010101011100101001000000000000
|
|
001000000000000001000010000001011001101001010000000000
|
|
|
|
.logic_tile 9 13
|
|
010000000000001101000110111101001110111111110100000000
|
|
001001000000000111100011111101011110011110100001000000
|
|
001000000000001101000011100001001110001110000000000000
|
|
100000000000000011100000000000001011001110000000000000
|
|
110000000000000001100011101101111100010110100000000000
|
|
011000000000001101000110101111000000000001010000000000
|
|
000000000000000111000010110001101110000000000000000000
|
|
001000000000001101100011010111001100000000100001000000
|
|
000000000000000001000111011001001000111111100110000000
|
|
001000000000000000100111010101011010011111101000000000
|
|
000000000000000101000000011001001111110111110100000000
|
|
001000000000000001100010010001101111111001110001000000
|
|
000000000001001001100000011001111011101000000000000000
|
|
001000000000101001100011101011111100010000100000000000
|
|
110000000000000111000110011101011100111000000000000000
|
|
111000000001010000000010001001111101100000000000000000
|
|
|
|
.ramb_tile 10 13
|
|
010000000000000000000000000000000000000000
|
|
001000010000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000
|
|
001010000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 13
|
|
010000000000001000000000010000000000000000100100000000
|
|
001000000000001011000011010000001100000000000101000000
|
|
001000000000000000000000010000001000000100000100000000
|
|
100000000000001111000011010000010000000000000110000000
|
|
010000000110001001100111100000000001000000100100000000
|
|
111000000000000001000100000000001001000000000101000000
|
|
000000000000000001100000001000001010000001010000000000
|
|
001000000000000000000000001111000000000010100000000000
|
|
000000000000000000000000000000000000000000100110000000
|
|
001000000000000001000000000000001000000000000100000000
|
|
000000000000000000000000000111100000000000000100000000
|
|
001000000000000000000000000000000000000001000101000000
|
|
000000000000000000000000011111001011101001000000000000
|
|
001000000000000000000010000001101010010110100000000000
|
|
010000001010000001000000010000001010000011000000000000
|
|
101000000000100000000010000000001010000011000000000000
|
|
|
|
.logic_tile 12 13
|
|
010000000000000000000000010000000000000000000000000000
|
|
001000000000000000000010100000000000000000000000000000
|
|
001000000000000101100110100000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
010000000000000000000110100000000000000000000000000000
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000101100000001101101001101001110100000000
|
|
001000000000000000000000000111011001100110110001000000
|
|
000000000000000000000000000001111000001000010100000000
|
|
001000000000001101000000000011101001011110110001000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000001101000000000000000000000000000000000000
|
|
|
|
.io_tile 13 13
|
|
000000000100000000
|
|
000100000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000000000100000000
|
|
000100011100000000
|
|
000000000100000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000010010
|
|
000000000000110000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000010
|
|
000000000000000000
|
|
|
|
.io_tile 0 14
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 14
|
|
000000000000001000000110000000001110111111000100100101
|
|
000000000000000001000000000000011000111111000100000010
|
|
111000000000000000000000000011100000101001010000000001
|
|
000000000000000000000000000101100000111111110000000000
|
|
010000000000000000000110000111001001000000010000000000
|
|
110000000000000101000100000000011010000000010000000000
|
|
000000000000000101000000000000000000000000100100100000
|
|
000000000000000000000000000000001111000000000110000000
|
|
000000000000000000000000001111101000010011110001000000
|
|
000000000000000000000000000101111000010011100000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000000000001000000000010000000000000000000000000000
|
|
000000000000000001000010000000000000000000000000000000
|
|
010000000000000000000000010000000000000000000000000000
|
|
100000000000000000000010100000000000000000000000000000
|
|
|
|
.logic_tile 2 14
|
|
000000000000000001100110100101100000000000001000000000
|
|
000000000000000000000000000000000000000000000000001000
|
|
111000000000001000000000000111111001001000011100000000
|
|
000000000000000001000000000101001011010010000100000000
|
|
010000000000001001100110100101001001100001000100000000
|
|
110000000000000101000100001011001011001000010100000000
|
|
000000000000001000000010000101001101110000110000000000
|
|
000000000000000001000010001001011101010000110000000000
|
|
000000000000000000000000010000011100000011110000000000
|
|
000000000000000000000010000000010000000011110000000000
|
|
000000000000000000000110000000000000010110100000000000
|
|
000000000000000000000000000001000000101001010000000000
|
|
000000000000000000000110000001011100100000000000000000
|
|
000000000000000000000000000000011101100000000000000000
|
|
010000000000000001100000000111000000010000100100000000
|
|
100000000000000000000000000000101010010000100100000000
|
|
|
|
.ramt_tile 3 14
|
|
000001000000000000000000000000000000000000
|
|
000000100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 4 14
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
111000000000000000000000000000001110000100000100000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000111000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
000100000000000111100000000000000000000000000000000000
|
|
000100000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000001000000100100000000
|
|
000000000000000000000000000000001010000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000001000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 5 14
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000010000000000000000000000000000000
|
|
001000000000000001100000000000000000000000000000000000
|
|
100000000000000000100000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000010000000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000001000000100110000000
|
|
000000000000000000000000000000001000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 6 14
|
|
000000000000000000000000001000001100101000000100000000
|
|
000000000000000000000000000111010000010100000100000010
|
|
001000000000000000000000000011111110101000000100000000
|
|
100000000000000000000000000000000000101000000100000000
|
|
010000000000000000000110100000001101110000000100000000
|
|
110000000000000000000100000000001110110000000100000000
|
|
000000000000000000000000000111111110101000000100000000
|
|
000000000000000000000000000000010000101000000100000000
|
|
000000000000000101100110100000001111110000000100000000
|
|
000000000000000000000000000000001110110000000100000010
|
|
000000000000001101100000001000011110101000000100000000
|
|
000000000000000101000000000011000000010100000100000000
|
|
000000000000001000000000011000011110111110100100000001
|
|
000000000000000101000010100111010000111101010100000000
|
|
010000000000000011100110100000011110110000000100000000
|
|
100000000000000000100010100000001111110000000100000000
|
|
|
|
.logic_tile 7 14
|
|
000001000000010111000011100001100000000000000100000000
|
|
000000100000100111000000000000000000000001000100000000
|
|
001000000000000111000000000011100000000000000100000000
|
|
100000000000000000100000000000100000000001000100000000
|
|
110000000000010000000000000001000000000000000100000000
|
|
110000000000000000000010000000100000000001000100000000
|
|
000000000000000001100000000000000000000000100100100000
|
|
000000000000000000100000000000001111000000000100000000
|
|
000000000000000000000010000000001100000100000100000000
|
|
000000000000000000000000000000010000000000000100000000
|
|
000000000000000000000000000000000000000000000100000000
|
|
000000000000000000000010000001000000000010000100000000
|
|
000000000010000000000010000000001011100000000001000000
|
|
000000000000000000000110000001011010010000000000000000
|
|
010000000000000000000000001000000000000000000100000010
|
|
100000000000000001000000000111000000000010000100000000
|
|
|
|
.logic_tile 8 14
|
|
000000000000101000000010100011011011100000000000000000
|
|
000000000001011111000000000011111010010000100010000000
|
|
001000000000000011100000001111101010000110100000000000
|
|
100000000000000000000000000011101001001111110000000000
|
|
010000000000000001000011100000011000000100000100000000
|
|
110000000000000111000000000000000000000000000000000000
|
|
000000000000000111100010000011011010000011010000000000
|
|
000000000000000111000010100101111100011111100000000000
|
|
000000000000000001000110000000000000000000000100000000
|
|
000000000000000001000010000111000000000010000000000000
|
|
000010100000000001100000000101101100101000000000000000
|
|
000001000000000000000000000101110000000000000000000010
|
|
000000000000000001000000000000000000000000000100000000
|
|
000000000000000000000000000001000000000010000000000000
|
|
000000000000000000000110000000000001000000100100000000
|
|
000000000000000000000000000000001010000000000000000000
|
|
|
|
.logic_tile 9 14
|
|
000000000000001101000000001101111001010111100000000000
|
|
000000001000010011100011111011001010000111010000000000
|
|
001000000000001101100111000011111111000110100000000000
|
|
100000000000000011000100000001111000001111110000000000
|
|
010000000000000000000000000000000001000000100100000000
|
|
010001000000000000000000000000001100000000000000000000
|
|
000000000000001101000111101001011011000000000000000000
|
|
000000000000000101100000000111011111010000000000000000
|
|
000000000000000000000000010000011000000100000100000000
|
|
000000000000000000000010000000010000000000000000000000
|
|
000000000000000000000000011111001101010111100000000000
|
|
000000001100000001000010010001011111001011100000000000
|
|
000000000000000001000000011111011110001000000000000001
|
|
000000000000000000100011101101101000000000000000000010
|
|
000000000000000000000110010001100000000000000100000000
|
|
000000000000000001000010010000000000000001000000000000
|
|
|
|
.ramt_tile 10 14
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 14
|
|
000000000000000000000111000111100000000000000100000000
|
|
000000000000010000000011110000000000000001000000000000
|
|
001000000000000011100111010000000000000000100100000000
|
|
100000000000000000000111010000001001000000000000000000
|
|
010000000000000000000000000000000001000000100100000000
|
|
010000000000000001000000000000001001000000000000000000
|
|
000000000000100011100000001000000000000000000100000000
|
|
000000000000000000100000000001000000000010000000000000
|
|
000000000000000000000000000000000001000000100100000000
|
|
000000000000000001000000000000001010000000000000000000
|
|
000000000000000000000000000011000000000000000100000000
|
|
000000000000000000000000000000000000000001000000000000
|
|
000000000000000000000000000001100000000000000100000000
|
|
000000000000000000000000000000100000000001000000000000
|
|
000000000000001000000000000000000000000000000100000000
|
|
000000000000001101000000000101000000000010000000000000
|
|
|
|
.logic_tile 12 14
|
|
000000000000000000000110101011101111000000000000000000
|
|
000000000000000000000000000011011111010000010000000000
|
|
001000000000000000000110101111111111000001000100000000
|
|
100000000000000000000000001001101111010111100000100000
|
|
110000000000001101100000011111111100111001110100000000
|
|
110000000000000001000010101111101010110100010001000000
|
|
000000000000000101100000011111111010011101000100000000
|
|
000000000000000000000010100011101111110100010001000000
|
|
000000000000000000000000000011111011011100100100100000
|
|
000000000000000000000000000000011111011100100000000100
|
|
000000000000001001100000000000011110001101000100000000
|
|
000000000000001001100000001001011010001110000001000000
|
|
000000000000000000000110010111000001000110000000000000
|
|
000000000000000000000110010000101100000110000000000000
|
|
000000000000000001100110010000011110110001110100000000
|
|
000000000000000000100110001101011010110010110000100000
|
|
|
|
.io_tile 13 14
|
|
000000000000000010
|
|
000100000000000000
|
|
000000011000000000
|
|
000000001000000001
|
|
000000000000100010
|
|
000000000000010000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000011000000000
|
|
000100001000000000
|
|
000000000000000010
|
|
000000000000110000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000010
|
|
000000000000000000
|
|
|
|
.io_tile 0 15
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 15
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
111000000000001000000000000001100000101111010100100100
|
|
000000000000000001000000000000001100101111010110000010
|
|
110000000000000001100110000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000010001100000000000000100000000
|
|
000000000000000000000011010000000000000001000110000010
|
|
000000000000000001100000000101100000000000000000000000
|
|
000000000000000000000000001101101010100000010000000000
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000010100000000000000000000000000000
|
|
000000000000000000000111100101101101001110000010000000
|
|
000000000000000000000100001101101101101101010000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 2 15
|
|
000000000000000101100110110011100000000000001000000000
|
|
000000000000000000000010000000000000000000000000001000
|
|
111000000000000000000000000111111110001000011100000000
|
|
000000000000000000000000000001101100010010000100000000
|
|
110000000000000101100000010011001000100001000100000000
|
|
010000000000000000000010000101001001000100100100000000
|
|
000000000000000000000000000011101010001100000100000000
|
|
000000000000000000000000001001101101101101010100000000
|
|
000000000000000001000110000000000000000000000000000000
|
|
000000000000000000000010000000000000000000000000000000
|
|
000001000000000001100000010000000000001111000000000000
|
|
000000000000000000000010000000001101001111000000000000
|
|
000000000000000001100000000011001010100000000000000000
|
|
000000000000000000000000000111111010000000000010100000
|
|
010000000000000001100110000111000000010110100000000000
|
|
100000000000000000000000000000000000010110100000000000
|
|
|
|
.ramb_tile 3 15
|
|
000000000000000000000000000000000000000000
|
|
000000010000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000001110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 4 15
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011100000000000000000000000000000
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000011100000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000111101011000000001001000100000000
|
|
000000000000000000000100000011101010000000000100100000
|
|
000000000000001000000111100000000001110110110000000000
|
|
000000000000000111000000001011001101111001110010000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 5 15
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000100000000000000000000000000000000000000000
|
|
000000000000000000000110000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000001110000100000100000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000001100000000000000000000000100100000010
|
|
000000000000000000100000000000001011000000000000100000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 6 15
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000100000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 7 15
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000010000000000000000000000000000
|
|
000000000000000000000011010000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000011110000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000001000000000000000101100000000000000100000000
|
|
000000000000100000000000000000100000000001000100000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 8 15
|
|
000000000000000000000010100111011100111110100100000000
|
|
000000000000000000000010101011110000101001010001000000
|
|
001000000000000101000000001101111000000110100000000000
|
|
100000000000001001000010100101001001001111110000000000
|
|
110000000000000000000011101001011000010111100000000000
|
|
110000000000000000000100001001101100001011100000000000
|
|
000000000000000101000011100000000000000000000000000000
|
|
000000000000001101000100000000000000000000000000000000
|
|
000000100000001001100000010000000000000000000000000000
|
|
000000000000000011000010000000000000000000000000000000
|
|
000000000000001000000010001101100000101111010100000000
|
|
000000000100001011000000001011101100001111000000100000
|
|
000000000000000000000011101001011000000110100000000000
|
|
000000000000000000000010010011101001001111110000000000
|
|
000000000000000000000000011000001011101111000100000000
|
|
000000000000000000000010001011011111011111000000100000
|
|
|
|
.logic_tile 9 15
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000011010000100000100000000
|
|
100000000000010000000010100000000000000000000100000000
|
|
010000000000000000000010100000000000000000000000000000
|
|
110000000000000000000000000000000000000000000000000000
|
|
000000000000000111100010000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000001100000000000011010000100000100000000
|
|
000000000000000000100000000000010000000000000100000000
|
|
000000000000000000000000000000011101110000000000000100
|
|
000000000000000000000000000000001001110000000010000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.ramb_tile 10 15
|
|
000001000000000000000000000000000000000000
|
|
000000110000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000100000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 15
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000111100000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000111000001100000101001010000000100
|
|
000000000000000000000100001111000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 12 15
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000001000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000100000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 15
|
|
000000000000000010
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000110010
|
|
000000000000010000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000100010
|
|
000001010000110000
|
|
000001010000000000
|
|
000000000000000001
|
|
000000000000000010
|
|
000000000000000000
|
|
|
|
.io_tile 0 16
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.logic_tile 1 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 2 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.ramt_tile 3 16
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 4 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000111000000000000000100100001
|
|
000000000000000000000000000000000000000001000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000001000000000000000000000000000000000000000
|
|
000000000000000101000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 5 16
|
|
000000000000000000000000000000001100000100000100000000
|
|
000000000000000000000000000000010000000000000000000000
|
|
111000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000011100000010110100000000000
|
|
000000000000000000000000000000100000010110100000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000110100000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000000000000111000000000000000000000000000000
|
|
000000000000000000000100000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 6 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 7 16
|
|
000000000000001000000000000000000000000000000000000000
|
|
000000000000000011000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000011110000011110100000000
|
|
000000000000000000000000000000000000000011110000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
010000000000000001100000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 8 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000010010000000000000000000000000000
|
|
001000000000000000000000000000000000000000000000000000
|
|
100000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
010000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000111000000000000000100000000
|
|
000000000000000000000000000000100000000001000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000011100000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 9 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.ramt_tile 10 16
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 11 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.logic_tile 12 16
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
000000000000000000000000000000000000000000000000000000
|
|
|
|
.io_tile 13 16
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 1 17
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000011000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 2 17
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000001010000000000
|
|
000000001000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000010010
|
|
000000000000010000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000010
|
|
000000000000000000
|
|
|
|
.io_tile 3 17
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 4 17
|
|
000000000001011010
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000100010
|
|
000000000000110000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000110000000000
|
|
000000001000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 5 17
|
|
000000000000011000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 6 17
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000001100
|
|
000000000000001000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000010000000000000
|
|
000000010000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 7 17
|
|
100000000000000000
|
|
011000000000000001
|
|
010000000000000000
|
|
001000000000000001
|
|
000000011000000100
|
|
000000001000000101
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 8 17
|
|
000000000000000000
|
|
100000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
010000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 9 17
|
|
000000000000000000
|
|
010000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
001000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
100100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 10 17
|
|
000000000000000010
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000100010
|
|
000000000000010000
|
|
000000000000000000
|
|
000000000000000000
|
|
000001111000000000
|
|
100000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 11 17
|
|
000000000000000010
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000001
|
|
000000000000110010
|
|
000000000000010000
|
|
001100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000001011000000000
|
|
000000001000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.io_tile 12 17
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000100000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
000000000000000000
|
|
|
|
.ram_data 10 3
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.ram_data 10 7
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.ram_data 3 1
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.ram_data 3 3
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.ram_data 3 7
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.ram_data 3 5
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.ram_data 10 5
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.ram_data 3 9
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
0000000000000000000000000000000000000000000000000000000000000000
|
|
|
|
.sym 1 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 2 r_counter_$glb_clk
|
|
.sym 3 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 4 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 5 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 6 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 7 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 8 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 51 w_rx_09_fifo_data[12]
|
|
.sym 53 w_rx_09_fifo_data[16]
|
|
.sym 54 w_rx_09_fifo_data[14]
|
|
.sym 182 w_rx_09_fifo_data[20]
|
|
.sym 183 w_rx_09_fifo_data[18]
|
|
.sym 184 w_rx_09_fifo_data[22]
|
|
.sym 293 w_rx_09_fifo_data[11]
|
|
.sym 296 w_rx_09_fifo_data[9]
|
|
.sym 297 w_rx_09_fifo_data[24]
|
|
.sym 298 rx_fifo.mem_q.0.2_WDATA_1
|
|
.sym 405 w_rx_24_fifo_data[9]
|
|
.sym 406 w_rx_24_fifo_data[11]
|
|
.sym 407 w_rx_24_fifo_data[12]
|
|
.sym 408 w_rx_24_fifo_data[8]
|
|
.sym 409 w_rx_24_fifo_data[13]
|
|
.sym 410 w_rx_24_fifo_data[10]
|
|
.sym 411 o_iq_tx_clk_n$SB_IO_OUT
|
|
.sym 412 w_rx_24_fifo_data[7]
|
|
.sym 460 rx_fifo.mem_q.0.2_WDATA_1
|
|
.sym 492 o_iq_tx_clk_n$SB_IO_OUT
|
|
.sym 497 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 504 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 509 o_iq_tx_clk_n$SB_IO_OUT
|
|
.sym 519 w_rx_09_fifo_data[8]
|
|
.sym 520 w_rx_09_fifo_data[6]
|
|
.sym 521 w_rx_09_fifo_data[2]
|
|
.sym 522 w_rx_09_fifo_data[3]
|
|
.sym 523 rx_fifo.mem_q.0.1_WDATA_2
|
|
.sym 524 w_rx_09_fifo_data[4]
|
|
.sym 525 rx_fifo.mem_q.0.2_WDATA_2
|
|
.sym 526 w_rx_09_fifo_data[10]
|
|
.sym 552 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 599 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 638 w_rx_24_fifo_data[1]
|
|
.sym 640 rx_fifo.mem_q.0.2_WDATA_3
|
|
.sym 746 $PACKER_GND_NET
|
|
.sym 748 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 750 rx_fifo.wr_addr[6]
|
|
.sym 751 rx_fifo.wr_addr[4]
|
|
.sym 796 w_lvds_rx_24_d0
|
|
.sym 801 rx_fifo.mem_q.0.2_WDATA_3
|
|
.sym 826 w_lvds_rx_24_d0
|
|
.sym 830 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 856 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 861 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
|
|
.sym 862 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
|
|
.sym 863 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2]
|
|
.sym 864 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
|
|
.sym 865 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1]
|
|
.sym 866 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 867 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 897 rx_fifo.wr_addr[6]
|
|
.sym 899 rx_fifo.wr_addr[4]
|
|
.sym 920 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 944 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 963 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 974 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 975 rx_fifo.wr_addr[1]
|
|
.sym 976 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
|
|
.sym 977 rx_fifo.wr_addr[5]
|
|
.sym 978 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 979 rx_fifo.wr_addr[7]
|
|
.sym 980 rx_fifo.wr_addr[3]
|
|
.sym 981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 984 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 1009 rx_fifo.wr_addr[8]
|
|
.sym 1031 $PACKER_VCC_NET
|
|
.sym 1046 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 1054 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 1055 $PACKER_VCC_NET
|
|
.sym 1061 $PACKER_GND_NET
|
|
.sym 1062 $PACKER_GND_NET
|
|
.sym 1066 $PACKER_VCC_NET
|
|
.sym 1067 $PACKER_VCC_NET
|
|
.sym 1069 $PACKER_VCC_NET
|
|
.sym 1071 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 1074 $PACKER_VCC_NET
|
|
.sym 1077 $PACKER_GND_NET
|
|
.sym 1085 $PACKER_GND_NET
|
|
.sym 1086 $PACKER_VCC_NET
|
|
.sym 1088 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 1089 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 1090 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 1091 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
|
|
.sym 1092 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3]
|
|
.sym 1093 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 1094 w_rx_fifo_full
|
|
.sym 1095 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
|
|
.sym 1120 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 1121 rx_fifo.wr_addr[3]
|
|
.sym 1123 rx_fifo.wr_addr[5]
|
|
.sym 1125 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 1126 $PACKER_VCC_NET
|
|
.sym 1127 rx_fifo.wr_addr[7]
|
|
.sym 1129 rx_fifo.wr_addr[3]
|
|
.sym 1130 $PACKER_VCC_NET
|
|
.sym 1132 rx_fifo.wr_addr[9]
|
|
.sym 1136 rx_fifo.wr_addr[1]
|
|
.sym 1160 $PACKER_GND_NET
|
|
.sym 1165 rx_fifo.wr_addr[1]
|
|
.sym 1173 w_lvds_rx_09_d0
|
|
.sym 1174 w_lvds_rx_09_d1
|
|
.sym 1183 $PACKER_VCC_NET
|
|
.sym 1184 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 1196 $PACKER_VCC_NET
|
|
.sym 1202 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.sym 1203 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 1204 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E
|
|
.sym 1206 rx_fifo.full_o_SB_LUT4_I0_O[2]
|
|
.sym 1207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
|
|
.sym 1208 rx_fifo.full_o_SB_LUT4_I0_O[1]
|
|
.sym 1209 rx_fifo.rd_addr_gray_wr_r[0]
|
|
.sym 1230 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 1234 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 1235 w_rx_fifo_full
|
|
.sym 1242 i_rst_b$SB_IO_IN
|
|
.sym 1246 $PACKER_VCC_NET
|
|
.sym 1261 w_rx_fifo_full
|
|
.sym 1269 w_lvds_rx_09_d0
|
|
.sym 1271 w_lvds_rx_09_d1
|
|
.sym 1282 w_lvds_rx_24_d0
|
|
.sym 1287 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 1297 $PACKER_VCC_NET
|
|
.sym 1313 $PACKER_VCC_NET
|
|
.sym 1316 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 1317 w_rx_09_fifo_data[0]
|
|
.sym 1318 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 1319 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.sym 1320 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E
|
|
.sym 1321 w_lvds_rx_09_d0_SB_LUT4_I2_O[2]
|
|
.sym 1322 w_rx_09_fifo_data[1]
|
|
.sym 1323 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
|
|
.sym 1343 rx_fifo.rd_addr_gray_wr[0]
|
|
.sym 1401 w_lvds_rx_24_d0
|
|
.sym 1402 w_lvds_rx_24_d1
|
|
.sym 1411 $PACKER_VCC_NET
|
|
.sym 1412 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 1416 $PACKER_VCC_NET
|
|
.sym 1430 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 1431 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
|
|
.sym 1432 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1]
|
|
.sym 1433 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 1434 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
|
|
.sym 1459 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 1463 i_rst_b$SB_IO_IN
|
|
.sym 1474 w_lvds_rx_24_d1
|
|
.sym 1481 $PACKER_VCC_NET
|
|
.sym 1510 i_rst_b$SB_IO_IN
|
|
.sym 1545 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 1547 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 1548 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.sym 1550 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O
|
|
.sym 1699 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O
|
|
.sym 1714 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
|
|
.sym 1880 w_rx_09_fifo_data[13]
|
|
.sym 1882 w_rx_09_fifo_data[15]
|
|
.sym 1883 rx_fifo.mem_q.0.3_WDATA_1
|
|
.sym 1884 w_rx_09_fifo_data[17]
|
|
.sym 1886 rx_fifo.mem_q.0.3_WDATA
|
|
.sym 1914 o_led0$SB_IO_OUT
|
|
.sym 1939 w_rx_09_fifo_data[10]
|
|
.sym 2063 w_rx_24_fifo_data[14]
|
|
.sym 2064 w_rx_24_fifo_data[16]
|
|
.sym 2065 w_rx_24_fifo_data[17]
|
|
.sym 2066 w_rx_24_fifo_data[22]
|
|
.sym 2067 w_rx_24_fifo_data[18]
|
|
.sym 2068 rx_fifo.mem_q.0.3_WDATA_2
|
|
.sym 2069 rx_fifo.mem_q.0.3_WDATA_3
|
|
.sym 2070 w_rx_24_fifo_data[15]
|
|
.sym 2072 rx_fifo.wr_addr[5]
|
|
.sym 2073 rx_fifo.wr_addr[5]
|
|
.sym 2079 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 2091 o_led1$SB_IO_OUT
|
|
.sym 2093 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2107 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2122 w_rx_09_fifo_data[11]
|
|
.sym 2124 w_rx_09_fifo_data[17]
|
|
.sym 2137 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2152 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2155 w_rx_09_fifo_data[10]
|
|
.sym 2180 w_rx_09_fifo_data[12]
|
|
.sym 2183 w_rx_09_fifo_data[14]
|
|
.sym 2209 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2212 w_rx_09_fifo_data[10]
|
|
.sym 2221 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2223 w_rx_09_fifo_data[14]
|
|
.sym 2228 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2229 w_rx_09_fifo_data[12]
|
|
.sym 2231 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 2232 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 2234 w_rx_09_fifo_data[25]
|
|
.sym 2235 w_rx_09_fifo_data[19]
|
|
.sym 2236 w_rx_09_fifo_data[21]
|
|
.sym 2237 rx_fifo.mem_i.0.1_WDATA_2
|
|
.sym 2238 rx_fifo.mem_i.0.0_WDATA_2
|
|
.sym 2239 w_rx_09_fifo_data[23]
|
|
.sym 2240 rx_fifo.mem_i.0.0_WDATA_3
|
|
.sym 2241 rx_fifo.mem_i.0.0_WDATA_1
|
|
.sym 2242 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2244 w_rx_09_fifo_data[0]
|
|
.sym 2245 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2251 rx_fifo.rd_addr[1]
|
|
.sym 2254 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2256 o_led1$SB_IO_OUT
|
|
.sym 2258 w_rx_24_fifo_data[17]
|
|
.sym 2260 w_rx_24_fifo_data[22]
|
|
.sym 2262 w_rx_24_fifo_data[12]
|
|
.sym 2266 w_rx_24_fifo_data[13]
|
|
.sym 2270 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2293 w_rx_09_fifo_data[18]
|
|
.sym 2301 w_rx_09_fifo_data[16]
|
|
.sym 2310 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2316 w_rx_09_fifo_data[20]
|
|
.sym 2350 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2353 w_rx_09_fifo_data[18]
|
|
.sym 2357 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2359 w_rx_09_fifo_data[16]
|
|
.sym 2364 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2365 w_rx_09_fifo_data[20]
|
|
.sym 2366 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 2367 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 2368 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 2369 w_rx_24_fifo_data[24]
|
|
.sym 2370 w_rx_24_fifo_data[26]
|
|
.sym 2371 rx_fifo.mem_i.0.0_WDATA
|
|
.sym 2372 w_rx_24_fifo_data[19]
|
|
.sym 2373 rx_fifo.mem_i.0.2_WDATA_3
|
|
.sym 2374 w_rx_24_fifo_data[21]
|
|
.sym 2375 w_rx_24_fifo_data[30]
|
|
.sym 2376 w_rx_24_fifo_data[28]
|
|
.sym 2378 w_rx_fifo_pulled_data[22]
|
|
.sym 2383 w_rx_09_fifo_data[20]
|
|
.sym 2384 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2388 w_rx_09_fifo_data[25]
|
|
.sym 2392 o_led1$SB_IO_OUT
|
|
.sym 2394 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2396 w_rx_24_fifo_data[21]
|
|
.sym 2402 o_led1$SB_IO_OUT
|
|
.sym 2403 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2405 rx_fifo.mem_q.0.2_WDATA_2
|
|
.sym 2407 w_rx_09_fifo_data[10]
|
|
.sym 2415 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2424 o_led1$SB_IO_OUT
|
|
.sym 2427 w_rx_09_fifo_data[9]
|
|
.sym 2429 w_rx_09_fifo_data[22]
|
|
.sym 2430 w_rx_24_fifo_data[9]
|
|
.sym 2442 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2445 w_rx_09_fifo_data[7]
|
|
.sym 2467 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2470 w_rx_09_fifo_data[9]
|
|
.sym 2485 w_rx_09_fifo_data[7]
|
|
.sym 2488 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2491 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2492 w_rx_09_fifo_data[22]
|
|
.sym 2497 w_rx_09_fifo_data[9]
|
|
.sym 2498 o_led1$SB_IO_OUT
|
|
.sym 2499 w_rx_24_fifo_data[9]
|
|
.sym 2501 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 2502 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 2503 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 2504 rx_fifo.mem_q.0.2_WDATA
|
|
.sym 2505 w_rx_09_fifo_data[5]
|
|
.sym 2506 rx_fifo.mem_q.0.1_WDATA_1
|
|
.sym 2507 rx_fifo.mem_q.0.1_WDATA
|
|
.sym 2508 rx_fifo.mem_i.0.2_WDATA_2
|
|
.sym 2509 w_rx_09_fifo_data[26]
|
|
.sym 2510 w_rx_09_fifo_data[28]
|
|
.sym 2511 w_rx_09_fifo_data[7]
|
|
.sym 2513 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2514 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2516 rx_fifo.rd_addr[4]
|
|
.sym 2517 w_rx_24_fifo_data[30]
|
|
.sym 2518 o_led1$SB_IO_OUT
|
|
.sym 2520 rx_fifo.rd_addr[8]
|
|
.sym 2528 rx_fifo.wr_addr[5]
|
|
.sym 2530 rx_fifo.wr_addr[3]
|
|
.sym 2531 rx_fifo.wr_addr[1]
|
|
.sym 2534 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2542 w_rx_24_fifo_data[8]
|
|
.sym 2557 w_rx_24_fifo_data[9]
|
|
.sym 2561 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 2568 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2570 w_rx_24_fifo_data[10]
|
|
.sym 2574 w_rx_24_fifo_data[11]
|
|
.sym 2575 w_rx_24_fifo_data[5]
|
|
.sym 2576 w_rx_24_fifo_data[8]
|
|
.sym 2580 w_rx_24_fifo_data[7]
|
|
.sym 2585 w_rx_24_fifo_data[6]
|
|
.sym 2587 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2591 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2593 w_rx_24_fifo_data[7]
|
|
.sym 2596 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2597 w_rx_24_fifo_data[9]
|
|
.sym 2603 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2604 w_rx_24_fifo_data[10]
|
|
.sym 2608 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2610 w_rx_24_fifo_data[6]
|
|
.sym 2615 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2617 w_rx_24_fifo_data[11]
|
|
.sym 2620 w_rx_24_fifo_data[8]
|
|
.sym 2622 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2626 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 2634 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 2635 w_rx_24_fifo_data[5]
|
|
.sym 2636 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2637 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 2638 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 2639 w_rx_24_fifo_data[2]
|
|
.sym 2640 rx_fifo.mem_q.0.0_WDATA_2
|
|
.sym 2641 w_rx_24_fifo_data[5]
|
|
.sym 2642 rx_fifo.mem_q.0.0_WDATA
|
|
.sym 2643 w_rx_24_fifo_data[6]
|
|
.sym 2644 w_rx_24_fifo_data[3]
|
|
.sym 2645 w_rx_24_fifo_data[4]
|
|
.sym 2646 rx_fifo.mem_q.0.1_WDATA_3
|
|
.sym 2652 w_rx_09_fifo_data[28]
|
|
.sym 2664 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 2667 rx_fifo.rd_addr_gray_wr[9]
|
|
.sym 2671 rx_fifo.wr_addr[6]
|
|
.sym 2673 rx_fifo.wr_addr[4]
|
|
.sym 2676 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2678 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2693 w_rx_09_fifo_data[6]
|
|
.sym 2697 w_rx_24_fifo_data[10]
|
|
.sym 2701 w_rx_09_fifo_data[6]
|
|
.sym 2702 w_rx_09_fifo_data[1]
|
|
.sym 2704 o_led1$SB_IO_OUT
|
|
.sym 2705 w_rx_09_fifo_data[4]
|
|
.sym 2707 w_rx_09_fifo_data[10]
|
|
.sym 2708 w_rx_09_fifo_data[8]
|
|
.sym 2709 w_rx_09_fifo_data[0]
|
|
.sym 2710 w_rx_09_fifo_data[2]
|
|
.sym 2712 w_rx_24_fifo_data[6]
|
|
.sym 2716 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2725 w_rx_09_fifo_data[6]
|
|
.sym 2726 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2731 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2732 w_rx_09_fifo_data[4]
|
|
.sym 2738 w_rx_09_fifo_data[0]
|
|
.sym 2740 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2743 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2745 w_rx_09_fifo_data[1]
|
|
.sym 2749 w_rx_24_fifo_data[6]
|
|
.sym 2750 w_rx_09_fifo_data[6]
|
|
.sym 2752 o_led1$SB_IO_OUT
|
|
.sym 2757 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2758 w_rx_09_fifo_data[2]
|
|
.sym 2762 o_led1$SB_IO_OUT
|
|
.sym 2763 w_rx_09_fifo_data[10]
|
|
.sym 2764 w_rx_24_fifo_data[10]
|
|
.sym 2767 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2770 w_rx_09_fifo_data[8]
|
|
.sym 2771 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 2772 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 2773 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 2774 rx_fifo.rd_addr_gray_wr[9]
|
|
.sym 2790 w_rx_09_fifo_data[1]
|
|
.sym 2792 o_led1$SB_IO_OUT
|
|
.sym 2794 rx_fifo.rd_addr[0]
|
|
.sym 2796 rx_fifo.rd_addr[1]
|
|
.sym 2799 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 2802 rx_fifo.rd_addr[9]
|
|
.sym 2803 rx_fifo.mem_q.0.1_WDATA_2
|
|
.sym 2807 w_rx_24_fifo_data[0]
|
|
.sym 2808 rx_fifo.mem_q.0.1_WDATA_3
|
|
.sym 2814 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2818 w_rx_09_fifo_data[1]
|
|
.sym 2819 $PACKER_GND_NET
|
|
.sym 2833 w_rx_24_fifo_data[8]
|
|
.sym 2835 w_rx_09_fifo_data[8]
|
|
.sym 2842 o_led1$SB_IO_OUT
|
|
.sym 2845 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2847 w_lvds_rx_24_d0
|
|
.sym 2893 w_lvds_rx_24_d0
|
|
.sym 2903 o_led1$SB_IO_OUT
|
|
.sym 2904 w_rx_09_fifo_data[8]
|
|
.sym 2905 w_rx_24_fifo_data[8]
|
|
.sym 2906 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2907 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 2910 rx_fifo.wr_addr_gray_rd[9]
|
|
.sym 2912 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 2913 rx_fifo.mem_q.0.0_WDATA_1
|
|
.sym 2921 rx_fifo.wr_addr[4]
|
|
.sym 2922 rx_fifo.mem_q.0.2_WDATA_2
|
|
.sym 2930 o_led1$SB_IO_OUT
|
|
.sym 2933 rx_fifo.wr_addr[6]
|
|
.sym 2935 rx_fifo.wr_addr[4]
|
|
.sym 2936 w_rx_09_fifo_data[0]
|
|
.sym 2937 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 2938 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 2939 rx_fifo.wr_addr[5]
|
|
.sym 2940 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 2941 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 2942 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 2943 rx_fifo.wr_addr[7]
|
|
.sym 2945 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 2951 rx_fifo.wr_addr[4]
|
|
.sym 2964 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 2970 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 2977 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 2982 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 2985 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 3008 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 3009 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 3019 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 3027 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 3041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 3042 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 3043 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 3044 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3]
|
|
.sym 3045 rx_fifo.mem_q.0.0_WDATA_3
|
|
.sym 3046 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
|
|
.sym 3047 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
|
|
.sym 3048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3]
|
|
.sym 3049 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 3050 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
|
|
.sym 3051 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
|
|
.sym 3052 rx_fifo.wr_addr[6]
|
|
.sym 3057 rx_fifo.wr_addr[9]
|
|
.sym 3058 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 3064 o_led1$SB_IO_OUT
|
|
.sym 3068 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 3069 rx_fifo.wr_addr[3]
|
|
.sym 3070 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E
|
|
.sym 3072 w_rx_09_fifo_data[1]
|
|
.sym 3073 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
|
|
.sym 3075 rx_fifo.wr_addr[1]
|
|
.sym 3078 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3079 rx_fifo.wr_addr[5]
|
|
.sym 3101 rx_fifo.wr_addr[6]
|
|
.sym 3102 rx_fifo.wr_addr[7]
|
|
.sym 3103 rx_fifo.wr_addr[8]
|
|
.sym 3106 rx_fifo.wr_addr[1]
|
|
.sym 3108 rx_fifo.wr_addr[5]
|
|
.sym 3109 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 3110 rx_fifo.wr_addr[4]
|
|
.sym 3111 rx_fifo.wr_addr[3]
|
|
.sym 3129 $nextpnr_ICESTORM_LC_6$O
|
|
.sym 3132 rx_fifo.wr_addr[1]
|
|
.sym 3135 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 3138 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 3139 rx_fifo.wr_addr[1]
|
|
.sym 3141 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
|
|
.sym 3143 rx_fifo.wr_addr[3]
|
|
.sym 3145 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 3147 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 3149 rx_fifo.wr_addr[4]
|
|
.sym 3151 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
|
|
.sym 3153 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3
|
|
.sym 3156 rx_fifo.wr_addr[5]
|
|
.sym 3157 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 3159 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 3161 rx_fifo.wr_addr[6]
|
|
.sym 3163 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3
|
|
.sym 3165 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 3167 rx_fifo.wr_addr[7]
|
|
.sym 3169 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 3171 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
|
|
.sym 3173 rx_fifo.wr_addr[8]
|
|
.sym 3175 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 3180 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 3181 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 3182 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 3183 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 3184 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 3185 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 3186 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 3198 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 3201 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 3202 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 3203 rx_fifo.wr_addr[9]
|
|
.sym 3204 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 3205 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 3207 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3208 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 3209 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 3210 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 3212 rx_fifo.rd_addr_gray_wr[9]
|
|
.sym 3213 rx_fifo.wr_addr[1]
|
|
.sym 3214 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 3218 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 3220 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 3227 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
|
|
.sym 3232 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3]
|
|
.sym 3234 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 3237 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1]
|
|
.sym 3238 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3245 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3246 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 3247 rx_fifo.wr_addr[9]
|
|
.sym 3249 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 3250 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 3255 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 3259 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 3261 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 3265 rx_fifo.wr_addr[9]
|
|
.sym 3268 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
|
|
.sym 3273 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 3277 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3]
|
|
.sym 3278 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 3279 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3280 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1]
|
|
.sym 3284 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 3291 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 3295 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 3303 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 3307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1]
|
|
.sym 3308 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3309 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 3311 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 3312 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 3313 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 3314 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 3315 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 3316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 3317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 3318 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 3319 rx_fifo.wr_addr[0]
|
|
.sym 3320 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 3321 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 3322 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 3329 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 3330 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 3334 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3336 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 3337 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 3338 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 3341 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 3343 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 3346 $PACKER_VCC_NET
|
|
.sym 3347 w_rx_24_fifo_data[0]
|
|
.sym 3349 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 3350 w_rx_09_fifo_data[1]
|
|
.sym 3351 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3357 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3358 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 3367 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.sym 3368 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
|
|
.sym 3369 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
|
|
.sym 3372 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
|
|
.sym 3373 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 3374 rx_fifo.rd_addr_gray_wr_r[0]
|
|
.sym 3375 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 3376 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 3377 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 3378 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
|
|
.sym 3379 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
|
|
.sym 3380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
|
|
.sym 3381 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 3382 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 3388 i_rst_b$SB_IO_IN
|
|
.sym 3389 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 3390 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
|
|
.sym 3391 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3393 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 3394 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
|
|
.sym 3398 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 3400 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 3402 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 3403 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 3408 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 3409 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 3413 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 3414 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 3418 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
|
|
.sym 3419 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
|
|
.sym 3420 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
|
|
.sym 3421 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
|
|
.sym 3424 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 3425 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 3426 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 3427 rx_fifo.rd_addr_gray_wr_r[0]
|
|
.sym 3431 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.sym 3432 i_rst_b$SB_IO_IN
|
|
.sym 3436 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
|
|
.sym 3437 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
|
|
.sym 3438 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
|
|
.sym 3439 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
|
|
.sym 3442 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 3443 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 3444 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 3445 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 3447 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 3448 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 3449 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 3450 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 3451 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 3452 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
|
|
.sym 3453 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 3454 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 3455 rx_fifo.rd_addr_gray_wr[8]
|
|
.sym 3456 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 3462 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 3467 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 3468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
|
|
.sym 3469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 3471 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3]
|
|
.sym 3472 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
|
|
.sym 3473 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3474 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 3476 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 3480 w_rx_09_fifo_data[0]
|
|
.sym 3482 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 3486 w_lvds_rx_09_d1
|
|
.sym 3488 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3489 w_lvds_rx_09_d0
|
|
.sym 3503 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 3508 w_rx_fifo_full
|
|
.sym 3511 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 3516 rx_fifo.rd_addr_gray_wr[0]
|
|
.sym 3518 rx_fifo.rd_addr_gray_wr[9]
|
|
.sym 3519 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 3521 rx_fifo.wr_addr[1]
|
|
.sym 3522 rx_fifo.full_o_SB_LUT4_I0_O[2]
|
|
.sym 3524 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3526 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3528 rx_fifo.full_o_SB_LUT4_I0_O[0]
|
|
.sym 3530 w_lvds_rx_09_d0
|
|
.sym 3531 w_lvds_rx_09_d1
|
|
.sym 3532 rx_fifo.full_o_SB_LUT4_I0_O[1]
|
|
.sym 3533 rx_fifo.rd_addr_gray_wr_r[0]
|
|
.sym 3535 w_lvds_rx_09_d1
|
|
.sym 3536 w_lvds_rx_09_d0
|
|
.sym 3537 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3538 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3542 rx_fifo.rd_addr_gray_wr[9]
|
|
.sym 3547 w_lvds_rx_09_d1
|
|
.sym 3548 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3549 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3550 w_lvds_rx_09_d0
|
|
.sym 3559 rx_fifo.rd_addr_gray_wr_r[0]
|
|
.sym 3560 rx_fifo.wr_addr[1]
|
|
.sym 3561 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 3562 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 3565 rx_fifo.full_o_SB_LUT4_I0_O[0]
|
|
.sym 3566 rx_fifo.full_o_SB_LUT4_I0_O[2]
|
|
.sym 3567 rx_fifo.full_o_SB_LUT4_I0_O[1]
|
|
.sym 3571 w_rx_fifo_full
|
|
.sym 3572 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 3573 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 3574 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 3577 rx_fifo.rd_addr_gray_wr[0]
|
|
.sym 3582 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 3584 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 3586 rx_fifo.full_o_SB_LUT4_I0_O[0]
|
|
.sym 3587 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E
|
|
.sym 3588 w_rx_24_fifo_data[0]
|
|
.sym 3590 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 3607 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 3609 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E
|
|
.sym 3610 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3612 w_rx_09_fifo_data[1]
|
|
.sym 3613 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3614 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 3615 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
|
|
.sym 3622 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.sym 3637 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3641 w_lvds_rx_24_d0
|
|
.sym 3644 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 3645 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.sym 3649 i_rst_b$SB_IO_IN
|
|
.sym 3650 w_lvds_rx_24_d1
|
|
.sym 3652 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
|
|
.sym 3655 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 3659 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 3661 w_lvds_rx_09_d1
|
|
.sym 3663 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3666 w_lvds_rx_09_d0
|
|
.sym 3667 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 3670 w_lvds_rx_24_d1
|
|
.sym 3671 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 3672 w_lvds_rx_24_d0
|
|
.sym 3673 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3676 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 3677 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 3678 w_lvds_rx_09_d1
|
|
.sym 3684 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
|
|
.sym 3685 i_rst_b$SB_IO_IN
|
|
.sym 3689 w_lvds_rx_24_d1
|
|
.sym 3691 w_lvds_rx_24_d0
|
|
.sym 3694 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 3696 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3697 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.sym 3702 w_lvds_rx_09_d1
|
|
.sym 3703 w_lvds_rx_09_d0
|
|
.sym 3708 w_lvds_rx_09_d0
|
|
.sym 3712 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3713 w_lvds_rx_24_d0
|
|
.sym 3714 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 3715 w_lvds_rx_24_d1
|
|
.sym 3716 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 3717 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 3720 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 3721 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 3722 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1]
|
|
.sym 3723 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 3724 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 3725 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 3726 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 3732 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 3740 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 3743 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 3761 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 3772 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3775 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3780 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 3783 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E
|
|
.sym 3785 w_lvds_rx_09_d0_SB_LUT4_I2_O[2]
|
|
.sym 3794 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 3796 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3798 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1]
|
|
.sym 3802 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 3807 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3808 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1]
|
|
.sym 3811 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 3812 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 3818 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3819 w_lvds_rx_09_d0_SB_LUT4_I2_O[2]
|
|
.sym 3820 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3825 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1]
|
|
.sym 3829 w_lvds_rx_09_d0_SB_LUT4_I2_O[2]
|
|
.sym 3830 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 3831 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 3832 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3851 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E
|
|
.sym 3852 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 3853 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 3855 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0]
|
|
.sym 3856 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2]
|
|
.sym 3857 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 3859 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3]
|
|
.sym 3860 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 3861 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1]
|
|
.sym 3862 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
|
|
.sym 3874 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 3911 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.sym 3916 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3918 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 3921 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.sym 3924 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3929 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 3934 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
|
|
.sym 3947 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.sym 3948 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3959 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.sym 3964 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 3965 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.sym 3966 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3976 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 3977 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.sym 3978 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 3979 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 3986 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O
|
|
.sym 3987 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 4002 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 4005 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4009 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 4208 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 4238 w_rx_fifo_pulled_data[12]
|
|
.sym 4242 w_rx_fifo_pulled_data[14]
|
|
.sym 4285 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4286 w_rx_24_fifo_data[15]
|
|
.sym 4288 w_rx_24_fifo_data[13]
|
|
.sym 4290 w_rx_09_fifo_data[15]
|
|
.sym 4291 o_led1$SB_IO_OUT
|
|
.sym 4296 w_rx_09_fifo_data[13]
|
|
.sym 4303 w_rx_09_fifo_data[11]
|
|
.sym 4319 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4320 w_rx_09_fifo_data[11]
|
|
.sym 4332 w_rx_09_fifo_data[13]
|
|
.sym 4333 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4337 o_led1$SB_IO_OUT
|
|
.sym 4338 w_rx_24_fifo_data[13]
|
|
.sym 4339 w_rx_09_fifo_data[13]
|
|
.sym 4343 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4345 w_rx_09_fifo_data[15]
|
|
.sym 4354 o_led1$SB_IO_OUT
|
|
.sym 4355 w_rx_09_fifo_data[15]
|
|
.sym 4356 w_rx_24_fifo_data[15]
|
|
.sym 4358 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 4359 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 4360 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 4366 w_rx_fifo_pulled_data[13]
|
|
.sym 4370 w_rx_fifo_pulled_data[15]
|
|
.sym 4388 w_rx_24_fifo_data[13]
|
|
.sym 4393 $PACKER_VCC_NET
|
|
.sym 4394 rx_fifo.wr_addr[1]
|
|
.sym 4396 rx_fifo.wr_addr[7]
|
|
.sym 4398 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 4402 rx_fifo.wr_addr[3]
|
|
.sym 4408 rx_fifo.wr_addr[0]
|
|
.sym 4414 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 4424 rx_fifo.wr_addr[4]
|
|
.sym 4427 rx_fifo.wr_addr[6]
|
|
.sym 4428 rx_fifo.rd_addr[4]
|
|
.sym 4444 w_rx_24_fifo_data[20]
|
|
.sym 4446 w_rx_09_fifo_data[12]
|
|
.sym 4447 o_led1$SB_IO_OUT
|
|
.sym 4448 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4451 w_rx_24_fifo_data[16]
|
|
.sym 4453 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 4457 w_rx_09_fifo_data[14]
|
|
.sym 4458 w_rx_24_fifo_data[14]
|
|
.sym 4462 w_rx_24_fifo_data[13]
|
|
.sym 4466 w_rx_24_fifo_data[12]
|
|
.sym 4473 w_rx_24_fifo_data[15]
|
|
.sym 4477 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4478 w_rx_24_fifo_data[12]
|
|
.sym 4482 w_rx_24_fifo_data[14]
|
|
.sym 4484 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4487 w_rx_24_fifo_data[15]
|
|
.sym 4489 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4494 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4496 w_rx_24_fifo_data[20]
|
|
.sym 4499 w_rx_24_fifo_data[16]
|
|
.sym 4501 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4505 o_led1$SB_IO_OUT
|
|
.sym 4506 w_rx_09_fifo_data[14]
|
|
.sym 4508 w_rx_24_fifo_data[14]
|
|
.sym 4512 o_led1$SB_IO_OUT
|
|
.sym 4513 w_rx_09_fifo_data[12]
|
|
.sym 4514 w_rx_24_fifo_data[12]
|
|
.sym 4518 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4520 w_rx_24_fifo_data[13]
|
|
.sym 4521 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 4522 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 4523 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 4525 w_rx_fifo_pulled_data[16]
|
|
.sym 4529 w_rx_fifo_pulled_data[18]
|
|
.sym 4536 rx_fifo.rd_addr[0]
|
|
.sym 4537 o_led1$SB_IO_OUT
|
|
.sym 4538 w_rx_24_fifo_data[20]
|
|
.sym 4539 rx_fifo.rd_addr[8]
|
|
.sym 4540 rx_fifo.rd_addr[7]
|
|
.sym 4542 rx_fifo.rd_addr[2]
|
|
.sym 4543 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4544 rx_fifo.rd_addr[3]
|
|
.sym 4545 w_rx_24_fifo_data[21]
|
|
.sym 4546 w_rx_24_fifo_data[18]
|
|
.sym 4548 rx_fifo.mem_q.0.2_WDATA
|
|
.sym 4549 rx_fifo.rd_addr[5]
|
|
.sym 4550 rx_fifo.rd_addr[3]
|
|
.sym 4551 w_rx_24_fifo_data[28]
|
|
.sym 4554 rx_fifo.rd_addr[6]
|
|
.sym 4556 rx_fifo.rd_addr[0]
|
|
.sym 4558 rx_fifo.rd_addr[1]
|
|
.sym 4567 w_rx_24_fifo_data[17]
|
|
.sym 4568 o_led1$SB_IO_OUT
|
|
.sym 4569 w_rx_24_fifo_data[18]
|
|
.sym 4570 w_rx_09_fifo_data[23]
|
|
.sym 4571 w_rx_09_fifo_data[18]
|
|
.sym 4572 w_rx_09_fifo_data[22]
|
|
.sym 4574 w_rx_24_fifo_data[16]
|
|
.sym 4575 w_rx_09_fifo_data[17]
|
|
.sym 4576 w_rx_24_fifo_data[22]
|
|
.sym 4577 o_led1$SB_IO_OUT
|
|
.sym 4583 w_rx_09_fifo_data[21]
|
|
.sym 4586 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4587 w_rx_09_fifo_data[16]
|
|
.sym 4590 w_rx_09_fifo_data[19]
|
|
.sym 4599 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4601 w_rx_09_fifo_data[23]
|
|
.sym 4604 w_rx_09_fifo_data[17]
|
|
.sym 4606 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4610 w_rx_09_fifo_data[19]
|
|
.sym 4611 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4616 o_led1$SB_IO_OUT
|
|
.sym 4618 w_rx_09_fifo_data[22]
|
|
.sym 4619 w_rx_24_fifo_data[22]
|
|
.sym 4622 w_rx_24_fifo_data[18]
|
|
.sym 4623 o_led1$SB_IO_OUT
|
|
.sym 4624 w_rx_09_fifo_data[18]
|
|
.sym 4630 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4631 w_rx_09_fifo_data[21]
|
|
.sym 4634 w_rx_24_fifo_data[16]
|
|
.sym 4635 o_led1$SB_IO_OUT
|
|
.sym 4636 w_rx_09_fifo_data[16]
|
|
.sym 4640 o_led1$SB_IO_OUT
|
|
.sym 4642 w_rx_09_fifo_data[17]
|
|
.sym 4643 w_rx_24_fifo_data[17]
|
|
.sym 4644 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 4645 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 4646 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 4648 w_rx_fifo_pulled_data[17]
|
|
.sym 4652 w_rx_fifo_pulled_data[19]
|
|
.sym 4659 rx_fifo.mem_i.0.1_WDATA
|
|
.sym 4660 rx_fifo.wr_addr[5]
|
|
.sym 4661 w_rx_09_fifo_data[23]
|
|
.sym 4662 o_led1$SB_IO_OUT
|
|
.sym 4663 rx_fifo.wr_addr[1]
|
|
.sym 4664 rx_fifo.wr_addr[3]
|
|
.sym 4665 w_rx_09_fifo_data[21]
|
|
.sym 4667 rx_fifo.mem_i.0.1_WDATA_2
|
|
.sym 4668 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 4671 $PACKER_VCC_NET
|
|
.sym 4672 rx_fifo.wr_addr[1]
|
|
.sym 4673 rx_fifo.mem_q.0.0_WDATA_2
|
|
.sym 4674 rx_fifo.mem_i.0.2_WDATA
|
|
.sym 4676 rx_fifo.wr_addr[1]
|
|
.sym 4678 rx_fifo.wr_addr[3]
|
|
.sym 4679 rx_fifo.mem_i.0.2_WDATA_1
|
|
.sym 4680 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 4681 rx_fifo.wr_addr[7]
|
|
.sym 4689 w_rx_24_fifo_data[26]
|
|
.sym 4690 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4692 w_rx_24_fifo_data[17]
|
|
.sym 4694 w_rx_09_fifo_data[24]
|
|
.sym 4695 o_led1$SB_IO_OUT
|
|
.sym 4697 w_rx_09_fifo_data[19]
|
|
.sym 4702 w_rx_24_fifo_data[22]
|
|
.sym 4704 w_rx_24_fifo_data[24]
|
|
.sym 4707 w_rx_24_fifo_data[19]
|
|
.sym 4711 w_rx_24_fifo_data[28]
|
|
.sym 4715 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 4723 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4724 w_rx_24_fifo_data[22]
|
|
.sym 4728 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4730 w_rx_24_fifo_data[24]
|
|
.sym 4733 w_rx_09_fifo_data[19]
|
|
.sym 4734 o_led1$SB_IO_OUT
|
|
.sym 4736 w_rx_24_fifo_data[19]
|
|
.sym 4740 w_rx_24_fifo_data[17]
|
|
.sym 4742 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4745 w_rx_09_fifo_data[24]
|
|
.sym 4746 o_led1$SB_IO_OUT
|
|
.sym 4747 w_rx_24_fifo_data[24]
|
|
.sym 4751 w_rx_24_fifo_data[19]
|
|
.sym 4754 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4758 w_rx_24_fifo_data[28]
|
|
.sym 4759 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4764 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4765 w_rx_24_fifo_data[26]
|
|
.sym 4767 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 4768 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 4769 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 4771 w_rx_fifo_pulled_data[24]
|
|
.sym 4775 w_rx_fifo_pulled_data[26]
|
|
.sym 4784 w_smi_data_output[0]
|
|
.sym 4785 rx_fifo.wr_addr[4]
|
|
.sym 4786 rx_fifo.rd_addr[2]
|
|
.sym 4790 rx_fifo.rd_addr[6]
|
|
.sym 4793 rx_fifo.wr_addr[6]
|
|
.sym 4797 rx_fifo.wr_addr[0]
|
|
.sym 4801 w_rx_24_fifo_data[21]
|
|
.sym 4802 $PACKER_VCC_NET
|
|
.sym 4804 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 4805 rx_fifo.mem_q.0.0_WDATA
|
|
.sym 4812 w_rx_24_fifo_data[26]
|
|
.sym 4816 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4820 w_rx_24_fifo_data[11]
|
|
.sym 4821 w_rx_24_fifo_data[5]
|
|
.sym 4824 o_led1$SB_IO_OUT
|
|
.sym 4826 w_rx_24_fifo_data[7]
|
|
.sym 4828 w_rx_09_fifo_data[5]
|
|
.sym 4830 w_rx_09_fifo_data[3]
|
|
.sym 4832 w_rx_09_fifo_data[26]
|
|
.sym 4833 w_rx_09_fifo_data[24]
|
|
.sym 4834 w_rx_09_fifo_data[7]
|
|
.sym 4837 w_rx_09_fifo_data[11]
|
|
.sym 4844 o_led1$SB_IO_OUT
|
|
.sym 4845 w_rx_09_fifo_data[11]
|
|
.sym 4846 w_rx_24_fifo_data[11]
|
|
.sym 4850 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4852 w_rx_09_fifo_data[3]
|
|
.sym 4856 o_led1$SB_IO_OUT
|
|
.sym 4857 w_rx_09_fifo_data[5]
|
|
.sym 4859 w_rx_24_fifo_data[5]
|
|
.sym 4863 o_led1$SB_IO_OUT
|
|
.sym 4864 w_rx_09_fifo_data[7]
|
|
.sym 4865 w_rx_24_fifo_data[7]
|
|
.sym 4869 w_rx_24_fifo_data[26]
|
|
.sym 4870 o_led1$SB_IO_OUT
|
|
.sym 4871 w_rx_09_fifo_data[26]
|
|
.sym 4875 w_rx_09_fifo_data[24]
|
|
.sym 4876 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4881 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4883 w_rx_09_fifo_data[26]
|
|
.sym 4886 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 4888 w_rx_09_fifo_data[5]
|
|
.sym 4890 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 4891 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 4892 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 4894 w_rx_fifo_pulled_data[25]
|
|
.sym 4898 w_rx_fifo_pulled_data[27]
|
|
.sym 4905 $PACKER_VCC_NET
|
|
.sym 4908 rx_fifo.mem_q.0.1_WDATA_3
|
|
.sym 4910 rx_fifo.rd_addr[2]
|
|
.sym 4911 rx_fifo.mem_q.0.1_WDATA_1
|
|
.sym 4912 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 4913 rx_fifo.mem_q.0.1_WDATA
|
|
.sym 4914 rx_fifo.rd_addr[6]
|
|
.sym 4916 rx_fifo.mem_q.0.1_WDATA_2
|
|
.sym 4917 rx_fifo.rd_addr[4]
|
|
.sym 4918 rx_fifo.wr_addr[6]
|
|
.sym 4920 rx_fifo.wr_addr[4]
|
|
.sym 4924 rx_fifo.wr_addr[6]
|
|
.sym 4936 w_rx_09_fifo_data[2]
|
|
.sym 4937 w_rx_09_fifo_data[3]
|
|
.sym 4939 w_rx_09_fifo_data[4]
|
|
.sym 4942 w_rx_24_fifo_data[2]
|
|
.sym 4943 o_led1$SB_IO_OUT
|
|
.sym 4944 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4945 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 4947 w_rx_24_fifo_data[3]
|
|
.sym 4955 w_rx_24_fifo_data[0]
|
|
.sym 4956 w_rx_24_fifo_data[4]
|
|
.sym 4963 w_rx_24_fifo_data[1]
|
|
.sym 4968 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4970 w_rx_24_fifo_data[0]
|
|
.sym 4973 w_rx_24_fifo_data[2]
|
|
.sym 4974 o_led1$SB_IO_OUT
|
|
.sym 4976 w_rx_09_fifo_data[2]
|
|
.sym 4979 w_rx_24_fifo_data[3]
|
|
.sym 4980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4986 o_led1$SB_IO_OUT
|
|
.sym 4987 w_rx_09_fifo_data[3]
|
|
.sym 4988 w_rx_24_fifo_data[3]
|
|
.sym 4991 w_rx_24_fifo_data[4]
|
|
.sym 4994 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4997 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 4998 w_rx_24_fifo_data[1]
|
|
.sym 5004 w_rx_24_fifo_data[2]
|
|
.sym 5006 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 5010 o_led1$SB_IO_OUT
|
|
.sym 5011 w_rx_09_fifo_data[4]
|
|
.sym 5012 w_rx_24_fifo_data[4]
|
|
.sym 5013 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 5014 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 5015 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 5017 w_rx_fifo_pulled_data[8]
|
|
.sym 5021 w_rx_fifo_pulled_data[10]
|
|
.sym 5029 rx_fifo.rd_addr[7]
|
|
.sym 5030 rx_fifo.rd_addr[2]
|
|
.sym 5031 rx_fifo.rd_addr[3]
|
|
.sym 5032 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 5033 o_led1$SB_IO_OUT
|
|
.sym 5034 rx_fifo.wr_addr[7]
|
|
.sym 5035 rx_fifo.rd_addr[8]
|
|
.sym 5036 rx_fifo.wr_addr[6]
|
|
.sym 5037 rx_fifo.wr_addr[5]
|
|
.sym 5038 rx_fifo.wr_addr[4]
|
|
.sym 5041 rx_fifo.rd_addr[5]
|
|
.sym 5043 rx_fifo.rd_addr[6]
|
|
.sym 5045 rx_fifo.mem_q.0.2_WDATA
|
|
.sym 5047 rx_fifo.rd_addr[1]
|
|
.sym 5049 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 5051 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5086 rx_fifo.rd_addr[9]
|
|
.sym 5090 rx_fifo.rd_addr[9]
|
|
.sym 5137 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 5140 w_rx_fifo_pulled_data[9]
|
|
.sym 5144 w_rx_fifo_pulled_data[11]
|
|
.sym 5153 rx_fifo.wr_addr[5]
|
|
.sym 5154 rx_fifo.wr_addr[1]
|
|
.sym 5158 rx_fifo.wr_addr[3]
|
|
.sym 5159 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 5163 rx_fifo.mem_q.0.0_WDATA_1
|
|
.sym 5164 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 5165 o_led1$SB_IO_OUT
|
|
.sym 5166 rx_fifo.wr_addr[7]
|
|
.sym 5167 io_pmod[7]$SB_IO_IN
|
|
.sym 5168 rx_fifo.wr_addr[1]
|
|
.sym 5170 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 5172 rx_fifo.wr_addr[7]
|
|
.sym 5173 rx_fifo.mem_q.0.0_WDATA_2
|
|
.sym 5174 rx_fifo.wr_addr[3]
|
|
.sym 5183 o_led1$SB_IO_OUT
|
|
.sym 5184 rx_fifo.wr_addr[9]
|
|
.sym 5204 w_rx_09_fifo_data[1]
|
|
.sym 5205 rx_fifo.wr_addr_gray_rd[9]
|
|
.sym 5209 w_rx_24_fifo_data[1]
|
|
.sym 5220 rx_fifo.wr_addr[9]
|
|
.sym 5234 rx_fifo.wr_addr_gray_rd[9]
|
|
.sym 5238 w_rx_09_fifo_data[1]
|
|
.sym 5239 w_rx_24_fifo_data[1]
|
|
.sym 5240 o_led1$SB_IO_OUT
|
|
.sym 5260 r_counter_$glb_clk
|
|
.sym 5263 w_rx_fifo_pulled_data[0]
|
|
.sym 5267 w_rx_fifo_pulled_data[2]
|
|
.sym 5275 rx_fifo.rd_addr[0]
|
|
.sym 5277 rx_fifo.rd_addr[6]
|
|
.sym 5278 rx_fifo.rd_addr[2]
|
|
.sym 5281 rx_fifo.rd_addr[7]
|
|
.sym 5282 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5293 rx_fifo.mem_q.0.0_WDATA
|
|
.sym 5296 rx_fifo.wr_addr[0]
|
|
.sym 5297 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5303 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 5304 w_rx_24_fifo_data[0]
|
|
.sym 5305 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 5306 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2]
|
|
.sym 5307 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
|
|
.sym 5309 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 5310 w_rx_09_fifo_data[0]
|
|
.sym 5311 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 5312 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
|
|
.sym 5313 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
|
|
.sym 5314 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 5316 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 5317 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 5318 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 5319 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 5321 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
|
|
.sym 5322 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
|
|
.sym 5323 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3]
|
|
.sym 5325 o_led1$SB_IO_OUT
|
|
.sym 5326 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
|
|
.sym 5327 io_pmod[7]$SB_IO_IN
|
|
.sym 5330 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E
|
|
.sym 5336 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 5338 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
|
|
.sym 5342 w_rx_09_fifo_data[0]
|
|
.sym 5344 w_rx_24_fifo_data[0]
|
|
.sym 5345 o_led1$SB_IO_OUT
|
|
.sym 5348 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 5350 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
|
|
.sym 5351 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2]
|
|
.sym 5354 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2]
|
|
.sym 5355 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3]
|
|
.sym 5356 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
|
|
.sym 5357 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 5360 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
|
|
.sym 5361 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
|
|
.sym 5362 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 5367 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 5368 io_pmod[7]$SB_IO_IN
|
|
.sym 5369 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 5373 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
|
|
.sym 5374 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
|
|
.sym 5375 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
|
|
.sym 5378 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 5380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 5381 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 5382 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_E
|
|
.sym 5383 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 5384 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 5386 w_rx_fifo_pulled_data[1]
|
|
.sym 5390 w_rx_fifo_pulled_data[3]
|
|
.sym 5397 rx_fifo.rd_addr[9]
|
|
.sym 5398 w_rx_24_fifo_data[0]
|
|
.sym 5399 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 5401 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 5402 $PACKER_VCC_NET
|
|
.sym 5406 $PACKER_VCC_NET
|
|
.sym 5407 rx_fifo.rd_addr_gray[0]
|
|
.sym 5410 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 5412 rx_fifo.rd_addr[4]
|
|
.sym 5413 rx_fifo.wr_addr[6]
|
|
.sym 5414 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 5415 rx_fifo.wr_addr[4]
|
|
.sym 5416 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 5419 rx_fifo.wr_addr[8]
|
|
.sym 5420 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 5427 rx_fifo.wr_addr[1]
|
|
.sym 5429 rx_fifo.wr_addr[4]
|
|
.sym 5431 rx_fifo.wr_addr[7]
|
|
.sym 5435 rx_fifo.wr_addr[6]
|
|
.sym 5437 rx_fifo.wr_addr[5]
|
|
.sym 5438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 5439 rx_fifo.wr_addr[0]
|
|
.sym 5440 rx_fifo.wr_addr[3]
|
|
.sym 5458 $nextpnr_ICESTORM_LC_8$O
|
|
.sym 5461 rx_fifo.wr_addr[0]
|
|
.sym 5464 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 5467 rx_fifo.wr_addr[1]
|
|
.sym 5468 rx_fifo.wr_addr[0]
|
|
.sym 5470 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 5472 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 5474 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 5476 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 5479 rx_fifo.wr_addr[3]
|
|
.sym 5480 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 5482 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 5484 rx_fifo.wr_addr[4]
|
|
.sym 5486 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 5488 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 5490 rx_fifo.wr_addr[5]
|
|
.sym 5492 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 5494 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 5497 rx_fifo.wr_addr[6]
|
|
.sym 5498 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 5500 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 5503 rx_fifo.wr_addr[7]
|
|
.sym 5504 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 5523 rx_fifo.rd_addr[2]
|
|
.sym 5526 rx_fifo.rd_addr[7]
|
|
.sym 5527 rx_fifo.rd_addr[1]
|
|
.sym 5528 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 5529 rx_fifo.rd_addr[3]
|
|
.sym 5530 rx_fifo.rd_addr[0]
|
|
.sym 5532 rx_fifo.rd_addr_gray[8]
|
|
.sym 5534 rx_fifo.rd_addr[5]
|
|
.sym 5535 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5536 rx_fifo.rd_addr[6]
|
|
.sym 5544 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 5551 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 5552 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5553 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5554 rx_fifo.wr_addr[0]
|
|
.sym 5555 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 5556 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 5559 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 5560 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 5561 rx_fifo.wr_addr[9]
|
|
.sym 5562 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 5565 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 5579 rx_fifo.wr_addr[8]
|
|
.sym 5581 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 5583 rx_fifo.wr_addr[8]
|
|
.sym 5585 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 5590 rx_fifo.wr_addr[9]
|
|
.sym 5591 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 5594 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 5596 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 5600 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 5603 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 5606 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5608 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 5614 rx_fifo.wr_addr[0]
|
|
.sym 5620 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5621 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5624 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 5626 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5627 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 5628 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 5629 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 5630 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 5645 rx_fifo.wr_addr[0]
|
|
.sym 5649 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 5651 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 5653 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 5654 w_rx_fifo_full
|
|
.sym 5656 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 5661 $PACKER_VCC_NET
|
|
.sym 5662 $PACKER_VCC_NET
|
|
.sym 5672 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 5673 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 5674 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 5677 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 5678 rx_fifo.rd_addr_gray_wr[8]
|
|
.sym 5679 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 5681 rx_fifo.rd_addr_gray_wr[5]
|
|
.sym 5684 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 5687 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 5688 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 5689 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 5690 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 5692 rx_fifo.rd_addr_gray[8]
|
|
.sym 5693 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 5696 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 5697 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 5700 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 5703 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 5705 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 5706 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 5711 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 5712 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 5713 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 5714 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 5717 rx_fifo.rd_addr_gray_wr[8]
|
|
.sym 5723 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 5724 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 5725 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 5726 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 5729 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 5730 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 5731 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 5732 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 5738 rx_fifo.rd_addr_gray_wr[5]
|
|
.sym 5743 rx_fifo.rd_addr_gray[8]
|
|
.sym 5747 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 5748 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 5749 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 5750 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 5752 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 5766 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 5773 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 5776 rx_fifo.wr_addr[9]
|
|
.sym 5777 rx_fifo.rd_addr_gray_wr[5]
|
|
.sym 5780 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 5786 $PACKER_VCC_NET
|
|
.sym 5789 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O
|
|
.sym 5797 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 5798 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 5799 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E
|
|
.sym 5800 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 5801 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 5803 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 5804 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 5805 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5806 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 5807 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 5808 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 5814 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 5815 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 5819 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 5821 w_lvds_rx_24_d1
|
|
.sym 5826 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 5828 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 5829 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 5831 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 5840 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 5841 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 5842 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 5843 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 5847 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E
|
|
.sym 5852 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 5853 w_lvds_rx_24_d1
|
|
.sym 5854 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 5855 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 5865 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 5866 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 5867 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 5874 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 5875 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 5892 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 5895 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 5896 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 5898 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 5900 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 5919 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 5921 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 5922 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 5926 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 5927 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 5929 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
|
|
.sym 5930 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 5932 $PACKER_VCC_NET
|
|
.sym 5933 $PACKER_VCC_NET
|
|
.sym 5936 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 5941 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 5945 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1]
|
|
.sym 5947 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 5950 $nextpnr_ICESTORM_LC_2$O
|
|
.sym 5952 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 5956 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3
|
|
.sym 5957 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 5958 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 5959 $PACKER_VCC_NET
|
|
.sym 5960 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 5963 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 5964 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 5965 $PACKER_VCC_NET
|
|
.sym 5966 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3
|
|
.sym 5969 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 5970 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 5971 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 5972 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 5978 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 5981 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 5988 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 5989 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 5990 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 5994 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1]
|
|
.sym 5995 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 5997 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_E
|
|
.sym 5998 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 6042 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 6043 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2]
|
|
.sym 6044 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 6050 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 6051 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2]
|
|
.sym 6058 $PACKER_VCC_NET
|
|
.sym 6059 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O
|
|
.sym 6060 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 6062 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3]
|
|
.sym 6063 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 6066 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0]
|
|
.sym 6070 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3]
|
|
.sym 6072 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1]
|
|
.sym 6073 $nextpnr_ICESTORM_LC_0$O
|
|
.sym 6075 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3]
|
|
.sym 6079 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3
|
|
.sym 6080 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 6081 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1]
|
|
.sym 6082 $PACKER_VCC_NET
|
|
.sym 6083 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3]
|
|
.sym 6086 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 6087 $PACKER_VCC_NET
|
|
.sym 6088 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2]
|
|
.sym 6089 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3
|
|
.sym 6092 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 6093 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 6094 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 6095 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 6106 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 6110 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0]
|
|
.sym 6111 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 6112 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 6113 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2]
|
|
.sym 6117 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0]
|
|
.sym 6120 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O
|
|
.sym 6121 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 6122 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 6294 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 6305 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 6346 smi_ctrl_ins.r_fifo_pulled_data[13]
|
|
.sym 6347 smi_ctrl_ins.r_fifo_pulled_data[12]
|
|
.sym 6348 smi_ctrl_ins.r_fifo_pulled_data[7]
|
|
.sym 6349 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 6351 smi_ctrl_ins.r_fifo_pulled_data[15]
|
|
.sym 6352 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 6353 smi_ctrl_ins.r_fifo_pulled_data[14]
|
|
.sym 6390 $PACKER_VCC_NET
|
|
.sym 6391 rx_fifo.wr_addr[5]
|
|
.sym 6393 rx_fifo.wr_addr[7]
|
|
.sym 6395 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 6398 rx_fifo.wr_addr[3]
|
|
.sym 6399 rx_fifo.wr_addr[1]
|
|
.sym 6402 rx_fifo.wr_addr[4]
|
|
.sym 6404 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 6405 rx_fifo.wr_addr[9]
|
|
.sym 6408 rx_fifo.mem_q.0.3_WDATA_3
|
|
.sym 6412 rx_fifo.wr_addr[0]
|
|
.sym 6413 rx_fifo.wr_addr[6]
|
|
.sym 6415 rx_fifo.mem_q.0.3_WDATA_2
|
|
.sym 6417 rx_fifo.wr_addr[8]
|
|
.sym 6422 w_rx_24_fifo_data[23]
|
|
.sym 6423 w_rx_24_fifo_data[20]
|
|
.sym 6424 w_rx_24_fifo_data[25]
|
|
.sym 6425 rx_fifo.wr_addr[9]
|
|
.sym 6426 w_rx_24_fifo_data[31]
|
|
.sym 6427 w_rx_24_fifo_data[27]
|
|
.sym 6428 w_rx_24_fifo_data[29]
|
|
.sym 6429 rx_fifo.mem_i.0.2_WDATA_1
|
|
.sym 6438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 6439 rx_fifo.wr_addr[3]
|
|
.sym 6441 rx_fifo.wr_addr[4]
|
|
.sym 6442 rx_fifo.wr_addr[5]
|
|
.sym 6443 rx_fifo.wr_addr[6]
|
|
.sym 6444 rx_fifo.wr_addr[7]
|
|
.sym 6445 rx_fifo.wr_addr[8]
|
|
.sym 6446 rx_fifo.wr_addr[9]
|
|
.sym 6447 rx_fifo.wr_addr[1]
|
|
.sym 6448 rx_fifo.wr_addr[0]
|
|
.sym 6449 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 6450 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 6452 rx_fifo.mem_q.0.3_WDATA_3
|
|
.sym 6456 rx_fifo.mem_q.0.3_WDATA_2
|
|
.sym 6459 $PACKER_VCC_NET
|
|
.sym 6470 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 6486 w_rx_fifo_pulled_data[7]
|
|
.sym 6502 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 6514 w_smi_data_output[6]
|
|
.sym 6517 smi_ctrl_ins.r_fifo_pulled_data[14]
|
|
.sym 6518 rx_fifo.wr_addr[8]
|
|
.sym 6519 $PACKER_VCC_NET
|
|
.sym 6530 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 6531 rx_fifo.rd_addr[3]
|
|
.sym 6533 rx_fifo.rd_addr[0]
|
|
.sym 6534 rx_fifo.rd_addr[8]
|
|
.sym 6535 rx_fifo.rd_addr[7]
|
|
.sym 6537 rx_fifo.rd_addr[2]
|
|
.sym 6546 rx_fifo.rd_addr[6]
|
|
.sym 6548 rx_fifo.mem_q.0.3_WDATA_1
|
|
.sym 6549 rx_fifo.rd_addr[5]
|
|
.sym 6553 rx_fifo.rd_addr[4]
|
|
.sym 6555 rx_fifo.rd_addr[1]
|
|
.sym 6557 $PACKER_VCC_NET
|
|
.sym 6558 rx_fifo.rd_addr[9]
|
|
.sym 6559 rx_fifo.mem_q.0.3_WDATA
|
|
.sym 6560 rx_fifo.mem_i.0.1_WDATA_3
|
|
.sym 6561 smi_ctrl_ins.r_fifo_pulled_data[18]
|
|
.sym 6562 smi_ctrl_ins.r_fifo_pulled_data[16]
|
|
.sym 6563 smi_ctrl_ins.r_fifo_pulled_data[17]
|
|
.sym 6564 rx_fifo.mem_i.0.1_WDATA
|
|
.sym 6565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
|
|
.sym 6566 smi_ctrl_ins.r_fifo_pulled_data[19]
|
|
.sym 6567 rx_fifo.mem_i.0.1_WDATA_1
|
|
.sym 6576 rx_fifo.rd_addr[2]
|
|
.sym 6577 rx_fifo.rd_addr[3]
|
|
.sym 6579 rx_fifo.rd_addr[4]
|
|
.sym 6580 rx_fifo.rd_addr[5]
|
|
.sym 6581 rx_fifo.rd_addr[6]
|
|
.sym 6582 rx_fifo.rd_addr[7]
|
|
.sym 6583 rx_fifo.rd_addr[8]
|
|
.sym 6584 rx_fifo.rd_addr[9]
|
|
.sym 6585 rx_fifo.rd_addr[1]
|
|
.sym 6586 rx_fifo.rd_addr[0]
|
|
.sym 6587 r_counter_$glb_clk
|
|
.sym 6588 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 6589 $PACKER_VCC_NET
|
|
.sym 6593 rx_fifo.mem_q.0.3_WDATA
|
|
.sym 6597 rx_fifo.mem_q.0.3_WDATA_1
|
|
.sym 6607 rx_fifo.mem_i.0.2_WDATA_1
|
|
.sym 6612 rx_fifo.mem_i.0.2_WDATA
|
|
.sym 6614 rx_fifo.wr_addr[9]
|
|
.sym 6617 rx_fifo.rd_addr[7]
|
|
.sym 6619 smi_ctrl_ins.r_fifo_pulled_data[4]
|
|
.sym 6620 i_rst_b$SB_IO_IN
|
|
.sym 6622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
|
|
.sym 6623 $PACKER_VCC_NET
|
|
.sym 6624 rx_fifo.rd_addr[9]
|
|
.sym 6625 smi_ctrl_ins.r_fifo_pulled_data[24]
|
|
.sym 6630 rx_fifo.wr_addr[4]
|
|
.sym 6631 rx_fifo.wr_addr[9]
|
|
.sym 6632 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 6634 rx_fifo.mem_i.0.0_WDATA_2
|
|
.sym 6636 rx_fifo.mem_i.0.0_WDATA_3
|
|
.sym 6637 rx_fifo.wr_addr[0]
|
|
.sym 6641 rx_fifo.wr_addr[6]
|
|
.sym 6642 rx_fifo.wr_addr[5]
|
|
.sym 6644 rx_fifo.wr_addr[3]
|
|
.sym 6645 rx_fifo.wr_addr[1]
|
|
.sym 6650 $PACKER_VCC_NET
|
|
.sym 6659 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 6660 rx_fifo.wr_addr[7]
|
|
.sym 6661 rx_fifo.wr_addr[8]
|
|
.sym 6662 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
|
|
.sym 6663 w_smi_data_output[0]
|
|
.sym 6664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
|
|
.sym 6665 w_smi_data_output[6]
|
|
.sym 6666 w_smi_data_output[1]
|
|
.sym 6667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
|
|
.sym 6668 w_smi_data_output[3]
|
|
.sym 6669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
|
|
.sym 6678 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 6679 rx_fifo.wr_addr[3]
|
|
.sym 6681 rx_fifo.wr_addr[4]
|
|
.sym 6682 rx_fifo.wr_addr[5]
|
|
.sym 6683 rx_fifo.wr_addr[6]
|
|
.sym 6684 rx_fifo.wr_addr[7]
|
|
.sym 6685 rx_fifo.wr_addr[8]
|
|
.sym 6686 rx_fifo.wr_addr[9]
|
|
.sym 6687 rx_fifo.wr_addr[1]
|
|
.sym 6688 rx_fifo.wr_addr[0]
|
|
.sym 6689 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 6690 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 6692 rx_fifo.mem_i.0.0_WDATA_3
|
|
.sym 6696 rx_fifo.mem_i.0.0_WDATA_2
|
|
.sym 6699 $PACKER_VCC_NET
|
|
.sym 6704 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 6712 w_rx_24_fifo_data[21]
|
|
.sym 6713 rx_fifo.wr_addr[0]
|
|
.sym 6720 rx_fifo.wr_addr[5]
|
|
.sym 6721 smi_ctrl_ins.r_fifo_pulled_data[10]
|
|
.sym 6723 w_rx_fifo_pulled_data[5]
|
|
.sym 6734 rx_fifo.mem_i.0.0_WDATA
|
|
.sym 6737 rx_fifo.rd_addr[5]
|
|
.sym 6738 rx_fifo.rd_addr[1]
|
|
.sym 6743 rx_fifo.rd_addr[6]
|
|
.sym 6744 rx_fifo.rd_addr[0]
|
|
.sym 6746 rx_fifo.rd_addr[3]
|
|
.sym 6747 rx_fifo.rd_addr[2]
|
|
.sym 6748 rx_fifo.rd_addr[4]
|
|
.sym 6750 rx_fifo.rd_addr[8]
|
|
.sym 6755 rx_fifo.rd_addr[7]
|
|
.sym 6759 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 6761 $PACKER_VCC_NET
|
|
.sym 6762 rx_fifo.rd_addr[9]
|
|
.sym 6763 rx_fifo.mem_i.0.0_WDATA_1
|
|
.sym 6764 smi_ctrl_ins.r_fifo_pulled_data[27]
|
|
.sym 6765 smi_ctrl_ins.r_fifo_pulled_data[25]
|
|
.sym 6766 smi_ctrl_ins.r_fifo_pulled_data[4]
|
|
.sym 6767 smi_ctrl_ins.r_fifo_pulled_data[26]
|
|
.sym 6768 smi_ctrl_ins.r_fifo_pulled_data[6]
|
|
.sym 6769 smi_ctrl_ins.r_fifo_pulled_data[24]
|
|
.sym 6771 smi_ctrl_ins.r_fifo_pulled_data[5]
|
|
.sym 6780 rx_fifo.rd_addr[2]
|
|
.sym 6781 rx_fifo.rd_addr[3]
|
|
.sym 6783 rx_fifo.rd_addr[4]
|
|
.sym 6784 rx_fifo.rd_addr[5]
|
|
.sym 6785 rx_fifo.rd_addr[6]
|
|
.sym 6786 rx_fifo.rd_addr[7]
|
|
.sym 6787 rx_fifo.rd_addr[8]
|
|
.sym 6788 rx_fifo.rd_addr[9]
|
|
.sym 6789 rx_fifo.rd_addr[1]
|
|
.sym 6790 rx_fifo.rd_addr[0]
|
|
.sym 6791 r_counter_$glb_clk
|
|
.sym 6792 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 6793 $PACKER_VCC_NET
|
|
.sym 6797 rx_fifo.mem_i.0.0_WDATA
|
|
.sym 6801 rx_fifo.mem_i.0.0_WDATA_1
|
|
.sym 6807 w_smi_data_output[3]
|
|
.sym 6809 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 6813 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 6819 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 6821 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 6825 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 6827 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 6829 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
|
|
.sym 6834 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 6836 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 6837 rx_fifo.wr_addr[3]
|
|
.sym 6838 rx_fifo.mem_i.0.2_WDATA_2
|
|
.sym 6843 rx_fifo.wr_addr[1]
|
|
.sym 6847 $PACKER_VCC_NET
|
|
.sym 6848 rx_fifo.wr_addr[7]
|
|
.sym 6854 rx_fifo.mem_i.0.2_WDATA_3
|
|
.sym 6855 rx_fifo.wr_addr[9]
|
|
.sym 6858 rx_fifo.wr_addr[5]
|
|
.sym 6860 rx_fifo.wr_addr[0]
|
|
.sym 6861 rx_fifo.wr_addr[8]
|
|
.sym 6863 rx_fifo.wr_addr[6]
|
|
.sym 6865 rx_fifo.wr_addr[4]
|
|
.sym 6868 smi_ctrl_ins.r_fifo_pulled_data[10]
|
|
.sym 6882 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 6883 rx_fifo.wr_addr[3]
|
|
.sym 6885 rx_fifo.wr_addr[4]
|
|
.sym 6886 rx_fifo.wr_addr[5]
|
|
.sym 6887 rx_fifo.wr_addr[6]
|
|
.sym 6888 rx_fifo.wr_addr[7]
|
|
.sym 6889 rx_fifo.wr_addr[8]
|
|
.sym 6890 rx_fifo.wr_addr[9]
|
|
.sym 6891 rx_fifo.wr_addr[1]
|
|
.sym 6892 rx_fifo.wr_addr[0]
|
|
.sym 6893 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 6894 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 6896 rx_fifo.mem_i.0.2_WDATA_3
|
|
.sym 6900 rx_fifo.mem_i.0.2_WDATA_2
|
|
.sym 6903 $PACKER_VCC_NET
|
|
.sym 6908 rx_fifo.rd_addr[5]
|
|
.sym 6910 rx_fifo.rd_addr[3]
|
|
.sym 6912 rx_fifo.rd_addr[6]
|
|
.sym 6914 rx_fifo.rd_addr[0]
|
|
.sym 6916 rx_fifo.rd_addr[1]
|
|
.sym 6917 w_rx_fifo_pulled_data[6]
|
|
.sym 6918 w_rx_24_fifo_data[28]
|
|
.sym 6920 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
|
|
.sym 6921 rx_fifo.wr_addr[9]
|
|
.sym 6923 rx_fifo.wr_addr[8]
|
|
.sym 6924 rx_fifo.rd_addr[9]
|
|
.sym 6927 rx_fifo.wr_addr[8]
|
|
.sym 6929 rx_fifo.mem_q.0.2_WDATA_1
|
|
.sym 6936 rx_fifo.rd_addr[8]
|
|
.sym 6938 rx_fifo.mem_i.0.2_WDATA
|
|
.sym 6940 $PACKER_VCC_NET
|
|
.sym 6941 rx_fifo.rd_addr[9]
|
|
.sym 6945 rx_fifo.mem_i.0.2_WDATA_1
|
|
.sym 6948 rx_fifo.rd_addr[7]
|
|
.sym 6950 rx_fifo.rd_addr[3]
|
|
.sym 6951 rx_fifo.rd_addr[2]
|
|
.sym 6952 rx_fifo.rd_addr[1]
|
|
.sym 6957 rx_fifo.rd_addr[5]
|
|
.sym 6961 rx_fifo.rd_addr[4]
|
|
.sym 6963 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 6966 rx_fifo.rd_addr[0]
|
|
.sym 6967 rx_fifo.rd_addr[6]
|
|
.sym 6969 smi_ctrl_ins.r_fifo_pulled_data[9]
|
|
.sym 6970 smi_ctrl_ins.r_fifo_pulled_data[11]
|
|
.sym 6972 smi_ctrl_ins.r_fifo_pulled_data[8]
|
|
.sym 6973 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
|
|
.sym 6974 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
|
|
.sym 6975 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
|
|
.sym 6984 rx_fifo.rd_addr[2]
|
|
.sym 6985 rx_fifo.rd_addr[3]
|
|
.sym 6987 rx_fifo.rd_addr[4]
|
|
.sym 6988 rx_fifo.rd_addr[5]
|
|
.sym 6989 rx_fifo.rd_addr[6]
|
|
.sym 6990 rx_fifo.rd_addr[7]
|
|
.sym 6991 rx_fifo.rd_addr[8]
|
|
.sym 6992 rx_fifo.rd_addr[9]
|
|
.sym 6993 rx_fifo.rd_addr[1]
|
|
.sym 6994 rx_fifo.rd_addr[0]
|
|
.sym 6995 r_counter_$glb_clk
|
|
.sym 6996 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 6997 $PACKER_VCC_NET
|
|
.sym 7001 rx_fifo.mem_i.0.2_WDATA
|
|
.sym 7005 rx_fifo.mem_i.0.2_WDATA_1
|
|
.sym 7011 $PACKER_VCC_NET
|
|
.sym 7015 rx_fifo.wr_addr[3]
|
|
.sym 7017 io_pmod[7]$SB_IO_IN
|
|
.sym 7021 i_rst_b_SB_LUT4_I3_O
|
|
.sym 7022 $PACKER_VCC_NET
|
|
.sym 7024 rx_fifo.rd_addr[7]
|
|
.sym 7026 rx_fifo.wr_addr[9]
|
|
.sym 7027 i_rst_b$SB_IO_IN
|
|
.sym 7028 rx_fifo.rd_addr[3]
|
|
.sym 7029 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
|
|
.sym 7031 rx_fifo.rd_addr[9]
|
|
.sym 7042 $PACKER_VCC_NET
|
|
.sym 7044 rx_fifo.wr_addr[1]
|
|
.sym 7045 rx_fifo.wr_addr[5]
|
|
.sym 7046 rx_fifo.wr_addr[3]
|
|
.sym 7048 rx_fifo.wr_addr[0]
|
|
.sym 7049 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 7051 rx_fifo.wr_addr[6]
|
|
.sym 7053 rx_fifo.wr_addr[4]
|
|
.sym 7059 rx_fifo.wr_addr[9]
|
|
.sym 7060 rx_fifo.mem_q.0.2_WDATA_3
|
|
.sym 7061 rx_fifo.wr_addr[7]
|
|
.sym 7063 rx_fifo.mem_q.0.2_WDATA_2
|
|
.sym 7065 rx_fifo.wr_addr[8]
|
|
.sym 7067 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 7070 smi_ctrl_ins.r_fifo_pulled_data[2]
|
|
.sym 7073 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 7075 smi_ctrl_ins.r_fifo_pulled_data[3]
|
|
.sym 7076 smi_ctrl_ins.r_fifo_pulled_data[1]
|
|
.sym 7077 smi_ctrl_ins.r_fifo_pulled_data[0]
|
|
.sym 7086 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 7087 rx_fifo.wr_addr[3]
|
|
.sym 7089 rx_fifo.wr_addr[4]
|
|
.sym 7090 rx_fifo.wr_addr[5]
|
|
.sym 7091 rx_fifo.wr_addr[6]
|
|
.sym 7092 rx_fifo.wr_addr[7]
|
|
.sym 7093 rx_fifo.wr_addr[8]
|
|
.sym 7094 rx_fifo.wr_addr[9]
|
|
.sym 7095 rx_fifo.wr_addr[1]
|
|
.sym 7096 rx_fifo.wr_addr[0]
|
|
.sym 7097 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 7098 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 7100 rx_fifo.mem_q.0.2_WDATA_3
|
|
.sym 7104 rx_fifo.mem_q.0.2_WDATA_2
|
|
.sym 7107 $PACKER_VCC_NET
|
|
.sym 7115 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7118 $PACKER_VCC_NET
|
|
.sym 7124 rx_fifo.wr_addr[1]
|
|
.sym 7126 w_rx_fifo_pulled_data[1]
|
|
.sym 7128 rx_fifo.wr_addr[5]
|
|
.sym 7130 rx_fifo.wr_addr[3]
|
|
.sym 7134 w_rx_fifo_pulled_data[3]
|
|
.sym 7140 rx_fifo.rd_addr[4]
|
|
.sym 7142 rx_fifo.rd_addr[8]
|
|
.sym 7145 rx_fifo.rd_addr[5]
|
|
.sym 7146 rx_fifo.rd_addr[6]
|
|
.sym 7148 rx_fifo.rd_addr[7]
|
|
.sym 7149 rx_fifo.mem_q.0.2_WDATA
|
|
.sym 7151 rx_fifo.rd_addr[1]
|
|
.sym 7152 rx_fifo.rd_addr[0]
|
|
.sym 7155 rx_fifo.rd_addr[2]
|
|
.sym 7156 rx_fifo.mem_q.0.2_WDATA_1
|
|
.sym 7160 $PACKER_VCC_NET
|
|
.sym 7166 rx_fifo.rd_addr[3]
|
|
.sym 7167 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7168 rx_fifo.rd_addr[9]
|
|
.sym 7172 rx_fifo.rd_addr_gray[0]
|
|
.sym 7173 rx_fifo.rd_addr_gray[8]
|
|
.sym 7174 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 7175 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3]
|
|
.sym 7176 rx_fifo.rd_addr[9]
|
|
.sym 7177 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3]
|
|
.sym 7179 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 7188 rx_fifo.rd_addr[2]
|
|
.sym 7189 rx_fifo.rd_addr[3]
|
|
.sym 7191 rx_fifo.rd_addr[4]
|
|
.sym 7192 rx_fifo.rd_addr[5]
|
|
.sym 7193 rx_fifo.rd_addr[6]
|
|
.sym 7194 rx_fifo.rd_addr[7]
|
|
.sym 7195 rx_fifo.rd_addr[8]
|
|
.sym 7196 rx_fifo.rd_addr[9]
|
|
.sym 7197 rx_fifo.rd_addr[1]
|
|
.sym 7198 rx_fifo.rd_addr[0]
|
|
.sym 7199 r_counter_$glb_clk
|
|
.sym 7200 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7201 $PACKER_VCC_NET
|
|
.sym 7205 rx_fifo.mem_q.0.2_WDATA
|
|
.sym 7209 rx_fifo.mem_q.0.2_WDATA_1
|
|
.sym 7216 rx_fifo.rd_addr[8]
|
|
.sym 7224 rx_fifo.rd_addr[4]
|
|
.sym 7227 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7229 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 7233 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7234 rx_fifo.wr_addr_gray_rd[5]
|
|
.sym 7236 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 7244 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 7248 rx_fifo.mem_q.0.0_WDATA_2
|
|
.sym 7249 rx_fifo.wr_addr[7]
|
|
.sym 7251 rx_fifo.mem_q.0.0_WDATA_3
|
|
.sym 7253 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 7255 $PACKER_VCC_NET
|
|
.sym 7258 rx_fifo.wr_addr[6]
|
|
.sym 7260 rx_fifo.wr_addr[4]
|
|
.sym 7261 rx_fifo.wr_addr[0]
|
|
.sym 7262 rx_fifo.wr_addr[1]
|
|
.sym 7263 rx_fifo.wr_addr[9]
|
|
.sym 7266 rx_fifo.wr_addr[5]
|
|
.sym 7268 rx_fifo.wr_addr[3]
|
|
.sym 7269 rx_fifo.wr_addr[8]
|
|
.sym 7274 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 7275 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 7276 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 7277 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
|
|
.sym 7278 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 7279 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 7280 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0]
|
|
.sym 7281 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 7290 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 7291 rx_fifo.wr_addr[3]
|
|
.sym 7293 rx_fifo.wr_addr[4]
|
|
.sym 7294 rx_fifo.wr_addr[5]
|
|
.sym 7295 rx_fifo.wr_addr[6]
|
|
.sym 7296 rx_fifo.wr_addr[7]
|
|
.sym 7297 rx_fifo.wr_addr[8]
|
|
.sym 7298 rx_fifo.wr_addr[9]
|
|
.sym 7299 rx_fifo.wr_addr[1]
|
|
.sym 7300 rx_fifo.wr_addr[0]
|
|
.sym 7301 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 7302 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 7304 rx_fifo.mem_q.0.0_WDATA_3
|
|
.sym 7308 rx_fifo.mem_q.0.0_WDATA_2
|
|
.sym 7311 $PACKER_VCC_NET
|
|
.sym 7321 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 7322 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 7323 $PACKER_VCC_NET
|
|
.sym 7325 rx_fifo.rd_addr_gray[8]
|
|
.sym 7329 rx_fifo.wr_addr[9]
|
|
.sym 7332 rx_fifo.rd_addr[9]
|
|
.sym 7333 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 7334 rx_fifo.rd_addr[8]
|
|
.sym 7335 rx_fifo.wr_addr[8]
|
|
.sym 7344 rx_fifo.rd_addr[1]
|
|
.sym 7345 rx_fifo.rd_addr[7]
|
|
.sym 7348 $PACKER_VCC_NET
|
|
.sym 7349 rx_fifo.rd_addr[0]
|
|
.sym 7350 rx_fifo.rd_addr[2]
|
|
.sym 7353 rx_fifo.mem_q.0.0_WDATA_1
|
|
.sym 7354 rx_fifo.rd_addr[3]
|
|
.sym 7355 rx_fifo.mem_q.0.0_WDATA
|
|
.sym 7356 rx_fifo.rd_addr[9]
|
|
.sym 7359 rx_fifo.rd_addr[8]
|
|
.sym 7360 rx_fifo.rd_addr[6]
|
|
.sym 7362 rx_fifo.rd_addr[4]
|
|
.sym 7371 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7374 rx_fifo.rd_addr[5]
|
|
.sym 7376 rx_fifo.wr_addr_gray_rd[7]
|
|
.sym 7377 rx_fifo.wr_addr_gray_rd[2]
|
|
.sym 7378 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 7379 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7380 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
|
|
.sym 7381 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
|
|
.sym 7382 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
|
|
.sym 7383 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
|
|
.sym 7392 rx_fifo.rd_addr[2]
|
|
.sym 7393 rx_fifo.rd_addr[3]
|
|
.sym 7395 rx_fifo.rd_addr[4]
|
|
.sym 7396 rx_fifo.rd_addr[5]
|
|
.sym 7397 rx_fifo.rd_addr[6]
|
|
.sym 7398 rx_fifo.rd_addr[7]
|
|
.sym 7399 rx_fifo.rd_addr[8]
|
|
.sym 7400 rx_fifo.rd_addr[9]
|
|
.sym 7401 rx_fifo.rd_addr[1]
|
|
.sym 7402 rx_fifo.rd_addr[0]
|
|
.sym 7403 r_counter_$glb_clk
|
|
.sym 7404 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7405 $PACKER_VCC_NET
|
|
.sym 7409 rx_fifo.mem_q.0.0_WDATA
|
|
.sym 7413 rx_fifo.mem_q.0.0_WDATA_1
|
|
.sym 7418 $PACKER_VCC_NET
|
|
.sym 7420 o_led1$SB_IO_OUT
|
|
.sym 7424 $PACKER_VCC_NET
|
|
.sym 7425 i_rst_b$SB_IO_IN
|
|
.sym 7427 $PACKER_VCC_NET
|
|
.sym 7429 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 7433 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 7434 rx_fifo.wr_addr[9]
|
|
.sym 7435 i_rst_b$SB_IO_IN
|
|
.sym 7439 rx_fifo.wr_addr_gray_rd[4]
|
|
.sym 7440 rx_fifo.wr_addr[8]
|
|
.sym 7441 rx_fifo.wr_addr_gray_rd[6]
|
|
.sym 7478 rx_fifo.wr_addr[9]
|
|
.sym 7479 rx_fifo.wr_addr_gray[4]
|
|
.sym 7480 rx_fifo.wr_addr_gray[8]
|
|
.sym 7481 rx_fifo.wr_addr[8]
|
|
.sym 7482 rx_fifo.wr_addr_gray[3]
|
|
.sym 7483 rx_fifo.wr_addr_gray[7]
|
|
.sym 7484 rx_fifo.wr_addr_gray[6]
|
|
.sym 7485 rx_fifo.wr_addr_gray[2]
|
|
.sym 7516 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 7522 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 7525 $PACKER_VCC_NET
|
|
.sym 7527 i_rst_b$SB_IO_IN
|
|
.sym 7531 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 7532 rx_fifo.wr_addr_gray_rd[3]
|
|
.sym 7534 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7536 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 7541 rx_fifo.wr_addr[9]
|
|
.sym 7581 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 7582 rx_fifo.wr_addr_gray_rd[8]
|
|
.sym 7584 rx_fifo.wr_addr_gray_rd[4]
|
|
.sym 7585 rx_fifo.wr_addr_gray_rd[6]
|
|
.sym 7586 rx_fifo.wr_addr_gray_rd[3]
|
|
.sym 7587 rx_fifo.wr_addr_gray_rd[5]
|
|
.sym 7622 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 7624 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 7625 rx_fifo.wr_addr[8]
|
|
.sym 7628 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 7629 rx_fifo.wr_addr[9]
|
|
.sym 7630 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 7634 w_rx_fifo_full
|
|
.sym 7638 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 7641 rx_fifo.wr_addr_gray_rd[5]
|
|
.sym 7643 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2]
|
|
.sym 7683 rx_fifo.wr_addr_gray[1]
|
|
.sym 7686 rx_fifo.wr_addr_gray[5]
|
|
.sym 7741 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 7788 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2]
|
|
.sym 7789 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
|
|
.sym 7826 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 7830 spi_if_ins.r_tx_byte[2]
|
|
.sym 7838 i_rst_b$SB_IO_IN
|
|
.sym 7888 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 8093 w_smi_data_output[6]
|
|
.sym 8095 o_led0$SB_IO_OUT
|
|
.sym 8099 $PACKER_VCC_NET
|
|
.sym 8107 $PACKER_VCC_NET
|
|
.sym 8109 o_led0$SB_IO_OUT
|
|
.sym 8113 w_smi_data_output[6]
|
|
.sym 8119 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
|
|
.sym 8122 w_smi_data_output[4]
|
|
.sym 8124 w_smi_data_output[7]
|
|
.sym 8133 smi_ctrl_ins.r_fifo_pulled_data[2]
|
|
.sym 8137 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 8142 rx_fifo.wr_addr[9]
|
|
.sym 8151 $PACKER_VCC_NET
|
|
.sym 8152 w_smi_data_input[7]
|
|
.sym 8161 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8165 w_rx_fifo_pulled_data[14]
|
|
.sym 8169 w_rx_fifo_pulled_data[12]
|
|
.sym 8170 w_rx_fifo_pulled_data[7]
|
|
.sym 8172 smi_ctrl_ins.r_fifo_pulled_data[4]
|
|
.sym 8176 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8177 w_rx_fifo_pulled_data[13]
|
|
.sym 8178 smi_ctrl_ins.r_fifo_pulled_data[7]
|
|
.sym 8181 smi_ctrl_ins.r_fifo_pulled_data[15]
|
|
.sym 8185 smi_ctrl_ins.r_fifo_pulled_data[12]
|
|
.sym 8189 w_rx_fifo_pulled_data[15]
|
|
.sym 8194 w_rx_fifo_pulled_data[13]
|
|
.sym 8200 w_rx_fifo_pulled_data[12]
|
|
.sym 8206 w_rx_fifo_pulled_data[7]
|
|
.sym 8211 smi_ctrl_ins.r_fifo_pulled_data[15]
|
|
.sym 8212 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8213 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8214 smi_ctrl_ins.r_fifo_pulled_data[7]
|
|
.sym 8226 w_rx_fifo_pulled_data[15]
|
|
.sym 8229 smi_ctrl_ins.r_fifo_pulled_data[12]
|
|
.sym 8230 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8231 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8232 smi_ctrl_ins.r_fifo_pulled_data[4]
|
|
.sym 8235 w_rx_fifo_pulled_data[14]
|
|
.sym 8239 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 8240 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 8241 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 8246 rx_fifo.mem_i.0.2_WDATA
|
|
.sym 8247 w_rx_09_fifo_data[29]
|
|
.sym 8249 w_rx_09_fifo_data[30]
|
|
.sym 8250 rx_fifo.mem_i.0.3_WDATA_1
|
|
.sym 8251 rx_fifo.mem_i.0.3_WDATA
|
|
.sym 8252 lvds_rx_09_inst.o_fifo_data[31]
|
|
.sym 8253 w_rx_09_fifo_data[27]
|
|
.sym 8264 smi_ctrl_ins.r_fifo_pulled_data[4]
|
|
.sym 8265 $PACKER_VCC_NET
|
|
.sym 8267 i_rst_b$SB_IO_IN
|
|
.sym 8274 o_led1$SB_IO_OUT
|
|
.sym 8278 smi_ctrl_ins.r_fifo_pulled_data[5]
|
|
.sym 8287 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 8292 w_rx_09_fifo_data[25]
|
|
.sym 8294 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 8299 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8303 rx_fifo.mem_i.0.1_WDATA_1
|
|
.sym 8308 smi_ctrl_ins.r_fifo_pulled_data[28]
|
|
.sym 8309 w_smi_data_output[1]
|
|
.sym 8315 w_smi_data_output[2]
|
|
.sym 8323 w_rx_24_fifo_data[23]
|
|
.sym 8332 o_led1$SB_IO_OUT
|
|
.sym 8337 w_rx_24_fifo_data[29]
|
|
.sym 8339 w_rx_24_fifo_data[18]
|
|
.sym 8347 w_rx_09_fifo_data[25]
|
|
.sym 8349 w_rx_24_fifo_data[25]
|
|
.sym 8350 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 8351 rx_fifo.wr_addr[9]
|
|
.sym 8352 w_rx_24_fifo_data[27]
|
|
.sym 8353 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8354 w_rx_24_fifo_data[21]
|
|
.sym 8356 w_rx_24_fifo_data[21]
|
|
.sym 8359 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8362 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8363 w_rx_24_fifo_data[18]
|
|
.sym 8370 w_rx_24_fifo_data[23]
|
|
.sym 8371 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8374 rx_fifo.wr_addr[9]
|
|
.sym 8381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8383 w_rx_24_fifo_data[29]
|
|
.sym 8386 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8388 w_rx_24_fifo_data[25]
|
|
.sym 8394 w_rx_24_fifo_data[27]
|
|
.sym 8395 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 8398 w_rx_09_fifo_data[25]
|
|
.sym 8399 o_led1$SB_IO_OUT
|
|
.sym 8400 w_rx_24_fifo_data[25]
|
|
.sym 8402 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 8403 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 8404 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 8405 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 8406 smi_ctrl_ins.r_fifo_pulled_data[23]
|
|
.sym 8408 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 8410 smi_ctrl_ins.r_fifo_pulled_data[22]
|
|
.sym 8412 smi_ctrl_ins.r_fifo_pulled_data[20]
|
|
.sym 8421 w_rx_fifo_pulled_data[7]
|
|
.sym 8429 w_rx_09_fifo_data[28]
|
|
.sym 8435 i_rst_b$SB_IO_IN
|
|
.sym 8438 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 8439 w_smi_data_output[2]
|
|
.sym 8447 w_rx_fifo_pulled_data[16]
|
|
.sym 8448 smi_ctrl_ins.r_fifo_pulled_data[16]
|
|
.sym 8449 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8451 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8454 w_rx_24_fifo_data[23]
|
|
.sym 8455 w_rx_24_fifo_data[20]
|
|
.sym 8457 w_rx_24_fifo_data[21]
|
|
.sym 8459 w_rx_fifo_pulled_data[18]
|
|
.sym 8464 smi_ctrl_ins.r_fifo_pulled_data[24]
|
|
.sym 8467 w_rx_fifo_pulled_data[19]
|
|
.sym 8469 w_rx_09_fifo_data[20]
|
|
.sym 8471 w_rx_fifo_pulled_data[17]
|
|
.sym 8472 w_rx_09_fifo_data[23]
|
|
.sym 8474 w_rx_09_fifo_data[21]
|
|
.sym 8475 o_led1$SB_IO_OUT
|
|
.sym 8479 o_led1$SB_IO_OUT
|
|
.sym 8480 w_rx_09_fifo_data[20]
|
|
.sym 8481 w_rx_24_fifo_data[20]
|
|
.sym 8488 w_rx_fifo_pulled_data[18]
|
|
.sym 8492 w_rx_fifo_pulled_data[16]
|
|
.sym 8498 w_rx_fifo_pulled_data[17]
|
|
.sym 8503 o_led1$SB_IO_OUT
|
|
.sym 8504 w_rx_24_fifo_data[23]
|
|
.sym 8506 w_rx_09_fifo_data[23]
|
|
.sym 8509 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8510 smi_ctrl_ins.r_fifo_pulled_data[16]
|
|
.sym 8511 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8512 smi_ctrl_ins.r_fifo_pulled_data[24]
|
|
.sym 8518 w_rx_fifo_pulled_data[19]
|
|
.sym 8521 w_rx_09_fifo_data[21]
|
|
.sym 8522 o_led1$SB_IO_OUT
|
|
.sym 8524 w_rx_24_fifo_data[21]
|
|
.sym 8525 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 8526 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 8529 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
|
|
.sym 8530 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
|
|
.sym 8531 w_smi_data_output[2]
|
|
.sym 8532 smi_ctrl_ins.w_fifo_pull_trigger
|
|
.sym 8535 rx_fifo.mem_i.0.3_WDATA_2
|
|
.sym 8537 rx_fifo.wr_addr[8]
|
|
.sym 8538 rx_fifo.wr_addr[8]
|
|
.sym 8540 rx_fifo.mem_i.0.1_WDATA_3
|
|
.sym 8543 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8549 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8552 rx_fifo.rd_addr[0]
|
|
.sym 8554 rx_fifo.rd_addr[1]
|
|
.sym 8555 smi_ctrl_ins.r_fifo_pulled_data[5]
|
|
.sym 8559 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 8560 rx_fifo.rd_addr[7]
|
|
.sym 8561 o_led1$SB_IO_OUT
|
|
.sym 8562 rx_fifo.rd_addr[2]
|
|
.sym 8569 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8570 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
|
|
.sym 8571 i_rst_b$SB_IO_IN
|
|
.sym 8572 smi_ctrl_ins.r_fifo_pulled_data[14]
|
|
.sym 8573 smi_ctrl_ins.r_fifo_pulled_data[6]
|
|
.sym 8575 smi_ctrl_ins.r_fifo_pulled_data[19]
|
|
.sym 8577 smi_ctrl_ins.r_fifo_pulled_data[27]
|
|
.sym 8578 smi_ctrl_ins.r_fifo_pulled_data[25]
|
|
.sym 8580 smi_ctrl_ins.r_fifo_pulled_data[17]
|
|
.sym 8581 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
|
|
.sym 8582 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
|
|
.sym 8583 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8585 smi_ctrl_ins.r_fifo_pulled_data[2]
|
|
.sym 8587 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
|
|
.sym 8590 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8592 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
|
|
.sym 8595 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
|
|
.sym 8597 smi_ctrl_ins.r_fifo_pulled_data[10]
|
|
.sym 8598 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
|
|
.sym 8600 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
|
|
.sym 8602 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8603 smi_ctrl_ins.r_fifo_pulled_data[10]
|
|
.sym 8604 smi_ctrl_ins.r_fifo_pulled_data[2]
|
|
.sym 8605 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8609 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
|
|
.sym 8610 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
|
|
.sym 8614 smi_ctrl_ins.r_fifo_pulled_data[6]
|
|
.sym 8615 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8616 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8617 smi_ctrl_ins.r_fifo_pulled_data[14]
|
|
.sym 8622 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
|
|
.sym 8623 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
|
|
.sym 8628 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
|
|
.sym 8629 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
|
|
.sym 8632 smi_ctrl_ins.r_fifo_pulled_data[27]
|
|
.sym 8633 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8634 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8635 smi_ctrl_ins.r_fifo_pulled_data[19]
|
|
.sym 8638 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
|
|
.sym 8639 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
|
|
.sym 8644 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8645 smi_ctrl_ins.r_fifo_pulled_data[25]
|
|
.sym 8646 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8647 smi_ctrl_ins.r_fifo_pulled_data[17]
|
|
.sym 8648 i_rst_b$SB_IO_IN
|
|
.sym 8649 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 8651 rx_fifo.mem_i.0.3_WDATA_3
|
|
.sym 8652 rx_fifo.rd_addr[3]
|
|
.sym 8653 rx_fifo.rd_addr[7]
|
|
.sym 8654 rx_fifo.rd_addr[2]
|
|
.sym 8655 rx_fifo.rd_addr[5]
|
|
.sym 8656 rx_fifo.rd_addr[6]
|
|
.sym 8657 rx_fifo.rd_addr[0]
|
|
.sym 8658 rx_fifo.rd_addr[1]
|
|
.sym 8664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
|
|
.sym 8667 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 8671 tx_fifo.rd_addr_gray_wr[2]
|
|
.sym 8678 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 8680 smi_ctrl_ins.r_fifo_pulled_data[31]
|
|
.sym 8681 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8684 smi_ctrl_ins.r_fifo_pulled_data[30]
|
|
.sym 8685 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 8686 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 8693 w_rx_fifo_pulled_data[24]
|
|
.sym 8697 w_rx_fifo_pulled_data[26]
|
|
.sym 8701 w_rx_fifo_pulled_data[4]
|
|
.sym 8702 w_rx_fifo_pulled_data[6]
|
|
.sym 8703 w_rx_fifo_pulled_data[5]
|
|
.sym 8713 w_rx_fifo_pulled_data[27]
|
|
.sym 8717 w_rx_fifo_pulled_data[25]
|
|
.sym 8726 w_rx_fifo_pulled_data[27]
|
|
.sym 8732 w_rx_fifo_pulled_data[25]
|
|
.sym 8739 w_rx_fifo_pulled_data[4]
|
|
.sym 8743 w_rx_fifo_pulled_data[26]
|
|
.sym 8750 w_rx_fifo_pulled_data[6]
|
|
.sym 8757 w_rx_fifo_pulled_data[24]
|
|
.sym 8770 w_rx_fifo_pulled_data[5]
|
|
.sym 8771 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 8772 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 8775 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 8776 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 8777 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 8778 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 8779 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 8780 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 8781 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 8787 w_rx_fifo_pulled_data[4]
|
|
.sym 8790 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 8791 $PACKER_VCC_NET
|
|
.sym 8795 rx_fifo.rd_addr[3]
|
|
.sym 8797 rx_fifo.rd_addr[7]
|
|
.sym 8799 rx_fifo.rd_addr[4]
|
|
.sym 8800 smi_ctrl_ins.r_fifo_pulled_data[28]
|
|
.sym 8801 rx_fifo.rd_addr[8]
|
|
.sym 8804 rx_fifo.rd_addr[6]
|
|
.sym 8806 w_rx_fifo_pulled_data[21]
|
|
.sym 8836 w_rx_fifo_pulled_data[10]
|
|
.sym 8863 w_rx_fifo_pulled_data[10]
|
|
.sym 8894 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 8895 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 8896 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 8897 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 8898 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 8899 smi_ctrl_ins.r_fifo_pulled_data[31]
|
|
.sym 8900 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
|
|
.sym 8901 smi_ctrl_ins.r_fifo_pulled_data[30]
|
|
.sym 8902 smi_ctrl_ins.r_fifo_pulled_data[21]
|
|
.sym 8903 smi_ctrl_ins.r_fifo_pulled_data[29]
|
|
.sym 8904 smi_ctrl_ins.r_fifo_pulled_data[28]
|
|
.sym 8917 w_rx_fifo_pulled_data[5]
|
|
.sym 8921 rx_fifo.wr_addr[8]
|
|
.sym 8923 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 8924 rx_fifo.rd_addr[5]
|
|
.sym 8925 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 8926 rx_fifo.rd_addr[6]
|
|
.sym 8927 i_rst_b$SB_IO_IN
|
|
.sym 8929 rx_fifo.rd_addr[9]
|
|
.sym 8930 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 8931 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 8932 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 8939 w_rx_fifo_pulled_data[8]
|
|
.sym 8943 smi_ctrl_ins.r_fifo_pulled_data[3]
|
|
.sym 8945 smi_ctrl_ins.r_fifo_pulled_data[0]
|
|
.sym 8948 smi_ctrl_ins.r_fifo_pulled_data[11]
|
|
.sym 8949 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 8952 smi_ctrl_ins.r_fifo_pulled_data[1]
|
|
.sym 8953 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 8955 smi_ctrl_ins.r_fifo_pulled_data[9]
|
|
.sym 8959 w_rx_fifo_pulled_data[11]
|
|
.sym 8963 w_rx_fifo_pulled_data[9]
|
|
.sym 8966 smi_ctrl_ins.r_fifo_pulled_data[8]
|
|
.sym 8978 w_rx_fifo_pulled_data[9]
|
|
.sym 8984 w_rx_fifo_pulled_data[11]
|
|
.sym 8996 w_rx_fifo_pulled_data[8]
|
|
.sym 9001 smi_ctrl_ins.r_fifo_pulled_data[1]
|
|
.sym 9002 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 9003 smi_ctrl_ins.r_fifo_pulled_data[9]
|
|
.sym 9004 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 9007 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 9008 smi_ctrl_ins.r_fifo_pulled_data[11]
|
|
.sym 9009 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 9010 smi_ctrl_ins.r_fifo_pulled_data[3]
|
|
.sym 9013 smi_ctrl_ins.r_fifo_pulled_data[8]
|
|
.sym 9014 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 9015 smi_ctrl_ins.r_fifo_pulled_data[0]
|
|
.sym 9016 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 9017 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 9018 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 9019 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 9020 rx_fifo.rd_addr[4]
|
|
.sym 9021 rx_fifo.rd_addr[8]
|
|
.sym 9022 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 9023 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 9024 rx_fifo.rd_addr_gray[4]
|
|
.sym 9025 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 9026 rx_fifo.rd_addr_gray[5]
|
|
.sym 9027 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
|
|
.sym 9036 w_rx_fifo_pulled_data[30]
|
|
.sym 9037 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 9039 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9040 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 9041 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 9044 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 9046 rx_fifo.rd_addr[1]
|
|
.sym 9048 rx_fifo.rd_addr[7]
|
|
.sym 9051 rx_fifo.rd_addr[1]
|
|
.sym 9052 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 9053 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 9054 rx_fifo.rd_addr[2]
|
|
.sym 9055 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 9062 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 9078 w_rx_fifo_pulled_data[0]
|
|
.sym 9080 w_rx_fifo_pulled_data[1]
|
|
.sym 9082 w_rx_fifo_pulled_data[2]
|
|
.sym 9088 w_rx_fifo_pulled_data[3]
|
|
.sym 9095 w_rx_fifo_pulled_data[2]
|
|
.sym 9114 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 9125 w_rx_fifo_pulled_data[3]
|
|
.sym 9133 w_rx_fifo_pulled_data[1]
|
|
.sym 9138 w_rx_fifo_pulled_data[0]
|
|
.sym 9140 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 9141 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 9142 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 9143 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3]
|
|
.sym 9144 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 9145 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 9146 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3]
|
|
.sym 9147 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 9148 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3]
|
|
.sym 9149 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
|
|
.sym 9150 w_rx_fifo_empty
|
|
.sym 9162 rx_fifo.rd_addr[4]
|
|
.sym 9164 rx_fifo.rd_addr[8]
|
|
.sym 9168 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9170 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 9171 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 9172 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 9173 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 9174 w_rx_fifo_empty
|
|
.sym 9177 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 9184 rx_fifo.rd_addr[4]
|
|
.sym 9185 rx_fifo.rd_addr[8]
|
|
.sym 9186 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 9187 rx_fifo.rd_addr[7]
|
|
.sym 9188 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 9193 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9194 rx_fifo.rd_addr[5]
|
|
.sym 9195 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 9196 rx_fifo.rd_addr[6]
|
|
.sym 9197 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3]
|
|
.sym 9199 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 9200 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9202 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 9203 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3]
|
|
.sym 9206 rx_fifo.rd_addr[1]
|
|
.sym 9211 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 9212 rx_fifo.rd_addr[9]
|
|
.sym 9219 rx_fifo.rd_addr[1]
|
|
.sym 9224 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9226 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 9229 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 9230 rx_fifo.rd_addr[7]
|
|
.sym 9231 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3]
|
|
.sym 9232 rx_fifo.rd_addr[6]
|
|
.sym 9235 rx_fifo.rd_addr[8]
|
|
.sym 9236 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 9237 rx_fifo.rd_addr[9]
|
|
.sym 9238 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9241 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 9249 rx_fifo.rd_addr[5]
|
|
.sym 9250 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 9259 rx_fifo.rd_addr[5]
|
|
.sym 9260 rx_fifo.rd_addr[4]
|
|
.sym 9261 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3]
|
|
.sym 9262 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 9263 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 9264 r_counter_$glb_clk
|
|
.sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 9266 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
|
|
.sym 9267 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
|
|
.sym 9268 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
|
|
.sym 9269 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
|
|
.sym 9270 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
|
|
.sym 9271 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0]
|
|
.sym 9272 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 9273 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
|
|
.sym 9280 rx_fifo.wr_addr[9]
|
|
.sym 9283 w_rx_fifo_empty
|
|
.sym 9288 $PACKER_VCC_NET
|
|
.sym 9290 rx_fifo.wr_addr[9]
|
|
.sym 9292 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 9294 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 9295 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 9296 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 9298 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 9301 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 9307 i_rst_b$SB_IO_IN
|
|
.sym 9308 rx_fifo.wr_addr_gray_rd[2]
|
|
.sym 9311 rx_fifo.wr_addr_gray_rd[5]
|
|
.sym 9313 rx_fifo.wr_addr_gray_rd[3]
|
|
.sym 9315 rx_fifo.wr_addr_gray_rd[7]
|
|
.sym 9320 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 9321 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9330 rx_fifo.wr_addr_gray_rd[6]
|
|
.sym 9331 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 9334 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
|
|
.sym 9336 rx_fifo.wr_addr_gray_rd[4]
|
|
.sym 9338 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 9340 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 9342 i_rst_b$SB_IO_IN
|
|
.sym 9346 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9347 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 9348 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 9349 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
|
|
.sym 9353 rx_fifo.wr_addr_gray_rd[6]
|
|
.sym 9358 rx_fifo.wr_addr_gray_rd[7]
|
|
.sym 9364 rx_fifo.wr_addr_gray_rd[5]
|
|
.sym 9373 rx_fifo.wr_addr_gray_rd[3]
|
|
.sym 9377 rx_fifo.wr_addr_gray_rd[2]
|
|
.sym 9383 rx_fifo.wr_addr_gray_rd[4]
|
|
.sym 9387 r_counter_$glb_clk
|
|
.sym 9389 rx_fifo.rd_addr_gray[6]
|
|
.sym 9390 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.sym 9391 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 9392 rx_fifo.rd_addr_gray[2]
|
|
.sym 9393 rx_fifo.rd_addr_gray[3]
|
|
.sym 9394 rx_fifo.rd_addr_gray[1]
|
|
.sym 9395 rx_fifo.rd_addr_gray[7]
|
|
.sym 9409 rx_fifo.wr_addr_gray_rd[3]
|
|
.sym 9413 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 9415 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 9418 i_rst_b$SB_IO_IN
|
|
.sym 9422 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 9423 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 9424 rx_fifo.wr_addr[8]
|
|
.sym 9435 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
|
|
.sym 9437 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9438 i_rst_b$SB_IO_IN
|
|
.sym 9439 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 9443 rx_fifo.wr_addr_gray[7]
|
|
.sym 9445 rx_fifo.wr_addr_gray[2]
|
|
.sym 9446 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9448 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 9450 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 9451 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3]
|
|
.sym 9452 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 9454 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 9456 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 9458 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 9459 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 9460 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 9461 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
|
|
.sym 9465 rx_fifo.wr_addr_gray[7]
|
|
.sym 9472 rx_fifo.wr_addr_gray[2]
|
|
.sym 9475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 9476 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9477 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9481 i_rst_b$SB_IO_IN
|
|
.sym 9483 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 9487 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 9488 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3]
|
|
.sym 9489 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 9490 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 9495 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 9496 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 9499 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 9500 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 9501 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
|
|
.sym 9502 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
|
|
.sym 9506 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 9507 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 9510 r_counter_$glb_clk
|
|
.sym 9513 rx_fifo.rd_addr_gray_wr[6]
|
|
.sym 9514 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 9515 rx_fifo.rd_addr_gray_wr[0]
|
|
.sym 9516 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 9517 rx_fifo.rd_addr_gray_wr[3]
|
|
.sym 9518 rx_fifo.rd_addr_gray_wr[5]
|
|
.sym 9525 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.sym 9527 $PACKER_VCC_NET
|
|
.sym 9534 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2]
|
|
.sym 9535 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 9536 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 9537 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 9538 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 9539 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 9542 rx_fifo.rd_addr_gray[1]
|
|
.sym 9543 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 9544 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 9545 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 9546 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9553 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9554 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 9556 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 9564 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 9566 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 9568 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9569 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 9570 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 9577 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 9589 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 9595 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 9600 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9601 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 9605 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 9610 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 9616 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 9623 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 9629 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 9630 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 9632 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 9633 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 9634 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 9636 rx_fifo.rd_addr_gray_wr[4]
|
|
.sym 9637 rx_fifo.rd_addr_gray_wr[2]
|
|
.sym 9638 rx_fifo.rd_addr_gray_wr[1]
|
|
.sym 9639 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 9641 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 9642 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 9660 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 9664 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 9678 rx_fifo.wr_addr_gray[8]
|
|
.sym 9680 rx_fifo.wr_addr_gray[3]
|
|
.sym 9682 rx_fifo.wr_addr_gray[6]
|
|
.sym 9685 rx_fifo.wr_addr_gray[4]
|
|
.sym 9688 rx_fifo.wr_addr_gray[5]
|
|
.sym 9702 rx_fifo.wr_addr_gray_rd[8]
|
|
.sym 9717 rx_fifo.wr_addr_gray_rd[8]
|
|
.sym 9723 rx_fifo.wr_addr_gray[8]
|
|
.sym 9733 rx_fifo.wr_addr_gray[4]
|
|
.sym 9742 rx_fifo.wr_addr_gray[6]
|
|
.sym 9745 rx_fifo.wr_addr_gray[3]
|
|
.sym 9751 rx_fifo.wr_addr_gray[5]
|
|
.sym 9756 r_counter_$glb_clk
|
|
.sym 9763 spi_if_ins.r_tx_byte[2]
|
|
.sym 9782 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 9810 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 9812 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 9824 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 9841 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 9858 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 9878 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 9879 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 9880 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 9884 rx_fifo.wr_addr_gray_rd[1]
|
|
.sym 9887 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 9889 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 9892 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 9905 i_rst_b$SB_IO_IN
|
|
.sym 9914 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 9924 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
|
|
.sym 9931 w_rx_fifo_full
|
|
.sym 9941 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 9942 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 9945 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 9979 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 9980 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 9981 w_rx_fifo_full
|
|
.sym 9985 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 9987 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 10001 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
|
|
.sym 10002 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 10003 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 10004 rx_fifo.rd_addr_gray_wr[7]
|
|
.sym 10006 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.sym 10018 rx_fifo.full_o_SB_LUT4_I1_O_SB_DFFER_D_E
|
|
.sym 10069 rx_fifo.rd_addr_gray_wr[7]
|
|
.sym 10091 rx_fifo.rd_addr_gray_wr[7]
|
|
.sym 10125 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 10150 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 10172 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 10192 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 10197 i_rst_b$SB_IO_IN
|
|
.sym 10201 w_smi_data_output[2]
|
|
.sym 10203 o_led0$SB_IO_OUT
|
|
.sym 10204 w_smi_data_output[1]
|
|
.sym 10206 o_led0$SB_IO_OUT
|
|
.sym 10207 $PACKER_VCC_NET
|
|
.sym 10213 o_led0$SB_IO_OUT
|
|
.sym 10221 o_led0$SB_IO_OUT
|
|
.sym 10222 w_smi_data_output[1]
|
|
.sym 10223 $PACKER_VCC_NET
|
|
.sym 10225 w_smi_data_output[2]
|
|
.sym 10228 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.sym 10231 w_smi_data_output[5]
|
|
.sym 10261 o_led0$SB_IO_OUT
|
|
.sym 10268 smi_ctrl_ins.r_fifo_pulled_data[5]
|
|
.sym 10270 i_rst_b$SB_IO_IN
|
|
.sym 10271 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 10274 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 10276 smi_ctrl_ins.r_fifo_pulled_data[13]
|
|
.sym 10283 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10284 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 10290 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 10296 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10307 smi_ctrl_ins.r_fifo_pulled_data[13]
|
|
.sym 10308 smi_ctrl_ins.r_fifo_pulled_data[5]
|
|
.sym 10309 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10310 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10325 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 10327 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 10337 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 10340 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 10347 i_rst_b$SB_IO_IN
|
|
.sym 10348 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 10352 w_smi_data_input[7]
|
|
.sym 10354 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 10355 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 10356 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 10357 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 10358 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 10359 tx_fifo.rd_addr[0]
|
|
.sym 10360 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 10361 tx_fifo.rd_addr[1]
|
|
.sym 10364 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 10365 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 10376 w_smi_data_output[4]
|
|
.sym 10380 $PACKER_VCC_NET
|
|
.sym 10381 smi_ctrl_ins.soe_and_reset
|
|
.sym 10386 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 10403 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10405 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
|
|
.sym 10408 w_smi_data_input[7]
|
|
.sym 10412 w_smi_data_input[7]
|
|
.sym 10414 w_smi_data_output[0]
|
|
.sym 10416 w_rx_fifo_pulled_data[23]
|
|
.sym 10431 w_rx_09_fifo_data[25]
|
|
.sym 10435 w_rx_24_fifo_data[31]
|
|
.sym 10437 w_rx_24_fifo_data[29]
|
|
.sym 10439 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 10440 w_rx_09_fifo_data[29]
|
|
.sym 10443 o_led1$SB_IO_OUT
|
|
.sym 10444 w_rx_24_fifo_data[27]
|
|
.sym 10451 w_rx_09_fifo_data[28]
|
|
.sym 10453 lvds_rx_09_inst.o_fifo_data[31]
|
|
.sym 10454 w_rx_09_fifo_data[27]
|
|
.sym 10465 w_rx_09_fifo_data[27]
|
|
.sym 10466 w_rx_24_fifo_data[27]
|
|
.sym 10467 o_led1$SB_IO_OUT
|
|
.sym 10470 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 10472 w_rx_09_fifo_data[27]
|
|
.sym 10482 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 10483 w_rx_09_fifo_data[28]
|
|
.sym 10488 w_rx_24_fifo_data[29]
|
|
.sym 10489 o_led1$SB_IO_OUT
|
|
.sym 10490 w_rx_09_fifo_data[29]
|
|
.sym 10494 o_led1$SB_IO_OUT
|
|
.sym 10495 lvds_rx_09_inst.o_fifo_data[31]
|
|
.sym 10497 w_rx_24_fifo_data[31]
|
|
.sym 10502 w_rx_09_fifo_data[29]
|
|
.sym 10503 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 10506 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 10507 w_rx_09_fifo_data[25]
|
|
.sym 10510 w_lvds_rx_09_d0_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
|
|
.sym 10511 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 10512 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr
|
|
.sym 10513 tx_fifo.empty_o_SB_LUT4_I0_O[3]
|
|
.sym 10514 tx_fifo.rd_addr_gray[3]
|
|
.sym 10515 tx_fifo.rd_addr_gray[2]
|
|
.sym 10516 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 10518 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
|
|
.sym 10519 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 10520 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 10524 rx_fifo.rd_addr_gray[5]
|
|
.sym 10529 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 10530 tx_fifo.rd_addr[1]
|
|
.sym 10531 o_led1$SB_IO_OUT
|
|
.sym 10535 o_led1$SB_IO_OUT
|
|
.sym 10539 rx_fifo.rd_addr[3]
|
|
.sym 10540 w_rx_09_fifo_data[30]
|
|
.sym 10542 rx_fifo.mem_i.0.3_WDATA_1
|
|
.sym 10543 $PACKER_VCC_NET
|
|
.sym 10544 rx_fifo.mem_i.0.3_WDATA
|
|
.sym 10545 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 10548 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 10555 w_rx_fifo_pulled_data[22]
|
|
.sym 10558 smi_ctrl_ins.r_fifo_pulled_data[31]
|
|
.sym 10560 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10561 smi_ctrl_ins.r_fifo_pulled_data[20]
|
|
.sym 10563 w_rx_fifo_pulled_data[20]
|
|
.sym 10564 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10565 smi_ctrl_ins.r_fifo_pulled_data[28]
|
|
.sym 10571 smi_ctrl_ins.r_fifo_pulled_data[23]
|
|
.sym 10581 w_rx_fifo_pulled_data[23]
|
|
.sym 10587 smi_ctrl_ins.r_fifo_pulled_data[28]
|
|
.sym 10588 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10589 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10590 smi_ctrl_ins.r_fifo_pulled_data[20]
|
|
.sym 10594 w_rx_fifo_pulled_data[23]
|
|
.sym 10605 smi_ctrl_ins.r_fifo_pulled_data[23]
|
|
.sym 10606 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10607 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10608 smi_ctrl_ins.r_fifo_pulled_data[31]
|
|
.sym 10617 w_rx_fifo_pulled_data[22]
|
|
.sym 10630 w_rx_fifo_pulled_data[20]
|
|
.sym 10633 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 10634 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 10635 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 10636 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 10637 tx_fifo.rd_addr_gray_wr[3]
|
|
.sym 10638 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
|
|
.sym 10639 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
|
|
.sym 10641 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 10643 tx_fifo.rd_addr_gray_wr[2]
|
|
.sym 10645 w_rx_fifo_pulled_data[20]
|
|
.sym 10653 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 10654 smi_ctrl_ins.r_fifo_pulled_data[31]
|
|
.sym 10659 o_led1$SB_IO_OUT
|
|
.sym 10660 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 10661 rx_fifo.rd_addr[0]
|
|
.sym 10662 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 10663 rx_fifo.rd_addr[1]
|
|
.sym 10665 w_tx_fifo_pull
|
|
.sym 10666 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
|
|
.sym 10667 rx_fifo.rd_addr[3]
|
|
.sym 10669 rx_fifo.rd_addr[7]
|
|
.sym 10670 rx_fifo.rd_addr[8]
|
|
.sym 10671 rx_fifo.rd_addr[2]
|
|
.sym 10677 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
|
|
.sym 10679 i_rst_b$SB_IO_IN
|
|
.sym 10689 w_rx_24_fifo_data[30]
|
|
.sym 10690 smi_ctrl_ins.r_fifo_pulled_data[22]
|
|
.sym 10693 o_led1$SB_IO_OUT
|
|
.sym 10694 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
|
|
.sym 10696 smi_ctrl_ins.r_fifo_pulled_data[26]
|
|
.sym 10698 smi_ctrl_ins.r_fifo_pulled_data[30]
|
|
.sym 10700 w_rx_09_fifo_data[30]
|
|
.sym 10702 smi_ctrl_ins.r_fifo_pulled_data[18]
|
|
.sym 10703 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10704 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10716 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10717 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10718 smi_ctrl_ins.r_fifo_pulled_data[26]
|
|
.sym 10719 smi_ctrl_ins.r_fifo_pulled_data[18]
|
|
.sym 10722 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10723 smi_ctrl_ins.r_fifo_pulled_data[30]
|
|
.sym 10724 smi_ctrl_ins.r_fifo_pulled_data[22]
|
|
.sym 10725 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10729 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
|
|
.sym 10730 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
|
|
.sym 10735 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 10736 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10752 w_rx_24_fifo_data[30]
|
|
.sym 10754 w_rx_09_fifo_data[30]
|
|
.sym 10755 o_led1$SB_IO_OUT
|
|
.sym 10756 i_rst_b$SB_IO_IN
|
|
.sym 10757 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 10760 tx_fifo.empty_o_SB_LUT4_I0_O[2]
|
|
.sym 10761 w_tx_fifo_empty
|
|
.sym 10762 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 10763 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1]
|
|
.sym 10764 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 10765 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 10766 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 10773 o_led1$SB_IO_OUT
|
|
.sym 10775 rx_fifo.mem_i.0.1_WDATA_1
|
|
.sym 10776 w_rx_fifo_pulled_data[21]
|
|
.sym 10777 w_rx_24_fifo_data[30]
|
|
.sym 10778 rx_fifo.rd_addr[4]
|
|
.sym 10783 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 10788 smi_ctrl_ins.w_fifo_pull_trigger
|
|
.sym 10790 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
|
|
.sym 10791 rx_fifo.mem_i.0.3_WDATA_3
|
|
.sym 10793 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 10794 rx_fifo.mem_i.0.3_WDATA_2
|
|
.sym 10801 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 10802 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 10803 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 10805 o_led1$SB_IO_OUT
|
|
.sym 10811 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 10812 w_rx_09_fifo_data[28]
|
|
.sym 10813 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 10814 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 10815 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 10816 w_rx_24_fifo_data[28]
|
|
.sym 10830 rx_fifo.rd_addr[0]
|
|
.sym 10833 w_rx_24_fifo_data[28]
|
|
.sym 10834 o_led1$SB_IO_OUT
|
|
.sym 10836 w_rx_09_fifo_data[28]
|
|
.sym 10839 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 10847 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 10852 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 10857 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 10863 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 10870 rx_fifo.rd_addr[0]
|
|
.sym 10877 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 10879 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 10880 r_counter_$glb_clk
|
|
.sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 10884 w_tx_fifo_pull
|
|
.sym 10885 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
|
|
.sym 10886 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 10888 i_rst_b_SB_LUT4_I3_O
|
|
.sym 10893 rx_fifo.rd_addr_gray[7]
|
|
.sym 10895 rx_fifo.wr_addr[8]
|
|
.sym 10896 rx_fifo.rd_addr[6]
|
|
.sym 10900 w_rx_09_fifo_data[28]
|
|
.sym 10904 rx_fifo.rd_addr[5]
|
|
.sym 10906 w_rx_fifo_pulled_data[31]
|
|
.sym 10907 rx_fifo.rd_addr[7]
|
|
.sym 10908 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 10909 rx_fifo.rd_addr[2]
|
|
.sym 10910 w_rx_fifo_pulled_data[29]
|
|
.sym 10911 rx_fifo.rd_addr[5]
|
|
.sym 10913 rx_fifo.rd_addr[6]
|
|
.sym 10915 rx_fifo.rd_addr[0]
|
|
.sym 10916 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 10917 rx_fifo.rd_addr[1]
|
|
.sym 10924 rx_fifo.rd_addr[3]
|
|
.sym 10925 rx_fifo.rd_addr[7]
|
|
.sym 10929 rx_fifo.rd_addr[0]
|
|
.sym 10934 rx_fifo.rd_addr[2]
|
|
.sym 10935 rx_fifo.rd_addr[5]
|
|
.sym 10936 rx_fifo.rd_addr[6]
|
|
.sym 10938 rx_fifo.rd_addr[1]
|
|
.sym 10947 rx_fifo.rd_addr[4]
|
|
.sym 10955 $nextpnr_ICESTORM_LC_5$O
|
|
.sym 10958 rx_fifo.rd_addr[0]
|
|
.sym 10961 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 10963 rx_fifo.rd_addr[1]
|
|
.sym 10965 rx_fifo.rd_addr[0]
|
|
.sym 10967 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 10970 rx_fifo.rd_addr[2]
|
|
.sym 10971 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 10973 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 10976 rx_fifo.rd_addr[3]
|
|
.sym 10977 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 10979 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 10981 rx_fifo.rd_addr[4]
|
|
.sym 10983 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 10985 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 10988 rx_fifo.rd_addr[5]
|
|
.sym 10989 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 10991 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 10994 rx_fifo.rd_addr[6]
|
|
.sym 10995 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 10997 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 10999 rx_fifo.rd_addr[7]
|
|
.sym 11001 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 11005 smi_ctrl_ins.r_fifo_pull
|
|
.sym 11006 smi_ctrl_ins.r_fifo_pull_1
|
|
.sym 11007 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 11008 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
|
|
.sym 11012 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 11018 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 11021 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 11022 rx_fifo.rd_addr[7]
|
|
.sym 11023 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 11026 rx_fifo.rd_addr[0]
|
|
.sym 11027 o_led1$SB_IO_OUT
|
|
.sym 11028 rx_fifo.rd_addr[1]
|
|
.sym 11030 $PACKER_VCC_NET
|
|
.sym 11032 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 11035 $PACKER_VCC_NET
|
|
.sym 11036 rx_fifo.rd_addr[3]
|
|
.sym 11038 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 11039 w_tx_data_smi[2]
|
|
.sym 11041 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 11047 rx_fifo.rd_addr[8]
|
|
.sym 11050 w_rx_fifo_pulled_data[21]
|
|
.sym 11053 w_rx_fifo_pulled_data[30]
|
|
.sym 11055 w_rx_fifo_pulled_data[28]
|
|
.sym 11058 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 11059 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 11063 rx_fifo.rd_addr[9]
|
|
.sym 11066 w_rx_fifo_pulled_data[31]
|
|
.sym 11070 w_rx_fifo_pulled_data[29]
|
|
.sym 11078 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 11080 rx_fifo.rd_addr[8]
|
|
.sym 11082 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 11085 rx_fifo.rd_addr[9]
|
|
.sym 11088 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 11093 w_rx_fifo_pulled_data[31]
|
|
.sym 11097 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 11098 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 11106 w_rx_fifo_pulled_data[30]
|
|
.sym 11112 w_rx_fifo_pulled_data[21]
|
|
.sym 11116 w_rx_fifo_pulled_data[29]
|
|
.sym 11124 w_rx_fifo_pulled_data[28]
|
|
.sym 11125 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E_$glb_ce
|
|
.sym 11126 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 11127 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 11128 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 11129 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2]
|
|
.sym 11130 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1]
|
|
.sym 11131 w_tx_data_smi[2]
|
|
.sym 11133 w_tx_data_smi[1]
|
|
.sym 11134 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2]
|
|
.sym 11135 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3]
|
|
.sym 11137 w_rx_fifo_pulled_data[28]
|
|
.sym 11140 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 11144 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 11145 rx_fifo.wr_addr[4]
|
|
.sym 11148 w_rx_fifo_empty
|
|
.sym 11149 o_led1$SB_IO_OUT
|
|
.sym 11152 rx_fifo.rd_addr_gray[4]
|
|
.sym 11155 rx_fifo.rd_addr[3]
|
|
.sym 11156 rx_fifo.rd_addr[1]
|
|
.sym 11157 rx_fifo.rd_addr[7]
|
|
.sym 11159 rx_fifo.rd_addr[2]
|
|
.sym 11160 rx_fifo.rd_addr[4]
|
|
.sym 11161 rx_fifo.rd_addr[0]
|
|
.sym 11162 rx_fifo.rd_addr[8]
|
|
.sym 11169 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 11170 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 11171 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 11172 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
|
|
.sym 11177 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 11179 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 11180 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 11182 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 11184 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 11187 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 11188 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 11193 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 11194 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 11196 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 11200 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 11205 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 11209 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 11216 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 11217 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
|
|
.sym 11221 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 11223 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 11229 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
|
|
.sym 11232 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 11233 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 11234 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 11235 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 11240 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 11244 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 11245 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 11246 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 11247 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 11248 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 11249 r_counter_$glb_clk
|
|
.sym 11250 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 11251 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
|
|
.sym 11252 spi_if_ins.state_if[1]
|
|
.sym 11253 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 11254 spi_if_ins.state_if[0]
|
|
.sym 11255 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 11256 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 11257 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 11258 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 11264 rx_fifo.rd_addr[6]
|
|
.sym 11265 o_led1$SB_IO_OUT
|
|
.sym 11267 rx_fifo.rd_addr[8]
|
|
.sym 11268 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 11272 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 11274 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 11275 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 11276 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 11279 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 11281 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 11282 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 11283 w_rx_fifo_full
|
|
.sym 11285 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 11286 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 11292 rx_fifo.rd_addr[7]
|
|
.sym 11293 rx_fifo.rd_addr[8]
|
|
.sym 11294 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 11295 rx_fifo.rd_addr[1]
|
|
.sym 11298 rx_fifo.rd_addr[2]
|
|
.sym 11299 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 11300 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3]
|
|
.sym 11301 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
|
|
.sym 11302 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 11303 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 11304 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
|
|
.sym 11305 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 11306 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2]
|
|
.sym 11307 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
|
|
.sym 11308 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 11309 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 11310 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 11311 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3]
|
|
.sym 11312 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 11313 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 11314 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0]
|
|
.sym 11315 rx_fifo.rd_addr[3]
|
|
.sym 11317 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 11319 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
|
|
.sym 11321 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3]
|
|
.sym 11322 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
|
|
.sym 11325 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
|
|
.sym 11326 rx_fifo.rd_addr[8]
|
|
.sym 11327 rx_fifo.rd_addr[7]
|
|
.sym 11333 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 11334 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 11337 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 11338 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 11339 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 11340 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 11343 rx_fifo.rd_addr[1]
|
|
.sym 11344 rx_fifo.rd_addr[2]
|
|
.sym 11345 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3]
|
|
.sym 11346 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 11349 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 11351 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 11355 rx_fifo.rd_addr[3]
|
|
.sym 11356 rx_fifo.rd_addr[2]
|
|
.sym 11357 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3]
|
|
.sym 11358 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0]
|
|
.sym 11361 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 11362 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2]
|
|
.sym 11363 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3]
|
|
.sym 11364 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 11367 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
|
|
.sym 11368 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
|
|
.sym 11369 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
|
|
.sym 11370 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
|
|
.sym 11372 r_counter_$glb_clk
|
|
.sym 11373 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 11374 spi_if_ins.r_tx_data_valid
|
|
.sym 11375 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 11376 spi_if_ins.state_if_SB_DFFESR_Q_E
|
|
.sym 11377 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
|
|
.sym 11378 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 11379 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
|
|
.sym 11380 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 11381 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 11385 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 11388 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 11398 i_glob_clock$SB_IO_IN
|
|
.sym 11406 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 11409 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 11415 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 11416 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 11417 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 11419 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 11420 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 11421 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 11424 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 11425 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 11426 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
|
|
.sym 11428 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 11429 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0]
|
|
.sym 11431 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
|
|
.sym 11435 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 11437 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 11438 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
|
|
.sym 11441 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
|
|
.sym 11442 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.sym 11443 w_rx_fifo_full
|
|
.sym 11445 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 11446 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 11449 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 11450 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 11455 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 11456 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0]
|
|
.sym 11457 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 11460 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 11461 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 11462 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 11463 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 11467 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 11469 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
|
|
.sym 11473 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
|
|
.sym 11474 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
|
|
.sym 11475 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
|
|
.sym 11480 w_rx_fifo_full
|
|
.sym 11481 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 11486 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 11487 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 11490 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 11493 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 11494 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.sym 11495 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 11497 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 11499 w_cs[1]
|
|
.sym 11500 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.sym 11501 w_cs[2]
|
|
.sym 11504 w_cs[3]
|
|
.sym 11521 rx_fifo.rd_addr_gray[0]
|
|
.sym 11524 w_tx_data_smi[2]
|
|
.sym 11525 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 11527 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 11530 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 11531 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 11538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
|
|
.sym 11540 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 11543 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0]
|
|
.sym 11545 o_led1$SB_IO_OUT
|
|
.sym 11546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 11551 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2]
|
|
.sym 11552 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 11553 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
|
|
.sym 11555 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 11557 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 11565 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 11574 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 11577 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 11578 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 11584 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0]
|
|
.sym 11585 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2]
|
|
.sym 11586 o_led1$SB_IO_OUT
|
|
.sym 11591 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 11598 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 11602 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
|
|
.sym 11609 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
|
|
.sym 11617 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 11618 r_counter_$glb_clk
|
|
.sym 11619 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 11620 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
|
|
.sym 11622 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 11623 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 11624 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 11625 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 11626 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
|
|
.sym 11634 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 11637 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 11639 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 11641 o_led1$SB_IO_OUT
|
|
.sym 11642 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 11643 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 11645 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 11647 rx_fifo.rd_addr_gray[2]
|
|
.sym 11652 rx_fifo.rd_addr_gray[4]
|
|
.sym 11661 rx_fifo.rd_addr_gray[6]
|
|
.sym 11665 rx_fifo.rd_addr_gray[3]
|
|
.sym 11670 rx_fifo.rd_addr_gray_wr[6]
|
|
.sym 11681 rx_fifo.rd_addr_gray[0]
|
|
.sym 11689 rx_fifo.rd_addr_gray[5]
|
|
.sym 11690 rx_fifo.rd_addr_gray_wr[3]
|
|
.sym 11701 rx_fifo.rd_addr_gray[6]
|
|
.sym 11708 rx_fifo.rd_addr_gray_wr[3]
|
|
.sym 11713 rx_fifo.rd_addr_gray[0]
|
|
.sym 11720 rx_fifo.rd_addr_gray_wr[6]
|
|
.sym 11727 rx_fifo.rd_addr_gray[3]
|
|
.sym 11731 rx_fifo.rd_addr_gray[5]
|
|
.sym 11741 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 11743 r_tx_data[1]
|
|
.sym 11744 r_tx_data[4]
|
|
.sym 11745 r_tx_data[7]
|
|
.sym 11746 r_tx_data[6]
|
|
.sym 11747 r_tx_data[5]
|
|
.sym 11748 r_tx_data[2]
|
|
.sym 11749 r_tx_data[3]
|
|
.sym 11750 r_tx_data[0]
|
|
.sym 11776 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
|
|
.sym 11787 rx_fifo.rd_addr_gray_wr[1]
|
|
.sym 11794 rx_fifo.rd_addr_gray[1]
|
|
.sym 11807 rx_fifo.rd_addr_gray[2]
|
|
.sym 11809 rx_fifo.rd_addr_gray_wr[4]
|
|
.sym 11810 rx_fifo.rd_addr_gray_wr[2]
|
|
.sym 11812 rx_fifo.rd_addr_gray[4]
|
|
.sym 11823 rx_fifo.rd_addr_gray[4]
|
|
.sym 11832 rx_fifo.rd_addr_gray[2]
|
|
.sym 11837 rx_fifo.rd_addr_gray[1]
|
|
.sym 11844 rx_fifo.rd_addr_gray_wr[2]
|
|
.sym 11853 rx_fifo.rd_addr_gray_wr[4]
|
|
.sym 11859 rx_fifo.rd_addr_gray_wr[1]
|
|
.sym 11864 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 11866 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
|
|
.sym 11867 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
|
|
.sym 11868 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
|
|
.sym 11869 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
|
|
.sym 11870 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 11871 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
|
|
.sym 11872 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 11873 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
|
|
.sym 11879 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
|
|
.sym 11881 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 11893 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 11895 i_glob_clock$SB_IO_IN
|
|
.sym 11897 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 11909 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 11912 r_tx_data[2]
|
|
.sym 11972 r_tx_data[2]
|
|
.sym 11986 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 11987 r_counter_$glb_clk
|
|
.sym 11997 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 12014 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 12041 rx_fifo.wr_addr_gray_rd[1]
|
|
.sym 12055 rx_fifo.wr_addr_gray[1]
|
|
.sym 12084 rx_fifo.wr_addr_gray[1]
|
|
.sym 12101 rx_fifo.wr_addr_gray_rd[1]
|
|
.sym 12110 r_counter_$glb_clk
|
|
.sym 12128 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 12172 rx_fifo.rd_addr_gray[7]
|
|
.sym 12176 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 12189 rx_fifo.rd_addr_gray[7]
|
|
.sym 12199 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 12233 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 12305 i_rst_b$SB_IO_IN
|
|
.sym 12309 smi_ctrl_ins.soe_and_reset
|
|
.sym 12310 w_smi_data_output[0]
|
|
.sym 12312 o_led0$SB_IO_OUT
|
|
.sym 12313 w_smi_data_output[7]
|
|
.sym 12315 o_led0$SB_IO_OUT
|
|
.sym 12316 $PACKER_VCC_NET
|
|
.sym 12321 $PACKER_VCC_NET
|
|
.sym 12322 smi_ctrl_ins.soe_and_reset
|
|
.sym 12326 o_led0$SB_IO_OUT
|
|
.sym 12328 w_smi_data_output[0]
|
|
.sym 12333 w_smi_data_output[7]
|
|
.sym 12334 o_led0$SB_IO_OUT
|
|
.sym 12336 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 12337 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 12338 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 12339 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 12340 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 12341 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 12342 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 12377 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 12386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
|
|
.sym 12394 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
|
|
.sym 12395 i_rst_b$SB_IO_IN
|
|
.sym 12424 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 12441 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
|
|
.sym 12442 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
|
|
.sym 12456 i_rst_b$SB_IO_IN
|
|
.sym 12457 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 12463 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 12464 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 12465 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12466 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
|
|
.sym 12467 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 12468 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 12469 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 12470 tx_fifo.rd_addr[6]
|
|
.sym 12473 w_tx_data_smi[1]
|
|
.sym 12477 w_smi_data_output[5]
|
|
.sym 12481 w_smi_data_input[7]
|
|
.sym 12483 smi_ctrl_ins.soe_and_reset
|
|
.sym 12486 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 12506 tx_fifo.rd_addr[1]
|
|
.sym 12509 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 12512 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 12515 i_rst_b$SB_IO_IN
|
|
.sym 12516 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12517 w_smi_data_output[3]
|
|
.sym 12518 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 12520 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 12524 tx_fifo.rd_addr[1]
|
|
.sym 12528 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 12542 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 12543 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 12545 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 12549 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 12550 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 12552 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 12555 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 12569 tx_fifo.rd_addr[0]
|
|
.sym 12574 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 12576 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 12579 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 12585 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 12591 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 12593 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 12600 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 12606 tx_fifo.rd_addr[0]
|
|
.sym 12610 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 12618 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 12619 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 12620 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 12621 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 12622 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 12623 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0]
|
|
.sym 12624 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2]
|
|
.sym 12625 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 12627 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1]
|
|
.sym 12628 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 12629 rx_fifo.wr_addr_gray[0]
|
|
.sym 12641 o_led1$SB_IO_OUT
|
|
.sym 12643 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 12647 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 12649 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 12650 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 12651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 12652 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 12653 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12656 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 12657 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 12663 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 12665 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12666 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
|
|
.sym 12669 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 12670 tx_fifo.rd_addr[1]
|
|
.sym 12674 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 12677 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12680 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 12681 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 12683 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 12686 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 12690 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 12691 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12696 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 12698 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 12699 tx_fifo.rd_addr[1]
|
|
.sym 12703 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 12710 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 12714 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
|
|
.sym 12715 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 12716 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 12717 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12726 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12727 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 12728 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12729 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 12735 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 12738 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12739 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 12740 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12741 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 12742 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 12743 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 12746 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3]
|
|
.sym 12747 smi_ctrl_ins.r_fifo_push
|
|
.sym 12748 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3]
|
|
.sym 12750 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0]
|
|
.sym 12751 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2]
|
|
.sym 12752 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3]
|
|
.sym 12757 rx_fifo.mem_i.0.1_WDATA
|
|
.sym 12761 rx_fifo.mem_i.0.1_WDATA_2
|
|
.sym 12762 rx_fifo.wr_addr[3]
|
|
.sym 12764 rx_fifo.wr_addr[1]
|
|
.sym 12767 o_led1$SB_IO_OUT
|
|
.sym 12769 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 12770 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12771 i_rst_b_SB_LUT4_I3_O
|
|
.sym 12773 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 12777 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12787 tx_fifo.rd_addr_gray[3]
|
|
.sym 12788 tx_fifo.rd_addr_gray[2]
|
|
.sym 12792 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 12800 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 12801 tx_fifo.rd_addr[1]
|
|
.sym 12803 tx_fifo.rd_addr_gray_wr[3]
|
|
.sym 12804 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12805 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 12811 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 12812 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12813 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12816 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 12819 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12820 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 12821 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12822 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 12825 tx_fifo.rd_addr_gray[3]
|
|
.sym 12832 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 12833 tx_fifo.rd_addr[1]
|
|
.sym 12834 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 12837 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 12838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 12839 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12840 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 12851 tx_fifo.rd_addr_gray_wr[3]
|
|
.sym 12864 tx_fifo.rd_addr_gray[2]
|
|
.sym 12866 r_counter_$glb_clk
|
|
.sym 12868 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 12869 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 12870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 12871 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 12872 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0]
|
|
.sym 12873 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
|
|
.sym 12874 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 12875 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 12880 rx_fifo.rd_addr[7]
|
|
.sym 12881 rx_fifo.rd_addr[0]
|
|
.sym 12882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 12883 rx_fifo.rd_addr[6]
|
|
.sym 12884 rx_fifo.wr_addr[4]
|
|
.sym 12887 rx_fifo.wr_addr[6]
|
|
.sym 12888 w_rx_fifo_pulled_data[23]
|
|
.sym 12889 w_smi_data_input[7]
|
|
.sym 12894 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 12896 tx_fifo.rd_addr[1]
|
|
.sym 12899 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 12901 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 12902 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12903 i_rst_b$SB_IO_IN
|
|
.sym 12910 w_tx_fifo_pull
|
|
.sym 12911 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
|
|
.sym 12912 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
|
|
.sym 12913 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 12914 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0]
|
|
.sym 12916 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 12917 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 12919 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
|
|
.sym 12920 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3]
|
|
.sym 12923 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 12925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12927 i_rst_b$SB_IO_IN
|
|
.sym 12928 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12929 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1]
|
|
.sym 12931 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.sym 12932 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 12934 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 12935 w_tx_fifo_empty
|
|
.sym 12936 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 12940 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 12948 w_tx_fifo_empty
|
|
.sym 12949 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 12950 w_tx_fifo_pull
|
|
.sym 12951 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12954 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 12955 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 12956 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 12957 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 12960 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
|
|
.sym 12961 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1]
|
|
.sym 12962 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0]
|
|
.sym 12963 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3]
|
|
.sym 12966 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12967 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12968 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 12969 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 12974 w_tx_fifo_pull
|
|
.sym 12975 i_rst_b$SB_IO_IN
|
|
.sym 12978 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
|
|
.sym 12979 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12980 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 12981 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 12984 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
|
|
.sym 12985 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 12987 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.sym 12989 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 12990 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 12991 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12992 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
|
|
.sym 12993 tx_fifo.rd_addr_gray[4]
|
|
.sym 12994 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 12995 tx_fifo.rd_addr_gray[7]
|
|
.sym 12996 tx_fifo.rd_addr_gray[6]
|
|
.sym 12997 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.sym 13003 rx_fifo.mem_i.0.3_WDATA
|
|
.sym 13004 tx_fifo.wr_addr_gray_rd[2]
|
|
.sym 13005 rx_fifo.mem_i.0.3_WDATA_1
|
|
.sym 13006 rx_fifo.mem_q.0.1_WDATA_3
|
|
.sym 13007 rx_fifo.mem_q.0.1_WDATA
|
|
.sym 13008 tx_fifo.wr_addr_gray_rd[8]
|
|
.sym 13009 rx_fifo.mem_q.0.1_WDATA_1
|
|
.sym 13011 rx_fifo.rd_addr[2]
|
|
.sym 13012 rx_fifo.rd_addr[6]
|
|
.sym 13014 rx_fifo.mem_q.0.1_WDATA_2
|
|
.sym 13018 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 13019 rx_fifo.wr_addr[9]
|
|
.sym 13022 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 13025 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 13033 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 13034 w_tx_fifo_pull
|
|
.sym 13042 w_tx_fifo_empty
|
|
.sym 13043 i_rst_b_SB_LUT4_I3_O
|
|
.sym 13045 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
|
|
.sym 13047 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 13051 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
|
|
.sym 13057 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
|
|
.sym 13063 i_rst_b$SB_IO_IN
|
|
.sym 13078 w_tx_fifo_empty
|
|
.sym 13083 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 13084 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 13086 w_tx_fifo_pull
|
|
.sym 13089 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
|
|
.sym 13091 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
|
|
.sym 13092 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
|
|
.sym 13103 i_rst_b$SB_IO_IN
|
|
.sym 13111 i_rst_b_SB_LUT4_I3_O
|
|
.sym 13112 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 13113 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 13116 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
|
|
.sym 13117 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 13119 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 13126 rx_fifo.rd_addr[3]
|
|
.sym 13128 rx_fifo.rd_addr[2]
|
|
.sym 13129 rx_fifo.rd_addr[8]
|
|
.sym 13130 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 13131 o_led1$SB_IO_OUT
|
|
.sym 13132 rx_fifo.wr_addr[7]
|
|
.sym 13134 rx_fifo.wr_addr[6]
|
|
.sym 13135 rx_fifo.wr_addr[5]
|
|
.sym 13136 rx_fifo.wr_addr[4]
|
|
.sym 13137 rx_fifo.rd_addr[4]
|
|
.sym 13141 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 13144 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 13147 i_rst_b_SB_LUT4_I3_O
|
|
.sym 13148 w_tx_fifo_full
|
|
.sym 13158 w_rx_fifo_empty
|
|
.sym 13159 smi_ctrl_ins.w_fifo_pull_trigger
|
|
.sym 13160 smi_ctrl_ins.r_fifo_pulled_data[21]
|
|
.sym 13161 smi_ctrl_ins.r_fifo_pulled_data[29]
|
|
.sym 13164 smi_ctrl_ins.r_fifo_pull_1
|
|
.sym 13171 smi_ctrl_ins.r_fifo_pull
|
|
.sym 13174 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 13176 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 13184 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 13185 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 13190 smi_ctrl_ins.w_fifo_pull_trigger
|
|
.sym 13197 smi_ctrl_ins.r_fifo_pull
|
|
.sym 13201 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 13203 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 13206 smi_ctrl_ins.r_fifo_pulled_data[21]
|
|
.sym 13207 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 13208 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 13209 smi_ctrl_ins.r_fifo_pulled_data[29]
|
|
.sym 13230 w_rx_fifo_empty
|
|
.sym 13231 smi_ctrl_ins.r_fifo_pull
|
|
.sym 13233 smi_ctrl_ins.r_fifo_pull_1
|
|
.sym 13235 r_counter_$glb_clk
|
|
.sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 13241 w_tx_data_smi[0]
|
|
.sym 13245 io_pmod[6]$SB_IO_IN
|
|
.sym 13248 io_pmod[6]$SB_IO_IN
|
|
.sym 13251 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 13252 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 13253 rx_fifo.wr_addr[1]
|
|
.sym 13255 rx_fifo.mem_i.0.3_WDATA_2
|
|
.sym 13256 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 13257 rx_fifo.wr_addr[5]
|
|
.sym 13258 rx_fifo.wr_addr[1]
|
|
.sym 13259 rx_fifo.wr_addr[3]
|
|
.sym 13260 rx_fifo.mem_i.0.3_WDATA_3
|
|
.sym 13263 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 13267 $PACKER_VCC_NET
|
|
.sym 13272 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 13278 rx_fifo.rd_addr[4]
|
|
.sym 13280 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 13281 rx_fifo.rd_addr[3]
|
|
.sym 13282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 13284 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 13285 o_led1$SB_IO_OUT
|
|
.sym 13286 rx_fifo.rd_addr[4]
|
|
.sym 13288 rx_fifo.rd_addr[1]
|
|
.sym 13289 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 13290 rx_fifo.rd_addr[5]
|
|
.sym 13292 rx_fifo.wr_addr_gray_rd_r[0]
|
|
.sym 13295 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2]
|
|
.sym 13296 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 13301 w_rx_fifo_empty
|
|
.sym 13304 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1]
|
|
.sym 13308 w_tx_fifo_full
|
|
.sym 13309 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3]
|
|
.sym 13312 rx_fifo.wr_addr_gray_rd_r[0]
|
|
.sym 13314 rx_fifo.rd_addr[1]
|
|
.sym 13317 rx_fifo.rd_addr[4]
|
|
.sym 13318 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 13319 rx_fifo.rd_addr[5]
|
|
.sym 13324 rx_fifo.rd_addr[3]
|
|
.sym 13325 rx_fifo.rd_addr[4]
|
|
.sym 13331 o_led1$SB_IO_OUT
|
|
.sym 13341 w_tx_fifo_full
|
|
.sym 13347 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 13348 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1]
|
|
.sym 13349 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3]
|
|
.sym 13350 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2]
|
|
.sym 13353 rx_fifo.wr_addr_gray_rd_r[0]
|
|
.sym 13354 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 13355 w_rx_fifo_empty
|
|
.sym 13357 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 13358 r_counter_$glb_clk
|
|
.sym 13359 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 13361 $PACKER_VCC_NET
|
|
.sym 13362 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 13363 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 13364 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 13365 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 13366 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 13367 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
|
|
.sym 13372 rx_fifo.rd_addr[7]
|
|
.sym 13373 w_rx_fifo_pulled_data[31]
|
|
.sym 13374 rx_fifo.rd_addr[1]
|
|
.sym 13377 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 13378 rx_fifo.rd_addr[5]
|
|
.sym 13379 w_rx_fifo_pulled_data[29]
|
|
.sym 13380 rx_fifo.wr_addr_gray_rd_r[0]
|
|
.sym 13381 i_glob_clock$SB_IO_IN
|
|
.sym 13382 rx_fifo.rd_addr[0]
|
|
.sym 13384 spi_if_ins.w_rx_data[5]
|
|
.sym 13385 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 13393 spi_if_ins.w_rx_data[6]
|
|
.sym 13395 $PACKER_VCC_NET
|
|
.sym 13402 spi_if_ins.state_if[1]
|
|
.sym 13403 spi_if_ins.state_if_SB_DFFESR_Q_E
|
|
.sym 13406 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13408 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13416 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 13417 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 13419 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13420 spi_if_ins.state_if[0]
|
|
.sym 13423 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 13425 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
|
|
.sym 13434 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13436 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 13437 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13440 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13442 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
|
|
.sym 13443 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 13446 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 13454 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
|
|
.sym 13459 spi_if_ins.state_if[1]
|
|
.sym 13461 spi_if_ins.state_if[0]
|
|
.sym 13464 spi_if_ins.state_if[0]
|
|
.sym 13465 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13466 spi_if_ins.state_if[1]
|
|
.sym 13471 spi_if_ins.state_if[1]
|
|
.sym 13472 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13473 spi_if_ins.state_if[0]
|
|
.sym 13476 spi_if_ins.state_if[0]
|
|
.sym 13478 spi_if_ins.state_if[1]
|
|
.sym 13479 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13480 spi_if_ins.state_if_SB_DFFESR_Q_E
|
|
.sym 13481 r_counter_$glb_clk
|
|
.sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 13483 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
|
|
.sym 13484 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 13485 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
|
|
.sym 13486 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 13487 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 13488 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
|
|
.sym 13489 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
|
|
.sym 13490 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
|
|
.sym 13497 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13500 rx_fifo.rd_addr[9]
|
|
.sym 13502 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13504 $PACKER_VCC_NET
|
|
.sym 13507 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 13508 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13511 rx_fifo.wr_addr[9]
|
|
.sym 13512 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13516 w_cs[1]
|
|
.sym 13517 rx_fifo.wr_addr[8]
|
|
.sym 13526 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13528 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13529 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
|
|
.sym 13530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 13531 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13532 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 13535 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 13536 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13537 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13538 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 13539 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13540 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13545 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 13551 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
|
|
.sym 13554 i_rst_b$SB_IO_IN
|
|
.sym 13555 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13558 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 13563 i_rst_b$SB_IO_IN
|
|
.sym 13564 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13565 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13566 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
|
|
.sym 13569 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 13570 i_rst_b$SB_IO_IN
|
|
.sym 13571 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13572 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 13575 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 13576 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13577 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
|
|
.sym 13583 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13584 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 13588 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13589 i_rst_b$SB_IO_IN
|
|
.sym 13593 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13594 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13595 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13596 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
|
|
.sym 13599 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13600 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13602 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13603 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 13604 r_counter_$glb_clk
|
|
.sym 13605 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13606 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 13607 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 13608 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 13609 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 13610 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 13611 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 13612 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 13613 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 13618 spi_if_ins.r_tx_data_valid
|
|
.sym 13622 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 13627 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 13631 spi_if_ins.r_tx_byte[3]
|
|
.sym 13632 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 13633 spi_if_ins.r_tx_byte[4]
|
|
.sym 13634 w_tx_data_io[0]
|
|
.sym 13635 spi_if_ins.r_tx_byte[7]
|
|
.sym 13637 spi_if_ins.r_tx_byte[1]
|
|
.sym 13639 w_tx_data_io[1]
|
|
.sym 13640 i_rst_b$SB_IO_IN
|
|
.sym 13641 spi_if_ins.r_tx_byte[0]
|
|
.sym 13648 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.sym 13649 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 13651 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 13655 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13656 spi_if_ins.w_rx_data[5]
|
|
.sym 13661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13663 spi_if_ins.w_rx_data[6]
|
|
.sym 13681 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13683 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 13692 spi_if_ins.w_rx_data[5]
|
|
.sym 13694 spi_if_ins.w_rx_data[6]
|
|
.sym 13698 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.sym 13704 spi_if_ins.w_rx_data[5]
|
|
.sym 13706 spi_if_ins.w_rx_data[6]
|
|
.sym 13723 spi_if_ins.w_rx_data[6]
|
|
.sym 13725 spi_if_ins.w_rx_data[5]
|
|
.sym 13726 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 13727 r_counter_$glb_clk
|
|
.sym 13728 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 13729 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 13730 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
|
|
.sym 13731 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 13732 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13733 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
|
|
.sym 13734 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
|
|
.sym 13735 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13736 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 13742 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 13743 rx_fifo.wr_addr[0]
|
|
.sym 13745 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 13747 w_cs[1]
|
|
.sym 13748 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 13751 w_cs[2]
|
|
.sym 13753 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
|
|
.sym 13754 w_cs[1]
|
|
.sym 13755 spi_if_ins.r_tx_byte[5]
|
|
.sym 13756 spi_if_ins.r_tx_byte[2]
|
|
.sym 13757 i_rst_b$SB_IO_IN
|
|
.sym 13760 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 13761 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 13770 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 13771 w_tx_data_io[2]
|
|
.sym 13772 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 13779 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 13781 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 13784 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 13785 w_tx_data_smi[2]
|
|
.sym 13787 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
|
|
.sym 13788 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 13789 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13796 w_tx_data_smi[1]
|
|
.sym 13798 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 13799 w_tx_data_io[1]
|
|
.sym 13800 i_rst_b$SB_IO_IN
|
|
.sym 13801 io_pmod[6]$SB_IO_IN
|
|
.sym 13803 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 13804 w_tx_data_smi[1]
|
|
.sym 13805 w_tx_data_io[1]
|
|
.sym 13806 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13816 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 13821 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 13822 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 13824 io_pmod[6]$SB_IO_IN
|
|
.sym 13827 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 13828 i_rst_b$SB_IO_IN
|
|
.sym 13829 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 13833 i_rst_b$SB_IO_IN
|
|
.sym 13835 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
|
|
.sym 13839 w_tx_data_smi[2]
|
|
.sym 13840 w_tx_data_io[2]
|
|
.sym 13841 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 13842 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13849 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 13850 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 13851 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 13852 spi_if_ins.r_tx_byte[3]
|
|
.sym 13853 spi_if_ins.r_tx_byte[4]
|
|
.sym 13854 spi_if_ins.r_tx_byte[7]
|
|
.sym 13855 spi_if_ins.r_tx_byte[1]
|
|
.sym 13856 spi_if_ins.r_tx_byte[6]
|
|
.sym 13857 spi_if_ins.r_tx_byte[0]
|
|
.sym 13858 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
|
|
.sym 13859 spi_if_ins.r_tx_byte[5]
|
|
.sym 13874 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 13875 w_tx_data_io[2]
|
|
.sym 13880 w_cs[0]
|
|
.sym 13881 w_rx_data[1]
|
|
.sym 13883 w_rx_data[2]
|
|
.sym 13886 i_rst_b$SB_IO_IN
|
|
.sym 13893 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
|
|
.sym 13894 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
|
|
.sym 13895 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
|
|
.sym 13896 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13897 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
|
|
.sym 13898 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
|
|
.sym 13899 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13900 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
|
|
.sym 13901 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 13904 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
|
|
.sym 13905 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
|
|
.sym 13906 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
|
|
.sym 13907 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
|
|
.sym 13908 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
|
|
.sym 13909 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
|
|
.sym 13913 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
|
|
.sym 13917 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 13918 i_glob_clock$SB_IO_IN
|
|
.sym 13920 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 13921 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 13923 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
|
|
.sym 13926 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
|
|
.sym 13927 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
|
|
.sym 13928 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13932 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
|
|
.sym 13933 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
|
|
.sym 13934 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13935 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13938 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
|
|
.sym 13939 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
|
|
.sym 13940 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13944 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13945 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13946 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 13947 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
|
|
.sym 13950 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13951 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
|
|
.sym 13952 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
|
|
.sym 13956 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 13957 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13958 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
|
|
.sym 13959 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
|
|
.sym 13962 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13963 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
|
|
.sym 13964 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
|
|
.sym 13965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 13968 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 13969 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 13970 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 13971 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
|
|
.sym 13972 spi_if_ins.o_cs_SB_LUT4_I0_O_SB_LUT4_I3_O
|
|
.sym 13973 i_glob_clock$SB_IO_IN
|
|
.sym 13975 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 13976 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0]
|
|
.sym 13977 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0]
|
|
.sym 13978 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 13979 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 13980 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0]
|
|
.sym 13981 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 13982 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 13987 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 13992 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
|
|
.sym 13996 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
|
|
.sym 14000 i_glob_clock$SB_IO_IN
|
|
.sym 14001 w_rx_data[0]
|
|
.sym 14003 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 14027 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 14033 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0]
|
|
.sym 14035 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 14036 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 14037 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0]
|
|
.sym 14040 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 14042 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0]
|
|
.sym 14045 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14046 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0]
|
|
.sym 14047 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 14049 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14052 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 14056 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 14058 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14063 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14064 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0]
|
|
.sym 14068 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14070 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 14075 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14076 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 14079 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0]
|
|
.sym 14082 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14085 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14088 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0]
|
|
.sym 14093 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0]
|
|
.sym 14094 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 14095 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 14096 r_counter_$glb_clk
|
|
.sym 14097 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 14104 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0]
|
|
.sym 14131 i_rst_b$SB_IO_IN
|
|
.sym 14226 r_counter
|
|
.sym 14243 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
|
|
.sym 14249 i_rst_b$SB_IO_IN
|
|
.sym 14344 i_rst_b$SB_IO_IN
|
|
.sym 14373 i_rst_b$SB_IO_IN
|
|
.sym 14388 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.sym 14408 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.sym 14418 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.sym 14419 w_smi_data_output[3]
|
|
.sym 14421 o_led0$SB_IO_OUT
|
|
.sym 14425 $PACKER_VCC_NET
|
|
.sym 14430 $PACKER_VCC_NET
|
|
.sym 14431 o_led0$SB_IO_OUT
|
|
.sym 14432 w_smi_data_output[3]
|
|
.sym 14438 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R
|
|
.sym 14445 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 14447 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 14448 smi_ctrl_ins.swe_and_reset
|
|
.sym 14449 tx_fifo.wr_addr_gray_rd[4]
|
|
.sym 14450 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 14451 smi_ctrl_ins.soe_and_reset
|
|
.sym 14456 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 14458 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 14459 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 14462 $PACKER_VCC_NET
|
|
.sym 14468 w_tx_data_smi[0]
|
|
.sym 14501 tx_fifo.rd_addr[6]
|
|
.sym 14503 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 14504 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 14507 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 14508 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 14509 tx_fifo.rd_addr[1]
|
|
.sym 14514 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 14515 tx_fifo.rd_addr[0]
|
|
.sym 14518 $nextpnr_ICESTORM_LC_7$O
|
|
.sym 14521 tx_fifo.rd_addr[0]
|
|
.sym 14524 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 14527 tx_fifo.rd_addr[1]
|
|
.sym 14528 tx_fifo.rd_addr[0]
|
|
.sym 14530 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3
|
|
.sym 14532 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 14534 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 14536 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3
|
|
.sym 14539 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 14540 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3
|
|
.sym 14542 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 14544 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 14546 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3
|
|
.sym 14548 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 14550 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 14552 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 14554 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 14557 tx_fifo.rd_addr[6]
|
|
.sym 14558 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 14560 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3
|
|
.sym 14562 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 14564 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 14568 i_smi_swe_srw$SB_IO_IN
|
|
.sym 14573 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 14574 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 14575 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 14576 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 14577 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 14578 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 14579 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 14580 i_rst_b$SB_IO_IN
|
|
.sym 14583 i_rst_b$SB_IO_IN
|
|
.sym 14588 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 14597 i_smi_soe_se$SB_IO_IN
|
|
.sym 14609 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 14611 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 14617 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 14624 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 14627 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 14628 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 14634 tx_fifo.rd_addr_gray_wr[6]
|
|
.sym 14637 rx_fifo.wr_addr_gray_rd[0]
|
|
.sym 14638 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 14641 $PACKER_VCC_NET
|
|
.sym 14644 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3
|
|
.sym 14650 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 14651 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 14653 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 14654 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 14655 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 14656 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 14657 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14658 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 14659 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 14663 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14667 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 14673 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 14681 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3
|
|
.sym 14683 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14685 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3
|
|
.sym 14690 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14691 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3
|
|
.sym 14695 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 14696 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 14697 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 14700 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 14702 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 14703 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 14707 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 14708 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 14713 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 14714 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 14718 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 14719 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 14725 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 14728 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 14729 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 14731 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 14732 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 14733 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 14734 rx_fifo.wr_addr_gray_rd[0]
|
|
.sym 14735 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 14736 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 14737 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 14738 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 14743 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14745 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 14752 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 14758 tx_fifo.rd_addr_gray_wr[4]
|
|
.sym 14761 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 14762 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 14763 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
|
|
.sym 14765 $PACKER_VCC_NET
|
|
.sym 14766 tx_fifo.rd_addr[6]
|
|
.sym 14774 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 14776 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14778 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 14779 tx_fifo.rd_addr[6]
|
|
.sym 14780 rx_fifo.wr_addr[1]
|
|
.sym 14781 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3]
|
|
.sym 14783 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 14784 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 14788 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 14789 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 14790 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 14794 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 14796 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 14798 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 14799 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 14807 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 14808 tx_fifo.rd_addr[6]
|
|
.sym 14811 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 14812 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 14813 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 14814 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14817 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 14818 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 14819 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3]
|
|
.sym 14820 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 14824 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 14825 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 14835 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 14836 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3]
|
|
.sym 14837 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 14838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 14841 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 14843 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 14847 rx_fifo.wr_addr[1]
|
|
.sym 14851 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 14852 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 14854 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
|
|
.sym 14855 smi_ctrl_ins.w_fifo_push_trigger
|
|
.sym 14856 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 14858 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
|
|
.sym 14859 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 14861 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 14866 tx_fifo.wr_addr[8]
|
|
.sym 14868 rx_fifo.wr_addr[0]
|
|
.sym 14870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 14871 i_rst_b$SB_IO_IN
|
|
.sym 14872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 14876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 14878 tx_fifo.wr_addr_gray_rd[9]
|
|
.sym 14880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 14881 w_rx_fifo_pulled_data[7]
|
|
.sym 14882 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 14884 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 14895 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 14896 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0]
|
|
.sym 14897 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2]
|
|
.sym 14898 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 14899 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0]
|
|
.sym 14900 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 14902 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 14904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 14906 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 14908 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1]
|
|
.sym 14911 tx_fifo.empty_o_SB_LUT4_I0_O[3]
|
|
.sym 14912 tx_fifo.empty_o_SB_LUT4_I0_O[2]
|
|
.sym 14918 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3]
|
|
.sym 14920 smi_ctrl_ins.w_fifo_push_trigger
|
|
.sym 14921 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 14925 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2]
|
|
.sym 14926 tx_fifo.rd_addr[6]
|
|
.sym 14935 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0]
|
|
.sym 14937 tx_fifo.rd_addr[6]
|
|
.sym 14942 smi_ctrl_ins.w_fifo_push_trigger
|
|
.sym 14946 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0]
|
|
.sym 14947 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1]
|
|
.sym 14948 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3]
|
|
.sym 14949 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2]
|
|
.sym 14958 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 14959 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 14960 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2]
|
|
.sym 14964 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 14965 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 14967 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 14970 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 14971 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 14972 tx_fifo.empty_o_SB_LUT4_I0_O[2]
|
|
.sym 14973 tx_fifo.empty_o_SB_LUT4_I0_O[3]
|
|
.sym 14975 r_counter_$glb_clk
|
|
.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 14977 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 14978 tx_fifo.rd_addr_gray_wr[4]
|
|
.sym 14979 tx_fifo.rd_addr_gray_wr[8]
|
|
.sym 14980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 14981 tx_fifo.rd_addr_gray_wr[7]
|
|
.sym 14982 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 14983 tx_fifo.rd_addr_gray_wr[1]
|
|
.sym 14984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 14995 smi_ctrl_ins.r_fifo_push
|
|
.sym 14996 rx_fifo.wr_addr[9]
|
|
.sym 14998 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 15007 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 15011 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 15018 tx_fifo.wr_addr_gray_rd[1]
|
|
.sym 15020 tx_fifo.wr_addr_gray_rd[3]
|
|
.sym 15022 tx_fifo.wr_addr_gray_rd[5]
|
|
.sym 15024 tx_fifo.wr_addr_gray_rd[8]
|
|
.sym 15025 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 15030 tx_fifo.wr_addr_gray_rd[2]
|
|
.sym 15031 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 15032 tx_fifo.wr_addr_gray_rd[7]
|
|
.sym 15038 tx_fifo.wr_addr_gray_rd[9]
|
|
.sym 15040 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 15046 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0]
|
|
.sym 15054 tx_fifo.wr_addr_gray_rd[7]
|
|
.sym 15060 tx_fifo.wr_addr_gray_rd[8]
|
|
.sym 15066 tx_fifo.wr_addr_gray_rd[2]
|
|
.sym 15072 tx_fifo.wr_addr_gray_rd[3]
|
|
.sym 15075 tx_fifo.wr_addr_gray_rd[5]
|
|
.sym 15081 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0]
|
|
.sym 15082 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 15083 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 15084 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 15089 tx_fifo.wr_addr_gray_rd[1]
|
|
.sym 15094 tx_fifo.wr_addr_gray_rd[9]
|
|
.sym 15098 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 15101 tx_fifo.rd_addr_gray[1]
|
|
.sym 15104 tx_fifo.rd_addr_gray[8]
|
|
.sym 15105 tx_fifo.rd_addr_gray[5]
|
|
.sym 15107 tx_fifo.rd_addr_gray[0]
|
|
.sym 15111 i_rst_b$SB_IO_IN
|
|
.sym 15112 rx_fifo.rd_addr[5]
|
|
.sym 15113 rx_fifo.rd_addr[3]
|
|
.sym 15114 tx_fifo.wr_addr_gray_rd[3]
|
|
.sym 15115 w_tx_fifo_full
|
|
.sym 15117 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 15118 tx_fifo.wr_addr_gray_rd[5]
|
|
.sym 15120 tx_fifo.wr_addr_gray_rd[7]
|
|
.sym 15121 w_rx_fifo_pulled_data[6]
|
|
.sym 15122 tx_fifo.wr_addr_gray_rd[1]
|
|
.sym 15123 rx_fifo.rd_addr[1]
|
|
.sym 15126 tx_fifo.rd_addr_gray_wr[6]
|
|
.sym 15127 rx_fifo.wr_addr_gray_rd[0]
|
|
.sym 15128 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 15131 tx_fifo.rd_addr_gray_wr[2]
|
|
.sym 15133 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
|
|
.sym 15147 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 15148 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 15149 tx_fifo.rd_addr[1]
|
|
.sym 15154 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 15155 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 15156 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 15159 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 15160 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 15161 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 15162 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 15177 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 15180 tx_fifo.rd_addr[1]
|
|
.sym 15181 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 15182 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 15183 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 15186 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 15195 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 15200 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 15201 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 15204 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 15206 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 15212 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 15213 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 15220 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 15221 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 15222 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 15229 tx_fifo.rd_addr_gray_wr[9]
|
|
.sym 15230 tx_fifo.rd_addr_gray_wr[6]
|
|
.sym 15237 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 15238 rx_fifo.wr_addr[3]
|
|
.sym 15242 io_pmod[7]$SB_IO_IN
|
|
.sym 15244 $PACKER_VCC_NET
|
|
.sym 15249 $PACKER_VCC_NET
|
|
.sym 15252 rx_fifo.wr_addr[9]
|
|
.sym 15253 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 15255 w_rx_fifo_empty
|
|
.sym 15258 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 15267 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 15292 i_rst_b$SB_IO_IN
|
|
.sym 15293 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 15309 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 15310 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 15312 i_rst_b$SB_IO_IN
|
|
.sym 15315 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 15327 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 15330 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 15344 smi_ctrl_ins.soe_and_reset_$glb_clk
|
|
.sym 15345 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 15353 rx_fifo.wr_addr_gray_rd_r[0]
|
|
.sym 15359 tx_fifo.rd_addr_gray_wr[9]
|
|
.sym 15369 spi_if_ins.spi.r2_rx_done
|
|
.sym 15374 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 15381 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 15400 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 15405 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 15415 w_rx_fifo_empty
|
|
.sym 15445 w_rx_fifo_empty
|
|
.sym 15466 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 15467 r_counter_$glb_clk
|
|
.sym 15468 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 15471 int_miso
|
|
.sym 15474 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 15487 rx_fifo.wr_addr[8]
|
|
.sym 15488 rx_fifo.wr_addr[9]
|
|
.sym 15493 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.sym 15495 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15496 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 15499 i_ss$SB_IO_IN
|
|
.sym 15503 $PACKER_VCC_NET
|
|
.sym 15510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
|
|
.sym 15512 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 15514 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15517 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
|
|
.sym 15520 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15522 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15524 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
|
|
.sym 15527 $PACKER_VCC_NET
|
|
.sym 15528 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 15535 $PACKER_VCC_NET
|
|
.sym 15539 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 15542 $nextpnr_ICESTORM_LC_9$O
|
|
.sym 15544 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15548 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
|
|
.sym 15550 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15551 $PACKER_VCC_NET
|
|
.sym 15555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 15557 $PACKER_VCC_NET
|
|
.sym 15558 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
|
|
.sym 15561 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
|
|
.sym 15562 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
|
|
.sym 15563 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
|
|
.sym 15564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 15570 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15573 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15574 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15576 $PACKER_VCC_NET
|
|
.sym 15579 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15585 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15586 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 15588 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15589 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 15590 r_counter_$glb_clk
|
|
.sym 15591 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 15592 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 15596 w_fetch
|
|
.sym 15597 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 15598 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.sym 15602 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 15608 $PACKER_VCC_NET
|
|
.sym 15614 i_rst_b_SB_LUT4_I3_O
|
|
.sym 15615 int_miso
|
|
.sym 15619 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 15623 w_tx_data_io[7]
|
|
.sym 15627 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
|
|
.sym 15634 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 15635 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 15637 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 15640 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
|
|
.sym 15644 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 15645 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15646 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 15647 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 15648 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 15650 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 15651 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
|
|
.sym 15653 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.sym 15654 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
|
|
.sym 15655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15656 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 15658 spi_if_ins.r_tx_byte[7]
|
|
.sym 15661 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 15662 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 15664 spi_if_ins.r_tx_byte[4]
|
|
.sym 15666 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15667 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15668 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 15669 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 15673 spi_if_ins.r_tx_byte[4]
|
|
.sym 15679 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 15680 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 15681 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15684 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
|
|
.sym 15686 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 15687 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 15692 spi_if_ins.r_tx_byte[7]
|
|
.sym 15696 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15697 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 15698 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 15702 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
|
|
.sym 15704 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15705 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
|
|
.sym 15708 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 15709 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 15710 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 15711 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 15712 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 15713 r_counter_$glb_clk
|
|
.sym 15714 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.sym 15715 w_cs[0]
|
|
.sym 15718 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 15720 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 15721 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 15722 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 15728 $PACKER_VCC_NET
|
|
.sym 15729 o_led1$SB_IO_OUT
|
|
.sym 15734 i_rst_b$SB_IO_IN
|
|
.sym 15741 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 15743 spi_if_ins.r_tx_byte[7]
|
|
.sym 15747 spi_if_ins.r_tx_byte[6]
|
|
.sym 15757 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15758 w_cs[1]
|
|
.sym 15760 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15763 w_cs[3]
|
|
.sym 15767 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 15768 w_cs[2]
|
|
.sym 15769 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15772 w_cs[0]
|
|
.sym 15773 spi_if_ins.r_tx_byte[6]
|
|
.sym 15776 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.sym 15778 spi_if_ins.r_tx_byte[1]
|
|
.sym 15780 spi_if_ins.r_tx_byte[3]
|
|
.sym 15782 spi_if_ins.r_tx_byte[0]
|
|
.sym 15784 i_rst_b$SB_IO_IN
|
|
.sym 15786 spi_if_ins.r_tx_byte[5]
|
|
.sym 15787 spi_if_ins.r_tx_byte[2]
|
|
.sym 15789 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15790 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15791 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15792 i_rst_b$SB_IO_IN
|
|
.sym 15795 spi_if_ins.r_tx_byte[0]
|
|
.sym 15801 spi_if_ins.r_tx_byte[2]
|
|
.sym 15807 w_cs[2]
|
|
.sym 15808 w_cs[1]
|
|
.sym 15809 w_cs[3]
|
|
.sym 15810 w_cs[0]
|
|
.sym 15814 spi_if_ins.r_tx_byte[5]
|
|
.sym 15819 spi_if_ins.r_tx_byte[6]
|
|
.sym 15826 spi_if_ins.r_tx_byte[3]
|
|
.sym 15834 spi_if_ins.r_tx_byte[1]
|
|
.sym 15835 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 15836 r_counter_$glb_clk
|
|
.sym 15837 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O
|
|
.sym 15838 w_load
|
|
.sym 15839 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 15842 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0]
|
|
.sym 15843 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
|
|
.sym 15844 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 15845 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 15850 w_rx_data[2]
|
|
.sym 15852 w_rx_data[1]
|
|
.sym 15853 i_rst_b$SB_IO_IN
|
|
.sym 15855 spi_if_ins.w_rx_data[6]
|
|
.sym 15856 spi_if_ins.w_rx_data[0]
|
|
.sym 15857 w_cs[0]
|
|
.sym 15859 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 15860 spi_if_ins.w_rx_data[5]
|
|
.sym 15865 w_fetch
|
|
.sym 15866 w_rx_data[7]
|
|
.sym 15868 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
|
|
.sym 15871 w_load
|
|
.sym 15872 w_rx_data[7]
|
|
.sym 15879 w_tx_data_io[0]
|
|
.sym 15884 w_rx_data[2]
|
|
.sym 15887 w_cs[0]
|
|
.sym 15888 w_rx_data[0]
|
|
.sym 15890 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 15893 w_tx_data_io[7]
|
|
.sym 15895 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 15897 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
|
|
.sym 15898 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 15899 w_cs[2]
|
|
.sym 15903 w_tx_data_smi[0]
|
|
.sym 15905 w_cs[1]
|
|
.sym 15910 w_cs[3]
|
|
.sym 15912 w_cs[2]
|
|
.sym 15913 w_cs[1]
|
|
.sym 15914 w_cs[3]
|
|
.sym 15915 w_cs[0]
|
|
.sym 15918 w_cs[0]
|
|
.sym 15919 w_cs[2]
|
|
.sym 15920 w_cs[1]
|
|
.sym 15921 w_cs[3]
|
|
.sym 15927 w_rx_data[2]
|
|
.sym 15930 w_cs[1]
|
|
.sym 15931 w_cs[3]
|
|
.sym 15932 w_cs[0]
|
|
.sym 15933 w_cs[2]
|
|
.sym 15936 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 15937 w_tx_data_smi[0]
|
|
.sym 15938 w_tx_data_io[0]
|
|
.sym 15939 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 15942 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 15944 w_tx_data_io[7]
|
|
.sym 15945 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 15948 w_cs[2]
|
|
.sym 15949 w_cs[1]
|
|
.sym 15950 w_cs[3]
|
|
.sym 15951 w_cs[0]
|
|
.sym 15957 w_rx_data[0]
|
|
.sym 15958 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_E
|
|
.sym 15959 r_counter_$glb_clk
|
|
.sym 15960 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 15961 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 15963 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
|
|
.sym 15964 i_button_SB_LUT4_I0_O[1]
|
|
.sym 15965 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 15966 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2]
|
|
.sym 15967 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 15968 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 15974 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 15979 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15980 w_rx_data[2]
|
|
.sym 15981 i_glob_clock$SB_IO_IN
|
|
.sym 15982 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 15983 w_cs[1]
|
|
.sym 15984 w_rx_data[0]
|
|
.sym 15987 w_rx_data[3]
|
|
.sym 15989 w_ioc[1]
|
|
.sym 15991 w_rx_data[5]
|
|
.sym 15992 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 15993 w_rx_data[4]
|
|
.sym 15996 w_tx_data_io[5]
|
|
.sym 16002 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 16003 w_tx_data_io[5]
|
|
.sym 16005 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 16006 r_tx_data[5]
|
|
.sym 16008 r_tx_data[3]
|
|
.sym 16010 r_tx_data[1]
|
|
.sym 16011 r_tx_data[4]
|
|
.sym 16012 r_tx_data[7]
|
|
.sym 16013 r_tx_data[6]
|
|
.sym 16017 r_tx_data[0]
|
|
.sym 16020 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 16035 r_tx_data[3]
|
|
.sym 16042 r_tx_data[4]
|
|
.sym 16048 r_tx_data[7]
|
|
.sym 16055 r_tx_data[1]
|
|
.sym 16059 r_tx_data[6]
|
|
.sym 16066 r_tx_data[0]
|
|
.sym 16071 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 16072 w_tx_data_io[5]
|
|
.sym 16074 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 16080 r_tx_data[5]
|
|
.sym 16081 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 16082 r_counter_$glb_clk
|
|
.sym 16084 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E
|
|
.sym 16085 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3]
|
|
.sym 16086 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 16087 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 16088 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
|
|
.sym 16089 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 16090 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 16091 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 16095 i_rst_b$SB_IO_IN
|
|
.sym 16096 w_tx_data_io[0]
|
|
.sym 16097 i_rst_b$SB_IO_IN
|
|
.sym 16098 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 16099 i_button_SB_LUT4_I0_O[1]
|
|
.sym 16106 w_tx_data_io[1]
|
|
.sym 16110 w_tx_data_io[7]
|
|
.sym 16125 w_cs[0]
|
|
.sym 16126 w_rx_data[1]
|
|
.sym 16128 w_rx_data[2]
|
|
.sym 16130 w_rx_data[6]
|
|
.sym 16135 w_fetch
|
|
.sym 16138 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2]
|
|
.sym 16144 w_rx_data[7]
|
|
.sym 16147 w_rx_data[3]
|
|
.sym 16151 w_rx_data[5]
|
|
.sym 16152 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 16153 w_rx_data[4]
|
|
.sym 16159 w_rx_data[6]
|
|
.sym 16165 w_rx_data[3]
|
|
.sym 16171 w_rx_data[2]
|
|
.sym 16178 w_rx_data[5]
|
|
.sym 16185 w_rx_data[7]
|
|
.sym 16188 w_rx_data[1]
|
|
.sym 16194 w_cs[0]
|
|
.sym 16196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2]
|
|
.sym 16197 w_fetch
|
|
.sym 16200 w_rx_data[4]
|
|
.sym 16204 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 16205 r_counter_$glb_clk
|
|
.sym 16206 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 16207 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
|
|
.sym 16208 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
|
|
.sym 16209 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
|
|
.sym 16212 w_tx_data_io[5]
|
|
.sym 16213 i_button_SB_LUT4_I0_O[2]
|
|
.sym 16214 w_tx_data_io[7]
|
|
.sym 16219 w_cs[1]
|
|
.sym 16221 i_rst_b$SB_IO_IN
|
|
.sym 16226 w_rx_data[6]
|
|
.sym 16232 i_config[3]$SB_IO_IN
|
|
.sym 16238 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 16262 w_rx_data[0]
|
|
.sym 16266 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 16318 w_rx_data[0]
|
|
.sym 16327 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 16328 r_counter_$glb_clk
|
|
.sym 16329 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 16334 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 16354 i_button$SB_IO_IN
|
|
.sym 16361 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E
|
|
.sym 16371 i_glob_clock$SB_IO_IN
|
|
.sym 16400 r_counter
|
|
.sym 16437 r_counter
|
|
.sym 16451 i_glob_clock$SB_IO_IN
|
|
.sym 16452 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 16453 i_config[3]$SB_IO_IN
|
|
.sym 16455 i_button$SB_IO_IN
|
|
.sym 16479 w_rx_data[5]
|
|
.sym 16497 r_counter
|
|
.sym 16512 r_counter
|
|
.sym 16554 tx_fifo.wr_addr_gray_rd[6]
|
|
.sym 16560 tx_fifo.wr_addr_gray_rd[0]
|
|
.sym 16585 i_smi_soe_se$SB_IO_IN
|
|
.sym 16586 $PACKER_VCC_NET
|
|
.sym 16587 w_smi_data_input[7]
|
|
.sym 16596 i_smi_soe_se$SB_IO_IN
|
|
.sym 16599 i_smi_swe_srw$SB_IO_IN
|
|
.sym 16600 tx_fifo.wr_addr_gray_rd[4]
|
|
.sym 16606 i_rst_b$SB_IO_IN
|
|
.sym 16612 tx_fifo.wr_addr_gray[4]
|
|
.sym 16618 tx_fifo.wr_addr_gray_rd[0]
|
|
.sym 16620 tx_fifo.wr_addr_gray_rd[6]
|
|
.sym 16635 tx_fifo.wr_addr_gray_rd[6]
|
|
.sym 16648 tx_fifo.wr_addr_gray_rd[0]
|
|
.sym 16652 i_smi_swe_srw$SB_IO_IN
|
|
.sym 16654 i_rst_b$SB_IO_IN
|
|
.sym 16658 tx_fifo.wr_addr_gray[4]
|
|
.sym 16667 tx_fifo.wr_addr_gray_rd[4]
|
|
.sym 16670 i_smi_soe_se$SB_IO_IN
|
|
.sym 16671 i_rst_b$SB_IO_IN
|
|
.sym 16675 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 16681 tx_fifo.wr_addr_gray[0]
|
|
.sym 16682 tx_fifo.wr_addr_gray[4]
|
|
.sym 16683 tx_fifo.wr_addr[6]
|
|
.sym 16684 tx_fifo.wr_addr[7]
|
|
.sym 16685 tx_fifo.wr_addr[4]
|
|
.sym 16686 tx_fifo.wr_addr[3]
|
|
.sym 16687 tx_fifo.wr_addr[5]
|
|
.sym 16688 tx_fifo.wr_addr_gray[6]
|
|
.sym 16703 smi_ctrl_ins.swe_and_reset
|
|
.sym 16704 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
|
|
.sym 16723 smi_ctrl_ins.swe_and_reset
|
|
.sym 16740 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 16743 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 16751 w_smi_data_output[4]
|
|
.sym 16776 tx_fifo.wr_addr[1]
|
|
.sym 16777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 16778 tx_fifo.wr_addr[4]
|
|
.sym 16779 tx_fifo.wr_addr[3]
|
|
.sym 16780 tx_fifo.wr_addr[0]
|
|
.sym 16784 tx_fifo.wr_addr[6]
|
|
.sym 16785 tx_fifo.wr_addr[7]
|
|
.sym 16788 tx_fifo.wr_addr[5]
|
|
.sym 16790 $nextpnr_ICESTORM_LC_3$O
|
|
.sym 16793 tx_fifo.wr_addr[0]
|
|
.sym 16796 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 16798 tx_fifo.wr_addr[1]
|
|
.sym 16800 tx_fifo.wr_addr[0]
|
|
.sym 16802 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 16804 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 16806 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 16808 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 16811 tx_fifo.wr_addr[3]
|
|
.sym 16812 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 16814 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 16817 tx_fifo.wr_addr[4]
|
|
.sym 16818 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 16820 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 16823 tx_fifo.wr_addr[5]
|
|
.sym 16824 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 16826 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 16828 tx_fifo.wr_addr[6]
|
|
.sym 16830 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 16832 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 16834 tx_fifo.wr_addr[7]
|
|
.sym 16836 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 16840 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 16841 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 16842 tx_fifo.wr_addr[1]
|
|
.sym 16843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 16844 tx_fifo.wr_addr[8]
|
|
.sym 16845 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 16846 tx_fifo.wr_addr[0]
|
|
.sym 16847 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 16853 tx_fifo.wr_addr[5]
|
|
.sym 16865 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 16867 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 16875 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 16876 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 16881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 16882 tx_fifo.wr_addr[9]
|
|
.sym 16883 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 16884 tx_fifo.rd_addr_gray_wr[6]
|
|
.sym 16885 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 16886 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 16888 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 16892 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 16895 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 16896 rx_fifo.wr_addr_gray[0]
|
|
.sym 16903 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 16907 tx_fifo.rd_addr_gray_wr[4]
|
|
.sym 16909 tx_fifo.wr_addr[8]
|
|
.sym 16910 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 16911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 16913 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 16915 tx_fifo.wr_addr[8]
|
|
.sym 16917 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 16920 tx_fifo.wr_addr[9]
|
|
.sym 16923 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 16929 tx_fifo.rd_addr_gray_wr[6]
|
|
.sym 16933 rx_fifo.wr_addr_gray[0]
|
|
.sym 16938 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 16939 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 16940 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 16941 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 16944 tx_fifo.rd_addr_gray_wr[4]
|
|
.sym 16950 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 16952 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 16953 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 16956 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 16957 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 16959 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 16961 r_counter_$glb_clk
|
|
.sym 16963 tx_fifo.wr_addr_gray[8]
|
|
.sym 16964 tx_fifo.full_o_SB_LUT4_I1_O[2]
|
|
.sym 16965 tx_fifo.wr_addr_gray[2]
|
|
.sym 16966 tx_fifo.wr_addr_gray[1]
|
|
.sym 16967 tx_fifo.wr_addr_gray[7]
|
|
.sym 16968 tx_fifo.wr_addr_gray[3]
|
|
.sym 16970 tx_fifo.wr_addr_gray[5]
|
|
.sym 16977 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 16978 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 16979 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 16980 rx_fifo.mem_i.0.1_WDATA_3
|
|
.sym 16981 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 16986 tx_fifo.wr_addr[9]
|
|
.sym 16988 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 16989 tx_fifo.rd_addr[1]
|
|
.sym 16990 o_led1$SB_IO_OUT
|
|
.sym 16993 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 16998 o_led1$SB_IO_OUT
|
|
.sym 17004 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 17005 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 17008 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
|
|
.sym 17009 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 17011 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 17012 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 17013 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 17014 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 17015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 17016 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 17019 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 17020 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
|
|
.sym 17022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 17024 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
|
|
.sym 17025 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 17026 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 17027 w_smi_data_input[7]
|
|
.sym 17029 smi_ctrl_ins.swe_and_reset
|
|
.sym 17030 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 17037 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 17038 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 17039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 17040 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 17045 w_smi_data_input[7]
|
|
.sym 17050 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 17052 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 17061 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 17063 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 17064 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 17067 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 17068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 17069 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 17070 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 17079 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 17080 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
|
|
.sym 17081 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 17082 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
|
|
.sym 17084 smi_ctrl_ins.swe_and_reset
|
|
.sym 17085 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
|
|
.sym 17086 tx_fifo.wr_addr_gray_rd[1]
|
|
.sym 17087 tx_fifo.wr_addr_gray_rd[3]
|
|
.sym 17088 tx_fifo.wr_addr_gray_rd[2]
|
|
.sym 17089 tx_fifo.wr_addr_gray_rd[8]
|
|
.sym 17092 tx_fifo.wr_addr_gray_rd[5]
|
|
.sym 17093 tx_fifo.wr_addr_gray_rd[7]
|
|
.sym 17098 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 17102 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 17112 o_led1$SB_IO_OUT
|
|
.sym 17115 smi_ctrl_ins.swe_and_reset
|
|
.sym 17129 tx_fifo.rd_addr_gray_wr[8]
|
|
.sym 17131 tx_fifo.rd_addr_gray[8]
|
|
.sym 17136 tx_fifo.rd_addr_gray[1]
|
|
.sym 17141 tx_fifo.rd_addr_gray_wr[1]
|
|
.sym 17145 tx_fifo.rd_addr_gray[4]
|
|
.sym 17147 tx_fifo.rd_addr_gray[7]
|
|
.sym 17154 tx_fifo.rd_addr_gray_wr[2]
|
|
.sym 17155 tx_fifo.rd_addr_gray_wr[7]
|
|
.sym 17160 tx_fifo.rd_addr_gray_wr[8]
|
|
.sym 17169 tx_fifo.rd_addr_gray[4]
|
|
.sym 17172 tx_fifo.rd_addr_gray[8]
|
|
.sym 17181 tx_fifo.rd_addr_gray_wr[2]
|
|
.sym 17184 tx_fifo.rd_addr_gray[7]
|
|
.sym 17192 tx_fifo.rd_addr_gray_wr[1]
|
|
.sym 17198 tx_fifo.rd_addr_gray[1]
|
|
.sym 17204 tx_fifo.rd_addr_gray_wr[7]
|
|
.sym 17207 r_counter_$glb_clk
|
|
.sym 17209 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 17214 tx_fifo.rd_addr_gray_wr[0]
|
|
.sym 17221 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 17223 w_rx_fifo_pulled_data[4]
|
|
.sym 17229 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 17232 rx_fifo.wr_addr[9]
|
|
.sym 17240 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 17242 rx_fifo.rd_addr[8]
|
|
.sym 17244 o_led1$SB_IO_OUT
|
|
.sym 17261 tx_fifo.rd_addr[1]
|
|
.sym 17263 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 17264 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.sym 17265 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 17268 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 17292 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 17308 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.sym 17316 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 17326 tx_fifo.rd_addr[1]
|
|
.sym 17329 lvds_tx_inst.r_pulled_SB_LUT4_I3_O
|
|
.sym 17330 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 17331 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 17333 spi_if_ins.spi.r3_rx_done
|
|
.sym 17335 tx_fifo.rd_addr_gray_wr[5]
|
|
.sym 17336 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 17343 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 17345 tx_fifo.wr_addr_gray_rd[9]
|
|
.sym 17346 w_rx_fifo_pulled_data[5]
|
|
.sym 17348 w_rx_fifo_pulled_data[7]
|
|
.sym 17394 tx_fifo.rd_addr_gray[6]
|
|
.sym 17397 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 17445 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 17448 tx_fifo.rd_addr_gray[6]
|
|
.sym 17453 r_counter_$glb_clk
|
|
.sym 17461 spi_if_ins.spi.SCKr[0]
|
|
.sym 17471 w_rx_fifo_pulled_data[30]
|
|
.sym 17473 $PACKER_VCC_NET
|
|
.sym 17476 i_ss$SB_IO_IN
|
|
.sym 17482 o_led1$SB_IO_OUT
|
|
.sym 17487 w_fetch
|
|
.sym 17506 rx_fifo.wr_addr_gray_rd[0]
|
|
.sym 17573 rx_fifo.wr_addr_gray_rd[0]
|
|
.sym 17576 r_counter_$glb_clk
|
|
.sym 17578 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
|
|
.sym 17582 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17584 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 17591 rx_fifo.rd_addr[4]
|
|
.sym 17594 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
|
|
.sym 17598 i_sck$SB_IO_IN
|
|
.sym 17603 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17608 o_led1$SB_IO_OUT
|
|
.sym 17610 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 17621 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 17624 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 17630 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 17632 spi_if_ins.r_tx_byte[7]
|
|
.sym 17635 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
|
|
.sym 17641 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 17664 spi_if_ins.r_tx_byte[7]
|
|
.sym 17666 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 17667 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 17682 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 17683 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 17685 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
|
|
.sym 17698 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 17699 r_counter_$glb_clk
|
|
.sym 17702 o_led1$SB_IO_OUT
|
|
.sym 17703 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 17715 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 17720 spi_if_ins.r_tx_byte[7]
|
|
.sym 17721 w_rx_fifo_empty
|
|
.sym 17727 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 17728 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 17736 o_led1$SB_IO_OUT
|
|
.sym 17746 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17752 i_ss$SB_IO_IN
|
|
.sym 17755 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 17760 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 17764 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17766 spi_if_ins.r_tx_data_valid
|
|
.sym 17777 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17799 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17805 i_ss$SB_IO_IN
|
|
.sym 17807 spi_if_ins.r_tx_data_valid
|
|
.sym 17812 spi_if_ins.r_tx_data_valid
|
|
.sym 17814 i_ss$SB_IO_IN
|
|
.sym 17821 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 17822 r_counter_$glb_clk
|
|
.sym 17823 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 17824 w_ioc[1]
|
|
.sym 17827 w_ioc[4]
|
|
.sym 17828 w_ioc[3]
|
|
.sym 17829 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 17830 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 17831 w_ioc[2]
|
|
.sym 17836 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 17839 w_rx_data[7]
|
|
.sym 17846 w_fetch
|
|
.sym 17847 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 17849 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 17853 w_fetch
|
|
.sym 17855 spi_if_ins.w_rx_data[4]
|
|
.sym 17857 w_ioc[1]
|
|
.sym 17858 i_config[1]$SB_IO_IN
|
|
.sym 17868 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 17870 spi_if_ins.w_rx_data[5]
|
|
.sym 17871 i_rst_b$SB_IO_IN
|
|
.sym 17874 spi_if_ins.w_rx_data[0]
|
|
.sym 17876 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 17877 w_fetch
|
|
.sym 17879 spi_if_ins.w_rx_data[6]
|
|
.sym 17881 w_ioc[1]
|
|
.sym 17889 w_cs[2]
|
|
.sym 17894 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 17895 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 17901 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 17916 spi_if_ins.w_rx_data[5]
|
|
.sym 17918 spi_if_ins.w_rx_data[6]
|
|
.sym 17928 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 17929 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 17930 w_cs[2]
|
|
.sym 17931 w_ioc[1]
|
|
.sym 17936 i_rst_b$SB_IO_IN
|
|
.sym 17937 w_fetch
|
|
.sym 17941 spi_if_ins.w_rx_data[0]
|
|
.sym 17944 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 17945 r_counter_$glb_clk
|
|
.sym 17947 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
|
|
.sym 17948 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 17949 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2]
|
|
.sym 17950 o_led1_SB_DFFER_Q_E
|
|
.sym 17951 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
|
|
.sym 17952 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
|
|
.sym 17953 w_tx_data_io[2]
|
|
.sym 17954 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 17959 spi_if_ins.w_rx_data[3]
|
|
.sym 17960 w_rx_data[5]
|
|
.sym 17964 w_rx_data[4]
|
|
.sym 17966 w_ioc[1]
|
|
.sym 17970 w_rx_data[3]
|
|
.sym 17971 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 17972 w_fetch
|
|
.sym 17973 o_tr_vc2$SB_IO_OUT
|
|
.sym 17976 w_rx_data[0]
|
|
.sym 17977 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 17979 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 17980 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 17981 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 17982 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 17988 w_cs[0]
|
|
.sym 17990 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 17993 w_cs[1]
|
|
.sym 17994 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 17995 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 17996 w_ioc[1]
|
|
.sym 17997 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 18001 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18002 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 18003 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18008 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 18010 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 18012 w_load
|
|
.sym 18013 w_fetch
|
|
.sym 18016 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0]
|
|
.sym 18021 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 18027 w_ioc[1]
|
|
.sym 18029 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18030 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18045 w_cs[0]
|
|
.sym 18047 w_fetch
|
|
.sym 18048 w_load
|
|
.sym 18051 w_ioc[1]
|
|
.sym 18052 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 18053 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0]
|
|
.sym 18054 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18058 w_ioc[1]
|
|
.sym 18059 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 18063 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 18064 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18065 w_cs[1]
|
|
.sym 18066 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 18067 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 18068 r_counter_$glb_clk
|
|
.sym 18069 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R
|
|
.sym 18070 w_tx_data_io[1]
|
|
.sym 18071 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3]
|
|
.sym 18072 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
|
|
.sym 18073 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
|
|
.sym 18074 w_tx_data_io[0]
|
|
.sym 18075 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
|
|
.sym 18076 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 18077 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
|
|
.sym 18078 io_pmod[0]$SB_IO_IN
|
|
.sym 18090 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 18094 io_pmod[1]$SB_IO_IN
|
|
.sym 18097 w_rx_data[2]
|
|
.sym 18099 w_rx_data[1]
|
|
.sym 18102 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 18104 io_pmod[2]$SB_IO_IN
|
|
.sym 18105 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 18112 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 18114 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18115 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0]
|
|
.sym 18117 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 18120 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3]
|
|
.sym 18122 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 18123 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 18126 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 18127 w_ioc[1]
|
|
.sym 18130 i_config[1]$SB_IO_IN
|
|
.sym 18133 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 18137 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18139 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 18141 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 18142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18145 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 18146 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0]
|
|
.sym 18156 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 18157 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 18159 i_config[1]$SB_IO_IN
|
|
.sym 18163 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 18165 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18168 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18169 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 18170 w_ioc[1]
|
|
.sym 18174 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 18175 w_ioc[1]
|
|
.sym 18176 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18177 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18180 w_ioc[1]
|
|
.sym 18181 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18182 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18186 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 18187 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3]
|
|
.sym 18188 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18189 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 18190 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 18191 r_counter_$glb_clk
|
|
.sym 18193 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 18194 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2]
|
|
.sym 18195 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 18196 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E
|
|
.sym 18197 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
|
|
.sym 18198 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 18199 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 18200 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0]
|
|
.sym 18205 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2_SB_DFFER_Q_1_E
|
|
.sym 18206 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 18214 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 18220 i_button_SB_LUT4_I0_O[1]
|
|
.sym 18226 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 18234 w_rx_data[6]
|
|
.sym 18237 i_button_SB_LUT4_I0_O[1]
|
|
.sym 18239 w_rx_data[7]
|
|
.sym 18242 w_ioc[1]
|
|
.sym 18243 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 18245 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 18246 w_rx_data[4]
|
|
.sym 18247 w_cs[1]
|
|
.sym 18248 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 18249 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18250 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 18251 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 18252 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18253 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18255 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 18259 w_rx_data[1]
|
|
.sym 18265 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 18267 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 18268 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18269 w_cs[1]
|
|
.sym 18270 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 18273 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 18274 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 18275 i_button_SB_LUT4_I0_O[1]
|
|
.sym 18276 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 18282 w_rx_data[7]
|
|
.sym 18285 w_ioc[1]
|
|
.sym 18286 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18287 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 18288 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18291 w_rx_data[1]
|
|
.sym 18297 w_ioc[1]
|
|
.sym 18298 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 18300 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 18303 w_rx_data[6]
|
|
.sym 18311 w_rx_data[4]
|
|
.sym 18313 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 18314 r_counter_$glb_clk
|
|
.sym 18317 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1]
|
|
.sym 18321 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 18322 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 18328 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E
|
|
.sym 18332 w_load
|
|
.sym 18345 i_config[2]$SB_IO_IN
|
|
.sym 18349 i_config[1]$SB_IO_IN
|
|
.sym 18359 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 18360 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18361 i_config[2]$SB_IO_IN
|
|
.sym 18362 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 18363 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 18368 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 18369 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 18370 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 18372 o_tr_vc1$SB_IO_OUT
|
|
.sym 18373 i_config[3]$SB_IO_IN
|
|
.sym 18374 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
|
|
.sym 18375 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
|
|
.sym 18377 i_button$SB_IO_IN
|
|
.sym 18380 i_button_SB_LUT4_I0_O[1]
|
|
.sym 18383 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 18384 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E
|
|
.sym 18387 i_button_SB_LUT4_I0_O[2]
|
|
.sym 18390 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
|
|
.sym 18391 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 18393 i_button_SB_LUT4_I0_O[1]
|
|
.sym 18396 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 18397 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 18398 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18399 i_config[2]$SB_IO_IN
|
|
.sym 18402 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 18403 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18404 i_config[3]$SB_IO_IN
|
|
.sym 18405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 18420 i_button_SB_LUT4_I0_O[1]
|
|
.sym 18421 o_tr_vc1$SB_IO_OUT
|
|
.sym 18422 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
|
|
.sym 18426 i_button$SB_IO_IN
|
|
.sym 18427 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 18428 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 18429 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 18432 i_button_SB_LUT4_I0_O[1]
|
|
.sym 18434 i_button_SB_LUT4_I0_O[2]
|
|
.sym 18435 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 18436 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E
|
|
.sym 18437 r_counter_$glb_clk
|
|
.sym 18451 w_rx_data[0]
|
|
.sym 18452 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 18456 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 18460 o_tr_vc1$SB_IO_OUT
|
|
.sym 18469 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 18471 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 18482 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 18506 w_rx_data[5]
|
|
.sym 18538 w_rx_data[5]
|
|
.sym 18559 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 18560 r_counter_$glb_clk
|
|
.sym 18562 i_config[1]$SB_IO_IN
|
|
.sym 18564 i_config[2]$SB_IO_IN
|
|
.sym 18636 w_smi_data_output[4]
|
|
.sym 18638 o_led0$SB_IO_OUT
|
|
.sym 18642 $PACKER_VCC_NET
|
|
.sym 18645 w_smi_data_output[4]
|
|
.sym 18648 o_led0$SB_IO_OUT
|
|
.sym 18658 $PACKER_VCC_NET
|
|
.sym 18687 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 18691 tx_fifo.wr_addr[1]
|
|
.sym 18694 o_miso_$_TBUF__Y_E
|
|
.sym 18696 o_led0$SB_IO_OUT
|
|
.sym 18703 tx_fifo.wr_addr_gray[0]
|
|
.sym 18710 tx_fifo.wr_addr_gray[6]
|
|
.sym 18744 tx_fifo.wr_addr_gray[6]
|
|
.sym 18779 tx_fifo.wr_addr_gray[0]
|
|
.sym 18783 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 18785 i_smi_soe_se$SB_IO_IN
|
|
.sym 18815 $PACKER_VCC_NET
|
|
.sym 18846 rx_fifo.wr_addr[4]
|
|
.sym 18847 w_smi_data_output[5]
|
|
.sym 18853 tx_fifo.wr_addr[1]
|
|
.sym 18854 rx_fifo.wr_addr[6]
|
|
.sym 18855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 18868 tx_fifo.wr_addr[1]
|
|
.sym 18871 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 18872 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 18877 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 18878 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 18881 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 18893 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 18899 tx_fifo.wr_addr[1]
|
|
.sym 18905 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 18907 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 18911 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 18920 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 18926 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 18930 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 18938 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 18942 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 18944 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 18945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 18946 r_counter_$glb_clk
|
|
.sym 18947 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 18949 w_rx_fifo_pulled_data[20]
|
|
.sym 18953 w_rx_fifo_pulled_data[22]
|
|
.sym 18962 tx_fifo.wr_addr[3]
|
|
.sym 18966 tx_fifo.wr_addr[6]
|
|
.sym 18968 tx_fifo.wr_addr[7]
|
|
.sym 18970 tx_fifo.wr_addr[4]
|
|
.sym 18978 rx_fifo.rd_addr[6]
|
|
.sym 18979 rx_fifo.rd_addr[2]
|
|
.sym 18980 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 18982 rx_fifo.rd_addr[9]
|
|
.sym 18983 $PACKER_VCC_NET
|
|
.sym 18989 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 18991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 18995 tx_fifo.wr_addr[0]
|
|
.sym 18999 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 19006 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 19007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 19008 i_rst_b$SB_IO_IN
|
|
.sym 19011 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 19012 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 19015 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 19016 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 19017 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 19018 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 19019 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 19022 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 19025 i_rst_b$SB_IO_IN
|
|
.sym 19028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 19029 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 19030 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 19035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 19042 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 19048 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 19054 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 19055 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 19058 tx_fifo.wr_addr[0]
|
|
.sym 19064 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 19067 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 19068 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 19069 r_counter_$glb_clk
|
|
.sym 19070 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 19072 w_rx_fifo_pulled_data[21]
|
|
.sym 19076 w_rx_fifo_pulled_data[23]
|
|
.sym 19081 o_led1_SB_DFFER_Q_E
|
|
.sym 19095 rx_fifo.wr_addr[5]
|
|
.sym 19096 tx_fifo.wr_addr[1]
|
|
.sym 19098 rx_fifo.wr_addr[4]
|
|
.sym 19100 rx_fifo.wr_addr[7]
|
|
.sym 19102 rx_fifo.wr_addr[6]
|
|
.sym 19104 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 19105 o_led1$SB_IO_OUT
|
|
.sym 19117 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 19119 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 19122 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 19123 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 19125 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 19127 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 19128 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 19136 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 19137 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 19141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 19147 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 19148 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 19151 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 19152 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 19153 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 19154 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 19157 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 19165 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 19169 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 19170 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 19175 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 19189 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 19191 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 19192 r_counter_$glb_clk
|
|
.sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 19195 w_rx_fifo_pulled_data[4]
|
|
.sym 19199 w_rx_fifo_pulled_data[6]
|
|
.sym 19206 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 19207 rx_fifo.rd_addr[4]
|
|
.sym 19208 rx_fifo.mem_i.0.1_WDATA_1
|
|
.sym 19209 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 19210 tx_fifo.full_o_SB_LUT4_I1_O[2]
|
|
.sym 19214 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 19215 w_rx_fifo_pulled_data[21]
|
|
.sym 19216 rx_fifo.rd_addr[8]
|
|
.sym 19219 rx_fifo.wr_addr[0]
|
|
.sym 19221 o_led1$SB_IO_OUT
|
|
.sym 19222 rx_fifo.mem_i.0.1_WDATA
|
|
.sym 19223 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 19227 rx_fifo.wr_addr[1]
|
|
.sym 19228 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 19235 tx_fifo.wr_addr_gray[8]
|
|
.sym 19238 tx_fifo.wr_addr_gray[1]
|
|
.sym 19239 tx_fifo.wr_addr_gray[7]
|
|
.sym 19245 tx_fifo.wr_addr_gray[2]
|
|
.sym 19248 tx_fifo.wr_addr_gray[3]
|
|
.sym 19250 tx_fifo.wr_addr_gray[5]
|
|
.sym 19271 tx_fifo.wr_addr_gray[1]
|
|
.sym 19275 tx_fifo.wr_addr_gray[3]
|
|
.sym 19281 tx_fifo.wr_addr_gray[2]
|
|
.sym 19287 tx_fifo.wr_addr_gray[8]
|
|
.sym 19306 tx_fifo.wr_addr_gray[5]
|
|
.sym 19313 tx_fifo.wr_addr_gray[7]
|
|
.sym 19315 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 19318 w_rx_fifo_pulled_data[5]
|
|
.sym 19322 w_rx_fifo_pulled_data[7]
|
|
.sym 19325 tx_fifo.wr_addr[1]
|
|
.sym 19330 rx_fifo.wr_addr[8]
|
|
.sym 19333 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 19344 rx_fifo.rd_addr[0]
|
|
.sym 19346 rx_fifo.wr_addr[6]
|
|
.sym 19351 rx_fifo.rd_addr[6]
|
|
.sym 19361 tx_fifo.rd_addr_gray_wr[5]
|
|
.sym 19365 tx_fifo.rd_addr_gray[0]
|
|
.sym 19394 tx_fifo.rd_addr_gray_wr[5]
|
|
.sym 19421 tx_fifo.rd_addr_gray[0]
|
|
.sym 19438 r_counter_$glb_clk
|
|
.sym 19441 w_rx_fifo_pulled_data[28]
|
|
.sym 19445 w_rx_fifo_pulled_data[30]
|
|
.sym 19454 tx_fifo.rd_addr_gray_wr[0]
|
|
.sym 19459 rx_fifo.rd_addr[1]
|
|
.sym 19460 rx_fifo.rd_addr[7]
|
|
.sym 19461 rx_fifo.rd_addr[0]
|
|
.sym 19464 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 19465 rx_fifo.mem_i.0.3_WDATA
|
|
.sym 19466 rx_fifo.rd_addr[9]
|
|
.sym 19467 rx_fifo.mem_q.0.1_WDATA
|
|
.sym 19470 $PACKER_VCC_NET
|
|
.sym 19472 rx_fifo.mem_q.0.1_WDATA_1
|
|
.sym 19474 rx_fifo.rd_addr[2]
|
|
.sym 19475 rx_fifo.mem_i.0.3_WDATA_1
|
|
.sym 19498 spi_if_ins.spi.r3_rx_done
|
|
.sym 19506 spi_if_ins.spi.r2_rx_done
|
|
.sym 19510 tx_fifo.rd_addr_gray[5]
|
|
.sym 19521 spi_if_ins.spi.r2_rx_done
|
|
.sym 19533 tx_fifo.rd_addr_gray[5]
|
|
.sym 19538 spi_if_ins.spi.r2_rx_done
|
|
.sym 19539 spi_if_ins.spi.r3_rx_done
|
|
.sym 19561 r_counter_$glb_clk
|
|
.sym 19564 w_rx_fifo_pulled_data[29]
|
|
.sym 19568 w_rx_fifo_pulled_data[31]
|
|
.sym 19583 rx_fifo.wr_addr[4]
|
|
.sym 19588 rx_fifo.rd_addr[3]
|
|
.sym 19589 o_led1$SB_IO_OUT
|
|
.sym 19592 rx_fifo.wr_addr[7]
|
|
.sym 19593 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 19615 i_sck$SB_IO_IN
|
|
.sym 19673 i_sck$SB_IO_IN
|
|
.sym 19684 r_counter_$glb_clk
|
|
.sym 19699 rx_fifo.rd_addr[6]
|
|
.sym 19705 rx_fifo.rd_addr[8]
|
|
.sym 19710 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 19715 rx_fifo.wr_addr[0]
|
|
.sym 19717 o_led1$SB_IO_OUT
|
|
.sym 19736 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 19741 spi_if_ins.spi.SCKr[0]
|
|
.sym 19757 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 19761 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 19784 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 19799 spi_if_ins.spi.SCKr[0]
|
|
.sym 19807 r_counter_$glb_clk
|
|
.sym 19821 spi_if_ins.w_rx_data[4]
|
|
.sym 19825 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 19833 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
|
|
.sym 19854 w_rx_data[0]
|
|
.sym 19862 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 19868 o_led1_SB_DFFER_Q_E
|
|
.sym 19871 i_rst_b$SB_IO_IN
|
|
.sym 19881 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 19892 w_rx_data[0]
|
|
.sym 19896 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 19897 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 19898 i_rst_b$SB_IO_IN
|
|
.sym 19929 o_led1_SB_DFFER_Q_E
|
|
.sym 19930 r_counter_$glb_clk
|
|
.sym 19931 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 19950 w_rx_data[0]
|
|
.sym 19960 spi_if_ins.w_rx_data[1]
|
|
.sym 19964 spi_if_ins.w_rx_data[2]
|
|
.sym 19967 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 19975 spi_if_ins.w_rx_data[2]
|
|
.sym 19976 w_ioc[4]
|
|
.sym 19977 w_ioc[3]
|
|
.sym 19978 spi_if_ins.w_rx_data[3]
|
|
.sym 19984 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 19986 spi_if_ins.w_rx_data[1]
|
|
.sym 19995 spi_if_ins.w_rx_data[4]
|
|
.sym 20004 w_ioc[2]
|
|
.sym 20006 spi_if_ins.w_rx_data[1]
|
|
.sym 20025 spi_if_ins.w_rx_data[4]
|
|
.sym 20031 spi_if_ins.w_rx_data[3]
|
|
.sym 20036 w_ioc[4]
|
|
.sym 20037 w_ioc[2]
|
|
.sym 20039 w_ioc[3]
|
|
.sym 20042 w_ioc[2]
|
|
.sym 20044 w_ioc[3]
|
|
.sym 20045 w_ioc[4]
|
|
.sym 20051 spi_if_ins.w_rx_data[2]
|
|
.sym 20052 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 20053 r_counter_$glb_clk
|
|
.sym 20068 io_pmod[1]$SB_IO_IN
|
|
.sym 20069 w_rx_data[1]
|
|
.sym 20070 spi_if_ins.o_ioc_SB_DFFE_Q_E
|
|
.sym 20072 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 20074 io_pmod[2]$SB_IO_IN
|
|
.sym 20075 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 20077 w_rx_data[2]
|
|
.sym 20079 io_pmod[3]$SB_IO_IN
|
|
.sym 20096 w_ioc[1]
|
|
.sym 20097 w_fetch
|
|
.sym 20098 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
|
|
.sym 20099 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 20100 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
|
|
.sym 20101 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 20103 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 20104 w_load
|
|
.sym 20105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 20106 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
|
|
.sym 20107 io_pmod[0]$SB_IO_IN
|
|
.sym 20109 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 20110 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 20116 io_pmod[1]$SB_IO_IN
|
|
.sym 20118 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20119 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20123 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20125 w_cs[2]
|
|
.sym 20127 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20129 w_cs[2]
|
|
.sym 20130 w_fetch
|
|
.sym 20131 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20132 w_load
|
|
.sym 20136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
|
|
.sym 20138 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20141 io_pmod[0]$SB_IO_IN
|
|
.sym 20142 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20144 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 20147 w_fetch
|
|
.sym 20148 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20149 w_load
|
|
.sym 20150 w_cs[2]
|
|
.sym 20153 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 20154 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20156 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 20159 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 20160 w_ioc[1]
|
|
.sym 20161 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20166 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 20167 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 20168 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
|
|
.sym 20171 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 20172 io_pmod[1]$SB_IO_IN
|
|
.sym 20173 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 20174 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
|
|
.sym 20176 r_counter_$glb_clk
|
|
.sym 20177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
|
|
.sym 20192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_E
|
|
.sym 20194 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 20198 o_led0$SB_IO_OUT
|
|
.sym 20200 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20202 w_rx_data[3]
|
|
.sym 20203 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 20208 w_rx_data[1]
|
|
.sym 20209 o_led1$SB_IO_OUT
|
|
.sym 20210 w_cs[1]
|
|
.sym 20211 w_cs[2]
|
|
.sym 20219 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 20220 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2]
|
|
.sym 20221 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 20222 i_button_SB_LUT4_I0_O[1]
|
|
.sym 20223 w_fetch
|
|
.sym 20224 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 20226 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20227 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 20228 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3]
|
|
.sym 20229 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2]
|
|
.sym 20230 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 20231 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
|
|
.sym 20232 io_ctrl_ins.mixer_en_state
|
|
.sym 20233 o_tr_vc2$SB_IO_OUT
|
|
.sym 20234 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 20236 w_cs[1]
|
|
.sym 20237 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 20238 io_pmod[2]$SB_IO_IN
|
|
.sym 20239 io_pmod[3]$SB_IO_IN
|
|
.sym 20240 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20241 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 20243 w_load
|
|
.sym 20244 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 20245 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 20248 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 20249 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 20250 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
|
|
.sym 20252 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 20253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 20254 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 20255 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 20259 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 20260 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2]
|
|
.sym 20261 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 20264 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
|
|
.sym 20265 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
|
|
.sym 20267 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20270 w_load
|
|
.sym 20271 w_fetch
|
|
.sym 20272 w_cs[1]
|
|
.sym 20273 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 20276 io_ctrl_ins.mixer_en_state
|
|
.sym 20277 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2]
|
|
.sym 20278 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3]
|
|
.sym 20279 i_button_SB_LUT4_I0_O[1]
|
|
.sym 20282 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 20283 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 20284 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 20285 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 20288 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 20289 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20290 io_pmod[3]$SB_IO_IN
|
|
.sym 20291 o_tr_vc2$SB_IO_OUT
|
|
.sym 20294 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 20295 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 20296 io_pmod[2]$SB_IO_IN
|
|
.sym 20297 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 20298 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 20299 r_counter_$glb_clk
|
|
.sym 20300 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 20313 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 20318 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 20320 io_ctrl_ins.mixer_en_state
|
|
.sym 20323 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 20329 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 20342 w_fetch
|
|
.sym 20343 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1]
|
|
.sym 20344 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 20346 w_rx_data[0]
|
|
.sym 20347 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20349 w_rx_data[2]
|
|
.sym 20354 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
|
|
.sym 20355 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 20357 w_load
|
|
.sym 20360 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 20362 w_rx_data[3]
|
|
.sym 20364 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20367 i_config[0]$SB_IO_IN
|
|
.sym 20368 i_rst_b$SB_IO_IN
|
|
.sym 20370 w_cs[1]
|
|
.sym 20372 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20373 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0]
|
|
.sym 20375 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20376 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
|
|
.sym 20377 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 20378 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20381 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1]
|
|
.sym 20382 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20383 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20384 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0]
|
|
.sym 20389 w_rx_data[3]
|
|
.sym 20393 w_cs[1]
|
|
.sym 20394 w_fetch
|
|
.sym 20395 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20396 w_load
|
|
.sym 20402 w_rx_data[2]
|
|
.sym 20405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20406 i_config[0]$SB_IO_IN
|
|
.sym 20407 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 20408 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 20411 w_load
|
|
.sym 20412 i_rst_b$SB_IO_IN
|
|
.sym 20413 w_fetch
|
|
.sym 20414 w_cs[1]
|
|
.sym 20418 w_rx_data[0]
|
|
.sym 20421 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 20422 r_counter_$glb_clk
|
|
.sym 20437 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 20440 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
|
|
.sym 20441 o_tr_vc2$SB_IO_OUT
|
|
.sym 20445 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 20453 i_config[0]$SB_IO_IN
|
|
.sym 20471 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 20476 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E
|
|
.sym 20478 w_rx_data[0]
|
|
.sym 20480 w_rx_data[1]
|
|
.sym 20486 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20507 w_rx_data[0]
|
|
.sym 20531 w_rx_data[1]
|
|
.sym 20536 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 20537 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 20544 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1_SB_DFFER_Q_E
|
|
.sym 20545 r_counter_$glb_clk
|
|
.sym 20546 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 20672 i_config[0]$SB_IO_IN
|
|
.sym 20698 o_led1$SB_IO_OUT
|
|
.sym 20748 w_smi_data_output[5]
|
|
.sym 20750 o_led0$SB_IO_OUT
|
|
.sym 20751 $PACKER_VCC_NET
|
|
.sym 20756 $PACKER_VCC_NET
|
|
.sym 20766 w_smi_data_output[5]
|
|
.sym 20769 o_led0$SB_IO_OUT
|
|
.sym 20771 smi_ctrl_ins.tx_reg_state[2]
|
|
.sym 20772 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 20773 smi_ctrl_ins.tx_reg_state[1]
|
|
.sym 20774 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 20775 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 20776 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R
|
|
.sym 20777 smi_ctrl_ins.tx_reg_state[3]
|
|
.sym 20844 i_mosi$SB_IO_IN
|
|
.sym 20847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
|
|
.sym 20848 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 20849 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 20850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 20851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 20852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
|
|
.sym 20853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 20888 w_smi_data_input[7]
|
|
.sym 20912 int_miso
|
|
.sym 20924 tx_fifo.wr_addr[8]
|
|
.sym 20927 i_rst_b$SB_IO_IN
|
|
.sym 20941 rx_fifo.wr_addr[9]
|
|
.sym 20984 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
|
|
.sym 20985 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 20986 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 20987 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
|
|
.sym 20988 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
|
|
.sym 20989 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
|
|
.sym 20990 tx_fifo.wr_addr[9]
|
|
.sym 20991 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 21026 tx_fifo.wr_addr[1]
|
|
.sym 21033 tx_fifo.wr_addr[1]
|
|
.sym 21039 rx_fifo.rd_addr[5]
|
|
.sym 21040 rx_fifo.rd_addr[1]
|
|
.sym 21043 $PACKER_VCC_NET
|
|
.sym 21044 rx_fifo.rd_addr[3]
|
|
.sym 21045 int_miso
|
|
.sym 21046 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 21047 $PACKER_VCC_NET
|
|
.sym 21048 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 21056 rx_fifo.mem_i.0.1_WDATA_2
|
|
.sym 21058 $PACKER_VCC_NET
|
|
.sym 21060 rx_fifo.wr_addr[6]
|
|
.sym 21063 rx_fifo.wr_addr[1]
|
|
.sym 21065 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21067 rx_fifo.wr_addr[8]
|
|
.sym 21068 rx_fifo.wr_addr[3]
|
|
.sym 21069 rx_fifo.wr_addr[4]
|
|
.sym 21071 rx_fifo.wr_addr[7]
|
|
.sym 21077 rx_fifo.wr_addr[0]
|
|
.sym 21081 rx_fifo.mem_i.0.1_WDATA_3
|
|
.sym 21082 rx_fifo.wr_addr[5]
|
|
.sym 21083 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 21084 rx_fifo.wr_addr[9]
|
|
.sym 21086 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 21087 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
|
|
.sym 21088 tx_fifo.full_o_SB_LUT4_I1_O[1]
|
|
.sym 21089 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1]
|
|
.sym 21090 tx_fifo.wr_addr_gray_rd[9]
|
|
.sym 21091 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 21092 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0]
|
|
.sym 21093 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 21102 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 21103 rx_fifo.wr_addr[3]
|
|
.sym 21105 rx_fifo.wr_addr[4]
|
|
.sym 21106 rx_fifo.wr_addr[5]
|
|
.sym 21107 rx_fifo.wr_addr[6]
|
|
.sym 21108 rx_fifo.wr_addr[7]
|
|
.sym 21109 rx_fifo.wr_addr[8]
|
|
.sym 21110 rx_fifo.wr_addr[9]
|
|
.sym 21111 rx_fifo.wr_addr[1]
|
|
.sym 21112 rx_fifo.wr_addr[0]
|
|
.sym 21113 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 21114 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21116 rx_fifo.mem_i.0.1_WDATA_3
|
|
.sym 21120 rx_fifo.mem_i.0.1_WDATA_2
|
|
.sym 21123 $PACKER_VCC_NET
|
|
.sym 21129 rx_fifo.wr_addr[1]
|
|
.sym 21131 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21132 rx_fifo.mem_i.0.1_WDATA_2
|
|
.sym 21136 rx_fifo.wr_addr[3]
|
|
.sym 21139 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 21140 $PACKER_VCC_NET
|
|
.sym 21141 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 21146 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 21150 rx_fifo.wr_addr[3]
|
|
.sym 21151 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21157 rx_fifo.rd_addr[0]
|
|
.sym 21158 rx_fifo.rd_addr[6]
|
|
.sym 21160 rx_fifo.rd_addr[4]
|
|
.sym 21164 rx_fifo.rd_addr[7]
|
|
.sym 21167 rx_fifo.rd_addr[2]
|
|
.sym 21169 rx_fifo.rd_addr[8]
|
|
.sym 21170 rx_fifo.rd_addr[9]
|
|
.sym 21171 rx_fifo.mem_i.0.1_WDATA_1
|
|
.sym 21172 rx_fifo.mem_i.0.1_WDATA
|
|
.sym 21174 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21177 rx_fifo.rd_addr[5]
|
|
.sym 21178 rx_fifo.rd_addr[1]
|
|
.sym 21182 rx_fifo.rd_addr[3]
|
|
.sym 21185 $PACKER_VCC_NET
|
|
.sym 21190 tx_fifo.full_o_SB_LUT4_I1_O[0]
|
|
.sym 21192 w_tx_fifo_full
|
|
.sym 21193 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 21195 smi_ctrl_ins.r_fifo_push_1
|
|
.sym 21204 rx_fifo.rd_addr[2]
|
|
.sym 21205 rx_fifo.rd_addr[3]
|
|
.sym 21207 rx_fifo.rd_addr[4]
|
|
.sym 21208 rx_fifo.rd_addr[5]
|
|
.sym 21209 rx_fifo.rd_addr[6]
|
|
.sym 21210 rx_fifo.rd_addr[7]
|
|
.sym 21211 rx_fifo.rd_addr[8]
|
|
.sym 21212 rx_fifo.rd_addr[9]
|
|
.sym 21213 rx_fifo.rd_addr[1]
|
|
.sym 21214 rx_fifo.rd_addr[0]
|
|
.sym 21215 r_counter_$glb_clk
|
|
.sym 21216 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21217 $PACKER_VCC_NET
|
|
.sym 21221 rx_fifo.mem_i.0.1_WDATA
|
|
.sym 21225 rx_fifo.mem_i.0.1_WDATA_1
|
|
.sym 21232 w_rx_fifo_pulled_data[23]
|
|
.sym 21234 tx_fifo.wr_addr[1]
|
|
.sym 21236 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 21240 rx_fifo.rd_addr[7]
|
|
.sym 21241 rx_fifo.rd_addr[0]
|
|
.sym 21242 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 21245 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 21248 tx_fifo.rd_addr_gray_wr[9]
|
|
.sym 21250 spi_if_ins.spi.r2_rx_done
|
|
.sym 21259 rx_fifo.wr_addr[7]
|
|
.sym 21260 rx_fifo.mem_q.0.1_WDATA_3
|
|
.sym 21262 rx_fifo.wr_addr[8]
|
|
.sym 21267 rx_fifo.mem_q.0.1_WDATA_2
|
|
.sym 21269 rx_fifo.wr_addr[6]
|
|
.sym 21270 rx_fifo.wr_addr[5]
|
|
.sym 21271 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 21273 rx_fifo.wr_addr[4]
|
|
.sym 21274 rx_fifo.wr_addr[1]
|
|
.sym 21275 rx_fifo.wr_addr[9]
|
|
.sym 21278 $PACKER_VCC_NET
|
|
.sym 21282 rx_fifo.wr_addr[0]
|
|
.sym 21285 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21288 rx_fifo.wr_addr[3]
|
|
.sym 21290 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 21291 o_smi_read_req$SB_IO_OUT
|
|
.sym 21292 spi_if_ins.spi.r2_rx_done
|
|
.sym 21296 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 21306 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 21307 rx_fifo.wr_addr[3]
|
|
.sym 21309 rx_fifo.wr_addr[4]
|
|
.sym 21310 rx_fifo.wr_addr[5]
|
|
.sym 21311 rx_fifo.wr_addr[6]
|
|
.sym 21312 rx_fifo.wr_addr[7]
|
|
.sym 21313 rx_fifo.wr_addr[8]
|
|
.sym 21314 rx_fifo.wr_addr[9]
|
|
.sym 21315 rx_fifo.wr_addr[1]
|
|
.sym 21316 rx_fifo.wr_addr[0]
|
|
.sym 21317 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 21318 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21320 rx_fifo.mem_q.0.1_WDATA_3
|
|
.sym 21324 rx_fifo.mem_q.0.1_WDATA_2
|
|
.sym 21327 $PACKER_VCC_NET
|
|
.sym 21336 rx_fifo.mem_q.0.1_WDATA_3
|
|
.sym 21343 rx_fifo.mem_q.0.1_WDATA_2
|
|
.sym 21348 rx_fifo.wr_addr[9]
|
|
.sym 21349 smi_ctrl_ins.r_fifo_push
|
|
.sym 21355 rx_fifo.wr_addr[8]
|
|
.sym 21360 rx_fifo.rd_addr[1]
|
|
.sym 21362 rx_fifo.rd_addr[8]
|
|
.sym 21363 rx_fifo.rd_addr[7]
|
|
.sym 21368 rx_fifo.rd_addr[3]
|
|
.sym 21369 rx_fifo.rd_addr[2]
|
|
.sym 21370 rx_fifo.rd_addr[0]
|
|
.sym 21373 rx_fifo.rd_addr[4]
|
|
.sym 21378 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21380 rx_fifo.mem_q.0.1_WDATA_1
|
|
.sym 21381 rx_fifo.rd_addr[5]
|
|
.sym 21387 rx_fifo.rd_addr[6]
|
|
.sym 21389 $PACKER_VCC_NET
|
|
.sym 21390 rx_fifo.rd_addr[9]
|
|
.sym 21391 rx_fifo.mem_q.0.1_WDATA
|
|
.sym 21393 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 21395 o_miso_$_TBUF__Y_E
|
|
.sym 21396 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 21408 rx_fifo.rd_addr[2]
|
|
.sym 21409 rx_fifo.rd_addr[3]
|
|
.sym 21411 rx_fifo.rd_addr[4]
|
|
.sym 21412 rx_fifo.rd_addr[5]
|
|
.sym 21413 rx_fifo.rd_addr[6]
|
|
.sym 21414 rx_fifo.rd_addr[7]
|
|
.sym 21415 rx_fifo.rd_addr[8]
|
|
.sym 21416 rx_fifo.rd_addr[9]
|
|
.sym 21417 rx_fifo.rd_addr[1]
|
|
.sym 21418 rx_fifo.rd_addr[0]
|
|
.sym 21419 r_counter_$glb_clk
|
|
.sym 21420 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21421 $PACKER_VCC_NET
|
|
.sym 21425 rx_fifo.mem_q.0.1_WDATA
|
|
.sym 21429 rx_fifo.mem_q.0.1_WDATA_1
|
|
.sym 21434 rx_fifo.rd_addr[3]
|
|
.sym 21435 rx_fifo.rd_addr[2]
|
|
.sym 21438 rx_fifo.rd_addr[8]
|
|
.sym 21441 rx_fifo.rd_addr[4]
|
|
.sym 21447 rx_fifo.rd_addr[5]
|
|
.sym 21448 int_miso
|
|
.sym 21455 $PACKER_VCC_NET
|
|
.sym 21456 o_led0$SB_IO_OUT
|
|
.sym 21462 rx_fifo.mem_i.0.3_WDATA_2
|
|
.sym 21463 rx_fifo.wr_addr[5]
|
|
.sym 21464 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21470 rx_fifo.wr_addr[3]
|
|
.sym 21471 rx_fifo.wr_addr[6]
|
|
.sym 21473 rx_fifo.wr_addr[4]
|
|
.sym 21474 rx_fifo.wr_addr[0]
|
|
.sym 21475 rx_fifo.mem_i.0.3_WDATA_3
|
|
.sym 21477 rx_fifo.wr_addr[1]
|
|
.sym 21479 rx_fifo.wr_addr[7]
|
|
.sym 21480 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 21482 $PACKER_VCC_NET
|
|
.sym 21486 rx_fifo.wr_addr[9]
|
|
.sym 21493 rx_fifo.wr_addr[8]
|
|
.sym 21494 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 21495 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 21496 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 21497 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 21498 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 21499 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 21500 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 21501 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 21510 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 21511 rx_fifo.wr_addr[3]
|
|
.sym 21513 rx_fifo.wr_addr[4]
|
|
.sym 21514 rx_fifo.wr_addr[5]
|
|
.sym 21515 rx_fifo.wr_addr[6]
|
|
.sym 21516 rx_fifo.wr_addr[7]
|
|
.sym 21517 rx_fifo.wr_addr[8]
|
|
.sym 21518 rx_fifo.wr_addr[9]
|
|
.sym 21519 rx_fifo.wr_addr[1]
|
|
.sym 21520 rx_fifo.wr_addr[0]
|
|
.sym 21521 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 21522 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21524 rx_fifo.mem_i.0.3_WDATA_3
|
|
.sym 21528 rx_fifo.mem_i.0.3_WDATA_2
|
|
.sym 21531 $PACKER_VCC_NET
|
|
.sym 21536 rx_fifo.mem_i.0.3_WDATA_2
|
|
.sym 21538 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 21542 rx_fifo.wr_addr[0]
|
|
.sym 21543 rx_fifo.mem_i.0.3_WDATA_3
|
|
.sym 21545 rx_fifo.wr_addr[1]
|
|
.sym 21546 rx_fifo.wr_addr[3]
|
|
.sym 21547 rx_fifo.wr_addr[5]
|
|
.sym 21564 rx_fifo.rd_addr[8]
|
|
.sym 21568 rx_fifo.rd_addr[6]
|
|
.sym 21570 rx_fifo.rd_addr[2]
|
|
.sym 21571 rx_fifo.rd_addr[5]
|
|
.sym 21572 rx_fifo.rd_addr[7]
|
|
.sym 21573 rx_fifo.rd_addr[1]
|
|
.sym 21574 rx_fifo.rd_addr[0]
|
|
.sym 21575 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21577 rx_fifo.mem_i.0.3_WDATA
|
|
.sym 21578 rx_fifo.rd_addr[9]
|
|
.sym 21579 rx_fifo.mem_i.0.3_WDATA_1
|
|
.sym 21588 rx_fifo.rd_addr[3]
|
|
.sym 21589 rx_fifo.rd_addr[4]
|
|
.sym 21593 $PACKER_VCC_NET
|
|
.sym 21596 spi_if_ins.w_rx_data[5]
|
|
.sym 21597 spi_if_ins.w_rx_data[6]
|
|
.sym 21598 spi_if_ins.w_rx_data[2]
|
|
.sym 21599 spi_if_ins.w_rx_data[1]
|
|
.sym 21600 spi_if_ins.w_rx_data[4]
|
|
.sym 21601 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 21602 spi_if_ins.w_rx_data[0]
|
|
.sym 21603 spi_if_ins.w_rx_data[3]
|
|
.sym 21612 rx_fifo.rd_addr[2]
|
|
.sym 21613 rx_fifo.rd_addr[3]
|
|
.sym 21615 rx_fifo.rd_addr[4]
|
|
.sym 21616 rx_fifo.rd_addr[5]
|
|
.sym 21617 rx_fifo.rd_addr[6]
|
|
.sym 21618 rx_fifo.rd_addr[7]
|
|
.sym 21619 rx_fifo.rd_addr[8]
|
|
.sym 21620 rx_fifo.rd_addr[9]
|
|
.sym 21621 rx_fifo.rd_addr[1]
|
|
.sym 21622 rx_fifo.rd_addr[0]
|
|
.sym 21623 r_counter_$glb_clk
|
|
.sym 21624 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21625 $PACKER_VCC_NET
|
|
.sym 21629 rx_fifo.mem_i.0.3_WDATA
|
|
.sym 21633 rx_fifo.mem_i.0.3_WDATA_1
|
|
.sym 21634 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 21639 rx_fifo.rd_addr[1]
|
|
.sym 21640 w_rx_fifo_pulled_data[31]
|
|
.sym 21641 rx_fifo.wr_addr[6]
|
|
.sym 21642 w_rx_fifo_pulled_data[29]
|
|
.sym 21643 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 21644 i_glob_clock$SB_IO_IN
|
|
.sym 21647 rx_fifo.rd_addr[5]
|
|
.sym 21648 rx_fifo.rd_addr[7]
|
|
.sym 21652 w_rx_data[7]
|
|
.sym 21653 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 21655 spi_if_ins.w_rx_data[0]
|
|
.sym 21659 spi_if_ins.w_rx_data[5]
|
|
.sym 21661 spi_if_ins.w_rx_data[6]
|
|
.sym 21704 w_rx_data[0]
|
|
.sym 21705 w_rx_data[7]
|
|
.sym 21743 spi_if_ins.w_rx_data[1]
|
|
.sym 21749 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 21751 spi_if_ins.w_rx_data[2]
|
|
.sym 21752 i_glob_clock$SB_IO_IN
|
|
.sym 21756 w_rx_data[2]
|
|
.sym 21757 w_rx_data[0]
|
|
.sym 21800 w_rx_data[2]
|
|
.sym 21801 w_rx_data[1]
|
|
.sym 21802 w_rx_data[5]
|
|
.sym 21803 w_rx_data[4]
|
|
.sym 21804 w_rx_data[6]
|
|
.sym 21806 w_rx_data[3]
|
|
.sym 21843 io_pmod[3]$SB_IO_IN
|
|
.sym 21856 o_led0$SB_IO_OUT
|
|
.sym 21863 w_rx_data[2]
|
|
.sym 21865 w_rx_data[1]
|
|
.sym 21905 io_pmod_SB_DFFE_Q_E
|
|
.sym 21909 o_led0$SB_IO_OUT
|
|
.sym 21945 w_rx_data[3]
|
|
.sym 21953 w_rx_data[1]
|
|
.sym 21958 w_rx_data[4]
|
|
.sym 21960 w_rx_data[6]
|
|
.sym 22004 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 22005 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 22006 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 22007 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 22008 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 22009 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 22010 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
|
|
.sym 22011 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 22053 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 22055 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
|
|
.sym 22059 w_rx_data[2]
|
|
.sym 22060 w_rx_data[7]
|
|
.sym 22061 w_rx_data[1]
|
|
.sym 22106 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 22107 io_ctrl_ins.rf_pin_state[4]
|
|
.sym 22108 io_ctrl_ins.rf_pin_state[7]
|
|
.sym 22109 io_ctrl_ins.rf_pin_state[6]
|
|
.sym 22110 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 22111 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 22112 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 22113 io_ctrl_ins.rf_pin_state[5]
|
|
.sym 22156 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
|
|
.sym 22214 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
|
|
.sym 22272 i_button_SB_LUT4_I0_O[1]
|
|
.sym 22352 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 22372 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
|
|
.sym 22487 o_led1$SB_IO_OUT
|
|
.sym 22505 o_led1$SB_IO_OUT
|
|
.sym 22517 int_miso
|
|
.sym 22519 o_miso_$_TBUF__Y_E
|
|
.sym 22527 o_miso_$_TBUF__Y_E
|
|
.sym 22528 int_miso
|
|
.sym 22554 i_mosi$SB_IO_IN
|
|
.sym 22563 i_mosi$SB_IO_IN
|
|
.sym 22587 smi_ctrl_ins.tx_reg_state[1]
|
|
.sym 22588 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 22589 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 22592 i_rst_b$SB_IO_IN
|
|
.sym 22593 smi_ctrl_ins.tx_reg_state[2]
|
|
.sym 22597 w_smi_data_input[7]
|
|
.sym 22599 smi_ctrl_ins.tx_reg_state[3]
|
|
.sym 22600 smi_ctrl_ins.swe_and_reset
|
|
.sym 22601 i_rst_b$SB_IO_IN
|
|
.sym 22602 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 22605 w_smi_data_input[7]
|
|
.sym 22623 i_rst_b$SB_IO_IN
|
|
.sym 22625 w_smi_data_input[7]
|
|
.sym 22626 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 22630 smi_ctrl_ins.tx_reg_state[1]
|
|
.sym 22631 smi_ctrl_ins.tx_reg_state[2]
|
|
.sym 22632 w_smi_data_input[7]
|
|
.sym 22635 w_smi_data_input[7]
|
|
.sym 22636 smi_ctrl_ins.tx_reg_state[2]
|
|
.sym 22637 i_rst_b$SB_IO_IN
|
|
.sym 22641 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 22644 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 22647 w_smi_data_input[7]
|
|
.sym 22648 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 22649 i_rst_b$SB_IO_IN
|
|
.sym 22650 smi_ctrl_ins.tx_reg_state[3]
|
|
.sym 22653 smi_ctrl_ins.tx_reg_state[3]
|
|
.sym 22655 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 22656 i_rst_b$SB_IO_IN
|
|
.sym 22659 smi_ctrl_ins.tx_reg_state[1]
|
|
.sym 22661 i_rst_b$SB_IO_IN
|
|
.sym 22662 w_smi_data_input[7]
|
|
.sym 22664 smi_ctrl_ins.swe_and_reset
|
|
.sym 22666 i_sck$SB_IO_IN
|
|
.sym 22668 i_ss$SB_IO_IN
|
|
.sym 22699 w_smi_data_input[7]
|
|
.sym 22715 i_ss$SB_IO_IN
|
|
.sym 22720 i_sck$SB_IO_IN
|
|
.sym 22723 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 22729 i_sck$SB_IO_IN
|
|
.sym 22733 i_ss$SB_IO_IN
|
|
.sym 22734 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 22740 smi_ctrl_ins.swe_and_reset
|
|
.sym 22747 tx_fifo.wr_addr[1]
|
|
.sym 22750 tx_fifo.wr_addr[8]
|
|
.sym 22760 tx_fifo.wr_addr[1]
|
|
.sym 22763 tx_fifo.wr_addr[4]
|
|
.sym 22765 tx_fifo.wr_addr[3]
|
|
.sym 22767 tx_fifo.wr_addr[5]
|
|
.sym 22769 tx_fifo.wr_addr[7]
|
|
.sym 22775 tx_fifo.wr_addr[6]
|
|
.sym 22777 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 22779 $nextpnr_ICESTORM_LC_1$O
|
|
.sym 22782 tx_fifo.wr_addr[1]
|
|
.sym 22785 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22788 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 22789 tx_fifo.wr_addr[1]
|
|
.sym 22791 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22794 tx_fifo.wr_addr[3]
|
|
.sym 22795 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22797 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22799 tx_fifo.wr_addr[4]
|
|
.sym 22801 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22803 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22806 tx_fifo.wr_addr[5]
|
|
.sym 22807 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22809 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22812 tx_fifo.wr_addr[6]
|
|
.sym 22813 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22815 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 22818 tx_fifo.wr_addr[7]
|
|
.sym 22819 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 22821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
|
|
.sym 22824 tx_fifo.wr_addr[8]
|
|
.sym 22825 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 22854 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 22860 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 22865 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
|
|
.sym 22870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 22871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
|
|
.sym 22872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 22873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 22875 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
|
|
.sym 22877 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22879 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 22881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 22882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 22887 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 22891 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
|
|
.sym 22893 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 22895 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 22897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
|
|
.sym 22899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 22900 tx_fifo.wr_addr[9]
|
|
.sym 22901 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 22904 tx_fifo.wr_addr[9]
|
|
.sym 22906 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
|
|
.sym 22909 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 22911 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22912 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 22915 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
|
|
.sym 22916 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
|
|
.sym 22917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 22918 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22922 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 22923 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
|
|
.sym 22924 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 22927 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 22928 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22929 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
|
|
.sym 22930 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 22933 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22934 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 22936 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 22939 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 22945 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 22946 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 22947 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 22948 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
|
|
.sym 22949 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 22950 r_counter_$glb_clk
|
|
.sym 22951 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 22967 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_O
|
|
.sym 22976 tx_fifo.wr_addr_gray_rd[9]
|
|
.sym 22995 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 22996 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1]
|
|
.sym 22998 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 22999 tx_fifo.wr_addr[9]
|
|
.sym 23000 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 23001 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
|
|
.sym 23002 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 23003 tx_fifo.full_o_SB_LUT4_I1_O[0]
|
|
.sym 23005 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
|
|
.sym 23007 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 23008 tx_fifo.wr_addr[1]
|
|
.sym 23009 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 23011 tx_fifo.full_o_SB_LUT4_I1_O[2]
|
|
.sym 23013 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 23015 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0]
|
|
.sym 23017 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 23018 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
|
|
.sym 23019 tx_fifo.full_o_SB_LUT4_I1_O[1]
|
|
.sym 23020 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 23021 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 23023 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 23024 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 23026 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
|
|
.sym 23027 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
|
|
.sym 23028 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0]
|
|
.sym 23029 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1]
|
|
.sym 23032 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 23033 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 23034 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
|
|
.sym 23035 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 23038 tx_fifo.wr_addr[1]
|
|
.sym 23039 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 23040 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 23041 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 23044 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 23045 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 23046 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
|
|
.sym 23047 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 23050 tx_fifo.wr_addr[9]
|
|
.sym 23056 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 23059 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 23063 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 23064 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 23065 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 23068 tx_fifo.full_o_SB_LUT4_I1_O[1]
|
|
.sym 23069 tx_fifo.full_o_SB_LUT4_I1_O[2]
|
|
.sym 23070 tx_fifo.full_o_SB_LUT4_I1_O[0]
|
|
.sym 23073 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk
|
|
.sym 23086 w_rx_data[0]
|
|
.sym 23100 i_ss$SB_IO_IN
|
|
.sym 23104 i_sck$SB_IO_IN
|
|
.sym 23105 i_ss$SB_IO_IN
|
|
.sym 23106 o_smi_read_req$SB_IO_OUT
|
|
.sym 23108 i_sck$SB_IO_IN
|
|
.sym 23116 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 23120 tx_fifo.wr_addr[1]
|
|
.sym 23121 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 23124 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 23131 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 23136 w_tx_fifo_full
|
|
.sym 23139 smi_ctrl_ins.r_fifo_push_1
|
|
.sym 23141 smi_ctrl_ins.r_fifo_push
|
|
.sym 23142 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 23161 w_tx_fifo_full
|
|
.sym 23162 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 23163 tx_fifo.wr_addr[1]
|
|
.sym 23173 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 23174 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 23175 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 23176 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 23179 smi_ctrl_ins.r_fifo_push_1
|
|
.sym 23180 smi_ctrl_ins.r_fifo_push
|
|
.sym 23182 w_tx_fifo_full
|
|
.sym 23194 smi_ctrl_ins.r_fifo_push
|
|
.sym 23196 r_counter_$glb_clk
|
|
.sym 23197 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 23203 o_miso_$_TBUF__Y_E
|
|
.sym 23204 spi_if_ins.spi.r_rx_done
|
|
.sym 23220 w_tx_fifo_full
|
|
.sym 23222 i_sck$SB_IO_IN
|
|
.sym 23223 i_ss$SB_IO_IN
|
|
.sym 23225 o_miso_$_TBUF__Y_E
|
|
.sym 23226 i_sck$SB_IO_IN
|
|
.sym 23230 i_ss$SB_IO_IN
|
|
.sym 23241 tx_fifo.rd_addr_gray_wr[9]
|
|
.sym 23251 w_tx_fifo_full
|
|
.sym 23261 o_led0$SB_IO_OUT
|
|
.sym 23265 tx_fifo.rd_addr_gray_wr[0]
|
|
.sym 23266 w_rx_fifo_empty
|
|
.sym 23269 spi_if_ins.spi.r_rx_done
|
|
.sym 23273 tx_fifo.rd_addr_gray_wr[0]
|
|
.sym 23278 w_tx_fifo_full
|
|
.sym 23279 w_rx_fifo_empty
|
|
.sym 23281 o_led0$SB_IO_OUT
|
|
.sym 23285 spi_if_ins.spi.r_rx_done
|
|
.sym 23310 tx_fifo.rd_addr_gray_wr[9]
|
|
.sym 23319 r_counter_$glb_clk
|
|
.sym 23322 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 23323 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 23325 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 23326 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 23327 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 23344 io_pmod[7]$SB_IO_IN
|
|
.sym 23352 w_rx_fifo_empty
|
|
.sym 23367 o_miso_$_TBUF__Y_E
|
|
.sym 23373 o_miso_$_TBUF__Y_E
|
|
.sym 23378 i_sck$SB_IO_IN
|
|
.sym 23379 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23386 i_mosi$SB_IO_IN
|
|
.sym 23403 i_mosi$SB_IO_IN
|
|
.sym 23413 o_miso_$_TBUF__Y_E
|
|
.sym 23422 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23441 o_miso_$_TBUF__Y_E
|
|
.sym 23442 i_sck$SB_IO_IN
|
|
.sym 23444 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 23447 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 23448 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 23449 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 23450 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 23451 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 23454 o_led0$SB_IO_OUT
|
|
.sym 23470 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 23486 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23494 i_sck$SB_IO_IN
|
|
.sym 23496 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 23497 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 23501 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 23504 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 23505 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 23506 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 23508 i_mosi$SB_IO_IN
|
|
.sym 23516 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 23518 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 23525 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 23533 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 23538 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 23542 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 23548 i_mosi$SB_IO_IN
|
|
.sym 23555 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 23560 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23564 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 23565 i_sck$SB_IO_IN
|
|
.sym 23580 i_glob_clock$SB_IO_IN
|
|
.sym 23591 spi_if_ins.w_rx_data[4]
|
|
.sym 23592 w_rx_data[0]
|
|
.sym 23597 spi_if_ins.w_rx_data[3]
|
|
.sym 23602 $io_pmod[3]$iobuf_i
|
|
.sym 23608 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 23609 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 23610 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 23612 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 23614 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 23615 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 23618 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 23619 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 23621 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 23642 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 23648 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 23656 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 23661 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 23667 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 23674 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 23677 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 23686 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 23687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 23688 r_counter_$glb_clk
|
|
.sym 23708 i_rst_b_SB_LUT4_I3_O
|
|
.sym 23715 spi_if_ins.w_rx_data[2]
|
|
.sym 23717 spi_if_ins.w_rx_data[1]
|
|
.sym 23742 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 23744 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 23745 spi_if_ins.w_rx_data[0]
|
|
.sym 23803 spi_if_ins.w_rx_data[0]
|
|
.sym 23807 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 23810 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 23811 r_counter_$glb_clk
|
|
.sym 23814 $io_pmod[2]$iobuf_i
|
|
.sym 23816 $io_pmod[1]$iobuf_i
|
|
.sym 23818 $io_pmod[3]$iobuf_i
|
|
.sym 23846 w_rx_data[0]
|
|
.sym 23854 spi_if_ins.w_rx_data[5]
|
|
.sym 23863 spi_if_ins.w_rx_data[4]
|
|
.sym 23864 spi_if_ins.w_rx_data[6]
|
|
.sym 23869 spi_if_ins.w_rx_data[3]
|
|
.sym 23875 spi_if_ins.w_rx_data[2]
|
|
.sym 23877 spi_if_ins.w_rx_data[1]
|
|
.sym 23881 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 23888 spi_if_ins.w_rx_data[2]
|
|
.sym 23893 spi_if_ins.w_rx_data[1]
|
|
.sym 23899 spi_if_ins.w_rx_data[5]
|
|
.sym 23906 spi_if_ins.w_rx_data[4]
|
|
.sym 23914 spi_if_ins.w_rx_data[6]
|
|
.sym 23925 spi_if_ins.w_rx_data[3]
|
|
.sym 23933 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 23934 r_counter_$glb_clk
|
|
.sym 23943 $io_pmod[0]$iobuf_i
|
|
.sym 23948 w_rx_data[2]
|
|
.sym 23952 w_rx_data[1]
|
|
.sym 23961 w_rx_data[5]
|
|
.sym 23969 w_rx_data[3]
|
|
.sym 23977 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 23978 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 23979 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
|
|
.sym 23989 w_rx_data[0]
|
|
.sym 23993 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 24028 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 24029 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 24031 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 24052 w_rx_data[0]
|
|
.sym 24056 smi_ctrl_ins.r_dir_SB_DFFER_Q_E
|
|
.sym 24057 r_counter_$glb_clk
|
|
.sym 24058 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 24062 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 24063 io_ctrl_ins.mixer_en_state
|
|
.sym 24072 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 24084 w_rx_data[0]
|
|
.sym 24085 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 24089 o_tr_vc1$SB_IO_OUT
|
|
.sym 24100 w_rx_data[2]
|
|
.sym 24102 w_rx_data[1]
|
|
.sym 24104 i_rst_b$SB_IO_IN
|
|
.sym 24106 w_rx_data[4]
|
|
.sym 24108 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 24109 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 24111 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
|
|
.sym 24113 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 24116 w_rx_data[0]
|
|
.sym 24126 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 24129 w_rx_data[3]
|
|
.sym 24130 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
|
|
.sym 24135 w_rx_data[0]
|
|
.sym 24142 w_rx_data[1]
|
|
.sym 24147 w_rx_data[4]
|
|
.sym 24151 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
|
|
.sym 24154 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 24159 w_rx_data[2]
|
|
.sym 24164 w_rx_data[3]
|
|
.sym 24169 i_rst_b$SB_IO_IN
|
|
.sym 24170 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 24171 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 24172 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 24177 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 24178 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 24179 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E
|
|
.sym 24180 r_counter_$glb_clk
|
|
.sym 24181 i_rst_b_SB_LUT4_I3_O_$glb_sr
|
|
.sym 24182 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 24183 o_tr_vc1$SB_IO_OUT
|
|
.sym 24184 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 24185 o_tr_vc2$SB_IO_OUT
|
|
.sym 24186 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 24187 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 24188 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 24189 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 24198 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 24200 i_rst_b$SB_IO_IN
|
|
.sym 24207 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 24225 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
|
|
.sym 24226 w_rx_data[4]
|
|
.sym 24228 w_rx_data[6]
|
|
.sym 24229 w_rx_data[7]
|
|
.sym 24230 w_rx_data[1]
|
|
.sym 24231 w_rx_data[5]
|
|
.sym 24236 w_rx_data[2]
|
|
.sym 24239 w_rx_data[3]
|
|
.sym 24251 w_rx_data[0]
|
|
.sym 24257 w_rx_data[0]
|
|
.sym 24264 w_rx_data[4]
|
|
.sym 24270 w_rx_data[7]
|
|
.sym 24274 w_rx_data[6]
|
|
.sym 24282 w_rx_data[2]
|
|
.sym 24287 w_rx_data[3]
|
|
.sym 24293 w_rx_data[1]
|
|
.sym 24298 w_rx_data[5]
|
|
.sym 24302 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
|
|
.sym 24303 r_counter_$glb_clk
|
|
.sym 24321 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O
|
|
.sym 24351 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 24373 i_button_SB_LUT4_I0_O[1]
|
|
.sym 24415 i_button_SB_LUT4_I0_O[1]
|
|
.sym 24416 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 24596 o_led0$SB_IO_OUT
|
|
.sym 24618 o_led0$SB_IO_OUT
|
|
.sym 24655 i_ss$SB_IO_IN
|
|
.sym 24664 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 25100 o_smi_read_req$SB_IO_OUT
|
|
.sym 25261 o_miso_$_TBUF__Y_E
|
|
.sym 25401 io_pmod[7]$SB_IO_IN
|
|
.sym 25478 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 25481 i_sck$SB_IO_IN
|
|
.sym 25485 i_ss$SB_IO_IN
|
|
.sym 25491 i_ss$SB_IO_IN
|
|
.sym 25499 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 25537 i_ss$SB_IO_IN
|
|
.sym 25541 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 25551 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 25552 i_sck$SB_IO_IN
|
|
.sym 25553 i_ss$SB_IO_IN
|
|
.sym 25554 io_pmod[3]$SB_IO_IN
|
|
.sym 25556 io_pmod[6]$SB_IO_IN
|
|
.sym 25627 i_sck$SB_IO_IN
|
|
.sym 25631 i_ss$SB_IO_IN
|
|
.sym 25636 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 25640 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 25651 i_ss$SB_IO_IN
|
|
.sym 25653 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 25659 $nextpnr_ICESTORM_LC_4$O
|
|
.sym 25662 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 25665 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
|
|
.sym 25667 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 25669 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 25673 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 25675 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
|
|
.sym 25684 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 25685 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 25686 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 25687 i_ss$SB_IO_IN
|
|
.sym 25693 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 25696 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 25697 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 25698 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 25707 i_sck$SB_IO_IN
|
|
.sym 25708 i_ss$SB_IO_IN
|
|
.sym 25711 i_glob_clock$SB_IO_IN
|
|
.sym 25719 $io_pmod[3]$iobuf_i
|
|
.sym 25782 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 25784 o_miso_$_TBUF__Y_E
|
|
.sym 25788 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 25790 i_ss$SB_IO_IN
|
|
.sym 25791 i_sck$SB_IO_IN
|
|
.sym 25795 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 25801 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 25802 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 25805 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 25817 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 25833 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 25840 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 25846 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 25851 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 25852 i_ss$SB_IO_IN
|
|
.sym 25858 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 25861 o_miso_$_TBUF__Y_E
|
|
.sym 25862 i_sck$SB_IO_IN
|
|
.sym 25879 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
|
|
.sym 26174 io_pmod[2]$SB_IO_IN
|
|
.sym 26176 io_pmod[1]$SB_IO_IN
|
|
.sym 26247 w_rx_data[2]
|
|
.sym 26248 w_rx_data[1]
|
|
.sym 26261 w_rx_data[3]
|
|
.sym 26274 io_pmod_SB_DFFE_Q_E
|
|
.sym 26287 w_rx_data[2]
|
|
.sym 26300 w_rx_data[1]
|
|
.sym 26310 w_rx_data[3]
|
|
.sym 26326 io_pmod_SB_DFFE_Q_E
|
|
.sym 26327 r_counter_$glb_clk
|
|
.sym 26329 io_pmod[0]$SB_IO_IN
|
|
.sym 26413 io_pmod_SB_DFFE_Q_E
|
|
.sym 26415 w_rx_data[0]
|
|
.sym 26480 w_rx_data[0]
|
|
.sym 26481 io_pmod_SB_DFFE_Q_E
|
|
.sym 26482 r_counter_$glb_clk
|
|
.sym 26559 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 26562 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26564 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26568 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 26570 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26573 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 26585 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 26608 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 26609 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26610 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26611 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 26614 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 26615 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26616 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 26617 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26636 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 26637 r_counter_$glb_clk
|
|
.sym 26715 io_ctrl_ins.rf_pin_state[6]
|
|
.sym 26719 io_ctrl_ins.rf_pin_state[5]
|
|
.sym 26720 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26721 io_ctrl_ins.rf_pin_state[4]
|
|
.sym 26722 io_ctrl_ins.rf_pin_state[7]
|
|
.sym 26725 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 26726 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 26732 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 26733 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26738 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 26739 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 26741 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26742 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 26743 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26745 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 26746 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26747 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26748 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 26751 io_ctrl_ins.rf_pin_state[5]
|
|
.sym 26752 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26753 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 26754 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26757 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26758 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 26759 io_ctrl_ins.rf_pin_state[4]
|
|
.sym 26760 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26763 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26764 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26765 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 26766 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 26770 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 26771 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26772 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 26775 io_ctrl_ins.rf_pin_state[6]
|
|
.sym 26777 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26778 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26782 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 26783 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 26787 io_ctrl_ins.rf_pin_state[7]
|
|
.sym 26789 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26790 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 26791 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 26792 r_counter_$glb_clk
|
|
.sym 27283 o_smi_read_req$SB_IO_OUT
|
|
.sym 27292 o_smi_read_req$SB_IO_OUT
|
|
.sym 27338 o_led0$SB_IO_OUT
|
|
.sym 27395 io_pmod[3]$SB_IO_IN
|
|
.sym 27400 $io_pmod[3]$iobuf_i
|
|
.sym 27411 $io_pmod[3]$iobuf_i
|
|
.sym 27429 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
|
|
.sym 27444 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E
|
|
.sym 27458 o_led0$SB_IO_OUT
|
|
.sym 27459 i_rst_b_SB_LUT4_I3_O
|
|
.sym 27470 i_rst_b_SB_LUT4_I3_O
|
|
.sym 27519 $io_pmod[2]$iobuf_i
|
|
.sym 27522 $io_pmod[1]$iobuf_i
|
|
.sym 27531 $io_pmod[1]$iobuf_i
|
|
.sym 27537 $io_pmod[2]$iobuf_i
|
|
.sym 27549 $io_pmod[0]$iobuf_i
|
|
.sym 27573 $io_pmod[0]$iobuf_i
|
|
.sym 27582 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 27595 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 27605 o_tr_vc1$SB_IO_OUT
|
|
.sym 27608 o_tr_vc2$SB_IO_OUT
|
|
.sym 27617 o_tr_vc2$SB_IO_OUT
|
|
.sym 27623 o_tr_vc1$SB_IO_OUT
|
|
.sym 27631 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 27634 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 27650 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 27653 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 27732 w_rx_09_fifo_data[10]
|
|
.sym 27733 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27740 w_rx_09_fifo_data[14]
|
|
.sym 27741 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27744 w_rx_09_fifo_data[12]
|
|
.sym 27745 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27768 w_rx_09_fifo_data[18]
|
|
.sym 27769 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27772 w_rx_09_fifo_data[16]
|
|
.sym 27773 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27776 w_rx_09_fifo_data[20]
|
|
.sym 27777 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27788 w_rx_09_fifo_data[9]
|
|
.sym 27789 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27800 w_rx_09_fifo_data[7]
|
|
.sym 27801 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27804 w_rx_09_fifo_data[22]
|
|
.sym 27805 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27807 w_rx_09_fifo_data[9]
|
|
.sym 27808 w_rx_24_fifo_data[9]
|
|
.sym 27809 o_led1$SB_IO_OUT
|
|
.sym 27812 w_rx_24_fifo_data[7]
|
|
.sym 27813 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 27816 w_rx_24_fifo_data[9]
|
|
.sym 27817 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 27820 w_rx_24_fifo_data[10]
|
|
.sym 27821 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 27824 w_rx_24_fifo_data[6]
|
|
.sym 27825 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 27828 w_rx_24_fifo_data[11]
|
|
.sym 27829 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 27832 w_rx_24_fifo_data[8]
|
|
.sym 27833 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 27837 o_iq_tx_clk_p$SB_IO_OUT
|
|
.sym 27840 w_rx_24_fifo_data[5]
|
|
.sym 27841 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 27844 w_rx_09_fifo_data[6]
|
|
.sym 27845 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27848 w_rx_09_fifo_data[4]
|
|
.sym 27849 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27852 w_rx_09_fifo_data[0]
|
|
.sym 27853 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27856 w_rx_09_fifo_data[1]
|
|
.sym 27857 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27859 w_rx_24_fifo_data[6]
|
|
.sym 27860 w_rx_09_fifo_data[6]
|
|
.sym 27861 o_led1$SB_IO_OUT
|
|
.sym 27864 w_rx_09_fifo_data[2]
|
|
.sym 27865 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27867 w_rx_24_fifo_data[10]
|
|
.sym 27868 w_rx_09_fifo_data[10]
|
|
.sym 27869 o_led1$SB_IO_OUT
|
|
.sym 27872 w_rx_09_fifo_data[8]
|
|
.sym 27873 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 27897 w_lvds_rx_24_d0
|
|
.sym 27903 w_rx_24_fifo_data[8]
|
|
.sym 27904 w_rx_09_fifo_data[8]
|
|
.sym 27905 o_led1$SB_IO_OUT
|
|
.sym 27916 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 27917 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 27922 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 27926 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 27939 rx_fifo.wr_addr[1]
|
|
.sym 27944 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 27945 rx_fifo.wr_addr[1]
|
|
.sym 27948 rx_fifo.wr_addr[3]
|
|
.sym 27949 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 27952 rx_fifo.wr_addr[4]
|
|
.sym 27953 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
|
|
.sym 27956 rx_fifo.wr_addr[5]
|
|
.sym 27957 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 27960 rx_fifo.wr_addr[6]
|
|
.sym 27961 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3
|
|
.sym 27964 rx_fifo.wr_addr[7]
|
|
.sym 27965 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 27968 rx_fifo.wr_addr[8]
|
|
.sym 27969 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 27972 rx_fifo.wr_addr[9]
|
|
.sym 27973 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
|
|
.sym 27974 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 27978 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 27979 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1]
|
|
.sym 27980 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 27981 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3]
|
|
.sym 27982 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 27986 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 27990 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 27994 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 27999 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 28000 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[1]
|
|
.sym 28001 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 28003 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 28004 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 28005 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 28008 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 28009 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 28012 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 28013 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 28014 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[0]
|
|
.sym 28015 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[1]
|
|
.sym 28016 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[2]
|
|
.sym 28017 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0[3]
|
|
.sym 28018 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 28019 rx_fifo.rd_addr_gray_wr_r[0]
|
|
.sym 28020 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 28021 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 28024 i_rst_b$SB_IO_IN
|
|
.sym 28025 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.sym 28026 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[0]
|
|
.sym 28027 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[1]
|
|
.sym 28028 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[2]
|
|
.sym 28029 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O[3]
|
|
.sym 28030 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 28031 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 28032 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 28033 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 28034 w_lvds_rx_09_d0
|
|
.sym 28035 w_lvds_rx_09_d1
|
|
.sym 28036 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 28037 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28038 rx_fifo.rd_addr_gray_wr[9]
|
|
.sym 28042 w_lvds_rx_09_d0
|
|
.sym 28043 w_lvds_rx_09_d1
|
|
.sym 28044 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 28045 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28050 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 28051 rx_fifo.wr_addr[1]
|
|
.sym 28052 rx_fifo.rd_addr_gray_wr_r[0]
|
|
.sym 28053 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 28055 rx_fifo.full_o_SB_LUT4_I0_O[0]
|
|
.sym 28056 rx_fifo.full_o_SB_LUT4_I0_O[1]
|
|
.sym 28057 rx_fifo.full_o_SB_LUT4_I0_O[2]
|
|
.sym 28058 w_rx_fifo_full
|
|
.sym 28059 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 28060 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 28061 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 28062 rx_fifo.rd_addr_gray_wr[0]
|
|
.sym 28066 w_lvds_rx_24_d1
|
|
.sym 28067 w_lvds_rx_24_d0
|
|
.sym 28068 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 28069 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28071 w_lvds_rx_09_d1
|
|
.sym 28072 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 28073 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 28076 i_rst_b$SB_IO_IN
|
|
.sym 28077 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
|
|
.sym 28080 w_lvds_rx_24_d1
|
|
.sym 28081 w_lvds_rx_24_d0
|
|
.sym 28083 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28084 w_lvds_rx_09_d0_SB_LUT4_I0_O[1]
|
|
.sym 28085 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 28088 w_lvds_rx_09_d0
|
|
.sym 28089 w_lvds_rx_09_d1
|
|
.sym 28090 w_lvds_rx_09_d0
|
|
.sym 28094 w_lvds_rx_24_d1
|
|
.sym 28095 w_lvds_rx_24_d0
|
|
.sym 28096 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 28097 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28100 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28101 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1]
|
|
.sym 28104 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[0]
|
|
.sym 28105 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 28107 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 28108 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28109 w_lvds_rx_09_d0_SB_LUT4_I2_O[2]
|
|
.sym 28110 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_D[1]
|
|
.sym 28114 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 28115 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28116 w_lvds_rx_09_d0_SB_LUT4_I2_O[2]
|
|
.sym 28117 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 28136 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28137 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.sym 28142 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_D[1]
|
|
.sym 28147 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 28148 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28149 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.sym 28154 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 28155 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28156 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[2]
|
|
.sym 28157 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 28200 w_rx_09_fifo_data[11]
|
|
.sym 28201 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28208 w_rx_09_fifo_data[13]
|
|
.sym 28209 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28211 w_rx_09_fifo_data[13]
|
|
.sym 28212 w_rx_24_fifo_data[13]
|
|
.sym 28213 o_led1$SB_IO_OUT
|
|
.sym 28216 w_rx_09_fifo_data[15]
|
|
.sym 28217 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28223 w_rx_09_fifo_data[15]
|
|
.sym 28224 w_rx_24_fifo_data[15]
|
|
.sym 28225 o_led1$SB_IO_OUT
|
|
.sym 28228 w_rx_24_fifo_data[12]
|
|
.sym 28229 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28232 w_rx_24_fifo_data[14]
|
|
.sym 28233 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28236 w_rx_24_fifo_data[15]
|
|
.sym 28237 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28240 w_rx_24_fifo_data[20]
|
|
.sym 28241 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28244 w_rx_24_fifo_data[16]
|
|
.sym 28245 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28247 w_rx_09_fifo_data[14]
|
|
.sym 28248 w_rx_24_fifo_data[14]
|
|
.sym 28249 o_led1$SB_IO_OUT
|
|
.sym 28251 w_rx_09_fifo_data[12]
|
|
.sym 28252 w_rx_24_fifo_data[12]
|
|
.sym 28253 o_led1$SB_IO_OUT
|
|
.sym 28256 w_rx_24_fifo_data[13]
|
|
.sym 28257 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28260 w_rx_09_fifo_data[23]
|
|
.sym 28261 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28264 w_rx_09_fifo_data[17]
|
|
.sym 28265 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28268 w_rx_09_fifo_data[19]
|
|
.sym 28269 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28271 w_rx_24_fifo_data[22]
|
|
.sym 28272 w_rx_09_fifo_data[22]
|
|
.sym 28273 o_led1$SB_IO_OUT
|
|
.sym 28275 w_rx_09_fifo_data[18]
|
|
.sym 28276 w_rx_24_fifo_data[18]
|
|
.sym 28277 o_led1$SB_IO_OUT
|
|
.sym 28280 w_rx_09_fifo_data[21]
|
|
.sym 28281 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28283 w_rx_09_fifo_data[16]
|
|
.sym 28284 w_rx_24_fifo_data[16]
|
|
.sym 28285 o_led1$SB_IO_OUT
|
|
.sym 28287 w_rx_09_fifo_data[17]
|
|
.sym 28288 w_rx_24_fifo_data[17]
|
|
.sym 28289 o_led1$SB_IO_OUT
|
|
.sym 28292 w_rx_24_fifo_data[22]
|
|
.sym 28293 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28296 w_rx_24_fifo_data[24]
|
|
.sym 28297 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28299 w_rx_24_fifo_data[19]
|
|
.sym 28300 w_rx_09_fifo_data[19]
|
|
.sym 28301 o_led1$SB_IO_OUT
|
|
.sym 28304 w_rx_24_fifo_data[17]
|
|
.sym 28305 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28307 w_rx_09_fifo_data[24]
|
|
.sym 28308 w_rx_24_fifo_data[24]
|
|
.sym 28309 o_led1$SB_IO_OUT
|
|
.sym 28312 w_rx_24_fifo_data[19]
|
|
.sym 28313 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28316 w_rx_24_fifo_data[28]
|
|
.sym 28317 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28320 w_rx_24_fifo_data[26]
|
|
.sym 28321 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28323 w_rx_09_fifo_data[11]
|
|
.sym 28324 w_rx_24_fifo_data[11]
|
|
.sym 28325 o_led1$SB_IO_OUT
|
|
.sym 28328 w_rx_09_fifo_data[3]
|
|
.sym 28329 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28331 w_rx_09_fifo_data[5]
|
|
.sym 28332 w_rx_24_fifo_data[5]
|
|
.sym 28333 o_led1$SB_IO_OUT
|
|
.sym 28335 w_rx_09_fifo_data[7]
|
|
.sym 28336 w_rx_24_fifo_data[7]
|
|
.sym 28337 o_led1$SB_IO_OUT
|
|
.sym 28339 w_rx_24_fifo_data[26]
|
|
.sym 28340 w_rx_09_fifo_data[26]
|
|
.sym 28341 o_led1$SB_IO_OUT
|
|
.sym 28344 w_rx_09_fifo_data[24]
|
|
.sym 28345 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28348 w_rx_09_fifo_data[26]
|
|
.sym 28349 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28352 w_rx_09_fifo_data[5]
|
|
.sym 28353 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28356 w_rx_24_fifo_data[0]
|
|
.sym 28357 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28359 w_rx_24_fifo_data[2]
|
|
.sym 28360 w_rx_09_fifo_data[2]
|
|
.sym 28361 o_led1$SB_IO_OUT
|
|
.sym 28364 w_rx_24_fifo_data[3]
|
|
.sym 28365 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28367 w_rx_09_fifo_data[3]
|
|
.sym 28368 w_rx_24_fifo_data[3]
|
|
.sym 28369 o_led1$SB_IO_OUT
|
|
.sym 28372 w_rx_24_fifo_data[4]
|
|
.sym 28373 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28376 w_rx_24_fifo_data[1]
|
|
.sym 28377 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28380 w_rx_24_fifo_data[2]
|
|
.sym 28381 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28383 w_rx_24_fifo_data[4]
|
|
.sym 28384 w_rx_09_fifo_data[4]
|
|
.sym 28385 o_led1$SB_IO_OUT
|
|
.sym 28386 rx_fifo.rd_addr[9]
|
|
.sym 28422 rx_fifo.wr_addr[9]
|
|
.sym 28430 rx_fifo.wr_addr_gray_rd[9]
|
|
.sym 28435 w_rx_24_fifo_data[1]
|
|
.sym 28436 w_rx_09_fifo_data[1]
|
|
.sym 28437 o_led1$SB_IO_OUT
|
|
.sym 28452 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 28453 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
|
|
.sym 28455 w_rx_24_fifo_data[0]
|
|
.sym 28456 w_rx_09_fifo_data[0]
|
|
.sym 28457 o_led1$SB_IO_OUT
|
|
.sym 28459 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 28460 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2]
|
|
.sym 28461 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[2]
|
|
.sym 28462 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 28463 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
|
|
.sym 28464 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[2]
|
|
.sym 28465 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[3]
|
|
.sym 28467 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 28468 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[1]
|
|
.sym 28469 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[2]
|
|
.sym 28471 io_pmod[7]$SB_IO_IN
|
|
.sym 28472 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 28473 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 28475 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[0]
|
|
.sym 28476 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[1]
|
|
.sym 28477 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1[2]
|
|
.sym 28479 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 28480 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[2]
|
|
.sym 28481 rx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 28483 rx_fifo.wr_addr[0]
|
|
.sym 28488 rx_fifo.wr_addr[1]
|
|
.sym 28489 rx_fifo.wr_addr[0]
|
|
.sym 28492 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 28493 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 28496 rx_fifo.wr_addr[3]
|
|
.sym 28497 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 28500 rx_fifo.wr_addr[4]
|
|
.sym 28501 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 28504 rx_fifo.wr_addr[5]
|
|
.sym 28505 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 28508 rx_fifo.wr_addr[6]
|
|
.sym 28509 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 28512 rx_fifo.wr_addr[7]
|
|
.sym 28513 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 28516 rx_fifo.wr_addr[8]
|
|
.sym 28517 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 28520 rx_fifo.wr_addr[9]
|
|
.sym 28521 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 28524 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 28525 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 28528 rx_fifo.wr_addr_SB_DFFESR_Q_D[0]
|
|
.sym 28529 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 28532 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 28533 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 28537 rx_fifo.wr_addr[0]
|
|
.sym 28540 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 28541 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 28543 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 28544 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 28545 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 28548 rx_fifo.rd_addr_gray_wr_r[5]
|
|
.sym 28549 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 28550 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 28551 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 28552 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 28553 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 28554 rx_fifo.rd_addr_gray_wr[8]
|
|
.sym 28558 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 28559 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 28560 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 28561 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 28562 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I1[0]
|
|
.sym 28563 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 28564 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 28565 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 28566 rx_fifo.rd_addr_gray_wr[5]
|
|
.sym 28570 rx_fifo.rd_addr_gray[8]
|
|
.sym 28574 rx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 28575 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 28576 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 28577 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 28579 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I1[0]
|
|
.sym 28580 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 28581 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 28586 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 28587 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 28588 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 28589 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 28593 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_DFFER_Q_E
|
|
.sym 28594 w_lvds_rx_24_d1
|
|
.sym 28595 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_Q[1]
|
|
.sym 28596 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 28597 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 28603 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 28604 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28605 w_lvds_rx_09_d0_SB_LUT4_I0_O[2]
|
|
.sym 28611 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 28614 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28615 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 28616 $PACKER_VCC_NET
|
|
.sym 28617 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 28618 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28619 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 28620 $PACKER_VCC_NET
|
|
.sym 28621 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I3
|
|
.sym 28622 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 28623 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 28624 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 28625 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 28629 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 28633 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 28635 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
|
|
.sym 28636 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[1]
|
|
.sym 28637 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1[2]
|
|
.sym 28640 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 28641 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_DFFER_Q_2_D_SB_LUT4_O_I3[1]
|
|
.sym 28643 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3]
|
|
.sym 28646 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28647 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[1]
|
|
.sym 28648 $PACKER_VCC_NET
|
|
.sym 28649 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_1_D_SB_LUT4_O_I1[3]
|
|
.sym 28650 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28651 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2]
|
|
.sym 28652 $PACKER_VCC_NET
|
|
.sym 28653 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_1_O_SB_DFFER_E_D_SB_LUT4_O_I3
|
|
.sym 28654 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 28655 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 28656 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28657 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 28665 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 28666 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0]
|
|
.sym 28667 rx_fifo.full_o_SB_LUT4_I1_I3[0]
|
|
.sym 28668 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[2]
|
|
.sym 28669 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28673 rx_fifo.full_o_SB_LUT4_I1_I3_SB_LUT4_I3_O_SB_DFFER_D_Q[0]
|
|
.sym 28706 w_rx_fifo_pulled_data[13]
|
|
.sym 28710 w_rx_fifo_pulled_data[12]
|
|
.sym 28714 w_rx_fifo_pulled_data[7]
|
|
.sym 28718 smi_ctrl_ins.r_fifo_pulled_data[15]
|
|
.sym 28719 smi_ctrl_ins.r_fifo_pulled_data[7]
|
|
.sym 28720 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28721 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28726 w_rx_fifo_pulled_data[15]
|
|
.sym 28730 smi_ctrl_ins.r_fifo_pulled_data[12]
|
|
.sym 28731 smi_ctrl_ins.r_fifo_pulled_data[4]
|
|
.sym 28732 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28733 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28734 w_rx_fifo_pulled_data[14]
|
|
.sym 28740 w_rx_24_fifo_data[21]
|
|
.sym 28741 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28744 w_rx_24_fifo_data[18]
|
|
.sym 28745 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28748 w_rx_24_fifo_data[23]
|
|
.sym 28749 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28753 rx_fifo.wr_addr[9]
|
|
.sym 28756 w_rx_24_fifo_data[29]
|
|
.sym 28757 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28760 w_rx_24_fifo_data[25]
|
|
.sym 28761 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28764 w_rx_24_fifo_data[27]
|
|
.sym 28765 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 28767 w_rx_24_fifo_data[25]
|
|
.sym 28768 w_rx_09_fifo_data[25]
|
|
.sym 28769 o_led1$SB_IO_OUT
|
|
.sym 28771 w_rx_09_fifo_data[20]
|
|
.sym 28772 w_rx_24_fifo_data[20]
|
|
.sym 28773 o_led1$SB_IO_OUT
|
|
.sym 28774 w_rx_fifo_pulled_data[18]
|
|
.sym 28778 w_rx_fifo_pulled_data[16]
|
|
.sym 28782 w_rx_fifo_pulled_data[17]
|
|
.sym 28787 w_rx_24_fifo_data[23]
|
|
.sym 28788 w_rx_09_fifo_data[23]
|
|
.sym 28789 o_led1$SB_IO_OUT
|
|
.sym 28790 smi_ctrl_ins.r_fifo_pulled_data[24]
|
|
.sym 28791 smi_ctrl_ins.r_fifo_pulled_data[16]
|
|
.sym 28792 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28793 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28794 w_rx_fifo_pulled_data[19]
|
|
.sym 28799 w_rx_09_fifo_data[21]
|
|
.sym 28800 w_rx_24_fifo_data[21]
|
|
.sym 28801 o_led1$SB_IO_OUT
|
|
.sym 28802 smi_ctrl_ins.r_fifo_pulled_data[10]
|
|
.sym 28803 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28804 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28805 smi_ctrl_ins.r_fifo_pulled_data[2]
|
|
.sym 28808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[0]
|
|
.sym 28809 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I2[1]
|
|
.sym 28810 smi_ctrl_ins.r_fifo_pulled_data[14]
|
|
.sym 28811 smi_ctrl_ins.r_fifo_pulled_data[6]
|
|
.sym 28812 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28813 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28816 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[0]
|
|
.sym 28817 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I2[1]
|
|
.sym 28820 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[0]
|
|
.sym 28821 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I2[1]
|
|
.sym 28822 smi_ctrl_ins.r_fifo_pulled_data[27]
|
|
.sym 28823 smi_ctrl_ins.r_fifo_pulled_data[19]
|
|
.sym 28824 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28825 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[0]
|
|
.sym 28829 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I2[1]
|
|
.sym 28830 smi_ctrl_ins.r_fifo_pulled_data[25]
|
|
.sym 28831 smi_ctrl_ins.r_fifo_pulled_data[17]
|
|
.sym 28832 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28833 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28834 w_rx_fifo_pulled_data[27]
|
|
.sym 28838 w_rx_fifo_pulled_data[25]
|
|
.sym 28842 w_rx_fifo_pulled_data[4]
|
|
.sym 28846 w_rx_fifo_pulled_data[26]
|
|
.sym 28850 w_rx_fifo_pulled_data[6]
|
|
.sym 28854 w_rx_fifo_pulled_data[24]
|
|
.sym 28862 w_rx_fifo_pulled_data[5]
|
|
.sym 28874 w_rx_fifo_pulled_data[10]
|
|
.sym 28902 w_rx_fifo_pulled_data[9]
|
|
.sym 28906 w_rx_fifo_pulled_data[11]
|
|
.sym 28914 w_rx_fifo_pulled_data[8]
|
|
.sym 28918 smi_ctrl_ins.r_fifo_pulled_data[9]
|
|
.sym 28919 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28920 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28921 smi_ctrl_ins.r_fifo_pulled_data[1]
|
|
.sym 28922 smi_ctrl_ins.r_fifo_pulled_data[11]
|
|
.sym 28923 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28924 smi_ctrl_ins.r_fifo_pulled_data[3]
|
|
.sym 28925 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28926 smi_ctrl_ins.r_fifo_pulled_data[8]
|
|
.sym 28927 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 28928 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 28929 smi_ctrl_ins.r_fifo_pulled_data[0]
|
|
.sym 28930 w_rx_fifo_pulled_data[2]
|
|
.sym 28945 smi_ctrl_ins.r_fifo_pull_1_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 28950 w_rx_fifo_pulled_data[3]
|
|
.sym 28954 w_rx_fifo_pulled_data[1]
|
|
.sym 28958 w_rx_fifo_pulled_data[0]
|
|
.sym 28965 rx_fifo.rd_addr[1]
|
|
.sym 28968 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 28969 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 28970 rx_fifo.rd_addr[7]
|
|
.sym 28971 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 28972 rx_fifo.rd_addr[6]
|
|
.sym 28973 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[3]
|
|
.sym 28974 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 28975 rx_fifo.rd_addr[9]
|
|
.sym 28976 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 28977 rx_fifo.rd_addr[8]
|
|
.sym 28978 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 28984 rx_fifo.rd_addr[5]
|
|
.sym 28985 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 28990 rx_fifo.rd_addr[5]
|
|
.sym 28991 rx_fifo.rd_addr[4]
|
|
.sym 28992 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 28993 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3]
|
|
.sym 28996 i_rst_b$SB_IO_IN
|
|
.sym 28997 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 28998 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[0]
|
|
.sym 28999 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 29000 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 29001 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D_SB_LUT4_I3_O[3]
|
|
.sym 29002 rx_fifo.wr_addr_gray_rd[6]
|
|
.sym 29006 rx_fifo.wr_addr_gray_rd[7]
|
|
.sym 29010 rx_fifo.wr_addr_gray_rd[5]
|
|
.sym 29014 rx_fifo.wr_addr_gray_rd[3]
|
|
.sym 29018 rx_fifo.wr_addr_gray_rd[2]
|
|
.sym 29022 rx_fifo.wr_addr_gray_rd[4]
|
|
.sym 29026 rx_fifo.wr_addr_gray[7]
|
|
.sym 29030 rx_fifo.wr_addr_gray[2]
|
|
.sym 29035 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 29036 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 29037 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 29040 i_rst_b$SB_IO_IN
|
|
.sym 29041 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 29042 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[0]
|
|
.sym 29043 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[1]
|
|
.sym 29044 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O
|
|
.sym 29045 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q_SB_LUT4_I1_O_SB_LUT4_I2_I3[3]
|
|
.sym 29048 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_I3_SB_LUT4_O_I3[0]
|
|
.sym 29049 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 29050 rx_fifo.rd_addr_gray_wr_r[7]
|
|
.sym 29051 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 29052 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[2]
|
|
.sym 29053 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[3]
|
|
.sym 29056 rx_fifo.full_o_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_2_I0_SB_LUT4_O_2_I1_SB_LUT4_O_1_I3[0]
|
|
.sym 29057 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 29058 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 29062 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
|
|
.sym 29068 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 29069 rx_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 29070 rx_fifo.wr_addr_SB_DFFESR_Q_D[1]
|
|
.sym 29074 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[1]
|
|
.sym 29078 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I3_O[1]
|
|
.sym 29082 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3]
|
|
.sym 29088 rx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 29089 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 29094 rx_fifo.wr_addr_gray_rd[8]
|
|
.sym 29098 rx_fifo.wr_addr_gray[8]
|
|
.sym 29106 rx_fifo.wr_addr_gray[4]
|
|
.sym 29110 rx_fifo.wr_addr_gray[6]
|
|
.sym 29114 rx_fifo.wr_addr_gray[3]
|
|
.sym 29118 rx_fifo.wr_addr_gray[5]
|
|
.sym 29126 rx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 29138 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 29171 w_rx_fifo_full
|
|
.sym 29172 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 29173 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E[1]
|
|
.sym 29176 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_Q[0]
|
|
.sym 29177 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 29194 rx_fifo.rd_addr_gray_wr[7]
|
|
.sym 29222 smi_ctrl_ins.r_fifo_pulled_data[13]
|
|
.sym 29223 smi_ctrl_ins.r_fifo_pulled_data[5]
|
|
.sym 29224 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 29225 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 29236 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 29237 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 29244 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 29245 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 29251 w_rx_24_fifo_data[27]
|
|
.sym 29252 w_rx_09_fifo_data[27]
|
|
.sym 29253 o_led1$SB_IO_OUT
|
|
.sym 29256 w_rx_09_fifo_data[27]
|
|
.sym 29257 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 29264 w_rx_09_fifo_data[28]
|
|
.sym 29265 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 29267 w_rx_24_fifo_data[29]
|
|
.sym 29268 w_rx_09_fifo_data[29]
|
|
.sym 29269 o_led1$SB_IO_OUT
|
|
.sym 29271 w_rx_24_fifo_data[31]
|
|
.sym 29272 lvds_rx_09_inst.o_fifo_data[31]
|
|
.sym 29273 o_led1$SB_IO_OUT
|
|
.sym 29276 w_rx_09_fifo_data[29]
|
|
.sym 29277 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 29280 w_rx_09_fifo_data[25]
|
|
.sym 29281 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 29282 smi_ctrl_ins.r_fifo_pulled_data[28]
|
|
.sym 29283 smi_ctrl_ins.r_fifo_pulled_data[20]
|
|
.sym 29284 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 29285 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 29286 w_rx_fifo_pulled_data[23]
|
|
.sym 29294 smi_ctrl_ins.r_fifo_pulled_data[31]
|
|
.sym 29295 smi_ctrl_ins.r_fifo_pulled_data[23]
|
|
.sym 29296 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 29297 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 29302 w_rx_fifo_pulled_data[22]
|
|
.sym 29310 w_rx_fifo_pulled_data[20]
|
|
.sym 29318 smi_ctrl_ins.r_fifo_pulled_data[26]
|
|
.sym 29319 smi_ctrl_ins.r_fifo_pulled_data[18]
|
|
.sym 29320 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 29321 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 29322 smi_ctrl_ins.r_fifo_pulled_data[30]
|
|
.sym 29323 smi_ctrl_ins.r_fifo_pulled_data[22]
|
|
.sym 29324 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 29325 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 29328 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[0]
|
|
.sym 29329 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I2[1]
|
|
.sym 29332 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 29333 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 29343 w_rx_09_fifo_data[30]
|
|
.sym 29344 w_rx_24_fifo_data[30]
|
|
.sym 29345 o_led1$SB_IO_OUT
|
|
.sym 29347 w_rx_24_fifo_data[28]
|
|
.sym 29348 w_rx_09_fifo_data[28]
|
|
.sym 29349 o_led1$SB_IO_OUT
|
|
.sym 29350 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 29354 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 29358 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 29362 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 29366 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 29373 rx_fifo.rd_addr[0]
|
|
.sym 29374 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 29379 rx_fifo.rd_addr[0]
|
|
.sym 29384 rx_fifo.rd_addr[1]
|
|
.sym 29385 rx_fifo.rd_addr[0]
|
|
.sym 29388 rx_fifo.rd_addr[2]
|
|
.sym 29389 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 29392 rx_fifo.rd_addr[3]
|
|
.sym 29393 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 29396 rx_fifo.rd_addr[4]
|
|
.sym 29397 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 29400 rx_fifo.rd_addr[5]
|
|
.sym 29401 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 29404 rx_fifo.rd_addr[6]
|
|
.sym 29405 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 29408 rx_fifo.rd_addr[7]
|
|
.sym 29409 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 29412 rx_fifo.rd_addr[8]
|
|
.sym 29413 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 29416 rx_fifo.rd_addr[9]
|
|
.sym 29417 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 29418 w_rx_fifo_pulled_data[31]
|
|
.sym 29424 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 29425 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 29426 w_rx_fifo_pulled_data[30]
|
|
.sym 29430 w_rx_fifo_pulled_data[21]
|
|
.sym 29434 w_rx_fifo_pulled_data[29]
|
|
.sym 29438 w_rx_fifo_pulled_data[28]
|
|
.sym 29442 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 29446 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 29452 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 29453 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
|
|
.sym 29456 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
|
|
.sym 29457 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 29458 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
|
|
.sym 29462 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 29463 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 29464 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 29465 rx_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3]
|
|
.sym 29466 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
|
|
.sym 29470 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[0]
|
|
.sym 29471 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[1]
|
|
.sym 29472 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[2]
|
|
.sym 29473 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D_SB_LUT4_I3_O[3]
|
|
.sym 29475 rx_fifo.rd_addr[8]
|
|
.sym 29476 rx_fifo.rd_addr[7]
|
|
.sym 29477 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
|
|
.sym 29480 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 29481 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[0]
|
|
.sym 29482 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 29483 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 29484 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 29485 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 29486 rx_fifo.rd_addr[2]
|
|
.sym 29487 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 29488 rx_fifo.rd_addr[1]
|
|
.sym 29489 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3]
|
|
.sym 29492 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 29493 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 29494 rx_fifo.rd_addr[3]
|
|
.sym 29495 rx_fifo.rd_addr[2]
|
|
.sym 29496 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0]
|
|
.sym 29497 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3[3]
|
|
.sym 29498 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 29499 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 29500 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[2]
|
|
.sym 29501 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O[3]
|
|
.sym 29502 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[0]
|
|
.sym 29503 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[1]
|
|
.sym 29504 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[2]
|
|
.sym 29505 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O_SB_LUT4_I2_O[3]
|
|
.sym 29508 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 29509 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 29511 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0]
|
|
.sym 29512 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 29513 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 29514 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_I3[1]
|
|
.sym 29515 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 29516 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 29517 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 29520 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2_I3_SB_LUT4_O_I3[1]
|
|
.sym 29521 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
|
|
.sym 29523 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0]
|
|
.sym 29524 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
|
|
.sym 29525 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2]
|
|
.sym 29528 w_rx_fifo_full
|
|
.sym 29529 lvds_rx_09_inst.i_sync_input_SB_DFFER_D_Q[2]
|
|
.sym 29532 rx_fifo.rd_addr_SB_DFFESR_Q_6_D[0]
|
|
.sym 29533 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 29536 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 29537 rx_fifo.rd_addr_SB_DFFESR_Q_D[1]
|
|
.sym 29538 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[3]
|
|
.sym 29544 w_lvds_rx_09_d0_SB_LUT4_I2_O[0]
|
|
.sym 29545 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 29547 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[0]
|
|
.sym 29548 o_led1$SB_IO_OUT
|
|
.sym 29549 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_Q[2]
|
|
.sym 29550 rx_fifo.rd_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 29554 rx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
|
|
.sym 29558 rx_fifo.rd_addr_gray_SB_DFFESR_Q_8_D[1]
|
|
.sym 29562 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1]
|
|
.sym 29574 rx_fifo.rd_addr_gray[6]
|
|
.sym 29578 rx_fifo.rd_addr_gray_wr[3]
|
|
.sym 29582 rx_fifo.rd_addr_gray[0]
|
|
.sym 29586 rx_fifo.rd_addr_gray_wr[6]
|
|
.sym 29590 rx_fifo.rd_addr_gray[3]
|
|
.sym 29594 rx_fifo.rd_addr_gray[5]
|
|
.sym 29606 rx_fifo.rd_addr_gray[4]
|
|
.sym 29610 rx_fifo.rd_addr_gray[2]
|
|
.sym 29614 rx_fifo.rd_addr_gray[1]
|
|
.sym 29618 rx_fifo.rd_addr_gray_wr[2]
|
|
.sym 29626 rx_fifo.rd_addr_gray_wr[4]
|
|
.sym 29630 rx_fifo.rd_addr_gray_wr[1]
|
|
.sym 29654 r_tx_data[2]
|
|
.sym 29678 rx_fifo.wr_addr_gray[1]
|
|
.sym 29690 rx_fifo.wr_addr_gray_rd[1]
|
|
.sym 29698 rx_fifo.rd_addr_gray[7]
|
|
.sym 29709 lvds_rx_24_inst.i_sync_input_SB_DFFER_D_E_SB_LUT4_I2_O_SB_DFFER_E_1_Q[1]
|
|
.sym 29741 w_lvds_rx_09_d0_SB_LUT4_I0_O[0]
|
|
.sym 29752 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[0]
|
|
.sym 29753 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I2[1]
|
|
.sym 29764 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 29765 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 29766 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 29770 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 29776 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 29777 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 29778 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[1]
|
|
.sym 29785 tx_fifo.rd_addr[0]
|
|
.sym 29786 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 29790 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 29795 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 29796 tx_fifo.rd_addr[1]
|
|
.sym 29797 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 29798 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 29802 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 29806 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 29807 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[1]
|
|
.sym 29808 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 29809 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 29814 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 29815 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 29816 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 29817 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 29818 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 29822 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 29823 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 29824 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[2]
|
|
.sym 29825 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[3]
|
|
.sym 29826 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 29827 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 29828 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 29829 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 29830 tx_fifo.rd_addr_gray[3]
|
|
.sym 29835 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 29836 tx_fifo.rd_addr[1]
|
|
.sym 29837 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 29838 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 29839 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
|
|
.sym 29840 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 29841 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 29846 tx_fifo.rd_addr_gray_wr[3]
|
|
.sym 29854 tx_fifo.rd_addr_gray[2]
|
|
.sym 29862 w_tx_fifo_empty
|
|
.sym 29863 w_tx_fifo_pull
|
|
.sym 29864 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 29865 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 29866 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 29867 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 29868 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 29869 lvds_tx_inst.r_pulled_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 29870 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[0]
|
|
.sym 29871 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[1]
|
|
.sym 29872 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[2]
|
|
.sym 29873 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O[3]
|
|
.sym 29874 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 29875 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 29876 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 29877 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 29880 i_rst_b$SB_IO_IN
|
|
.sym 29881 w_tx_fifo_pull
|
|
.sym 29882 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 29883 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 29884 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 29885 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[3]
|
|
.sym 29887 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[1]
|
|
.sym 29888 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[1]
|
|
.sym 29889 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.sym 29901 w_tx_fifo_empty
|
|
.sym 29903 w_tx_fifo_pull
|
|
.sym 29904 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 29905 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 29907 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[0]
|
|
.sym 29908 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[1]
|
|
.sym 29909 lvds_tx_inst.r_pulled_SB_LUT4_I1_O[2]
|
|
.sym 29917 i_rst_b$SB_IO_IN
|
|
.sym 29922 smi_ctrl_ins.w_fifo_pull_trigger
|
|
.sym 29926 smi_ctrl_ins.r_fifo_pull
|
|
.sym 29932 rx_fifo.rd_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 29933 rx_fifo.rd_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[0]
|
|
.sym 29934 smi_ctrl_ins.r_fifo_pulled_data[29]
|
|
.sym 29935 smi_ctrl_ins.r_fifo_pulled_data[21]
|
|
.sym 29936 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 29937 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 29951 w_rx_fifo_empty
|
|
.sym 29952 smi_ctrl_ins.r_fifo_pull
|
|
.sym 29953 smi_ctrl_ins.r_fifo_pull_1
|
|
.sym 29956 rx_fifo.rd_addr[1]
|
|
.sym 29957 rx_fifo.wr_addr_gray_rd_r[0]
|
|
.sym 29959 rx_fifo.rd_addr[5]
|
|
.sym 29960 rx_fifo.rd_addr[4]
|
|
.sym 29961 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1_I3[2]
|
|
.sym 29964 rx_fifo.rd_addr[4]
|
|
.sym 29965 rx_fifo.rd_addr[3]
|
|
.sym 29966 o_led1$SB_IO_OUT
|
|
.sym 29974 w_tx_fifo_full
|
|
.sym 29978 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[0]
|
|
.sym 29979 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[1]
|
|
.sym 29980 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[2]
|
|
.sym 29981 rx_fifo.rd_addr_SB_DFFESR_Q_7_D_SB_LUT4_I3_O[3]
|
|
.sym 29983 w_rx_fifo_empty
|
|
.sym 29984 rx_fifo.wr_addr_gray_rd_r[0]
|
|
.sym 29985 rx_fifo.rd_addr_SB_DFFESR_Q_7_D[0]
|
|
.sym 29987 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 29988 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 29989 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 29991 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 29992 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 29993 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
|
|
.sym 29994 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 29998 spi_if_ins.state_if_SB_DFFESR_Q_2_D[2]
|
|
.sym 30004 spi_if_ins.state_if[1]
|
|
.sym 30005 spi_if_ins.state_if[0]
|
|
.sym 30007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30008 spi_if_ins.state_if[1]
|
|
.sym 30009 spi_if_ins.state_if[0]
|
|
.sym 30011 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30012 spi_if_ins.state_if[1]
|
|
.sym 30013 spi_if_ins.state_if[0]
|
|
.sym 30015 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30016 spi_if_ins.state_if[1]
|
|
.sym 30017 spi_if_ins.state_if[0]
|
|
.sym 30018 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 30022 i_rst_b$SB_IO_IN
|
|
.sym 30023 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30024 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 30025 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[3]
|
|
.sym 30026 i_rst_b$SB_IO_IN
|
|
.sym 30027 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 30028 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 30029 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 30031 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 30032 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30033 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30035 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 30036 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
|
|
.sym 30037 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 30040 i_rst_b$SB_IO_IN
|
|
.sym 30041 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 30042 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30043 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30044 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30045 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I2[3]
|
|
.sym 30047 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30048 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30049 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30052 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30053 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 30060 spi_if_ins.w_rx_data[6]
|
|
.sym 30061 spi_if_ins.w_rx_data[5]
|
|
.sym 30065 rx_fifo.full_o_SB_LUT4_I2_O_SB_DFFER_D_E
|
|
.sym 30068 spi_if_ins.w_rx_data[6]
|
|
.sym 30069 spi_if_ins.w_rx_data[5]
|
|
.sym 30080 spi_if_ins.w_rx_data[6]
|
|
.sym 30081 spi_if_ins.w_rx_data[5]
|
|
.sym 30082 w_tx_data_smi[1]
|
|
.sym 30083 w_tx_data_io[1]
|
|
.sym 30084 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 30085 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30093 spi_if_ins.r_tx_byte_SB_DFFE_Q_E
|
|
.sym 30095 io_pmod[6]$SB_IO_IN
|
|
.sym 30096 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 30097 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[2]
|
|
.sym 30099 i_rst_b$SB_IO_IN
|
|
.sym 30100 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
|
|
.sym 30101 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_I3_O[2]
|
|
.sym 30104 i_rst_b$SB_IO_IN
|
|
.sym 30105 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
|
|
.sym 30106 w_tx_data_io[2]
|
|
.sym 30107 w_tx_data_smi[2]
|
|
.sym 30108 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 30109 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30115 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[0]
|
|
.sym 30116 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30117 r_tx_data_SB_DFFE_Q_6_D_SB_LUT4_O_I1[2]
|
|
.sym 30118 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[0]
|
|
.sym 30119 r_tx_data_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
|
|
.sym 30120 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30121 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30123 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[0]
|
|
.sym 30124 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30125 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1[2]
|
|
.sym 30126 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[0]
|
|
.sym 30127 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[1]
|
|
.sym 30128 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30129 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30131 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[0]
|
|
.sym 30132 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30133 r_tx_data_SB_DFFE_Q_2_D_SB_LUT4_O_I1[2]
|
|
.sym 30134 spi_if_ins.o_cs_SB_LUT4_I0_3_O[0]
|
|
.sym 30135 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 30136 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30137 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3]
|
|
.sym 30138 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[0]
|
|
.sym 30139 r_tx_data_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
|
|
.sym 30140 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30142 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 30143 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 30144 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[2]
|
|
.sym 30145 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[3]
|
|
.sym 30148 lvds_rx_24_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 30149 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30152 r_tx_data_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 30153 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30156 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_1_I2[0]
|
|
.sym 30157 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30160 lvds_rx_09_inst.i_sync_input_SB_LUT4_O_I2[1]
|
|
.sym 30161 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30164 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[0]
|
|
.sym 30165 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30168 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_3_I2[0]
|
|
.sym 30169 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30172 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_I2[0]
|
|
.sym 30173 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30176 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O_SB_LUT4_I3_2_I2[0]
|
|
.sym 30177 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 30243 tx_fifo.rd_addr[0]
|
|
.sym 30248 tx_fifo.rd_addr[1]
|
|
.sym 30249 tx_fifo.rd_addr[0]
|
|
.sym 30252 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2]
|
|
.sym 30253 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 30256 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 30257 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_O_I3
|
|
.sym 30260 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 30261 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D_SB_LUT4_O_I3
|
|
.sym 30264 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 30265 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 30268 tx_fifo.rd_addr[6]
|
|
.sym 30269 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 30272 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 30273 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_CARRY_CI_CO
|
|
.sym 30276 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 30277 tx_fifo.rd_addr_SB_DFFNESR_Q_D_SB_LUT4_O_I3
|
|
.sym 30280 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 30281 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D_SB_LUT4_O_I3
|
|
.sym 30283 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 30284 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 30285 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 30287 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 30288 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 30289 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 30292 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 30293 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D[0]
|
|
.sym 30296 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 30297 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 30300 tx_fifo.rd_addr_SB_DFFNESR_Q_4_D[0]
|
|
.sym 30301 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[0]
|
|
.sym 30302 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 30308 tx_fifo.rd_addr[6]
|
|
.sym 30309 tx_fifo.wr_addr_gray_rd_r[6]
|
|
.sym 30310 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 30311 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 30312 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[2]
|
|
.sym 30313 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 30314 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 30315 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 30316 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 30317 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3]
|
|
.sym 30320 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 30321 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 30326 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[0]
|
|
.sym 30327 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[1]
|
|
.sym 30328 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 30329 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[3]
|
|
.sym 30332 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 30333 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 30337 rx_fifo.wr_addr[1]
|
|
.sym 30344 tx_fifo.rd_addr[6]
|
|
.sym 30345 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0]
|
|
.sym 30346 smi_ctrl_ins.w_fifo_push_trigger
|
|
.sym 30350 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[0]
|
|
.sym 30351 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[1]
|
|
.sym 30352 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[2]
|
|
.sym 30353 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O[3]
|
|
.sym 30359 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[1]
|
|
.sym 30360 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3[3]
|
|
.sym 30361 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3[2]
|
|
.sym 30363 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_2_I3[2]
|
|
.sym 30364 tx_fifo.rd_addr_SB_DFFNESR_Q_5_D_SB_LUT4_I3_O[0]
|
|
.sym 30365 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3[0]
|
|
.sym 30366 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 30367 tx_fifo.empty_o_SB_LUT4_I0_O[1]
|
|
.sym 30368 tx_fifo.empty_o_SB_LUT4_I0_O[2]
|
|
.sym 30369 tx_fifo.empty_o_SB_LUT4_I0_O[3]
|
|
.sym 30370 tx_fifo.wr_addr_gray_rd[7]
|
|
.sym 30374 tx_fifo.wr_addr_gray_rd[8]
|
|
.sym 30378 tx_fifo.wr_addr_gray_rd[2]
|
|
.sym 30382 tx_fifo.wr_addr_gray_rd[3]
|
|
.sym 30386 tx_fifo.wr_addr_gray_rd[5]
|
|
.sym 30390 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[0]
|
|
.sym 30391 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[1]
|
|
.sym 30392 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 30393 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 30394 tx_fifo.wr_addr_gray_rd[1]
|
|
.sym 30398 tx_fifo.wr_addr_gray_rd[9]
|
|
.sym 30402 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 30406 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3[0]
|
|
.sym 30407 tx_fifo.rd_addr[1]
|
|
.sym 30408 tx_fifo.empty_o_SB_LUT4_I0_O[0]
|
|
.sym 30409 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 30410 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_5_D[1]
|
|
.sym 30414 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 30420 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 30421 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 30424 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D[1]
|
|
.sym 30425 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 30428 tx_fifo.rd_addr_SB_DFFNESR_Q_D[2]
|
|
.sym 30429 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_D[3]
|
|
.sym 30443 i_rst_b$SB_IO_IN
|
|
.sym 30444 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 30445 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 30449 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 30456 smi_ctrl_ins.int_cnt_rx[4]
|
|
.sym 30457 smi_ctrl_ins.int_cnt_rx[3]
|
|
.sym 30482 w_rx_fifo_empty
|
|
.sym 30499 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30503 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 30504 $PACKER_VCC_NET
|
|
.sym 30507 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 30508 $PACKER_VCC_NET
|
|
.sym 30509 spi_if_ins.spi.r_tx_bit_count_SB_DFFESS_Q_D_SB_LUT4_O_I3
|
|
.sym 30510 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 30511 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[1]
|
|
.sym 30512 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[2]
|
|
.sym 30513 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[3]
|
|
.sym 30517 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30519 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 30520 $PACKER_VCC_NET
|
|
.sym 30521 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30524 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30527 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1[0]
|
|
.sym 30528 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 30529 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30530 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 30531 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 30532 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 30533 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30534 spi_if_ins.r_tx_byte[4]
|
|
.sym 30539 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 30540 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30541 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 30543 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 30544 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[1]
|
|
.sym 30545 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E[2]
|
|
.sym 30546 spi_if_ins.r_tx_byte[7]
|
|
.sym 30551 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 30552 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 30553 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 30556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[1]
|
|
.sym 30557 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[2]
|
|
.sym 30558 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 30559 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 30560 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_2_I2[0]
|
|
.sym 30561 spi_if_ins.spi.r_tx_bit_count[0]
|
|
.sym 30562 i_rst_b$SB_IO_IN
|
|
.sym 30563 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30564 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30565 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30566 spi_if_ins.r_tx_byte[0]
|
|
.sym 30570 spi_if_ins.r_tx_byte[2]
|
|
.sym 30574 w_cs[3]
|
|
.sym 30575 w_cs[2]
|
|
.sym 30576 w_cs[1]
|
|
.sym 30577 w_cs[0]
|
|
.sym 30578 spi_if_ins.r_tx_byte[5]
|
|
.sym 30582 spi_if_ins.r_tx_byte[6]
|
|
.sym 30586 spi_if_ins.r_tx_byte[3]
|
|
.sym 30590 spi_if_ins.r_tx_byte[1]
|
|
.sym 30594 w_cs[3]
|
|
.sym 30595 w_cs[2]
|
|
.sym 30596 w_cs[1]
|
|
.sym 30597 w_cs[0]
|
|
.sym 30598 w_cs[3]
|
|
.sym 30599 w_cs[2]
|
|
.sym 30600 w_cs[1]
|
|
.sym 30601 w_cs[0]
|
|
.sym 30602 w_rx_data[2]
|
|
.sym 30606 w_cs[3]
|
|
.sym 30607 w_cs[2]
|
|
.sym 30608 w_cs[1]
|
|
.sym 30609 w_cs[0]
|
|
.sym 30610 w_tx_data_smi[0]
|
|
.sym 30611 w_tx_data_io[0]
|
|
.sym 30612 spi_if_ins.o_cs_SB_LUT4_I0_4_O[2]
|
|
.sym 30613 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30615 w_tx_data_io[7]
|
|
.sym 30616 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 30617 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30618 w_cs[3]
|
|
.sym 30619 w_cs[2]
|
|
.sym 30620 w_cs[1]
|
|
.sym 30621 w_cs[0]
|
|
.sym 30622 w_rx_data[0]
|
|
.sym 30626 r_tx_data[3]
|
|
.sym 30630 r_tx_data[4]
|
|
.sym 30634 r_tx_data[7]
|
|
.sym 30638 r_tx_data[1]
|
|
.sym 30642 r_tx_data[6]
|
|
.sym 30646 r_tx_data[0]
|
|
.sym 30651 w_tx_data_io[5]
|
|
.sym 30652 r_tx_data_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 30653 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1[3]
|
|
.sym 30654 r_tx_data[5]
|
|
.sym 30658 w_rx_data[6]
|
|
.sym 30662 w_rx_data[3]
|
|
.sym 30666 w_rx_data[2]
|
|
.sym 30670 w_rx_data[5]
|
|
.sym 30674 w_rx_data[7]
|
|
.sym 30678 w_rx_data[1]
|
|
.sym 30683 w_fetch
|
|
.sym 30684 w_cs[0]
|
|
.sym 30685 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O[2]
|
|
.sym 30686 w_rx_data[4]
|
|
.sym 30714 w_rx_data[0]
|
|
.sym 30745 r_counter
|
|
.sym 30758 tx_fifo.wr_addr_gray_rd[6]
|
|
.sym 30766 tx_fifo.wr_addr_gray_rd[0]
|
|
.sym 30772 i_smi_swe_srw$SB_IO_IN
|
|
.sym 30773 i_rst_b$SB_IO_IN
|
|
.sym 30774 tx_fifo.wr_addr_gray[4]
|
|
.sym 30778 tx_fifo.wr_addr_gray_rd[4]
|
|
.sym 30784 i_smi_soe_se$SB_IO_IN
|
|
.sym 30785 i_rst_b$SB_IO_IN
|
|
.sym 30787 tx_fifo.wr_addr[0]
|
|
.sym 30792 tx_fifo.wr_addr[1]
|
|
.sym 30793 tx_fifo.wr_addr[0]
|
|
.sym 30796 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 30797 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3
|
|
.sym 30800 tx_fifo.wr_addr[3]
|
|
.sym 30801 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 30804 tx_fifo.wr_addr[4]
|
|
.sym 30805 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 30808 tx_fifo.wr_addr[5]
|
|
.sym 30809 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
|
|
.sym 30812 tx_fifo.wr_addr[6]
|
|
.sym 30813 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO
|
|
.sym 30816 tx_fifo.wr_addr[7]
|
|
.sym 30817 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 30820 tx_fifo.wr_addr[8]
|
|
.sym 30821 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 30824 tx_fifo.wr_addr[9]
|
|
.sym 30825 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3
|
|
.sym 30826 tx_fifo.rd_addr_gray_wr[6]
|
|
.sym 30830 rx_fifo.wr_addr_gray[0]
|
|
.sym 30834 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 30835 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 30836 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 30837 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 30838 tx_fifo.rd_addr_gray_wr[4]
|
|
.sym 30843 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 30844 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 30845 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 30847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 30848 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 30849 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 30850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 30851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 30852 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 30853 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 30857 w_smi_data_input[7]
|
|
.sym 30860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 30861 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 30867 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 30868 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 30869 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 30870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 30871 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1]
|
|
.sym 30872 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 30873 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3]
|
|
.sym 30878 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
|
|
.sym 30879 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
|
|
.sym 30880 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 30881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 30882 tx_fifo.rd_addr_gray_wr[8]
|
|
.sym 30886 tx_fifo.rd_addr_gray[4]
|
|
.sym 30890 tx_fifo.rd_addr_gray[8]
|
|
.sym 30894 tx_fifo.rd_addr_gray_wr[2]
|
|
.sym 30898 tx_fifo.rd_addr_gray[7]
|
|
.sym 30902 tx_fifo.rd_addr_gray_wr[1]
|
|
.sym 30906 tx_fifo.rd_addr_gray[1]
|
|
.sym 30910 tx_fifo.rd_addr_gray_wr[7]
|
|
.sym 30918 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[2]
|
|
.sym 30930 tx_fifo.rd_addr_gray_SB_DFFNESR_Q_1_D[2]
|
|
.sym 30934 tx_fifo.rd_addr_SB_DFFNESR_Q_3_D_SB_LUT4_I2_O[3]
|
|
.sym 30945 tx_fifo.rd_addr[1]
|
|
.sym 30970 tx_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[0]
|
|
.sym 30974 tx_fifo.rd_addr_gray[6]
|
|
.sym 31006 rx_fifo.wr_addr_gray_rd[0]
|
|
.sym 31019 spi_if_ins.r_tx_byte[7]
|
|
.sym 31020 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 31021 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 31031 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
|
|
.sym 31032 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 31033 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 31045 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 31058 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 31064 i_ss$SB_IO_IN
|
|
.sym 31065 spi_if_ins.r_tx_data_valid
|
|
.sym 31068 i_ss$SB_IO_IN
|
|
.sym 31069 spi_if_ins.r_tx_data_valid
|
|
.sym 31074 sys_ctrl_ins.i_cs_SB_DFFE_Q_D
|
|
.sym 31088 spi_if_ins.w_rx_data[6]
|
|
.sym 31089 spi_if_ins.w_rx_data[5]
|
|
.sym 31094 w_cs[2]
|
|
.sym 31095 w_ioc[1]
|
|
.sym 31096 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 31097 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31100 i_rst_b$SB_IO_IN
|
|
.sym 31101 w_fetch
|
|
.sym 31102 spi_if_ins.w_rx_data[0]
|
|
.sym 31106 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31111 w_ioc[1]
|
|
.sym 31112 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31113 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31123 w_load
|
|
.sym 31124 w_fetch
|
|
.sym 31125 w_cs[0]
|
|
.sym 31126 w_ioc[1]
|
|
.sym 31127 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31128 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0]
|
|
.sym 31129 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 31132 w_ioc[1]
|
|
.sym 31133 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 31134 w_cs[1]
|
|
.sym 31135 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 31136 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31137 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 31140 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I3_O[0]
|
|
.sym 31141 r_tx_data_SB_DFFE_Q_1_D_SB_LUT4_O_I1_SB_DFFER_Q_D_SB_LUT4_O_I2[1]
|
|
.sym 31147 i_config[1]$SB_IO_IN
|
|
.sym 31148 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31149 io_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 31152 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31153 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 31155 w_ioc[1]
|
|
.sym 31156 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31157 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 31158 w_ioc[1]
|
|
.sym 31159 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31160 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 31161 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31163 w_ioc[1]
|
|
.sym 31164 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31165 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31166 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 31167 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31168 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 31169 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3]
|
|
.sym 31170 w_cs[1]
|
|
.sym 31171 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[1]
|
|
.sym 31172 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31173 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 31174 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 31175 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 31176 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31177 i_button_SB_LUT4_I0_O[1]
|
|
.sym 31178 w_rx_data[7]
|
|
.sym 31182 w_ioc[1]
|
|
.sym 31183 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31184 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O_SB_LUT4_O_1_I2[1]
|
|
.sym 31185 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31186 w_rx_data[1]
|
|
.sym 31191 w_ioc[1]
|
|
.sym 31192 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31193 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31194 w_rx_data[6]
|
|
.sym 31198 w_rx_data[4]
|
|
.sym 31203 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 31204 i_button_SB_LUT4_I0_O[1]
|
|
.sym 31205 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[2]
|
|
.sym 31206 i_config[2]$SB_IO_IN
|
|
.sym 31207 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 31208 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31209 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 31210 i_config[3]$SB_IO_IN
|
|
.sym 31211 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 31212 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31213 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 31223 o_tr_vc1$SB_IO_OUT
|
|
.sym 31224 i_button_SB_LUT4_I0_O[1]
|
|
.sym 31225 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_I3[2]
|
|
.sym 31226 i_button$SB_IO_IN
|
|
.sym 31227 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 31228 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31229 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[2]
|
|
.sym 31231 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 31232 i_button_SB_LUT4_I0_O[1]
|
|
.sym 31233 i_button_SB_LUT4_I0_O[2]
|
|
.sym 31250 w_rx_data[5]
|
|
.sym 31270 tx_fifo.wr_addr_gray[6]
|
|
.sym 31294 tx_fifo.wr_addr_gray[0]
|
|
.sym 31301 tx_fifo.wr_addr[1]
|
|
.sym 31304 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 31305 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 31306 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 31310 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 31314 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 31318 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 31322 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 31328 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 31329 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 31332 i_rst_b$SB_IO_IN
|
|
.sym 31333 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 31335 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 31336 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 31337 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 31338 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 31342 tx_fifo.wr_addr_SB_DFFESR_Q_6_D[1]
|
|
.sym 31346 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 31352 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[2]
|
|
.sym 31353 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[1]
|
|
.sym 31357 tx_fifo.wr_addr[0]
|
|
.sym 31360 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 31361 tx_fifo.wr_addr_SB_DFFESR_Q_3_D[1]
|
|
.sym 31364 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 31365 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 31366 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 31367 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 31368 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 31369 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 31370 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[2]
|
|
.sym 31374 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
|
|
.sym 31380 tx_fifo.wr_addr_SB_DFFESR_Q_3_D_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[2]
|
|
.sym 31381 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[1]
|
|
.sym 31382 tx_fifo.wr_addr_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2]
|
|
.sym 31390 tx_fifo.wr_addr_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
|
|
.sym 31394 tx_fifo.wr_addr_gray[1]
|
|
.sym 31398 tx_fifo.wr_addr_gray[3]
|
|
.sym 31402 tx_fifo.wr_addr_gray[2]
|
|
.sym 31406 tx_fifo.wr_addr_gray[8]
|
|
.sym 31418 tx_fifo.wr_addr_gray[5]
|
|
.sym 31422 tx_fifo.wr_addr_gray[7]
|
|
.sym 31426 tx_fifo.rd_addr_gray_wr[5]
|
|
.sym 31446 tx_fifo.rd_addr_gray[0]
|
|
.sym 31462 spi_if_ins.spi.r2_rx_done
|
|
.sym 31470 tx_fifo.rd_addr_gray[5]
|
|
.sym 31476 spi_if_ins.spi.r3_rx_done
|
|
.sym 31477 spi_if_ins.spi.r2_rx_done
|
|
.sym 31514 i_sck$SB_IO_IN
|
|
.sym 31522 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 31538 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 31546 spi_if_ins.spi.SCKr[0]
|
|
.sym 31558 w_rx_data[0]
|
|
.sym 31563 i_rst_b$SB_IO_IN
|
|
.sym 31564 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 31565 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31586 spi_if_ins.w_rx_data[1]
|
|
.sym 31598 spi_if_ins.w_rx_data[4]
|
|
.sym 31602 spi_if_ins.w_rx_data[3]
|
|
.sym 31607 w_ioc[4]
|
|
.sym 31608 w_ioc[3]
|
|
.sym 31609 w_ioc[2]
|
|
.sym 31611 w_ioc[4]
|
|
.sym 31612 w_ioc[3]
|
|
.sym 31613 w_ioc[2]
|
|
.sym 31614 spi_if_ins.w_rx_data[2]
|
|
.sym 31618 w_cs[2]
|
|
.sym 31619 w_load
|
|
.sym 31620 w_fetch
|
|
.sym 31621 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31624 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31625 io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_R[1]
|
|
.sym 31627 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31628 io_pmod[0]$SB_IO_IN
|
|
.sym 31629 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 31630 w_cs[2]
|
|
.sym 31631 w_load
|
|
.sym 31632 w_fetch
|
|
.sym 31633 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31635 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31636 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1[2]
|
|
.sym 31637 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 31639 w_ioc[1]
|
|
.sym 31640 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31641 io_ctrl_ins.o_data_out_SB_DFFE_Q_3_E_SB_LUT4_O_I1_SB_LUT4_I1_O[2]
|
|
.sym 31643 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 31644 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 31645 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[2]
|
|
.sym 31646 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 31647 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31648 io_pmod[1]$SB_IO_IN
|
|
.sym 31649 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 31650 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 31651 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 31652 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 31653 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 31655 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 31656 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 31657 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_1_I3[2]
|
|
.sym 31659 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[0]
|
|
.sym 31660 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31661 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[2]
|
|
.sym 31662 w_cs[1]
|
|
.sym 31663 w_load
|
|
.sym 31664 w_fetch
|
|
.sym 31665 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 31666 io_ctrl_ins.mixer_en_state
|
|
.sym 31667 i_button_SB_LUT4_I0_O[1]
|
|
.sym 31668 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[2]
|
|
.sym 31669 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2[3]
|
|
.sym 31670 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 31671 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[1]
|
|
.sym 31672 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 31673 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 31674 o_tr_vc2$SB_IO_OUT
|
|
.sym 31675 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31676 io_pmod[3]$SB_IO_IN
|
|
.sym 31677 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 31678 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 31679 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 31680 io_pmod[2]$SB_IO_IN
|
|
.sym 31681 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 31682 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
|
|
.sym 31683 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 31684 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31685 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31686 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[0]
|
|
.sym 31687 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[1]
|
|
.sym 31688 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31689 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31690 w_rx_data[3]
|
|
.sym 31694 w_cs[1]
|
|
.sym 31695 w_load
|
|
.sym 31696 w_fetch
|
|
.sym 31697 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31698 w_rx_data[2]
|
|
.sym 31702 i_config[0]$SB_IO_IN
|
|
.sym 31703 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 31704 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_I2_SB_LUT4_O_I1[2]
|
|
.sym 31705 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31706 i_rst_b$SB_IO_IN
|
|
.sym 31707 w_cs[1]
|
|
.sym 31708 w_load
|
|
.sym 31709 w_fetch
|
|
.sym 31710 w_rx_data[0]
|
|
.sym 31718 w_rx_data[0]
|
|
.sym 31734 w_rx_data[1]
|
|
.sym 31740 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 31741 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O[1]
|
|
.sym 31783 i_rst_b$SB_IO_IN
|
|
.sym 31784 w_smi_data_input[7]
|
|
.sym 31785 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 31787 w_smi_data_input[7]
|
|
.sym 31788 smi_ctrl_ins.tx_reg_state[2]
|
|
.sym 31789 smi_ctrl_ins.tx_reg_state[1]
|
|
.sym 31791 i_rst_b$SB_IO_IN
|
|
.sym 31792 w_smi_data_input[7]
|
|
.sym 31793 smi_ctrl_ins.tx_reg_state[2]
|
|
.sym 31796 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 31797 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 31798 i_rst_b$SB_IO_IN
|
|
.sym 31799 w_smi_data_input[7]
|
|
.sym 31800 smi_ctrl_ins.tx_reg_state[3]
|
|
.sym 31801 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 31803 i_rst_b$SB_IO_IN
|
|
.sym 31804 smi_ctrl_ins.tx_reg_state[3]
|
|
.sym 31805 smi_ctrl_ins.tx_reg_state[0]
|
|
.sym 31807 i_rst_b$SB_IO_IN
|
|
.sym 31808 w_smi_data_input[7]
|
|
.sym 31809 smi_ctrl_ins.tx_reg_state[1]
|
|
.sym 31811 tx_fifo.wr_addr[1]
|
|
.sym 31816 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 31817 tx_fifo.wr_addr[1]
|
|
.sym 31820 tx_fifo.wr_addr[3]
|
|
.sym 31821 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 31824 tx_fifo.wr_addr[4]
|
|
.sym 31825 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 31828 tx_fifo.wr_addr[5]
|
|
.sym 31829 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 31832 tx_fifo.wr_addr[6]
|
|
.sym 31833 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 31836 tx_fifo.wr_addr[7]
|
|
.sym 31837 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI
|
|
.sym 31840 tx_fifo.wr_addr[8]
|
|
.sym 31841 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI
|
|
.sym 31844 tx_fifo.wr_addr[9]
|
|
.sym 31845 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3
|
|
.sym 31847 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 31848 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 31849 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 31850 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[0]
|
|
.sym 31851 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 31852 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
|
|
.sym 31853 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[3]
|
|
.sym 31855 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[0]
|
|
.sym 31856 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3_SB_LUT4_O_I2[1]
|
|
.sym 31857 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 31858 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 31859 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_I3[2]
|
|
.sym 31860 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 31861 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[3]
|
|
.sym 31863 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[0]
|
|
.sym 31864 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 31865 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 31866 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 31870 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[0]
|
|
.sym 31871 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 31872 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O[1]
|
|
.sym 31873 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I2_I3[3]
|
|
.sym 31874 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[0]
|
|
.sym 31875 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1]
|
|
.sym 31876 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
|
|
.sym 31877 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
|
|
.sym 31878 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 31879 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 31880 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[2]
|
|
.sym 31881 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
|
|
.sym 31882 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 31883 tx_fifo.wr_addr[1]
|
|
.sym 31884 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 31885 tx_fifo.wr_addr_gray_SB_DFFESR_Q_D[2]
|
|
.sym 31886 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[0]
|
|
.sym 31887 tx_fifo.rd_addr_gray_wr_r[8]
|
|
.sym 31888 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O[2]
|
|
.sym 31889 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[3]
|
|
.sym 31890 tx_fifo.wr_addr[9]
|
|
.sym 31896 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[0]
|
|
.sym 31897 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1]
|
|
.sym 31899 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[0]
|
|
.sym 31900 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[1]
|
|
.sym 31901 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O[2]
|
|
.sym 31903 tx_fifo.full_o_SB_LUT4_I1_O[0]
|
|
.sym 31904 tx_fifo.full_o_SB_LUT4_I1_O[1]
|
|
.sym 31905 tx_fifo.full_o_SB_LUT4_I1_O[2]
|
|
.sym 31915 w_tx_fifo_full
|
|
.sym 31916 tx_fifo.wr_addr[1]
|
|
.sym 31917 smi_ctrl_ins.r_fifo_push_1_SB_LUT4_I2_O_SB_LUT4_I3_1_O_SB_LUT4_O_I3[1]
|
|
.sym 31922 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 31923 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 31924 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[2]
|
|
.sym 31925 tx_fifo.full_o_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 31927 w_tx_fifo_full
|
|
.sym 31928 smi_ctrl_ins.r_fifo_push_1
|
|
.sym 31929 smi_ctrl_ins.r_fifo_push
|
|
.sym 31934 smi_ctrl_ins.r_fifo_push
|
|
.sym 31938 tx_fifo.rd_addr_gray_wr[0]
|
|
.sym 31943 w_rx_fifo_empty
|
|
.sym 31944 w_tx_fifo_full
|
|
.sym 31945 o_led0$SB_IO_OUT
|
|
.sym 31946 spi_if_ins.spi.r_rx_done
|
|
.sym 31962 tx_fifo.rd_addr_gray_wr[9]
|
|
.sym 31974 i_mosi$SB_IO_IN
|
|
.sym 31985 o_miso_$_TBUF__Y_E
|
|
.sym 31986 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 32002 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 32006 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 32010 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 32014 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 32018 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 32022 i_mosi$SB_IO_IN
|
|
.sym 32026 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 32030 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 32034 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 32038 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 32042 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 32046 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 32050 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 32054 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 32058 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 32062 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 32090 spi_if_ins.w_rx_data[0]
|
|
.sym 32094 spi_if_ins.state_if_SB_DFFESR_Q_2_D[0]
|
|
.sym 32098 spi_if_ins.w_rx_data[2]
|
|
.sym 32102 spi_if_ins.w_rx_data[1]
|
|
.sym 32106 spi_if_ins.w_rx_data[5]
|
|
.sym 32110 spi_if_ins.w_rx_data[4]
|
|
.sym 32114 spi_if_ins.w_rx_data[6]
|
|
.sym 32122 spi_if_ins.w_rx_data[3]
|
|
.sym 32143 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[0]
|
|
.sym 32144 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 32145 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[2]
|
|
.sym 32158 w_rx_data[0]
|
|
.sym 32162 w_rx_data[0]
|
|
.sym 32166 w_rx_data[1]
|
|
.sym 32170 w_rx_data[4]
|
|
.sym 32176 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 32177 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q_SB_LUT4_I1_O[1]
|
|
.sym 32178 w_rx_data[2]
|
|
.sym 32182 w_rx_data[3]
|
|
.sym 32186 i_rst_b$SB_IO_IN
|
|
.sym 32187 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 32188 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 32189 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32192 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_Q[0]
|
|
.sym 32193 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[1]
|
|
.sym 32194 w_rx_data[0]
|
|
.sym 32198 w_rx_data[4]
|
|
.sym 32202 w_rx_data[7]
|
|
.sym 32206 w_rx_data[6]
|
|
.sym 32210 w_rx_data[2]
|
|
.sym 32214 w_rx_data[3]
|
|
.sym 32218 w_rx_data[1]
|
|
.sym 32222 w_rx_data[5]
|
|
.sym 32252 io_pmod_SB_DFFE_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 32253 i_button_SB_LUT4_I0_O[1]
|
|
.sym 32473 i_ss$SB_IO_IN
|
|
.sym 32474 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 32483 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 32488 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 32489 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 32492 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 32493 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3
|
|
.sym 32498 i_ss$SB_IO_IN
|
|
.sym 32499 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 32500 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 32501 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 32505 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 32507 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 32508 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 32509 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 32514 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 32526 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 32530 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 32534 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 32540 i_ss$SB_IO_IN
|
|
.sym 32541 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 32542 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 32614 w_rx_data[2]
|
|
.sym 32622 w_rx_data[1]
|
|
.sym 32630 w_rx_data[3]
|
|
.sym 32670 w_rx_data[0]
|
|
.sym 32686 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 32687 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 32688 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32689 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32690 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 32691 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 32692 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32693 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32706 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 32707 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 32708 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32709 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32710 io_ctrl_ins.rf_pin_state[5]
|
|
.sym 32711 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32712 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 32713 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32714 io_ctrl_ins.rf_pin_state[4]
|
|
.sym 32715 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32716 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I2[2]
|
|
.sym 32717 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32718 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 32719 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 32720 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32721 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32723 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 32724 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[3]
|
|
.sym 32725 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32727 io_ctrl_ins.rf_pin_state[6]
|
|
.sym 32728 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32729 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 32732 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O_SB_DFFER_Q_E_SB_DFFER_E_3_Q[2]
|
|
.sym 32733 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I0_O_SB_LUT4_I3_O[0]
|
|
.sym 32735 io_ctrl_ins.rf_pin_state[7]
|
|
.sym 32736 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3]
|
|
.sym 32737 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|