kopia lustrzana https://github.com/cariboulabs/cariboulite
132 wiersze
4.3 KiB
Verilog
132 wiersze
4.3 KiB
Verilog
module smi_ctrl ( input i_rst_b,
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input i_sys_clk, // FPGA Clock
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input i_fast_clk,
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input [4:0] i_ioc,
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input [7:0] i_data_in,
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output reg [7:0] o_data_out,
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input i_cs,
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input i_fetch_cmd,
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input i_load_cmd,
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// FIFO INTERFACE
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output o_fifo_pull,
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input [31:0] i_fifo_pulled_data,
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input i_fifo_full,
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input i_fifo_empty,
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// SMI INTERFACE
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input i_smi_soe_se,
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input i_smi_swe_srw,
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output reg [7:0] o_smi_data_out,
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input [7:0] i_smi_data_in,
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output o_smi_read_req,
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output o_smi_write_req,
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input i_smi_test,
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output o_channel,
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// Errors
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output reg o_address_error);
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// MODULE SPECIFIC IOC LIST
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// ------------------------
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localparam
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ioc_module_version = 5'b00000, // read only
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ioc_fifo_status = 5'b00001, // read-only
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ioc_channel_select = 5'b00010;
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// MODULE SPECIFIC PARAMS
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// ----------------------
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localparam
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module_version = 8'b00000001;
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always @(posedge i_sys_clk or negedge i_rst_b)
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begin
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if (i_rst_b == 1'b0) begin
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o_address_error <= 1'b0;
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w_channel <= 1'b0;
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end else begin
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if (i_cs == 1'b1) begin
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//=============================================
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// READ OPERATIONS
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//=============================================
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if (i_fetch_cmd == 1'b1) begin
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case (i_ioc)
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//----------------------------------------------
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ioc_module_version: o_data_out <= module_version; // Module Version
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//----------------------------------------------
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ioc_fifo_status: begin
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o_data_out[0] <= i_fifo_empty;
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o_data_out[1] <= r_channel;
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o_data_out[7:2] <= 6'b000000;
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end
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endcase
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end
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//=============================================
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// WRITE OPERATIONS
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//=============================================
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else if (i_load_cmd == 1'b1) begin
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case (i_ioc)
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//----------------------------------------------
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ioc_channel_select: begin
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r_channel <= i_data_in[0];
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end
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endcase
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end
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end
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end
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end
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// Tell the RPI that data is pending in either of the two fifos
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assign o_smi_read_req = (!i_fifo_empty) || i_smi_test;
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reg [4:0] int_cnt;
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reg r_fifo_pull;
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reg r_fifo_pull_1;
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wire w_fifo_pull_trigger;
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reg r_channel;
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assign o_channel = r_channel;
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reg [7:0] r_smi_test_count;
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wire soe_and_reset;
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assign soe_and_reset = i_rst_b & i_smi_soe_se;
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always @(negedge soe_and_reset)
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begin
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if (i_rst_b == 1'b0) begin
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int_cnt <= 5'd31;
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r_smi_test_count <= 8'h56;
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end else begin
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w_fifo_pull_trigger <= (int_cnt == 5'd7) && !i_smi_test;
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if ( i_smi_test ) begin
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if (r_smi_test_count == 0) begin
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r_smi_test_count <= 8'h56;
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end else begin
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o_smi_data_out <= r_smi_test_count;
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r_smi_test_count <= {((r_smi_test_count[2] ^ r_smi_test_count[3]) & 1'b1), r_smi_test_count[7:1]};
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end
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end else begin
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int_cnt <= int_cnt - 8;
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o_smi_data_out <= i_fifo_pulled_data[int_cnt:int_cnt-7];
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end
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end
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end
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always @(posedge i_sys_clk)
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begin
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if (i_rst_b == 1'b0) begin
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r_fifo_pull <= 1'b0;
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r_fifo_pull_1 <= 1'b0;
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end else begin
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r_fifo_pull <= w_fifo_pull_trigger;
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r_fifo_pull_1 <= r_fifo_pull;
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end
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end
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assign o_fifo_pull = !r_fifo_pull_1 && r_fifo_pull && !i_fifo_empty;
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endmodule // smi_ctrl
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