kopia lustrzana https://github.com/cariboulabs/cariboulite
164 wiersze
5.6 KiB
Verilog
164 wiersze
5.6 KiB
Verilog
module smi_ctrl
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(
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input i_reset,
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input i_sys_clk, // FPGA Clock
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input [4:0] i_ioc,
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input [7:0] i_data_in,
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output reg [7:0] o_data_out,
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input i_cs,
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input i_fetch_cmd,
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input i_load_cmd,
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// FIFO INTERFACE 0.9 GHz
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output o_fifo_09_pull,
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input [31:0] i_fifo_09_pulled_data,
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input i_fifo_09_full,
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input i_fifo_09_empty,
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// FIFO INTERFACE 2.4 GHz
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output o_fifo_24_pull,
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input [31:0] i_fifo_24_pulled_data,
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input i_fifo_24_full,
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input i_fifo_24_empty,
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// SMI INTERFACE
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input [2:0] i_smi_a,
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input i_smi_soe_se,
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input i_smi_swe_srw,
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output reg [7:0] o_smi_data_out,
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input [7:0] i_smi_data_in,
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output o_smi_read_req,
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output o_smi_write_req,
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output o_smi_writing,
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input i_smi_test,
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// Errors
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output reg o_address_error );
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// MODULE SPECIFIC IOC LIST
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// ------------------------
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localparam
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ioc_module_version = 5'b00000, // read only
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ioc_fifo_status = 5'b00001; // read-only
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// MODULE SPECIFIC PARAMS
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// ----------------------
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localparam
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module_version = 8'b00000001;
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// SMI ADDRESS DEFS
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// ----------------
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localparam
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smi_address_idle = 3'b000,
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smi_address_write_900 = 3'b001,
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smi_address_write_2400 = 3'b010,
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smi_address_write_res2 = 3'b011,
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smi_address_read_res1 = 3'b100,
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smi_address_read_900 = 3'b101,
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smi_address_read_2400 = 3'b110,
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smi_address_read_res = 3'b111;
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always @(posedge i_sys_clk)
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begin
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if (i_reset) begin
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o_address_error <= 1'b0;
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// put the initial states here
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end else begin
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if (i_cs == 1'b1) begin
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if (i_fetch_cmd == 1'b1) begin
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case (i_ioc)
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//----------------------------------------------
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ioc_module_version: o_data_out <= module_version; // Module Version
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//----------------------------------------------
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ioc_fifo_status: begin
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o_data_out[0] <= i_fifo_09_empty;
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o_data_out[1] <= i_fifo_09_full;
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o_data_out[2] <= i_fifo_24_empty;
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o_data_out[3] <= i_fifo_24_full;
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o_data_out[7:4] <= 4'b0000;
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end
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endcase
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end
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end
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end
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end
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// Tell the RPI that data is pending in either of the two fifos
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assign o_smi_read_req = !i_fifo_09_empty || !i_fifo_24_empty /*|| i_smi_test*/;
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//assign o_smi_read_req = (!i_fifo_09_empty && (i_smi_a == smi_address_read_900)) ||
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// (!i_fifo_24_empty && (i_smi_a == smi_address_read_2400));
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//assign o_smi_read_req = 1'b1;
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//!i_fifo_09_empty || !i_fifo_24_empty;
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reg [4:0] int_cnt_09;
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reg [4:0] int_cnt_24;
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reg r_fifo_09_pull;
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reg r_fifo_09_pull_1;
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wire w_fifo_09_pull_trigger;
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reg r_fifo_24_pull;
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reg r_fifo_24_pull_1;
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wire w_fifo_24_pull_trigger;
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reg [7:0] r_smi_test_count_09;
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reg [7:0] r_smi_test_count_24;
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wire soe_and_reset;
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assign soe_and_reset = !i_reset && i_smi_soe_se;
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always @(negedge soe_and_reset)
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begin
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if (i_reset) begin
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int_cnt_09 <= 5'd31;
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int_cnt_24 <= 5'd31;
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r_smi_test_count_09 <= 8'b00000000;
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r_smi_test_count_24 <= 8'b00000000;
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end else begin
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w_fifo_09_pull_trigger <= !i_fifo_09_empty && (int_cnt_09 == 5'd7);
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w_fifo_24_pull_trigger <= !i_fifo_24_empty && (int_cnt_24 == 5'd7);
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if (i_smi_a == smi_address_read_900) begin
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if ( i_smi_test ) begin
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o_smi_data_out <= r_smi_test_count_09;
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r_smi_test_count_09 <= r_smi_test_count_09 + 1'b1;
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end else begin
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int_cnt_09 <= int_cnt_09 - 8;
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o_smi_data_out <= i_fifo_09_pulled_data[int_cnt_09:int_cnt_09-7];
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end
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end else if (i_smi_a == smi_address_read_2400) begin
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if ( i_smi_test ) begin
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o_smi_data_out <= r_smi_test_count_24;
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r_smi_test_count_24 <= r_smi_test_count_24 + 1'b1;
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end else begin
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int_cnt_24 <= int_cnt_24 - 8;
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o_smi_data_out <= i_fifo_24_pulled_data[int_cnt_24:int_cnt_24-7];
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end
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end
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end
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end
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always @(posedge i_sys_clk)
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begin
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if (i_reset) begin
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r_fifo_09_pull <= 1'b0;
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r_fifo_24_pull <= 1'b0;
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r_fifo_09_pull_1 <= 1'b0;
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r_fifo_24_pull_1 <= 1'b0;
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end else begin
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r_fifo_09_pull <= w_fifo_09_pull_trigger;
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r_fifo_24_pull <= w_fifo_24_pull_trigger;
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r_fifo_09_pull_1 <= r_fifo_09_pull;
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r_fifo_24_pull_1 <= r_fifo_24_pull;
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end
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end
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//assign o_smi_data_out = 8'b01011010;
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assign o_fifo_09_pull = !r_fifo_09_pull_1 && r_fifo_09_pull && !i_fifo_09_empty;
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assign o_fifo_24_pull = !r_fifo_24_pull_1 && r_fifo_24_pull && !i_fifo_24_empty;
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assign o_smi_writing = i_smi_a[2];
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endmodule // smi_ctrl
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