kopia lustrzana https://github.com/cariboulabs/cariboulite
123 wiersze
3.6 KiB
Verilog
123 wiersze
3.6 KiB
Verilog
/*
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* Copyright (c) 2012, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* All rights reserved.
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*
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* Based on vga_fifo_dc.v in Richard Herveille's VGA/LCD core
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* Copyright (C) 2001 Richard Herveille <richard@asics.ws>
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*
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* Redistribution and use in source and non-source forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in non-source form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module dual_clock_fifo #(
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parameter ADDR_WIDTH = 8,
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parameter DATA_WIDTH = 16
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)
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(
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input wire wr_rst_i,
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input wire wr_clk_i,
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input wire wr_en_i,
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input wire [DATA_WIDTH-1:0] wr_data_i,
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input wire rd_rst_i,
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input wire rd_clk_i,
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input wire rd_en_i,
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output reg [DATA_WIDTH-1:0] rd_data_o,
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output reg full_o,
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output reg empty_o
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);
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reg [ADDR_WIDTH-1:0] wr_addr;
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reg [ADDR_WIDTH-1:0] wr_addr_gray;
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reg [ADDR_WIDTH-1:0] wr_addr_gray_rd;
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reg [ADDR_WIDTH-1:0] wr_addr_gray_rd_r;
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reg [ADDR_WIDTH-1:0] rd_addr;
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reg [ADDR_WIDTH-1:0] rd_addr_gray;
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr;
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr_r;
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function [ADDR_WIDTH-1:0] gray_conv;
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input [ADDR_WIDTH-1:0] in;
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begin
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gray_conv = {in[ADDR_WIDTH-1],
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in[ADDR_WIDTH-2:0] ^ in[ADDR_WIDTH-1:1]};
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end
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endfunction
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always @(posedge wr_clk_i) begin
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if (wr_rst_i) begin
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wr_addr <= 0;
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wr_addr_gray <= 0;
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end else if (wr_en_i) begin
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wr_addr <= wr_addr + 1'b1;
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wr_addr_gray <= gray_conv(wr_addr + 1'b1);
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end
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end
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// synchronize read address to write clock domain
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always @(posedge wr_clk_i) begin
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rd_addr_gray_wr <= rd_addr_gray;
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rd_addr_gray_wr_r <= rd_addr_gray_wr;
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end
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always @(posedge wr_clk_i)
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if (wr_rst_i)
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full_o <= 0;
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else if (wr_en_i)
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full_o <= gray_conv(wr_addr + 2) == rd_addr_gray_wr_r;
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else
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full_o <= full_o & (gray_conv(wr_addr + 1'b1) == rd_addr_gray_wr_r);
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always @(posedge rd_clk_i) begin
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if (rd_rst_i) begin
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rd_addr <= 0;
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rd_addr_gray <= 0;
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end else if (rd_en_i) begin
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rd_addr <= rd_addr + 1'b1;
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rd_addr_gray <= gray_conv(rd_addr + 1'b1);
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end
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end
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// synchronize write address to read clock domain
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always @(posedge rd_clk_i) begin
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wr_addr_gray_rd <= wr_addr_gray;
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wr_addr_gray_rd_r <= wr_addr_gray_rd;
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end
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always @(posedge rd_clk_i)
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if (rd_rst_i)
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empty_o <= 1'b1;
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else if (rd_en_i)
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empty_o <= gray_conv(rd_addr + 1) == wr_addr_gray_rd_r;
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else
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empty_o <= empty_o & (gray_conv(rd_addr) == wr_addr_gray_rd_r);
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reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
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always @(posedge rd_clk_i)
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if (rd_en_i)
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rd_data_o <= mem[rd_addr];
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always @(posedge wr_clk_i)
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if (wr_en_i)
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mem[wr_addr] <= wr_data_i;
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endmodule
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