kopia lustrzana https://github.com/cariboulabs/cariboulite
70 wiersze
1.9 KiB
Verilog
70 wiersze
1.9 KiB
Verilog
module complex_fifo #(
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parameter ADDR_WIDTH = 10,
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parameter DATA_WIDTH = 16
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)
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(
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input wire wr_rst_i,
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input wire wr_clk_i,
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input wire wr_en_i,
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input wire [2*DATA_WIDTH-1:0] wr_data_i,
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input wire rd_rst_i,
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input wire rd_clk_i,
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input wire rd_en_i,
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output reg [2*DATA_WIDTH-1:0] rd_data_o,
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output reg full_o,
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output reg empty_o
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);
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reg [ADDR_WIDTH-1:0] wr_addr;
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reg [ADDR_WIDTH-1:0] rd_addr;
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always @(posedge wr_clk_i) begin
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if (wr_rst_i) begin
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wr_addr <= 0;
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full_o <= 1'b0;
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end else begin
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if (wr_en_i) begin
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wr_addr <= wr_addr + 1'b1;
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full_o <= (wr_addr + 2) == rd_addr;
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mem_i[wr_addr] <= wr_data_i[31:16];
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mem_q[wr_addr] <= wr_data_i[15:0];
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end else begin
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full_o <= full_o & ((wr_addr + 1'b1) == rd_addr);
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end
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end
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end
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//reg [1:0] cnt;
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always @(posedge rd_clk_i) begin
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if (rd_rst_i) begin
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rd_addr <= 0;
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empty_o <= 1'b1;
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//cnt <= 2'b00;
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end else begin
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if (rd_en_i) begin
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rd_addr <= rd_addr + 1'b1;
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empty_o <= (rd_addr + 1) == wr_addr;
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// big endien to little endien the following is the regular read, and it is
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// followed by the converted form
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//rd_data_o[29:16] <= mem_i[rd_addr][13:0];
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//rd_data_o[15:0] <= mem_q[rd_addr];
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//rd_data_o[31:30] <= cnt;
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//cnt <= cnt + 1;
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rd_data_o[31:24] <= mem_q[rd_addr][7:0];
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rd_data_o[23:16] <= mem_q[rd_addr][15:8];
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rd_data_o[15:8] <= mem_i[rd_addr][7:0];
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rd_data_o[7:0] <= mem_i[rd_addr][15:8];
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end else begin
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empty_o <= empty_o & (rd_addr == wr_addr);
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end
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end
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end
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reg [DATA_WIDTH-1:0] mem_i[(1<<ADDR_WIDTH)-1:0];
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reg [DATA_WIDTH-1:0] mem_q[(1<<ADDR_WIDTH)-1:0];
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endmodule
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