kopia lustrzana https://github.com/cariboulabs/cariboulite
80 wiersze
2.5 KiB
Verilog
80 wiersze
2.5 KiB
Verilog
module smi_ctrl
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(
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input i_rst_b, // FPGA Reset
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input i_sys_clk, // FPGA Clock
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input [4:0] i_ioc,
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input [7:0] i_data_in,
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output reg [7:0] o_data_out,
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input i_cs,
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input i_fetch_cmd,
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input i_load_cmd,
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// FIFO INTERFACE 0.9 GHz
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output o_fifo_09_pull,
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input [31:0] i_fifo_09_pulled_data,
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input i_fifo_09_full,
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input i_fifo_09_empty,
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// FIFO INTERFACE 2.4 GHz
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output o_fifo_24_pull,
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input [31:0] i_fifo_24_pulled_data,
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input i_fifo_24_full,
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input i_fifo_24_empty,
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// SMI INTERFACE
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input [2:0] i_smi_a,
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input i_smi_soe_se,
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input i_smi_swe_srw,
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output [7:0] o_smi_data_out,
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inout [7:0] i_smi_data_in,
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output o_smi_read_req,
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output o_smi_write_req,
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output o_smi_writing );
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// MODULE SPECIFIC IOC LIST
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// ------------------------
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localparam
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ioc_module_version = 5'b00000, // read only
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ioc_fifo_status = 5'b00001; // read-only
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// MODULE SPECIFIC PARAMS
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// ----------------------
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localparam
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module_version = 8'b00000001;
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assign o_smi_writing = 1'b0;
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always @(posedge i_sys_clk)
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begin
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if (i_cs == 1'b1) begin
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if (i_fetch_cmd == 1'b1) begin
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case (i_ioc)
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//----------------------------------------------
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ioc_module_version: o_data_out <= module_version; // Module Version
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//----------------------------------------------
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ioc_fifo_status: begin
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o_data_out[0] <= i_fifo_09_empty;
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o_data_out[1] <= i_fifo_09_full;
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o_data_out[2] <= i_fifo_24_empty;
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o_data_out[3] <= i_fifo_24_full;
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o_data_out[7:4] <= 4'b0000;
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end
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endcase
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end
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end else begin
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o_data_out <= 8'b00000000;
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end
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end
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always @(posedge i_sys_clk)
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begin
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if (i_fifo_09_empty == 1'b0) begin
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end
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end
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endmodule // smi_ctrl
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