kopia lustrzana https://github.com/cariboulabs/cariboulite
12667 wiersze
533 KiB
Plaintext
12667 wiersze
533 KiB
Plaintext
.comment from next-pnr
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.sym 1 i_sck$SB_IO_IN_$glb_clk
|
|
.sym 2 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 3 r_counter_$glb_clk
|
|
.sym 4 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 5 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 6 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 7 lvds_clock_$glb_clk
|
|
.sym 8 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 211 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 255 $PACKER_VCC_NET
|
|
.sym 296 lvds_rx_09_inst.r_data[14]
|
|
.sym 405 lvds_rx_09_inst.r_data[16]
|
|
.sym 406 lvds_rx_09_inst.r_data[18]
|
|
.sym 409 lvds_rx_09_inst.r_data[20]
|
|
.sym 431 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 433 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 435 rx_24_fifo.rd_addr[4]
|
|
.sym 483 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 485 lvds_clock
|
|
.sym 524 w_rx_09_fifo_data[20]
|
|
.sym 530 i_smi_a1$SB_IO_IN
|
|
.sym 539 rx_24_fifo.rd_addr[9]
|
|
.sym 633 lvds_rx_09_inst.r_data[1]
|
|
.sym 637 lvds_rx_09_inst.r_data[0]
|
|
.sym 642 w_rx_09_fifo_data[20]
|
|
.sym 779 w_lvds_rx_09_d1
|
|
.sym 823 w_lvds_rx_09_d0
|
|
.sym 826 w_lvds_rx_09_d1
|
|
.sym 827 w_lvds_rx_09_d0
|
|
.sym 830 lvds_clock
|
|
.sym 852 lvds_clock
|
|
.sym 940 lvds_clock
|
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.sym 941 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
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.sym 944 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
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.sym 963 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
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.sym 1037 $PACKER_VCC_NET
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.sym 1054 w_lvds_rx_09_d1
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.sym 1055 w_lvds_rx_09_d0
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.sym 1056 $PACKER_VCC_NET
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.sym 1164 smi_ctrl_ins.int_cnt_24[4]
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.sym 1169 w_lvds_rx_24_d0
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.sym 1173 w_lvds_rx_09_d1
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.sym 1174 w_lvds_rx_09_d0
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.sym 1183 $PACKER_VCC_NET
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.sym 1184 lvds_clock_$glb_clk
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.sym 1196 $PACKER_VCC_NET
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.sym 1203 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
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.sym 1205 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
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.sym 1209 w_lvds_rx_09_d1_SB_LUT4_I1_O[1]
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.sym 1235 w_lvds_rx_24_d1
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.sym 1278 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
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.sym 1279 w_lvds_rx_24_d0
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.sym 1282 w_lvds_rx_24_d1
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.sym 1283 w_lvds_rx_24_d0
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.sym 1287 lvds_clock
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.sym 1297 $PACKER_VCC_NET
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.sym 1313 $PACKER_VCC_NET
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.sym 1317 lvds_rx_09_inst.o_debug_state[0]
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.sym 1318 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
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.sym 1319 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E
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.sym 1322 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E
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.sym 1323 lvds_rx_09_inst.o_debug_state[1]
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.sym 1342 w_rx_24_fifo_data[7]
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.sym 1347 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
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.sym 1373 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
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.sym 1391 $PACKER_VCC_NET
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.sym 1401 w_lvds_rx_24_d1
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.sym 1402 w_lvds_rx_24_d0
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.sym 1411 $PACKER_VCC_NET
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.sym 1412 lvds_clock_$glb_clk
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.sym 1416 $PACKER_VCC_NET
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.sym 1438 w_lvds_rx_24_d1
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.sym 1440 w_lvds_rx_24_d0
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.sym 1457 lvds_rx_09_inst.o_debug_state[1]
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.sym 1463 w_lvds_rx_09_d1
|
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.sym 1474 $PACKER_VCC_NET
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.sym 1487 w_lvds_rx_09_d0
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.sym 1560 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
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.sym 1621 w_lvds_rx_24_d0
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.sym 1879 w_rx_09_fifo_data[11]
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.sym 1880 w_rx_09_fifo_data[8]
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.sym 1881 w_rx_09_fifo_data[9]
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.sym 1883 w_rx_09_fifo_data[10]
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.sym 2063 lvds_rx_09_inst.r_data[12]
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.sym 2064 lvds_rx_09_inst.r_data[11]
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.sym 2065 lvds_rx_09_inst.r_data[7]
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.sym 2066 lvds_rx_09_inst.r_data[10]
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.sym 2067 lvds_rx_09_inst.r_data[8]
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.sym 2068 lvds_rx_09_inst.r_data[6]
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.sym 2069 lvds_rx_09_inst.r_data[9]
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.sym 2070 lvds_rx_09_inst.r_data[13]
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.sym 2081 lvds_rx_09_inst.o_debug_state[0]
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.sym 2125 lvds_rx_09_inst.r_data[4]
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.sym 2127 lvds_rx_09_inst.r_data[12]
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.sym 2145 lvds_rx_09_inst.o_debug_state[0]
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.sym 2236 w_rx_09_fifo_data[24]
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.sym 2238 w_rx_09_fifo_data[25]
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.sym 2239 w_rx_09_fifo_data[26]
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.sym 2240 w_rx_09_fifo_data[27]
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.sym 2243 lvds_rx_09_inst.o_debug_state[0]
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.sym 2244 lvds_rx_09_inst.o_debug_state[0]
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.sym 2265 lvds_rx_09_inst.o_debug_state[0]
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.sym 2268 lvds_rx_09_inst.r_data[13]
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.sym 2369 lvds_rx_09_inst.r_data[23]
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.sym 2370 lvds_rx_09_inst.r_data[22]
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.sym 2371 lvds_rx_09_inst.r_data[24]
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.sym 2372 lvds_rx_09_inst.r_data[4]
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.sym 2373 lvds_rx_09_inst.r_data[25]
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.sym 2374 lvds_rx_09_inst.r_data[15]
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.sym 2382 w_smi_data_output[3]
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.sym 2396 lvds_rx_09_inst.r_data[21]
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.sym 2398 lvds_rx_09_inst.r_data[5]
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.sym 2402 lvds_rx_09_inst.r_data[2]
|
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.sym 2438 lvds_rx_09_inst.r_data[12]
|
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.sym 2451 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 2486 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 2488 lvds_rx_09_inst.r_data[12]
|
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.sym 2501 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
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.sym 2502 lvds_clock_$glb_clk
|
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.sym 2503 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
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.sym 2505 w_rx_09_fifo_data[19]
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.sym 2506 w_rx_09_fifo_data[22]
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.sym 2507 w_rx_09_fifo_data[17]
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.sym 2508 w_rx_09_fifo_data[16]
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.sym 2509 w_rx_09_fifo_data[18]
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.sym 2510 w_rx_09_fifo_data[5]
|
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.sym 2517 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 2519 rx_24_fifo.rd_addr[7]
|
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.sym 2532 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
|
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.sym 2534 lvds_rx_09_inst.r_data[15]
|
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.sym 2570 lvds_rx_09_inst.r_data[14]
|
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.sym 2574 lvds_rx_09_inst.r_data[18]
|
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.sym 2575 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 2581 lvds_rx_09_inst.r_data[16]
|
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.sym 2590 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 2592 lvds_rx_09_inst.r_data[14]
|
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.sym 2598 lvds_rx_09_inst.r_data[16]
|
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.sym 2599 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 2614 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 2617 lvds_rx_09_inst.r_data[18]
|
|
.sym 2636 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 2637 lvds_clock_$glb_clk
|
|
.sym 2638 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 2640 lvds_rx_09_inst.r_data[21]
|
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.sym 2641 lvds_rx_09_inst.r_data[5]
|
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.sym 2642 lvds_rx_09_inst.r_data[17]
|
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.sym 2643 lvds_rx_09_inst.r_data[2]
|
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.sym 2644 lvds_rx_09_inst.r_data[3]
|
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.sym 2645 lvds_rx_09_inst.r_data[19]
|
|
.sym 2652 w_rx_09_fifo_data[5]
|
|
.sym 2653 i_smi_a2$SB_IO_IN
|
|
.sym 2686 i_smi_a2$SB_IO_IN
|
|
.sym 2701 lvds_rx_09_inst.r_data[18]
|
|
.sym 2756 lvds_rx_09_inst.r_data[18]
|
|
.sym 2771 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 2772 lvds_clock_$glb_clk
|
|
.sym 2774 w_rx_09_fifo_data[2]
|
|
.sym 2777 w_rx_09_fifo_data[0]
|
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.sym 2778 w_rx_09_fifo_data[1]
|
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.sym 2779 w_rx_09_fifo_data[21]
|
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.sym 2781 w_rx_09_fifo_data[3]
|
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.sym 2805 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 2829 w_lvds_rx_09_d0
|
|
.sym 2839 w_lvds_rx_09_d1
|
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.sym 2857 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 2861 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 2863 w_lvds_rx_09_d1
|
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.sym 2885 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 2886 w_lvds_rx_09_d0
|
|
.sym 2906 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 2907 lvds_clock_$glb_clk
|
|
.sym 2908 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 2920 i_smi_a2$SB_IO_IN
|
|
.sym 2924 lvds_rx_24_inst.r_data[9]
|
|
.sym 2941 $PACKER_VCC_NET
|
|
.sym 3067 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 3069 lvds_rx_24_inst.r_data[5]
|
|
.sym 3070 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 3072 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
|
|
.sym 3179 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
|
|
.sym 3180 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 3181 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 3182 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
|
|
.sym 3183 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 3184 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 3186 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 3191 i_smi_a2$SB_IO_IN
|
|
.sym 3197 $PACKER_VCC_NET
|
|
.sym 3202 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 3205 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 3210 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 3221 i_smi_a2$SB_IO_IN
|
|
.sym 3223 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 3314 lvds_rx_24_inst.r_data[5]
|
|
.sym 3315 lvds_rx_24_inst.r_data[1]
|
|
.sym 3316 lvds_rx_24_inst.r_data[17]
|
|
.sym 3319 lvds_rx_24_inst.r_data[19]
|
|
.sym 3320 lvds_rx_24_inst.r_data[3]
|
|
.sym 3321 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
|
|
.sym 3331 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 3334 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
|
|
.sym 3335 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 3337 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
|
|
.sym 3340 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3343 lvds_rx_24_inst.r_data[27]
|
|
.sym 3450 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1]
|
|
.sym 3451 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2]
|
|
.sym 3452 lvds_rx_09_inst.r_phase_count[0]
|
|
.sym 3453 lvds_rx_09_inst.r_phase_count[1]
|
|
.sym 3454 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 3455 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 3456 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 3465 lvds_rx_24_inst.r_data[15]
|
|
.sym 3468 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 3469 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 3479 lvds_rx_24_inst.r_data[19]
|
|
.sym 3503 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3504 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
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.sym 3506 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 3509 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3512 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
|
|
.sym 3517 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3521 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
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.sym 3525 w_lvds_rx_09_d1_SB_LUT4_I1_O[1]
|
|
.sym 3526 w_lvds_rx_09_d1
|
|
.sym 3531 w_lvds_rx_09_d0
|
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.sym 3533 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 3541 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
|
|
.sym 3543 w_lvds_rx_09_d1_SB_LUT4_I1_O[1]
|
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.sym 3544 i_smi_a2_SB_LUT4_I1_O[1]
|
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.sym 3553 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3554 lvds_rx_09_inst.o_debug_state[1]
|
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.sym 3555 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
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.sym 3556 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 3577 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3578 w_lvds_rx_09_d0
|
|
.sym 3579 w_lvds_rx_09_d1
|
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.sym 3580 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 3581 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 3582 lvds_clock_$glb_clk
|
|
.sym 3583 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 3584 lvds_rx_24_inst.r_data[21]
|
|
.sym 3586 lvds_rx_24_inst.r_data[27]
|
|
.sym 3600 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 3601 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 3638 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3641 w_lvds_rx_09_d1
|
|
.sym 3646 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 3648 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 3652 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 3655 w_lvds_rx_09_d0
|
|
.sym 3659 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 3660 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3663 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 3676 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3677 w_lvds_rx_09_d1
|
|
.sym 3678 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3679 w_lvds_rx_09_d0
|
|
.sym 3682 w_lvds_rx_09_d0
|
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.sym 3683 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3684 w_lvds_rx_09_d1
|
|
.sym 3685 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3691 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 3706 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 3708 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 3709 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 3712 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3713 w_lvds_rx_09_d0
|
|
.sym 3714 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3715 w_lvds_rx_09_d1
|
|
.sym 3716 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 3717 lvds_clock_$glb_clk
|
|
.sym 3718 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 3720 lvds_rx_24_inst.r_data[25]
|
|
.sym 3722 lvds_rx_24_inst.r_data[23]
|
|
.sym 3733 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 3735 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 3738 lvds_rx_24_inst.r_data[21]
|
|
.sym 3742 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 3754 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 3760 i_smi_a2$SB_IO_IN
|
|
.sym 3859 w_rx_24_fifo_data[25]
|
|
.sym 3861 w_rx_24_fifo_data[27]
|
|
.sym 4007 rx_24_fifo.wr_addr[9]
|
|
.sym 4012 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 4138 i_smi_a2$SB_IO_IN
|
|
.sym 4238 w_rx_09_fifo_pulled_data[16]
|
|
.sym 4242 w_rx_09_fifo_pulled_data[17]
|
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.sym 4283 lvds_rx_09_inst.r_data[8]
|
|
.sym 4284 lvds_rx_09_inst.r_data[6]
|
|
.sym 4285 lvds_rx_09_inst.r_data[9]
|
|
.sym 4289 lvds_rx_09_inst.r_data[7]
|
|
.sym 4312 lvds_rx_09_inst.r_data[9]
|
|
.sym 4318 lvds_rx_09_inst.r_data[6]
|
|
.sym 4327 lvds_rx_09_inst.r_data[7]
|
|
.sym 4336 lvds_rx_09_inst.r_data[8]
|
|
.sym 4358 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 4359 lvds_clock_$glb_clk
|
|
.sym 4366 w_rx_09_fifo_pulled_data[18]
|
|
.sym 4370 w_rx_09_fifo_pulled_data[19]
|
|
.sym 4384 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 4402 rx_09_fifo.rd_addr[6]
|
|
.sym 4404 rx_09_fifo.rd_addr[7]
|
|
.sym 4406 rx_09_fifo.rd_addr[1]
|
|
.sym 4407 i_smi_a3$SB_IO_IN
|
|
.sym 4408 lvds_rx_09_inst.r_data[13]
|
|
.sym 4417 rx_09_fifo.rd_addr[9]
|
|
.sym 4418 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 4419 rx_09_fifo.wr_addr[7]
|
|
.sym 4422 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 4424 rx_09_fifo.wr_addr[2]
|
|
.sym 4426 rx_09_fifo.wr_addr[5]
|
|
.sym 4444 lvds_rx_09_inst.r_data[7]
|
|
.sym 4446 lvds_rx_09_inst.r_data[5]
|
|
.sym 4448 lvds_rx_09_inst.r_data[9]
|
|
.sym 4452 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4453 lvds_rx_09_inst.r_data[10]
|
|
.sym 4455 lvds_rx_09_inst.r_data[6]
|
|
.sym 4462 lvds_rx_09_inst.r_data[8]
|
|
.sym 4464 lvds_rx_09_inst.r_data[4]
|
|
.sym 4467 lvds_rx_09_inst.r_data[11]
|
|
.sym 4475 lvds_rx_09_inst.r_data[10]
|
|
.sym 4478 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4482 lvds_rx_09_inst.r_data[9]
|
|
.sym 4483 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4489 lvds_rx_09_inst.r_data[5]
|
|
.sym 4490 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4494 lvds_rx_09_inst.r_data[8]
|
|
.sym 4495 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4501 lvds_rx_09_inst.r_data[6]
|
|
.sym 4502 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4505 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4506 lvds_rx_09_inst.r_data[4]
|
|
.sym 4513 lvds_rx_09_inst.r_data[7]
|
|
.sym 4514 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4519 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4520 lvds_rx_09_inst.r_data[11]
|
|
.sym 4521 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 4522 lvds_clock_$glb_clk
|
|
.sym 4523 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 4525 w_rx_09_fifo_pulled_data[0]
|
|
.sym 4529 w_rx_09_fifo_pulled_data[1]
|
|
.sym 4533 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 4536 lvds_rx_09_inst.r_data[12]
|
|
.sym 4537 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 4540 lvds_rx_09_inst.r_data[11]
|
|
.sym 4541 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 4542 lvds_rx_09_inst.r_data[5]
|
|
.sym 4544 lvds_rx_09_inst.r_data[10]
|
|
.sym 4546 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 4547 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 4557 lvds_rx_09_inst.r_data[24]
|
|
.sym 4559 lvds_rx_09_inst.r_data[4]
|
|
.sym 4565 lvds_rx_09_inst.r_data[23]
|
|
.sym 4569 lvds_rx_09_inst.r_data[25]
|
|
.sym 4574 lvds_rx_09_inst.r_data[22]
|
|
.sym 4575 lvds_rx_09_inst.r_data[24]
|
|
.sym 4610 lvds_rx_09_inst.r_data[22]
|
|
.sym 4624 lvds_rx_09_inst.r_data[23]
|
|
.sym 4628 lvds_rx_09_inst.r_data[24]
|
|
.sym 4636 lvds_rx_09_inst.r_data[25]
|
|
.sym 4644 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 4645 lvds_clock_$glb_clk
|
|
.sym 4648 w_rx_09_fifo_pulled_data[2]
|
|
.sym 4652 w_rx_09_fifo_pulled_data[3]
|
|
.sym 4661 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
|
|
.sym 4664 rx_09_fifo.wr_addr[3]
|
|
.sym 4669 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0]
|
|
.sym 4671 lvds_rx_09_inst.r_data[25]
|
|
.sym 4672 rx_09_fifo.rd_addr[7]
|
|
.sym 4674 rx_09_fifo.rd_addr[5]
|
|
.sym 4676 rx_09_fifo.rd_addr[6]
|
|
.sym 4678 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 4680 smi_ctrl_ins.soe_and_reset
|
|
.sym 4682 rx_09_fifo.rd_addr[6]
|
|
.sym 4694 lvds_rx_09_inst.r_data[13]
|
|
.sym 4697 lvds_rx_09_inst.r_data[22]
|
|
.sym 4699 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4704 lvds_rx_09_inst.r_data[2]
|
|
.sym 4706 lvds_rx_09_inst.r_data[21]
|
|
.sym 4712 lvds_rx_09_inst.r_data[23]
|
|
.sym 4716 lvds_rx_09_inst.r_data[20]
|
|
.sym 4721 lvds_rx_09_inst.r_data[21]
|
|
.sym 4723 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4727 lvds_rx_09_inst.r_data[20]
|
|
.sym 4730 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4733 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4735 lvds_rx_09_inst.r_data[22]
|
|
.sym 4740 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4742 lvds_rx_09_inst.r_data[2]
|
|
.sym 4745 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4748 lvds_rx_09_inst.r_data[23]
|
|
.sym 4752 lvds_rx_09_inst.r_data[13]
|
|
.sym 4754 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4767 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 4768 lvds_clock_$glb_clk
|
|
.sym 4769 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 4771 w_rx_09_fifo_pulled_data[8]
|
|
.sym 4775 w_rx_09_fifo_pulled_data[9]
|
|
.sym 4782 rx_24_fifo.rd_addr[4]
|
|
.sym 4783 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 4786 rx_24_fifo.rd_addr[5]
|
|
.sym 4787 rx_09_fifo.rd_addr[5]
|
|
.sym 4788 rx_24_fifo.rd_addr[6]
|
|
.sym 4789 rx_09_fifo.rd_addr[6]
|
|
.sym 4791 rx_09_fifo.rd_addr[7]
|
|
.sym 4794 rx_09_fifo.rd_addr[1]
|
|
.sym 4797 rx_09_fifo.rd_addr[8]
|
|
.sym 4799 rx_09_fifo.rd_addr[9]
|
|
.sym 4804 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 4805 i_smi_a3$SB_IO_IN
|
|
.sym 4816 lvds_rx_09_inst.r_data[3]
|
|
.sym 4819 lvds_rx_09_inst.r_data[16]
|
|
.sym 4822 lvds_rx_09_inst.r_data[17]
|
|
.sym 4823 lvds_rx_09_inst.r_data[20]
|
|
.sym 4824 lvds_rx_09_inst.r_data[15]
|
|
.sym 4840 lvds_rx_09_inst.r_data[14]
|
|
.sym 4853 lvds_rx_09_inst.r_data[17]
|
|
.sym 4857 lvds_rx_09_inst.r_data[20]
|
|
.sym 4863 lvds_rx_09_inst.r_data[15]
|
|
.sym 4868 lvds_rx_09_inst.r_data[14]
|
|
.sym 4874 lvds_rx_09_inst.r_data[16]
|
|
.sym 4883 lvds_rx_09_inst.r_data[3]
|
|
.sym 4890 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 4891 lvds_clock_$glb_clk
|
|
.sym 4894 w_rx_09_fifo_pulled_data[10]
|
|
.sym 4898 w_rx_09_fifo_pulled_data[11]
|
|
.sym 4907 rx_24_fifo.rd_addr[9]
|
|
.sym 4908 rx_09_fifo.wr_addr[3]
|
|
.sym 4911 rx_24_fifo.rd_addr[1]
|
|
.sym 4912 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 4915 rx_24_fifo.rd_addr[8]
|
|
.sym 4917 rx_09_fifo.wr_addr[5]
|
|
.sym 4918 w_rx_09_fifo_data[22]
|
|
.sym 4919 rx_24_fifo.rd_addr[7]
|
|
.sym 4920 rx_09_fifo.wr_addr[8]
|
|
.sym 4921 rx_09_fifo.wr_addr[2]
|
|
.sym 4923 rx_09_fifo.wr_addr[7]
|
|
.sym 4927 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 4928 w_rx_09_fifo_data[0]
|
|
.sym 4936 lvds_rx_09_inst.r_data[15]
|
|
.sym 4950 lvds_rx_09_inst.r_data[1]
|
|
.sym 4953 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4954 lvds_rx_09_inst.r_data[0]
|
|
.sym 4956 lvds_rx_09_inst.r_data[19]
|
|
.sym 4961 lvds_rx_09_inst.r_data[17]
|
|
.sym 4963 lvds_rx_09_inst.r_data[3]
|
|
.sym 4973 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4976 lvds_rx_09_inst.r_data[19]
|
|
.sym 4979 lvds_rx_09_inst.r_data[3]
|
|
.sym 4982 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4985 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4986 lvds_rx_09_inst.r_data[15]
|
|
.sym 4992 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 4993 lvds_rx_09_inst.r_data[0]
|
|
.sym 4998 lvds_rx_09_inst.r_data[1]
|
|
.sym 4999 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 5003 lvds_rx_09_inst.r_data[17]
|
|
.sym 5006 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 5013 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 5014 lvds_clock_$glb_clk
|
|
.sym 5015 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 5017 w_rx_09_fifo_pulled_data[24]
|
|
.sym 5021 w_rx_09_fifo_pulled_data[25]
|
|
.sym 5024 lvds_rx_09_inst.r_data[2]
|
|
.sym 5028 w_rx_09_fifo_data[4]
|
|
.sym 5032 lvds_rx_09_inst.r_data[21]
|
|
.sym 5033 $PACKER_VCC_NET
|
|
.sym 5034 lvds_rx_09_inst.r_data[5]
|
|
.sym 5036 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 5038 $PACKER_VCC_NET
|
|
.sym 5039 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 5040 rx_24_fifo.rd_addr[9]
|
|
.sym 5057 lvds_rx_09_inst.r_data[1]
|
|
.sym 5069 lvds_rx_09_inst.r_data[0]
|
|
.sym 5071 lvds_rx_09_inst.r_data[19]
|
|
.sym 5082 w_lvds_rx_09_d1
|
|
.sym 5088 w_lvds_rx_09_d0
|
|
.sym 5091 lvds_rx_09_inst.r_data[0]
|
|
.sym 5109 w_lvds_rx_09_d0
|
|
.sym 5116 w_lvds_rx_09_d1
|
|
.sym 5120 lvds_rx_09_inst.r_data[19]
|
|
.sym 5133 lvds_rx_09_inst.r_data[1]
|
|
.sym 5136 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 5137 lvds_clock_$glb_clk
|
|
.sym 5140 w_rx_09_fifo_pulled_data[26]
|
|
.sym 5144 w_rx_09_fifo_pulled_data[27]
|
|
.sym 5151 lvds_rx_24_inst.r_data[5]
|
|
.sym 5153 w_rx_09_fifo_data[21]
|
|
.sym 5154 rx_24_fifo.wr_addr[5]
|
|
.sym 5156 rx_09_fifo.wr_addr[3]
|
|
.sym 5168 rx_09_fifo.rd_addr[6]
|
|
.sym 5170 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 5172 smi_ctrl_ins.soe_and_reset
|
|
.sym 5174 w_rx_24_fifo_pulled_data[11]
|
|
.sym 5263 w_rx_24_fifo_pulled_data[24]
|
|
.sym 5267 w_rx_24_fifo_pulled_data[25]
|
|
.sym 5275 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 5276 rx_09_fifo.rd_addr[7]
|
|
.sym 5280 rx_09_fifo.rd_addr[8]
|
|
.sym 5282 rx_09_fifo.rd_addr[5]
|
|
.sym 5283 rx_09_fifo.rd_addr[9]
|
|
.sym 5286 w_rx_24_fifo_pulled_data[1]
|
|
.sym 5287 rx_24_fifo.wr_addr[4]
|
|
.sym 5293 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5295 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 5296 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5386 w_rx_24_fifo_pulled_data[26]
|
|
.sym 5390 w_rx_24_fifo_pulled_data[27]
|
|
.sym 5397 rx_24_fifo.wr_addr[5]
|
|
.sym 5400 w_rx_24_fifo_push
|
|
.sym 5403 rx_24_fifo.wr_addr[8]
|
|
.sym 5408 lvds_rx_24_inst.r_data[27]
|
|
.sym 5410 lvds_rx_24_inst.r_data[3]
|
|
.sym 5411 rx_24_fifo.rd_addr[7]
|
|
.sym 5412 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 5414 lvds_rx_24_inst.r_data[5]
|
|
.sym 5418 rx_24_fifo.wr_addr[7]
|
|
.sym 5419 w_rx_24_fifo_pulled_data[3]
|
|
.sym 5420 rx_24_fifo.wr_addr[6]
|
|
.sym 5427 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5428 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 5431 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 5433 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5435 w_rx_24_fifo_pulled_data[24]
|
|
.sym 5437 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
|
|
.sym 5439 w_rx_24_fifo_pulled_data[25]
|
|
.sym 5441 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5442 smi_ctrl_ins.soe_and_reset
|
|
.sym 5443 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5444 w_rx_24_fifo_pulled_data[11]
|
|
.sym 5446 w_rx_24_fifo_pulled_data[1]
|
|
.sym 5447 w_rx_24_fifo_pulled_data[27]
|
|
.sym 5449 w_rx_24_fifo_pulled_data[16]
|
|
.sym 5451 w_rx_24_fifo_pulled_data[8]
|
|
.sym 5453 w_rx_24_fifo_pulled_data[0]
|
|
.sym 5455 w_rx_24_fifo_pulled_data[9]
|
|
.sym 5457 w_rx_24_fifo_pulled_data[17]
|
|
.sym 5459 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 5460 w_rx_24_fifo_pulled_data[16]
|
|
.sym 5461 w_rx_24_fifo_pulled_data[0]
|
|
.sym 5462 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5467 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5471 w_rx_24_fifo_pulled_data[24]
|
|
.sym 5472 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5473 w_rx_24_fifo_pulled_data[8]
|
|
.sym 5474 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5477 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5478 w_rx_24_fifo_pulled_data[17]
|
|
.sym 5479 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 5480 w_rx_24_fifo_pulled_data[1]
|
|
.sym 5483 w_rx_24_fifo_pulled_data[11]
|
|
.sym 5484 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5485 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5486 w_rx_24_fifo_pulled_data[27]
|
|
.sym 5489 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5490 w_rx_24_fifo_pulled_data[25]
|
|
.sym 5491 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5492 w_rx_24_fifo_pulled_data[9]
|
|
.sym 5503 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5504 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5505 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
|
|
.sym 5506 smi_ctrl_ins.soe_and_reset
|
|
.sym 5507 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 5509 w_rx_24_fifo_pulled_data[8]
|
|
.sym 5513 w_rx_24_fifo_pulled_data[9]
|
|
.sym 5524 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5528 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
|
|
.sym 5531 $PACKER_VCC_NET
|
|
.sym 5532 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 5533 i_smi_a3$SB_IO_IN
|
|
.sym 5534 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 5535 w_rx_24_fifo_pulled_data[16]
|
|
.sym 5537 rx_24_fifo.rd_addr[9]
|
|
.sym 5538 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 5539 w_rx_24_fifo_pulled_data[0]
|
|
.sym 5540 rx_24_fifo.rd_addr[9]
|
|
.sym 5543 w_rx_24_fifo_pulled_data[17]
|
|
.sym 5550 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5551 lvds_rx_24_inst.r_data[17]
|
|
.sym 5553 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 5555 lvds_rx_24_inst.r_data[3]
|
|
.sym 5556 lvds_rx_24_inst.r_data[15]
|
|
.sym 5558 lvds_rx_24_inst.r_data[1]
|
|
.sym 5568 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5574 w_lvds_rx_24_d1
|
|
.sym 5579 w_rx_24_fifo_pulled_data[3]
|
|
.sym 5580 w_rx_24_fifo_pulled_data[19]
|
|
.sym 5583 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5584 lvds_rx_24_inst.r_data[3]
|
|
.sym 5588 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5589 w_lvds_rx_24_d1
|
|
.sym 5595 lvds_rx_24_inst.r_data[15]
|
|
.sym 5597 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5613 lvds_rx_24_inst.r_data[17]
|
|
.sym 5614 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5619 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5620 lvds_rx_24_inst.r_data[1]
|
|
.sym 5624 w_rx_24_fifo_pulled_data[3]
|
|
.sym 5625 w_rx_24_fifo_pulled_data[19]
|
|
.sym 5626 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 5627 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 5628 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 5629 lvds_clock_$glb_clk
|
|
.sym 5630 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 5632 w_rx_24_fifo_pulled_data[10]
|
|
.sym 5636 w_rx_24_fifo_pulled_data[11]
|
|
.sym 5645 lvds_rx_24_inst.r_data[19]
|
|
.sym 5647 lvds_rx_24_inst.r_data[1]
|
|
.sym 5648 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5649 lvds_rx_24_inst.r_data[17]
|
|
.sym 5658 w_rx_24_fifo_pulled_data[11]
|
|
.sym 5661 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 5666 w_rx_24_fifo_pulled_data[19]
|
|
.sym 5673 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1]
|
|
.sym 5674 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2]
|
|
.sym 5675 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 5676 lvds_rx_09_inst.r_phase_count[1]
|
|
.sym 5677 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 5678 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 5679 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 5683 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 5689 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 5693 $PACKER_VCC_NET
|
|
.sym 5697 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 5699 lvds_rx_09_inst.r_phase_count[0]
|
|
.sym 5701 $PACKER_VCC_NET
|
|
.sym 5703 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 5704 $nextpnr_ICESTORM_LC_11$O
|
|
.sym 5707 lvds_rx_09_inst.r_phase_count[0]
|
|
.sym 5710 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2]
|
|
.sym 5712 lvds_rx_09_inst.r_phase_count[1]
|
|
.sym 5713 $PACKER_VCC_NET
|
|
.sym 5714 lvds_rx_09_inst.r_phase_count[0]
|
|
.sym 5718 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 5719 $PACKER_VCC_NET
|
|
.sym 5720 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2]
|
|
.sym 5725 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 5729 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 5735 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 5736 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 5737 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 5738 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2]
|
|
.sym 5741 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 5742 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1]
|
|
.sym 5743 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 5744 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 5747 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 5748 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 5749 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 5750 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 5751 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 5752 lvds_clock_$glb_clk
|
|
.sym 5753 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 5755 w_rx_24_fifo_pulled_data[16]
|
|
.sym 5759 w_rx_24_fifo_pulled_data[17]
|
|
.sym 5766 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 5768 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 5775 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
|
|
.sym 5779 rx_24_fifo.wr_addr[4]
|
|
.sym 5781 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 5782 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5783 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 5788 w_rx_24_fifo_data[11]
|
|
.sym 5789 w_rx_24_fifo_pulled_data[1]
|
|
.sym 5797 lvds_rx_24_inst.r_data[19]
|
|
.sym 5804 lvds_rx_24_inst.r_data[25]
|
|
.sym 5809 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5828 lvds_rx_24_inst.r_data[19]
|
|
.sym 5829 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5840 lvds_rx_24_inst.r_data[25]
|
|
.sym 5841 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5874 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 5875 lvds_clock_$glb_clk
|
|
.sym 5876 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 5878 w_rx_24_fifo_pulled_data[18]
|
|
.sym 5882 w_rx_24_fifo_pulled_data[19]
|
|
.sym 5891 rx_24_fifo.wr_addr[9]
|
|
.sym 5897 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5898 rx_24_fifo.wr_addr[5]
|
|
.sym 5904 w_rx_24_fifo_pulled_data[2]
|
|
.sym 5911 rx_24_fifo.wr_addr[7]
|
|
.sym 5912 rx_24_fifo.wr_addr[6]
|
|
.sym 5918 lvds_rx_24_inst.r_data[21]
|
|
.sym 5937 lvds_rx_24_inst.r_data[23]
|
|
.sym 5942 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5957 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5959 lvds_rx_24_inst.r_data[23]
|
|
.sym 5969 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 5970 lvds_rx_24_inst.r_data[21]
|
|
.sym 5997 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 5998 lvds_clock_$glb_clk
|
|
.sym 5999 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 6001 w_rx_24_fifo_pulled_data[0]
|
|
.sym 6005 w_rx_24_fifo_pulled_data[1]
|
|
.sym 6021 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6025 i_smi_a3$SB_IO_IN
|
|
.sym 6029 rx_24_fifo.rd_addr[9]
|
|
.sym 6030 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6031 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6034 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 6035 w_rx_24_fifo_pulled_data[0]
|
|
.sym 6042 lvds_rx_24_inst.r_data[25]
|
|
.sym 6044 lvds_rx_24_inst.r_data[23]
|
|
.sym 6104 lvds_rx_24_inst.r_data[23]
|
|
.sym 6116 lvds_rx_24_inst.r_data[25]
|
|
.sym 6120 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 6121 lvds_clock_$glb_clk
|
|
.sym 6124 w_rx_24_fifo_pulled_data[2]
|
|
.sym 6128 w_rx_24_fifo_pulled_data[3]
|
|
.sym 6246 i_smi_a3$SB_IO_IN
|
|
.sym 6259 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 6286 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 6294 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 6312 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 6346 lvds_rx_09_inst.r_data[26]
|
|
.sym 6378 i_smi_a3$SB_IO_IN
|
|
.sym 6388 w_rx_09_fifo_data[9]
|
|
.sym 6391 rx_09_fifo.wr_addr[9]
|
|
.sym 6392 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6394 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6395 w_rx_09_fifo_data[8]
|
|
.sym 6396 rx_09_fifo.wr_addr[3]
|
|
.sym 6397 rx_09_fifo.wr_addr[4]
|
|
.sym 6401 rx_09_fifo.wr_addr[6]
|
|
.sym 6402 rx_09_fifo.wr_addr[2]
|
|
.sym 6412 rx_09_fifo.wr_addr[5]
|
|
.sym 6413 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6414 rx_09_fifo.wr_addr[7]
|
|
.sym 6415 $PACKER_VCC_NET
|
|
.sym 6417 rx_09_fifo.wr_addr[8]
|
|
.sym 6422 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 6423 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
|
|
.sym 6424 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6425 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 6429 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
|
|
.sym 6438 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6439 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6441 rx_09_fifo.wr_addr[2]
|
|
.sym 6442 rx_09_fifo.wr_addr[3]
|
|
.sym 6443 rx_09_fifo.wr_addr[4]
|
|
.sym 6444 rx_09_fifo.wr_addr[5]
|
|
.sym 6445 rx_09_fifo.wr_addr[6]
|
|
.sym 6446 rx_09_fifo.wr_addr[7]
|
|
.sym 6447 rx_09_fifo.wr_addr[8]
|
|
.sym 6448 rx_09_fifo.wr_addr[9]
|
|
.sym 6449 lvds_clock_$glb_clk
|
|
.sym 6450 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6452 w_rx_09_fifo_data[8]
|
|
.sym 6456 w_rx_09_fifo_data[9]
|
|
.sym 6459 $PACKER_VCC_NET
|
|
.sym 6465 lvds_rx_09_inst.r_data[24]
|
|
.sym 6466 rx_09_fifo.wr_addr[3]
|
|
.sym 6469 rx_09_fifo.wr_addr[4]
|
|
.sym 6471 rx_09_fifo.wr_addr[9]
|
|
.sym 6472 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6473 rx_09_fifo.wr_addr[6]
|
|
.sym 6490 $PACKER_VCC_NET
|
|
.sym 6498 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 6502 w_smi_data_output[6]
|
|
.sym 6504 rx_09_fifo.rd_addr[8]
|
|
.sym 6505 w_rx_09_fifo_pulled_data[16]
|
|
.sym 6507 rx_09_fifo.rd_addr[1]
|
|
.sym 6508 w_rx_09_fifo_pulled_data[2]
|
|
.sym 6509 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6511 $PACKER_VCC_NET
|
|
.sym 6512 rx_09_fifo.wr_addr[4]
|
|
.sym 6516 rx_24_fifo.rd_addr[4]
|
|
.sym 6518 rx_09_fifo.wr_addr[8]
|
|
.sym 6528 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 6530 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6531 rx_09_fifo.rd_addr[7]
|
|
.sym 6532 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6533 rx_09_fifo.rd_addr[1]
|
|
.sym 6535 rx_09_fifo.rd_addr[9]
|
|
.sym 6537 rx_09_fifo.rd_addr[6]
|
|
.sym 6538 rx_09_fifo.rd_addr[5]
|
|
.sym 6542 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 6544 w_rx_09_fifo_data[11]
|
|
.sym 6546 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6548 w_rx_09_fifo_data[10]
|
|
.sym 6557 $PACKER_VCC_NET
|
|
.sym 6559 rx_09_fifo.rd_addr[8]
|
|
.sym 6560 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1]
|
|
.sym 6561 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6562 w_smi_data_output[3]
|
|
.sym 6563 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 6564 w_smi_data_output[6]
|
|
.sym 6565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1]
|
|
.sym 6566 w_smi_data_output[0]
|
|
.sym 6567 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6576 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6577 rx_09_fifo.rd_addr[1]
|
|
.sym 6579 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6580 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 6581 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 6582 rx_09_fifo.rd_addr[5]
|
|
.sym 6583 rx_09_fifo.rd_addr[6]
|
|
.sym 6584 rx_09_fifo.rd_addr[7]
|
|
.sym 6585 rx_09_fifo.rd_addr[8]
|
|
.sym 6586 rx_09_fifo.rd_addr[9]
|
|
.sym 6587 r_counter_$glb_clk
|
|
.sym 6588 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6589 $PACKER_VCC_NET
|
|
.sym 6593 w_rx_09_fifo_data[11]
|
|
.sym 6597 w_rx_09_fifo_data[10]
|
|
.sym 6602 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 6603 lvds_rx_09_inst.r_data[25]
|
|
.sym 6606 rx_09_fifo.rd_addr[5]
|
|
.sym 6608 rx_09_fifo.rd_addr[6]
|
|
.sym 6609 smi_ctrl_ins.soe_and_reset
|
|
.sym 6610 rx_09_fifo.rd_addr[7]
|
|
.sym 6612 smi_ctrl_ins.soe_and_reset
|
|
.sym 6614 rx_24_fifo.rd_addr[6]
|
|
.sym 6615 rx_24_fifo.rd_addr[8]
|
|
.sym 6616 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 6619 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 6620 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 6621 rx_24_fifo.rd_addr[0]
|
|
.sym 6625 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
|
|
.sym 6630 rx_09_fifo.wr_addr[2]
|
|
.sym 6632 w_rx_09_fifo_data[24]
|
|
.sym 6633 rx_09_fifo.wr_addr[9]
|
|
.sym 6634 w_rx_09_fifo_data[25]
|
|
.sym 6639 rx_09_fifo.wr_addr[6]
|
|
.sym 6640 rx_09_fifo.wr_addr[5]
|
|
.sym 6641 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6642 rx_09_fifo.wr_addr[7]
|
|
.sym 6644 rx_09_fifo.wr_addr[3]
|
|
.sym 6645 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6653 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6655 rx_09_fifo.wr_addr[4]
|
|
.sym 6659 $PACKER_VCC_NET
|
|
.sym 6661 rx_09_fifo.wr_addr[8]
|
|
.sym 6664 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 6665 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 6666 rx_24_fifo.rd_addr[4]
|
|
.sym 6667 rx_24_fifo.rd_addr[5]
|
|
.sym 6668 rx_24_fifo.rd_addr[6]
|
|
.sym 6669 rx_24_fifo.rd_addr[7]
|
|
.sym 6678 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6679 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6681 rx_09_fifo.wr_addr[2]
|
|
.sym 6682 rx_09_fifo.wr_addr[3]
|
|
.sym 6683 rx_09_fifo.wr_addr[4]
|
|
.sym 6684 rx_09_fifo.wr_addr[5]
|
|
.sym 6685 rx_09_fifo.wr_addr[6]
|
|
.sym 6686 rx_09_fifo.wr_addr[7]
|
|
.sym 6687 rx_09_fifo.wr_addr[8]
|
|
.sym 6688 rx_09_fifo.wr_addr[9]
|
|
.sym 6689 lvds_clock_$glb_clk
|
|
.sym 6690 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6692 w_rx_09_fifo_data[24]
|
|
.sym 6696 w_rx_09_fifo_data[25]
|
|
.sym 6699 $PACKER_VCC_NET
|
|
.sym 6706 rx_09_fifo.rd_addr[9]
|
|
.sym 6707 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6708 lvds_rx_09_inst.r_data[13]
|
|
.sym 6709 rx_09_fifo.wr_addr[9]
|
|
.sym 6712 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6713 rx_09_fifo.rd_addr[1]
|
|
.sym 6714 rx_09_fifo.rd_addr[8]
|
|
.sym 6715 rx_09_fifo.wr_addr[6]
|
|
.sym 6716 rx_24_fifo.rd_addr[1]
|
|
.sym 6718 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6719 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6720 rx_24_fifo.rd_addr[8]
|
|
.sym 6721 rx_24_fifo.rd_addr[6]
|
|
.sym 6722 rx_24_fifo.rd_addr[9]
|
|
.sym 6723 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 6724 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6725 $PACKER_VCC_NET
|
|
.sym 6726 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 6727 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6732 rx_09_fifo.rd_addr[6]
|
|
.sym 6734 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6736 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 6740 rx_09_fifo.rd_addr[1]
|
|
.sym 6741 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6742 rx_09_fifo.rd_addr[7]
|
|
.sym 6745 $PACKER_VCC_NET
|
|
.sym 6746 rx_09_fifo.rd_addr[5]
|
|
.sym 6747 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6749 rx_09_fifo.rd_addr[9]
|
|
.sym 6751 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 6754 w_rx_09_fifo_data[27]
|
|
.sym 6761 w_rx_09_fifo_data[26]
|
|
.sym 6763 rx_09_fifo.rd_addr[8]
|
|
.sym 6764 rx_24_fifo.rd_addr[8]
|
|
.sym 6765 rx_24_fifo.rd_addr[9]
|
|
.sym 6766 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 6767 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 6768 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 6769 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
|
|
.sym 6770 rx_24_fifo.rd_addr[1]
|
|
.sym 6771 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 6780 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6781 rx_09_fifo.rd_addr[1]
|
|
.sym 6783 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6784 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 6785 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 6786 rx_09_fifo.rd_addr[5]
|
|
.sym 6787 rx_09_fifo.rd_addr[6]
|
|
.sym 6788 rx_09_fifo.rd_addr[7]
|
|
.sym 6789 rx_09_fifo.rd_addr[8]
|
|
.sym 6790 rx_09_fifo.rd_addr[9]
|
|
.sym 6791 r_counter_$glb_clk
|
|
.sym 6792 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6793 $PACKER_VCC_NET
|
|
.sym 6797 w_rx_09_fifo_data[27]
|
|
.sym 6801 w_rx_09_fifo_data[26]
|
|
.sym 6803 rx_24_fifo.rd_addr[5]
|
|
.sym 6804 rx_24_fifo.rd_addr[5]
|
|
.sym 6807 rx_09_fifo.wr_addr[7]
|
|
.sym 6809 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 6811 rx_24_fifo.rd_addr[7]
|
|
.sym 6813 rx_09_fifo.wr_addr[2]
|
|
.sym 6815 rx_09_fifo.wr_addr[5]
|
|
.sym 6816 rx_09_fifo.wr_addr[8]
|
|
.sym 6817 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6818 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 6819 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 6820 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 6822 rx_24_fifo.rd_addr[4]
|
|
.sym 6824 rx_24_fifo.rd_addr[5]
|
|
.sym 6827 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
|
|
.sym 6828 rx_24_fifo.rd_addr[7]
|
|
.sym 6834 rx_09_fifo.wr_addr[4]
|
|
.sym 6835 rx_09_fifo.wr_addr[7]
|
|
.sym 6837 rx_09_fifo.wr_addr[9]
|
|
.sym 6838 w_rx_09_fifo_data[16]
|
|
.sym 6840 rx_09_fifo.wr_addr[6]
|
|
.sym 6842 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6845 w_rx_09_fifo_data[17]
|
|
.sym 6847 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6848 rx_09_fifo.wr_addr[3]
|
|
.sym 6850 rx_09_fifo.wr_addr[2]
|
|
.sym 6861 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6862 rx_09_fifo.wr_addr[5]
|
|
.sym 6863 $PACKER_VCC_NET
|
|
.sym 6865 rx_09_fifo.wr_addr[8]
|
|
.sym 6868 w_rx_09_fifo_data[23]
|
|
.sym 6869 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0]
|
|
.sym 6870 w_rx_09_fifo_data[4]
|
|
.sym 6872 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 6873 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[1]
|
|
.sym 6882 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6883 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6885 rx_09_fifo.wr_addr[2]
|
|
.sym 6886 rx_09_fifo.wr_addr[3]
|
|
.sym 6887 rx_09_fifo.wr_addr[4]
|
|
.sym 6888 rx_09_fifo.wr_addr[5]
|
|
.sym 6889 rx_09_fifo.wr_addr[6]
|
|
.sym 6890 rx_09_fifo.wr_addr[7]
|
|
.sym 6891 rx_09_fifo.wr_addr[8]
|
|
.sym 6892 rx_09_fifo.wr_addr[9]
|
|
.sym 6893 lvds_clock_$glb_clk
|
|
.sym 6894 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 6896 w_rx_09_fifo_data[16]
|
|
.sym 6900 w_rx_09_fifo_data[17]
|
|
.sym 6903 $PACKER_VCC_NET
|
|
.sym 6904 i_smi_a3$SB_IO_IN
|
|
.sym 6907 i_smi_a3$SB_IO_IN
|
|
.sym 6909 rx_09_fifo.wr_addr[7]
|
|
.sym 6910 w_rx_09_fifo_pulled_data[9]
|
|
.sym 6911 rx_09_fifo.wr_addr[9]
|
|
.sym 6912 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 6914 lvds_rx_09_inst.r_data[4]
|
|
.sym 6915 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6916 rx_09_fifo.wr_addr[6]
|
|
.sym 6917 rx_24_fifo.rd_addr[9]
|
|
.sym 6918 rx_09_fifo.wr_addr[4]
|
|
.sym 6922 w_rx_09_fifo_pulled_data[26]
|
|
.sym 6923 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 6924 $PACKER_VCC_NET
|
|
.sym 6925 rx_09_fifo.wr_addr[4]
|
|
.sym 6927 rx_09_fifo.rd_addr[1]
|
|
.sym 6928 rx_24_fifo.rd_addr[1]
|
|
.sym 6929 rx_24_fifo.rd_addr[4]
|
|
.sym 6930 w_rx_09_fifo_pulled_data[27]
|
|
.sym 6931 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 6937 rx_09_fifo.rd_addr[9]
|
|
.sym 6938 rx_09_fifo.rd_addr[6]
|
|
.sym 6940 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6942 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 6944 rx_09_fifo.rd_addr[7]
|
|
.sym 6946 rx_09_fifo.rd_addr[5]
|
|
.sym 6947 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6948 rx_09_fifo.rd_addr[1]
|
|
.sym 6949 $PACKER_VCC_NET
|
|
.sym 6951 rx_09_fifo.rd_addr[8]
|
|
.sym 6954 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6955 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 6961 w_rx_09_fifo_data[19]
|
|
.sym 6965 w_rx_09_fifo_data[18]
|
|
.sym 6968 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6974 lvds_rx_24_inst.r_data[7]
|
|
.sym 6975 lvds_rx_24_inst.r_data[9]
|
|
.sym 6984 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 6985 rx_09_fifo.rd_addr[1]
|
|
.sym 6987 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 6988 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 6989 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 6990 rx_09_fifo.rd_addr[5]
|
|
.sym 6991 rx_09_fifo.rd_addr[6]
|
|
.sym 6992 rx_09_fifo.rd_addr[7]
|
|
.sym 6993 rx_09_fifo.rd_addr[8]
|
|
.sym 6994 rx_09_fifo.rd_addr[9]
|
|
.sym 6995 r_counter_$glb_clk
|
|
.sym 6996 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 6997 $PACKER_VCC_NET
|
|
.sym 7001 w_rx_09_fifo_data[19]
|
|
.sym 7005 w_rx_09_fifo_data[18]
|
|
.sym 7010 smi_ctrl_ins.soe_and_reset
|
|
.sym 7018 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 7021 w_rx_09_fifo_data[23]
|
|
.sym 7023 rx_24_fifo.rd_addr[8]
|
|
.sym 7024 w_rx_09_fifo_pulled_data[25]
|
|
.sym 7025 rx_24_fifo.wr_addr[9]
|
|
.sym 7026 $PACKER_VCC_NET
|
|
.sym 7027 rx_24_fifo.rd_addr[6]
|
|
.sym 7029 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7030 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 7032 w_rx_09_fifo_pulled_data[24]
|
|
.sym 7033 rx_24_fifo.rd_addr[0]
|
|
.sym 7038 rx_09_fifo.wr_addr[2]
|
|
.sym 7040 rx_09_fifo.wr_addr[8]
|
|
.sym 7041 rx_09_fifo.wr_addr[9]
|
|
.sym 7042 w_rx_09_fifo_data[1]
|
|
.sym 7047 rx_09_fifo.wr_addr[6]
|
|
.sym 7048 rx_09_fifo.wr_addr[7]
|
|
.sym 7049 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7050 rx_09_fifo.wr_addr[5]
|
|
.sym 7051 $PACKER_VCC_NET
|
|
.sym 7052 rx_09_fifo.wr_addr[3]
|
|
.sym 7053 w_rx_09_fifo_data[0]
|
|
.sym 7061 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7063 rx_09_fifo.wr_addr[4]
|
|
.sym 7069 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7071 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 7072 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 7073 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 7074 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 7075 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 7076 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 7077 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 7086 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7087 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7089 rx_09_fifo.wr_addr[2]
|
|
.sym 7090 rx_09_fifo.wr_addr[3]
|
|
.sym 7091 rx_09_fifo.wr_addr[4]
|
|
.sym 7092 rx_09_fifo.wr_addr[5]
|
|
.sym 7093 rx_09_fifo.wr_addr[6]
|
|
.sym 7094 rx_09_fifo.wr_addr[7]
|
|
.sym 7095 rx_09_fifo.wr_addr[8]
|
|
.sym 7096 rx_09_fifo.wr_addr[9]
|
|
.sym 7097 lvds_clock_$glb_clk
|
|
.sym 7098 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7100 w_rx_09_fifo_data[0]
|
|
.sym 7104 w_rx_09_fifo_data[1]
|
|
.sym 7107 $PACKER_VCC_NET
|
|
.sym 7112 rx_24_fifo.wr_addr[4]
|
|
.sym 7114 rx_09_fifo.wr_addr[8]
|
|
.sym 7115 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7117 rx_09_fifo.wr_addr[9]
|
|
.sym 7120 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7122 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7123 rx_09_fifo.wr_addr[6]
|
|
.sym 7124 rx_24_fifo.rd_addr[8]
|
|
.sym 7125 rx_24_fifo.rd_addr[6]
|
|
.sym 7126 rx_24_fifo.rd_addr[9]
|
|
.sym 7129 rx_24_fifo.rd_addr[1]
|
|
.sym 7130 rx_24_fifo.rd_addr[6]
|
|
.sym 7131 w_rx_24_fifo_push
|
|
.sym 7132 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 7133 rx_24_fifo.rd_addr[8]
|
|
.sym 7135 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7140 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 7142 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 7143 rx_09_fifo.rd_addr[5]
|
|
.sym 7144 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 7147 rx_09_fifo.rd_addr[7]
|
|
.sym 7149 rx_09_fifo.rd_addr[8]
|
|
.sym 7150 rx_09_fifo.rd_addr[9]
|
|
.sym 7153 $PACKER_VCC_NET
|
|
.sym 7154 rx_09_fifo.rd_addr[1]
|
|
.sym 7156 w_rx_09_fifo_data[2]
|
|
.sym 7157 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 7158 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7160 rx_09_fifo.rd_addr[6]
|
|
.sym 7171 w_rx_09_fifo_data[3]
|
|
.sym 7172 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 7173 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 7174 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
|
|
.sym 7175 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
|
|
.sym 7177 rx_24_fifo.rd_addr[0]
|
|
.sym 7178 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 7179 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 7188 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 7189 rx_09_fifo.rd_addr[1]
|
|
.sym 7191 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 7192 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 7193 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 7194 rx_09_fifo.rd_addr[5]
|
|
.sym 7195 rx_09_fifo.rd_addr[6]
|
|
.sym 7196 rx_09_fifo.rd_addr[7]
|
|
.sym 7197 rx_09_fifo.rd_addr[8]
|
|
.sym 7198 rx_09_fifo.rd_addr[9]
|
|
.sym 7199 r_counter_$glb_clk
|
|
.sym 7200 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7201 $PACKER_VCC_NET
|
|
.sym 7205 w_rx_09_fifo_data[3]
|
|
.sym 7209 w_rx_09_fifo_data[2]
|
|
.sym 7214 w_rx_09_fifo_data[22]
|
|
.sym 7220 rx_24_fifo.wr_addr[6]
|
|
.sym 7224 rx_24_fifo.wr_addr[7]
|
|
.sym 7226 rx_24_fifo.wr_addr[8]
|
|
.sym 7227 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
|
|
.sym 7229 rx_24_fifo.rd_addr[7]
|
|
.sym 7230 rx_24_fifo.rd_addr[4]
|
|
.sym 7231 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7232 rx_24_fifo.rd_addr[5]
|
|
.sym 7233 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 7234 rx_24_fifo.wr_addr[5]
|
|
.sym 7235 rx_24_fifo.rd_addr[4]
|
|
.sym 7236 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7237 w_rx_24_fifo_data[0]
|
|
.sym 7247 rx_24_fifo.wr_addr[5]
|
|
.sym 7248 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7251 rx_24_fifo.wr_addr[8]
|
|
.sym 7252 rx_24_fifo.wr_addr[9]
|
|
.sym 7253 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7256 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7258 rx_24_fifo.wr_addr[4]
|
|
.sym 7260 w_rx_24_fifo_data[0]
|
|
.sym 7262 $PACKER_VCC_NET
|
|
.sym 7263 rx_24_fifo.wr_addr[7]
|
|
.sym 7264 w_rx_24_fifo_data[1]
|
|
.sym 7266 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7267 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7273 rx_24_fifo.wr_addr[6]
|
|
.sym 7276 sys_ctrl_ins.reset_count[2]
|
|
.sym 7277 sys_ctrl_ins.reset_count[3]
|
|
.sym 7278 sys_ctrl_ins.reset_count[0]
|
|
.sym 7279 sys_ctrl_ins.reset_count[1]
|
|
.sym 7280 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
|
|
.sym 7281 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 7290 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7291 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7293 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7294 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7295 rx_24_fifo.wr_addr[4]
|
|
.sym 7296 rx_24_fifo.wr_addr[5]
|
|
.sym 7297 rx_24_fifo.wr_addr[6]
|
|
.sym 7298 rx_24_fifo.wr_addr[7]
|
|
.sym 7299 rx_24_fifo.wr_addr[8]
|
|
.sym 7300 rx_24_fifo.wr_addr[9]
|
|
.sym 7301 lvds_clock_$glb_clk
|
|
.sym 7302 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7304 w_rx_24_fifo_data[0]
|
|
.sym 7308 w_rx_24_fifo_data[1]
|
|
.sym 7311 $PACKER_VCC_NET
|
|
.sym 7313 rx_24_fifo.rd_addr[0]
|
|
.sym 7314 w_rx_24_fifo_pulled_data[3]
|
|
.sym 7317 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 7319 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 7321 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7323 i_smi_a3$SB_IO_IN
|
|
.sym 7324 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7327 i_smi_a1$SB_IO_IN
|
|
.sym 7328 rx_24_fifo.rd_addr[7]
|
|
.sym 7329 rx_24_fifo.rd_addr[1]
|
|
.sym 7330 w_rx_24_fifo_data[1]
|
|
.sym 7331 w_rx_24_fifo_data[2]
|
|
.sym 7332 $PACKER_VCC_NET
|
|
.sym 7334 rx_24_fifo.rd_addr[0]
|
|
.sym 7337 rx_24_fifo.rd_addr[4]
|
|
.sym 7346 w_rx_24_fifo_data[2]
|
|
.sym 7348 $PACKER_VCC_NET
|
|
.sym 7353 rx_24_fifo.rd_addr[8]
|
|
.sym 7355 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7356 rx_24_fifo.rd_addr[1]
|
|
.sym 7357 rx_24_fifo.rd_addr[0]
|
|
.sym 7359 rx_24_fifo.rd_addr[6]
|
|
.sym 7366 w_rx_24_fifo_data[3]
|
|
.sym 7367 rx_24_fifo.rd_addr[7]
|
|
.sym 7369 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7370 rx_24_fifo.rd_addr[5]
|
|
.sym 7372 rx_24_fifo.rd_addr[9]
|
|
.sym 7373 rx_24_fifo.rd_addr[4]
|
|
.sym 7374 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7376 w_rx_24_fifo_data[11]
|
|
.sym 7378 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 7379 w_rx_24_fifo_data[17]
|
|
.sym 7380 w_rx_24_fifo_data[19]
|
|
.sym 7381 w_rx_24_fifo_data[0]
|
|
.sym 7382 w_rx_24_fifo_data[3]
|
|
.sym 7383 w_rx_24_fifo_data[1]
|
|
.sym 7392 rx_24_fifo.rd_addr[0]
|
|
.sym 7393 rx_24_fifo.rd_addr[1]
|
|
.sym 7395 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7396 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7397 rx_24_fifo.rd_addr[4]
|
|
.sym 7398 rx_24_fifo.rd_addr[5]
|
|
.sym 7399 rx_24_fifo.rd_addr[6]
|
|
.sym 7400 rx_24_fifo.rd_addr[7]
|
|
.sym 7401 rx_24_fifo.rd_addr[8]
|
|
.sym 7402 rx_24_fifo.rd_addr[9]
|
|
.sym 7403 r_counter_$glb_clk
|
|
.sym 7404 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7405 $PACKER_VCC_NET
|
|
.sym 7409 w_rx_24_fifo_data[3]
|
|
.sym 7413 w_rx_24_fifo_data[2]
|
|
.sym 7414 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 7419 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7423 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7433 rx_24_fifo.wr_addr[9]
|
|
.sym 7434 $PACKER_VCC_NET
|
|
.sym 7435 rx_24_fifo.rd_addr[6]
|
|
.sym 7437 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7439 rx_24_fifo.rd_addr[8]
|
|
.sym 7440 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 7446 rx_24_fifo.wr_addr[4]
|
|
.sym 7451 rx_24_fifo.wr_addr[7]
|
|
.sym 7454 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7455 rx_24_fifo.wr_addr[8]
|
|
.sym 7456 rx_24_fifo.wr_addr[9]
|
|
.sym 7459 $PACKER_VCC_NET
|
|
.sym 7460 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7461 rx_24_fifo.wr_addr[6]
|
|
.sym 7463 rx_24_fifo.wr_addr[5]
|
|
.sym 7464 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7468 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7471 w_rx_24_fifo_data[16]
|
|
.sym 7473 w_rx_24_fifo_data[17]
|
|
.sym 7475 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7479 w_rx_24_fifo_data[2]
|
|
.sym 7480 w_rx_24_fifo_data[7]
|
|
.sym 7482 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2]
|
|
.sym 7484 w_rx_24_fifo_data[9]
|
|
.sym 7494 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7495 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7497 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7498 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7499 rx_24_fifo.wr_addr[4]
|
|
.sym 7500 rx_24_fifo.wr_addr[5]
|
|
.sym 7501 rx_24_fifo.wr_addr[6]
|
|
.sym 7502 rx_24_fifo.wr_addr[7]
|
|
.sym 7503 rx_24_fifo.wr_addr[8]
|
|
.sym 7504 rx_24_fifo.wr_addr[9]
|
|
.sym 7505 lvds_clock_$glb_clk
|
|
.sym 7506 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7508 w_rx_24_fifo_data[16]
|
|
.sym 7512 w_rx_24_fifo_data[17]
|
|
.sym 7515 $PACKER_VCC_NET
|
|
.sym 7523 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 7527 w_rx_24_fifo_data[11]
|
|
.sym 7528 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 7530 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7531 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 7532 rx_24_fifo.rd_addr[8]
|
|
.sym 7533 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7534 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7537 w_rx_24_fifo_data[16]
|
|
.sym 7539 rx_24_fifo.rd_addr[9]
|
|
.sym 7541 rx_24_fifo.rd_addr[6]
|
|
.sym 7543 w_rx_24_fifo_data[26]
|
|
.sym 7548 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7550 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7551 rx_24_fifo.rd_addr[7]
|
|
.sym 7552 w_rx_24_fifo_data[19]
|
|
.sym 7556 rx_24_fifo.rd_addr[1]
|
|
.sym 7558 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7560 rx_24_fifo.rd_addr[9]
|
|
.sym 7561 $PACKER_VCC_NET
|
|
.sym 7563 rx_24_fifo.rd_addr[0]
|
|
.sym 7564 rx_24_fifo.rd_addr[4]
|
|
.sym 7565 rx_24_fifo.rd_addr[5]
|
|
.sym 7573 rx_24_fifo.rd_addr[6]
|
|
.sym 7577 rx_24_fifo.rd_addr[8]
|
|
.sym 7579 w_rx_24_fifo_data[18]
|
|
.sym 7581 rx_24_fifo.wr_addr[9]
|
|
.sym 7583 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7586 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7587 w_rx_24_fifo_data[18]
|
|
.sym 7596 rx_24_fifo.rd_addr[0]
|
|
.sym 7597 rx_24_fifo.rd_addr[1]
|
|
.sym 7599 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7600 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7601 rx_24_fifo.rd_addr[4]
|
|
.sym 7602 rx_24_fifo.rd_addr[5]
|
|
.sym 7603 rx_24_fifo.rd_addr[6]
|
|
.sym 7604 rx_24_fifo.rd_addr[7]
|
|
.sym 7605 rx_24_fifo.rd_addr[8]
|
|
.sym 7606 rx_24_fifo.rd_addr[9]
|
|
.sym 7607 r_counter_$glb_clk
|
|
.sym 7608 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7609 $PACKER_VCC_NET
|
|
.sym 7613 w_rx_24_fifo_data[19]
|
|
.sym 7617 w_rx_24_fifo_data[18]
|
|
.sym 7622 lvds_rx_24_inst.r_data[3]
|
|
.sym 7624 lvds_rx_24_inst.r_data[5]
|
|
.sym 7626 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7631 w_rx_24_fifo_pulled_data[2]
|
|
.sym 7634 rx_24_fifo.wr_addr[8]
|
|
.sym 7635 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 7637 rx_24_fifo.rd_addr[7]
|
|
.sym 7638 rx_24_fifo.rd_addr[4]
|
|
.sym 7641 w_rx_24_fifo_pulled_data[18]
|
|
.sym 7642 rx_24_fifo.wr_addr[5]
|
|
.sym 7643 rx_24_fifo.rd_addr[4]
|
|
.sym 7652 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7656 w_rx_24_fifo_data[9]
|
|
.sym 7659 rx_24_fifo.wr_addr[8]
|
|
.sym 7660 rx_24_fifo.wr_addr[5]
|
|
.sym 7663 $PACKER_VCC_NET
|
|
.sym 7666 rx_24_fifo.wr_addr[4]
|
|
.sym 7667 rx_24_fifo.wr_addr[9]
|
|
.sym 7668 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7669 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7670 w_rx_24_fifo_data[8]
|
|
.sym 7672 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7678 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7680 rx_24_fifo.wr_addr[7]
|
|
.sym 7681 rx_24_fifo.wr_addr[6]
|
|
.sym 7682 w_rx_24_fifo_data[20]
|
|
.sym 7684 w_rx_24_fifo_data[16]
|
|
.sym 7685 w_rx_24_fifo_data[24]
|
|
.sym 7686 w_rx_24_fifo_data[8]
|
|
.sym 7687 w_rx_24_fifo_data[26]
|
|
.sym 7688 w_rx_24_fifo_data[18]
|
|
.sym 7689 w_rx_24_fifo_data[10]
|
|
.sym 7698 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7699 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7701 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7702 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7703 rx_24_fifo.wr_addr[4]
|
|
.sym 7704 rx_24_fifo.wr_addr[5]
|
|
.sym 7705 rx_24_fifo.wr_addr[6]
|
|
.sym 7706 rx_24_fifo.wr_addr[7]
|
|
.sym 7707 rx_24_fifo.wr_addr[8]
|
|
.sym 7708 rx_24_fifo.wr_addr[9]
|
|
.sym 7709 lvds_clock_$glb_clk
|
|
.sym 7710 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7712 w_rx_24_fifo_data[8]
|
|
.sym 7716 w_rx_24_fifo_data[9]
|
|
.sym 7719 $PACKER_VCC_NET
|
|
.sym 7720 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 7725 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7727 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7733 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 7736 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7737 rx_24_fifo.rd_addr[1]
|
|
.sym 7738 rx_24_fifo.rd_addr[0]
|
|
.sym 7740 $PACKER_VCC_NET
|
|
.sym 7741 rx_24_fifo.rd_addr[7]
|
|
.sym 7742 rx_24_fifo.rd_addr[0]
|
|
.sym 7745 $PACKER_VCC_NET
|
|
.sym 7753 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7754 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7758 w_rx_24_fifo_data[11]
|
|
.sym 7760 rx_24_fifo.rd_addr[1]
|
|
.sym 7761 rx_24_fifo.rd_addr[8]
|
|
.sym 7763 rx_24_fifo.rd_addr[0]
|
|
.sym 7765 $PACKER_VCC_NET
|
|
.sym 7766 rx_24_fifo.rd_addr[9]
|
|
.sym 7767 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7768 rx_24_fifo.rd_addr[6]
|
|
.sym 7773 rx_24_fifo.rd_addr[5]
|
|
.sym 7775 rx_24_fifo.rd_addr[7]
|
|
.sym 7781 rx_24_fifo.rd_addr[4]
|
|
.sym 7783 w_rx_24_fifo_data[10]
|
|
.sym 7787 lvds_rx_24_inst.r_data[8]
|
|
.sym 7791 lvds_rx_24_inst.r_data[6]
|
|
.sym 7800 rx_24_fifo.rd_addr[0]
|
|
.sym 7801 rx_24_fifo.rd_addr[1]
|
|
.sym 7803 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7804 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7805 rx_24_fifo.rd_addr[4]
|
|
.sym 7806 rx_24_fifo.rd_addr[5]
|
|
.sym 7807 rx_24_fifo.rd_addr[6]
|
|
.sym 7808 rx_24_fifo.rd_addr[7]
|
|
.sym 7809 rx_24_fifo.rd_addr[8]
|
|
.sym 7810 rx_24_fifo.rd_addr[9]
|
|
.sym 7811 r_counter_$glb_clk
|
|
.sym 7812 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7813 $PACKER_VCC_NET
|
|
.sym 7817 w_rx_24_fifo_data[11]
|
|
.sym 7821 w_rx_24_fifo_data[10]
|
|
.sym 7847 $PACKER_VCC_NET
|
|
.sym 7854 rx_24_fifo.wr_addr[4]
|
|
.sym 7856 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7863 rx_24_fifo.wr_addr[8]
|
|
.sym 7865 w_rx_24_fifo_data[24]
|
|
.sym 7866 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7867 w_rx_24_fifo_data[25]
|
|
.sym 7868 rx_24_fifo.wr_addr[7]
|
|
.sym 7869 rx_24_fifo.wr_addr[6]
|
|
.sym 7871 rx_24_fifo.wr_addr[5]
|
|
.sym 7873 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7879 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7882 rx_24_fifo.wr_addr[9]
|
|
.sym 7883 $PACKER_VCC_NET
|
|
.sym 7885 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7902 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 7903 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 7905 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 7906 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 7907 rx_24_fifo.wr_addr[4]
|
|
.sym 7908 rx_24_fifo.wr_addr[5]
|
|
.sym 7909 rx_24_fifo.wr_addr[6]
|
|
.sym 7910 rx_24_fifo.wr_addr[7]
|
|
.sym 7911 rx_24_fifo.wr_addr[8]
|
|
.sym 7912 rx_24_fifo.wr_addr[9]
|
|
.sym 7913 lvds_clock_$glb_clk
|
|
.sym 7914 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 7916 w_rx_24_fifo_data[24]
|
|
.sym 7920 w_rx_24_fifo_data[25]
|
|
.sym 7923 $PACKER_VCC_NET
|
|
.sym 7941 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7947 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7948 rx_24_fifo.rd_addr[8]
|
|
.sym 7949 rx_24_fifo.rd_addr[6]
|
|
.sym 7951 w_rx_24_fifo_data[26]
|
|
.sym 7956 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 7957 rx_24_fifo.rd_addr[9]
|
|
.sym 7958 rx_24_fifo.rd_addr[8]
|
|
.sym 7964 rx_24_fifo.rd_addr[1]
|
|
.sym 7967 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 7968 rx_24_fifo.rd_addr[7]
|
|
.sym 7970 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 7971 rx_24_fifo.rd_addr[0]
|
|
.sym 7972 rx_24_fifo.rd_addr[6]
|
|
.sym 7973 rx_24_fifo.rd_addr[5]
|
|
.sym 7974 w_rx_24_fifo_data[26]
|
|
.sym 7976 rx_24_fifo.rd_addr[4]
|
|
.sym 7985 $PACKER_VCC_NET
|
|
.sym 7987 w_rx_24_fifo_data[27]
|
|
.sym 8000 rx_24_fifo.rd_addr[0]
|
|
.sym 8001 rx_24_fifo.rd_addr[1]
|
|
.sym 8003 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 8004 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 8005 rx_24_fifo.rd_addr[4]
|
|
.sym 8006 rx_24_fifo.rd_addr[5]
|
|
.sym 8007 rx_24_fifo.rd_addr[6]
|
|
.sym 8008 rx_24_fifo.rd_addr[7]
|
|
.sym 8009 rx_24_fifo.rd_addr[8]
|
|
.sym 8010 rx_24_fifo.rd_addr[9]
|
|
.sym 8011 r_counter_$glb_clk
|
|
.sym 8012 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 8013 $PACKER_VCC_NET
|
|
.sym 8017 w_rx_24_fifo_data[27]
|
|
.sym 8021 w_rx_24_fifo_data[26]
|
|
.sym 8038 rx_24_fifo.rd_addr[4]
|
|
.sym 8088 i_smi_a3$SB_IO_IN
|
|
.sym 8093 w_smi_data_output[6]
|
|
.sym 8095 i_smi_a3$SB_IO_IN
|
|
.sym 8102 w_smi_data_output[6]
|
|
.sym 8114 i_smi_a3$SB_IO_IN
|
|
.sym 8135 rx_24_fifo.rd_addr[5]
|
|
.sym 8137 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8140 rx_24_fifo.rd_addr[7]
|
|
.sym 8172 lvds_rx_09_inst.r_data[24]
|
|
.sym 8177 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 8194 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 8196 lvds_rx_09_inst.r_data[24]
|
|
.sym 8239 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 8240 lvds_clock_$glb_clk
|
|
.sym 8241 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 8248 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 8249 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 8250 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 8251 rx_09_fifo.rd_addr[5]
|
|
.sym 8252 rx_09_fifo.rd_addr[6]
|
|
.sym 8253 rx_09_fifo.rd_addr[7]
|
|
.sym 8257 lvds_rx_24_inst.r_data[7]
|
|
.sym 8258 lvds_rx_09_inst.r_data[26]
|
|
.sym 8276 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
|
|
.sym 8291 w_smi_data_output[1]
|
|
.sym 8295 w_smi_data_output[3]
|
|
.sym 8301 w_smi_data_output[0]
|
|
.sym 8302 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1]
|
|
.sym 8303 rx_09_fifo.rd_addr[5]
|
|
.sym 8307 rx_09_fifo.rd_addr[9]
|
|
.sym 8309 rx_24_fifo.rd_addr[4]
|
|
.sym 8311 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 8323 smi_ctrl_ins.soe_and_reset
|
|
.sym 8334 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8340 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 8341 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
|
|
.sym 8344 w_rx_09_fifo_pulled_data[1]
|
|
.sym 8347 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8348 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8351 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 8352 w_rx_09_fifo_pulled_data[17]
|
|
.sym 8356 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8357 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8362 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8363 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8364 w_rx_09_fifo_pulled_data[1]
|
|
.sym 8365 w_rx_09_fifo_pulled_data[17]
|
|
.sym 8369 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 8377 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8398 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 8399 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8402 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
|
|
.sym 8403 smi_ctrl_ins.soe_and_reset
|
|
.sym 8404 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 8405 rx_09_fifo.rd_addr[8]
|
|
.sym 8406 rx_09_fifo.rd_addr[9]
|
|
.sym 8407 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
|
|
.sym 8409 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 8415 rx_24_fifo.rd_addr[0]
|
|
.sym 8416 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 8417 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8418 rx_09_fifo.rd_addr[6]
|
|
.sym 8420 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 8421 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 8422 rx_09_fifo.rd_addr[7]
|
|
.sym 8425 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8427 $PACKER_VCC_NET
|
|
.sym 8428 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 8430 rx_24_fifo.rd_addr[6]
|
|
.sym 8432 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8433 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8435 rx_24_fifo.rd_addr[0]
|
|
.sym 8437 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 8438 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 8439 smi_ctrl_ins.soe_and_reset
|
|
.sym 8440 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 8446 smi_ctrl_ins.soe_and_reset
|
|
.sym 8447 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
|
|
.sym 8448 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 8449 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8451 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8452 w_rx_09_fifo_pulled_data[2]
|
|
.sym 8454 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8455 w_rx_09_fifo_pulled_data[0]
|
|
.sym 8456 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 8457 w_rx_09_fifo_pulled_data[16]
|
|
.sym 8459 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8462 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1]
|
|
.sym 8464 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
|
|
.sym 8466 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8467 w_rx_09_fifo_pulled_data[3]
|
|
.sym 8468 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1]
|
|
.sym 8469 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 8470 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0]
|
|
.sym 8471 w_rx_09_fifo_pulled_data[18]
|
|
.sym 8472 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
|
|
.sym 8473 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 8474 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 8475 w_rx_09_fifo_pulled_data[19]
|
|
.sym 8476 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 8479 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8480 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8481 w_rx_09_fifo_pulled_data[19]
|
|
.sym 8482 w_rx_09_fifo_pulled_data[3]
|
|
.sym 8487 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 8491 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8492 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
|
|
.sym 8493 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1]
|
|
.sym 8494 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
|
|
.sym 8497 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8498 w_rx_09_fifo_pulled_data[16]
|
|
.sym 8499 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8500 w_rx_09_fifo_pulled_data[0]
|
|
.sym 8503 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1]
|
|
.sym 8504 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0]
|
|
.sym 8505 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8506 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 8509 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8510 w_rx_09_fifo_pulled_data[2]
|
|
.sym 8511 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8512 w_rx_09_fifo_pulled_data[18]
|
|
.sym 8515 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
|
|
.sym 8516 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 8517 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 8518 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8523 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 8525 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 8526 smi_ctrl_ins.soe_and_reset
|
|
.sym 8529 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 8530 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[2]
|
|
.sym 8531 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[1]
|
|
.sym 8532 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 8533 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[5]
|
|
.sym 8534 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[6]
|
|
.sym 8535 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[7]
|
|
.sym 8538 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 8540 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 8541 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
|
|
.sym 8547 rx_09_fifo.rd_addr[8]
|
|
.sym 8549 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 8552 rx_24_fifo.rd_addr[4]
|
|
.sym 8553 rx_24_fifo.rd_addr[1]
|
|
.sym 8554 rx_24_fifo.rd_addr[5]
|
|
.sym 8555 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 8556 smi_ctrl_ins.soe_and_reset
|
|
.sym 8557 rx_24_fifo.rd_addr[8]
|
|
.sym 8558 rx_24_fifo.rd_addr[7]
|
|
.sym 8559 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1]
|
|
.sym 8560 rx_24_fifo.wr_addr[9]
|
|
.sym 8561 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 8562 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
|
|
.sym 8563 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 8571 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 8575 rx_24_fifo.rd_addr[1]
|
|
.sym 8576 rx_24_fifo.rd_addr[7]
|
|
.sym 8579 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 8581 rx_24_fifo.rd_addr[4]
|
|
.sym 8582 rx_24_fifo.rd_addr[5]
|
|
.sym 8583 rx_24_fifo.rd_addr[6]
|
|
.sym 8595 rx_24_fifo.rd_addr[0]
|
|
.sym 8596 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 8601 $nextpnr_ICESTORM_LC_13$O
|
|
.sym 8603 rx_24_fifo.rd_addr[0]
|
|
.sym 8607 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 8609 rx_24_fifo.rd_addr[1]
|
|
.sym 8613 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 8615 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 8617 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 8619 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
|
|
.sym 8621 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 8623 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 8625 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
|
|
.sym 8627 rx_24_fifo.rd_addr[4]
|
|
.sym 8629 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
|
|
.sym 8631 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
|
|
.sym 8633 rx_24_fifo.rd_addr[5]
|
|
.sym 8635 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
|
|
.sym 8637 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
|
|
.sym 8639 rx_24_fifo.rd_addr[6]
|
|
.sym 8641 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
|
|
.sym 8643 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 8646 rx_24_fifo.rd_addr[7]
|
|
.sym 8647 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
|
|
.sym 8648 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 8649 r_counter_$glb_clk
|
|
.sym 8650 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 8651 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[8]
|
|
.sym 8652 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[9]
|
|
.sym 8653 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[10]
|
|
.sym 8654 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[0]
|
|
.sym 8655 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
|
|
.sym 8656 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[2]
|
|
.sym 8657 w_smi_data_output[1]
|
|
.sym 8658 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[3]
|
|
.sym 8663 rx_09_fifo.rd_addr[1]
|
|
.sym 8665 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 8666 rx_09_fifo.wr_addr[4]
|
|
.sym 8669 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 8670 rx_09_fifo.wr_addr[8]
|
|
.sym 8671 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 8673 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 8678 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 8679 rx_24_fifo.rd_addr[1]
|
|
.sym 8680 w_smi_data_output[1]
|
|
.sym 8682 rx_24_fifo.rd_addr[5]
|
|
.sym 8684 rx_24_fifo.wr_addr[4]
|
|
.sym 8685 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 8686 rx_24_fifo.rd_addr[7]
|
|
.sym 8687 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 8693 rx_24_fifo.rd_addr[9]
|
|
.sym 8694 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 8695 i_smi_a3$SB_IO_IN
|
|
.sym 8701 w_rx_09_fifo_pulled_data[8]
|
|
.sym 8702 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8703 i_smi_a1$SB_IO_IN
|
|
.sym 8704 w_rx_09_fifo_pulled_data[24]
|
|
.sym 8706 rx_24_fifo.rd_addr[0]
|
|
.sym 8707 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 8708 rx_24_fifo.rd_addr[8]
|
|
.sym 8713 w_rx_09_fifo_pulled_data[11]
|
|
.sym 8714 w_rx_09_fifo_pulled_data[27]
|
|
.sym 8715 i_smi_a2$SB_IO_IN
|
|
.sym 8719 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8720 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 8722 rx_24_fifo.rd_addr[1]
|
|
.sym 8723 i_smi_a2$SB_IO_IN
|
|
.sym 8724 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9]
|
|
.sym 8727 rx_24_fifo.rd_addr[8]
|
|
.sym 8728 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 8731 rx_24_fifo.rd_addr[9]
|
|
.sym 8734 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9]
|
|
.sym 8737 i_smi_a1$SB_IO_IN
|
|
.sym 8738 i_smi_a3$SB_IO_IN
|
|
.sym 8739 i_smi_a2$SB_IO_IN
|
|
.sym 8745 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 8749 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 8750 i_smi_a3$SB_IO_IN
|
|
.sym 8751 i_smi_a1$SB_IO_IN
|
|
.sym 8752 i_smi_a2$SB_IO_IN
|
|
.sym 8755 w_rx_09_fifo_pulled_data[11]
|
|
.sym 8756 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8757 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8758 w_rx_09_fifo_pulled_data[27]
|
|
.sym 8762 rx_24_fifo.rd_addr[0]
|
|
.sym 8764 rx_24_fifo.rd_addr[1]
|
|
.sym 8767 w_rx_09_fifo_pulled_data[24]
|
|
.sym 8768 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8769 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8770 w_rx_09_fifo_pulled_data[8]
|
|
.sym 8771 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 8772 r_counter_$glb_clk
|
|
.sym 8773 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 8774 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[3]
|
|
.sym 8776 w_smi_data_output[2]
|
|
.sym 8777 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[2]
|
|
.sym 8779 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 8780 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[0]
|
|
.sym 8781 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I3[3]
|
|
.sym 8782 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 8786 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 8790 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 8792 w_rx_09_fifo_pulled_data[24]
|
|
.sym 8796 w_rx_09_fifo_pulled_data[25]
|
|
.sym 8797 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8799 rx_24_fifo.wr_addr[7]
|
|
.sym 8800 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 8801 lvds_rx_24_inst.r_data[28]
|
|
.sym 8802 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2]
|
|
.sym 8803 rx_24_fifo.rd_addr[7]
|
|
.sym 8804 rx_24_fifo.wr_addr[8]
|
|
.sym 8805 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 8806 rx_24_fifo.rd_addr[4]
|
|
.sym 8807 rx_24_fifo.rd_addr[1]
|
|
.sym 8808 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 8809 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 8816 w_rx_09_fifo_pulled_data[10]
|
|
.sym 8819 lvds_rx_09_inst.r_data[2]
|
|
.sym 8821 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8823 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[8]
|
|
.sym 8831 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8833 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 8834 w_rx_09_fifo_pulled_data[26]
|
|
.sym 8837 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 8839 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 8840 rx_24_fifo.wr_addr[8]
|
|
.sym 8841 lvds_rx_09_inst.r_data[21]
|
|
.sym 8845 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 8861 lvds_rx_09_inst.r_data[21]
|
|
.sym 8866 w_rx_09_fifo_pulled_data[26]
|
|
.sym 8867 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 8868 w_rx_09_fifo_pulled_data[10]
|
|
.sym 8869 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 8872 lvds_rx_09_inst.r_data[2]
|
|
.sym 8884 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 8887 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 8890 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[8]
|
|
.sym 8891 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 8892 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 8893 rx_24_fifo.wr_addr[8]
|
|
.sym 8894 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 8895 lvds_clock_$glb_clk
|
|
.sym 8897 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 8898 rx_24_fifo.wr_addr[8]
|
|
.sym 8900 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
|
|
.sym 8901 rx_24_fifo.wr_addr[4]
|
|
.sym 8904 rx_24_fifo.wr_addr[5]
|
|
.sym 8918 r_tx_data_SB_DFFE_Q_E
|
|
.sym 8919 $PACKER_VCC_NET
|
|
.sym 8921 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 8922 rx_24_fifo.rd_addr[6]
|
|
.sym 8926 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 8929 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 8930 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 8931 rx_24_fifo.rd_addr[0]
|
|
.sym 8932 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 8948 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 8949 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 8962 lvds_rx_24_inst.r_data[5]
|
|
.sym 8968 lvds_rx_24_inst.r_data[7]
|
|
.sym 8972 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 9007 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 9008 lvds_rx_24_inst.r_data[5]
|
|
.sym 9013 lvds_rx_24_inst.r_data[7]
|
|
.sym 9016 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 9017 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 9018 lvds_clock_$glb_clk
|
|
.sym 9019 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 9020 rx_24_fifo.wr_addr[7]
|
|
.sym 9021 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 9022 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 9023 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 9026 rx_24_fifo.wr_addr[6]
|
|
.sym 9027 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
|
|
.sym 9035 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 9037 rx_24_fifo.wr_addr[5]
|
|
.sym 9041 rx_24_fifo.wr_addr[8]
|
|
.sym 9045 rx_24_fifo.rd_addr[1]
|
|
.sym 9046 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
|
|
.sym 9047 rx_24_fifo.wr_addr[9]
|
|
.sym 9048 rx_24_fifo.wr_addr[4]
|
|
.sym 9049 rx_24_fifo.rd_addr[8]
|
|
.sym 9050 rx_24_fifo.rd_addr[7]
|
|
.sym 9051 rx_24_fifo.wr_addr[9]
|
|
.sym 9052 rx_24_fifo.rd_addr[4]
|
|
.sym 9053 rx_24_fifo.wr_addr[7]
|
|
.sym 9054 rx_24_fifo.wr_addr[5]
|
|
.sym 9055 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
|
|
.sym 9061 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 9065 rx_24_fifo.wr_addr[4]
|
|
.sym 9068 rx_24_fifo.wr_addr[5]
|
|
.sym 9070 rx_24_fifo.wr_addr[8]
|
|
.sym 9072 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 9077 rx_24_fifo.wr_addr[7]
|
|
.sym 9079 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 9083 rx_24_fifo.wr_addr[6]
|
|
.sym 9090 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 9093 $nextpnr_ICESTORM_LC_0$O
|
|
.sym 9096 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 9099 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[2]
|
|
.sym 9101 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 9103 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 9105 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[3]
|
|
.sym 9108 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 9109 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[2]
|
|
.sym 9111 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[4]
|
|
.sym 9113 rx_24_fifo.wr_addr[4]
|
|
.sym 9115 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[3]
|
|
.sym 9117 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5]
|
|
.sym 9119 rx_24_fifo.wr_addr[5]
|
|
.sym 9121 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[4]
|
|
.sym 9123 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[6]
|
|
.sym 9125 rx_24_fifo.wr_addr[6]
|
|
.sym 9127 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5]
|
|
.sym 9129 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[7]
|
|
.sym 9132 rx_24_fifo.wr_addr[7]
|
|
.sym 9133 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[6]
|
|
.sym 9135 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 9137 rx_24_fifo.wr_addr[8]
|
|
.sym 9139 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[7]
|
|
.sym 9143 lvds_rx_24_inst.r_data[11]
|
|
.sym 9144 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
|
|
.sym 9145 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 9146 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 9147 lvds_rx_24_inst.r_data[29]
|
|
.sym 9148 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
|
|
.sym 9149 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
|
|
.sym 9150 lvds_rx_24_inst.r_data[28]
|
|
.sym 9158 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 9161 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 9162 $PACKER_VCC_NET
|
|
.sym 9167 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 9168 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 9169 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 9170 rx_24_fifo.rd_addr[5]
|
|
.sym 9171 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 9172 lvds_rx_24_inst.r_data[9]
|
|
.sym 9173 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 9174 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 9175 rx_24_fifo.wr_addr[6]
|
|
.sym 9178 lvds_rx_24_inst.r_data[15]
|
|
.sym 9179 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 9184 i_smi_a3$SB_IO_IN
|
|
.sym 9186 rx_24_fifo.wr_addr[9]
|
|
.sym 9187 w_rx_24_fifo_push
|
|
.sym 9188 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 9189 rx_24_fifo.rd_addr[8]
|
|
.sym 9190 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 9191 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 9192 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 9193 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 9195 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 9196 i_smi_a1$SB_IO_IN
|
|
.sym 9197 rx_24_fifo.rd_addr[0]
|
|
.sym 9198 rx_24_fifo.rd_addr[9]
|
|
.sym 9205 i_smi_a2$SB_IO_IN
|
|
.sym 9209 rx_24_fifo.rd_addr[5]
|
|
.sym 9211 w_rx_24_fifo_push
|
|
.sym 9216 $nextpnr_ICESTORM_LC_1$I3
|
|
.sym 9219 rx_24_fifo.wr_addr[9]
|
|
.sym 9220 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 9226 $nextpnr_ICESTORM_LC_1$I3
|
|
.sym 9229 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 9230 rx_24_fifo.rd_addr[8]
|
|
.sym 9231 rx_24_fifo.rd_addr[5]
|
|
.sym 9232 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 9235 i_smi_a1$SB_IO_IN
|
|
.sym 9236 i_smi_a3$SB_IO_IN
|
|
.sym 9237 i_smi_a2$SB_IO_IN
|
|
.sym 9238 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 9248 rx_24_fifo.rd_addr[0]
|
|
.sym 9253 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 9254 w_rx_24_fifo_push
|
|
.sym 9259 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 9260 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 9261 rx_24_fifo.rd_addr[9]
|
|
.sym 9262 w_rx_24_fifo_push
|
|
.sym 9263 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 9264 r_counter_$glb_clk
|
|
.sym 9265 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 9267 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 9268 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 9269 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 9270 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 9271 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 9272 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 9273 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 9280 rx_24_fifo.rd_addr[0]
|
|
.sym 9282 rx_24_fifo.wr_addr[9]
|
|
.sym 9283 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O
|
|
.sym 9285 $PACKER_VCC_NET
|
|
.sym 9286 w_rx_24_fifo_data[28]
|
|
.sym 9291 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 9292 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 9293 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 9296 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
|
|
.sym 9297 rx_24_fifo.rd_addr[0]
|
|
.sym 9298 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2]
|
|
.sym 9299 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 9300 lvds_rx_24_inst.r_data[28]
|
|
.sym 9301 rx_24_fifo.wr_addr[8]
|
|
.sym 9314 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 9318 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
|
|
.sym 9319 sys_ctrl_ins.reset_count[0]
|
|
.sym 9320 sys_ctrl_ins.reset_count[1]
|
|
.sym 9333 sys_ctrl_ins.reset_count[2]
|
|
.sym 9334 sys_ctrl_ins.reset_count[3]
|
|
.sym 9336 sys_ctrl_ins.reset_cmd
|
|
.sym 9338 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 9339 $nextpnr_ICESTORM_LC_10$O
|
|
.sym 9341 sys_ctrl_ins.reset_count[0]
|
|
.sym 9345 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 9347 sys_ctrl_ins.reset_count[1]
|
|
.sym 9351 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 9352 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 9353 sys_ctrl_ins.reset_count[2]
|
|
.sym 9355 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 9358 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 9359 sys_ctrl_ins.reset_count[3]
|
|
.sym 9361 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 9367 sys_ctrl_ins.reset_count[0]
|
|
.sym 9370 sys_ctrl_ins.reset_count[0]
|
|
.sym 9372 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 9373 sys_ctrl_ins.reset_count[1]
|
|
.sym 9378 sys_ctrl_ins.reset_cmd
|
|
.sym 9379 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 9382 sys_ctrl_ins.reset_count[2]
|
|
.sym 9383 sys_ctrl_ins.reset_count[1]
|
|
.sym 9384 sys_ctrl_ins.reset_count[0]
|
|
.sym 9385 sys_ctrl_ins.reset_count[3]
|
|
.sym 9386 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
|
|
.sym 9387 r_counter_$glb_clk
|
|
.sym 9388 sys_ctrl_ins.reset_cmd
|
|
.sym 9389 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 9390 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 9394 sys_ctrl_ins.reset_cmd
|
|
.sym 9409 w_rx_24_fifo_push
|
|
.sym 9412 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 9415 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 9416 sys_ctrl_ins.reset_cmd
|
|
.sym 9417 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 9418 $PACKER_VCC_NET
|
|
.sym 9419 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 9422 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 9423 lvds_rx_24_inst.r_data[21]
|
|
.sym 9424 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 9433 w_lvds_rx_24_d0
|
|
.sym 9434 w_lvds_rx_24_d1
|
|
.sym 9441 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 9442 lvds_rx_24_inst.r_data[9]
|
|
.sym 9447 w_rx_24_fifo_pulled_data[10]
|
|
.sym 9448 lvds_rx_24_inst.r_data[15]
|
|
.sym 9449 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 9455 w_rx_24_fifo_pulled_data[26]
|
|
.sym 9456 lvds_rx_24_inst.r_data[1]
|
|
.sym 9458 lvds_rx_24_inst.r_data[17]
|
|
.sym 9466 lvds_rx_24_inst.r_data[9]
|
|
.sym 9475 w_rx_24_fifo_pulled_data[26]
|
|
.sym 9476 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 9477 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 9478 w_rx_24_fifo_pulled_data[10]
|
|
.sym 9484 lvds_rx_24_inst.r_data[15]
|
|
.sym 9490 lvds_rx_24_inst.r_data[17]
|
|
.sym 9493 w_lvds_rx_24_d0
|
|
.sym 9502 lvds_rx_24_inst.r_data[1]
|
|
.sym 9506 w_lvds_rx_24_d1
|
|
.sym 9509 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 9510 lvds_clock_$glb_clk
|
|
.sym 9513 w_rx_24_fifo_data[23]
|
|
.sym 9516 w_rx_24_fifo_data[6]
|
|
.sym 9517 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
|
|
.sym 9518 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 9524 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 9529 w_lvds_rx_24_d0
|
|
.sym 9530 w_lvds_rx_24_d1
|
|
.sym 9532 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 9537 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 9538 rx_24_fifo.rd_addr[1]
|
|
.sym 9542 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 9543 rx_24_fifo.wr_addr[9]
|
|
.sym 9545 lvds_rx_24_inst.r_data[0]
|
|
.sym 9555 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 9560 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 9563 w_rx_24_fifo_pulled_data[2]
|
|
.sym 9568 lvds_rx_24_inst.r_data[5]
|
|
.sym 9569 lvds_rx_24_inst.r_data[0]
|
|
.sym 9572 lvds_rx_24_inst.r_data[7]
|
|
.sym 9580 w_rx_24_fifo_pulled_data[18]
|
|
.sym 9593 lvds_rx_24_inst.r_data[0]
|
|
.sym 9598 lvds_rx_24_inst.r_data[5]
|
|
.sym 9610 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 9611 w_rx_24_fifo_pulled_data[2]
|
|
.sym 9612 w_rx_24_fifo_pulled_data[18]
|
|
.sym 9613 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 9625 lvds_rx_24_inst.r_data[7]
|
|
.sym 9632 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 9633 lvds_clock_$glb_clk
|
|
.sym 9636 lvds_rx_09_inst.r_push
|
|
.sym 9637 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
|
|
.sym 9638 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 9642 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 9647 w_rx_24_fifo_data[22]
|
|
.sym 9654 $PACKER_VCC_NET
|
|
.sym 9657 $PACKER_VCC_NET
|
|
.sym 9661 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 9662 lvds_rx_24_inst.r_data[15]
|
|
.sym 9663 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 9664 w_rx_24_fifo_data[20]
|
|
.sym 9667 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 9669 rx_24_fifo.wr_addr[9]
|
|
.sym 9678 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 9682 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 9687 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 9690 w_rx_24_fifo_data[18]
|
|
.sym 9694 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 9716 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 9730 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 9747 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 9751 w_rx_24_fifo_data[18]
|
|
.sym 9755 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 9756 lvds_clock_$glb_clk
|
|
.sym 9757 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 9758 lvds_rx_24_inst.r_data[20]
|
|
.sym 9759 lvds_rx_24_inst.r_data[14]
|
|
.sym 9760 lvds_rx_24_inst.r_data[18]
|
|
.sym 9761 lvds_rx_24_inst.r_data[26]
|
|
.sym 9762 lvds_rx_24_inst.r_data[0]
|
|
.sym 9763 lvds_rx_24_inst.r_data[16]
|
|
.sym 9764 lvds_rx_24_inst.r_data[22]
|
|
.sym 9765 lvds_rx_24_inst.r_data[24]
|
|
.sym 9774 rx_24_fifo.wr_addr[9]
|
|
.sym 9777 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 9778 $PACKER_VCC_NET
|
|
.sym 9782 lvds_rx_24_inst.r_data[4]
|
|
.sym 9784 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 9790 rx_24_fifo.rd_addr[0]
|
|
.sym 9802 lvds_rx_24_inst.r_data[8]
|
|
.sym 9814 lvds_rx_24_inst.r_data[6]
|
|
.sym 9817 lvds_rx_24_inst.r_data[18]
|
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.sym 9822 lvds_rx_24_inst.r_data[24]
|
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.sym 9824 lvds_rx_24_inst.r_data[14]
|
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.sym 9828 lvds_rx_24_inst.r_data[16]
|
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.sym 9829 lvds_rx_24_inst.r_data[22]
|
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.sym 9834 lvds_rx_24_inst.r_data[18]
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.sym 9846 lvds_rx_24_inst.r_data[14]
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.sym 9852 lvds_rx_24_inst.r_data[22]
|
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.sym 9856 lvds_rx_24_inst.r_data[6]
|
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.sym 9864 lvds_rx_24_inst.r_data[24]
|
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.sym 9870 lvds_rx_24_inst.r_data[16]
|
|
.sym 9874 lvds_rx_24_inst.r_data[8]
|
|
.sym 9878 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 9879 lvds_clock_$glb_clk
|
|
.sym 9881 lvds_rx_24_inst.r_data[10]
|
|
.sym 9882 lvds_rx_24_inst.r_data[15]
|
|
.sym 9883 lvds_rx_24_inst.r_data[13]
|
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.sym 9884 lvds_rx_24_inst.r_data[2]
|
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.sym 9885 lvds_rx_24_inst.r_data[12]
|
|
.sym 9887 lvds_rx_24_inst.r_data[4]
|
|
.sym 9889 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 9890 rx_24_fifo.rd_addr[0]
|
|
.sym 9895 w_lvds_rx_24_d0
|
|
.sym 9904 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 9929 lvds_rx_24_inst.r_data[6]
|
|
.sym 9930 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 9944 lvds_rx_24_inst.r_data[4]
|
|
.sym 9973 lvds_rx_24_inst.r_data[6]
|
|
.sym 9975 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 9998 lvds_rx_24_inst.r_data[4]
|
|
.sym 9999 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 10001 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 10002 lvds_clock_$glb_clk
|
|
.sym 10003 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 10024 w_rx_24_fifo_data[12]
|
|
.sym 10172 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 10190 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 10198 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 10201 w_smi_data_output[2]
|
|
.sym 10203 i_smi_a3$SB_IO_IN
|
|
.sym 10204 w_smi_data_output[1]
|
|
.sym 10206 i_smi_a3$SB_IO_IN
|
|
.sym 10210 i_smi_a3$SB_IO_IN
|
|
.sym 10218 i_smi_a3$SB_IO_IN
|
|
.sym 10222 w_smi_data_output[1]
|
|
.sym 10225 w_smi_data_output[2]
|
|
.sym 10241 w_smi_data_output[2]
|
|
.sym 10243 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[5]
|
|
.sym 10249 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 10259 w_smi_data_output[3]
|
|
.sym 10260 w_smi_data_output[0]
|
|
.sym 10356 w_rx_09_fifo_data[13]
|
|
.sym 10361 w_rx_09_fifo_data[12]
|
|
.sym 10364 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 10366 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 10373 smi_ctrl_ins.soe_and_reset
|
|
.sym 10384 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 10385 w_smi_data_output[7]
|
|
.sym 10388 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 10395 rx_09_fifo.rd_addr[6]
|
|
.sym 10397 rx_09_fifo.rd_addr[7]
|
|
.sym 10398 w_rx_09_fifo_data[12]
|
|
.sym 10400 w_rx_09_fifo_push
|
|
.sym 10404 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 10406 rx_09_fifo.rd_addr[1]
|
|
.sym 10408 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 10410 rx_09_fifo.rd_addr[5]
|
|
.sym 10413 rx_09_fifo.rd_addr[6]
|
|
.sym 10414 rx_09_fifo.rd_addr[8]
|
|
.sym 10415 rx_09_fifo.rd_addr[7]
|
|
.sym 10416 rx_09_fifo.rd_addr[9]
|
|
.sym 10422 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 10434 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 10435 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 10437 rx_09_fifo.rd_addr[6]
|
|
.sym 10442 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 10443 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 10446 rx_09_fifo.rd_addr[7]
|
|
.sym 10449 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 10460 rx_09_fifo.rd_addr[5]
|
|
.sym 10462 rx_09_fifo.rd_addr[1]
|
|
.sym 10463 $nextpnr_ICESTORM_LC_9$O
|
|
.sym 10465 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 10469 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 10471 rx_09_fifo.rd_addr[1]
|
|
.sym 10475 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 10478 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 10479 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 10481 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
|
|
.sym 10484 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 10485 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 10487 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
|
|
.sym 10490 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 10491 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
|
|
.sym 10493 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
|
|
.sym 10495 rx_09_fifo.rd_addr[5]
|
|
.sym 10497 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
|
|
.sym 10499 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
|
|
.sym 10502 rx_09_fifo.rd_addr[6]
|
|
.sym 10503 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
|
|
.sym 10505 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 10507 rx_09_fifo.rd_addr[7]
|
|
.sym 10509 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
|
|
.sym 10510 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 10511 r_counter_$glb_clk
|
|
.sym 10512 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 10513 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 10514 w_rx_09_fifo_data[14]
|
|
.sym 10515 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 10517 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 10518 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 10519 rx_09_fifo.full_o_SB_LUT4_I3_O[3]
|
|
.sym 10520 w_rx_09_fifo_data[15]
|
|
.sym 10526 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 10527 rx_09_fifo.rd_addr[5]
|
|
.sym 10528 smi_ctrl_ins.soe_and_reset
|
|
.sym 10531 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 10533 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 10535 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 10536 w_smi_data_output[4]
|
|
.sym 10537 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 10538 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 10539 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 10540 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 10541 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 10542 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 10544 rx_09_fifo.rd_addr[5]
|
|
.sym 10545 rx_09_fifo.rd_addr[8]
|
|
.sym 10546 rx_09_fifo.rd_addr[6]
|
|
.sym 10547 rx_09_fifo.wr_addr[3]
|
|
.sym 10548 rx_09_fifo.rd_addr[7]
|
|
.sym 10549 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 10554 rx_09_fifo.rd_addr[8]
|
|
.sym 10556 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 10571 rx_09_fifo.rd_addr[9]
|
|
.sym 10574 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 10577 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
|
|
.sym 10586 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9]
|
|
.sym 10589 rx_09_fifo.rd_addr[8]
|
|
.sym 10590 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 10595 rx_09_fifo.rd_addr[9]
|
|
.sym 10596 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9]
|
|
.sym 10602 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
|
|
.sym 10613 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 10633 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 10634 r_counter_$glb_clk
|
|
.sym 10635 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 10636 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 10637 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 10638 rx_09_fifo.wr_addr[7]
|
|
.sym 10639 rx_09_fifo.wr_addr[3]
|
|
.sym 10640 rx_09_fifo.wr_addr[2]
|
|
.sym 10641 rx_09_fifo.wr_addr[5]
|
|
.sym 10642 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 10643 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2]
|
|
.sym 10652 rx_09_fifo.rd_addr[9]
|
|
.sym 10654 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 10658 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 10660 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 10661 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 10662 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 10663 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 10664 lvds_rx_09_inst.r_data[12]
|
|
.sym 10665 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 10666 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 10667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
|
|
.sym 10669 rx_24_fifo.wr_addr[6]
|
|
.sym 10670 w_rx_09_fifo_full
|
|
.sym 10671 lvds_rx_09_inst.r_data[5]
|
|
.sym 10679 rx_24_fifo.rd_addr[0]
|
|
.sym 10680 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 10681 rx_24_fifo.rd_addr[4]
|
|
.sym 10683 rx_24_fifo.rd_addr[6]
|
|
.sym 10687 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 10690 rx_24_fifo.rd_addr[5]
|
|
.sym 10692 rx_24_fifo.rd_addr[7]
|
|
.sym 10699 rx_24_fifo.rd_addr[1]
|
|
.sym 10709 $nextpnr_ICESTORM_LC_6$O
|
|
.sym 10712 rx_24_fifo.rd_addr[0]
|
|
.sym 10715 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[2]
|
|
.sym 10717 rx_24_fifo.rd_addr[1]
|
|
.sym 10719 rx_24_fifo.rd_addr[0]
|
|
.sym 10721 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[3]
|
|
.sym 10723 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 10725 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[2]
|
|
.sym 10727 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[4]
|
|
.sym 10730 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 10731 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[3]
|
|
.sym 10733 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[5]
|
|
.sym 10736 rx_24_fifo.rd_addr[4]
|
|
.sym 10737 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[4]
|
|
.sym 10739 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[6]
|
|
.sym 10741 rx_24_fifo.rd_addr[5]
|
|
.sym 10743 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[5]
|
|
.sym 10745 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[7]
|
|
.sym 10748 rx_24_fifo.rd_addr[6]
|
|
.sym 10749 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[6]
|
|
.sym 10751 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[8]
|
|
.sym 10753 rx_24_fifo.rd_addr[7]
|
|
.sym 10755 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[7]
|
|
.sym 10759 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
|
|
.sym 10760 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2]
|
|
.sym 10761 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
|
|
.sym 10762 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 10763 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 10764 w_rx_09_fifo_data[7]
|
|
.sym 10765 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 10766 w_rx_09_fifo_data[6]
|
|
.sym 10772 rx_09_fifo.rd_addr[9]
|
|
.sym 10774 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 10776 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1]
|
|
.sym 10779 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[1]
|
|
.sym 10780 lvds_rx_24_inst.r_data[28]
|
|
.sym 10781 rx_09_fifo.rd_addr[5]
|
|
.sym 10782 rx_09_fifo.wr_addr[7]
|
|
.sym 10783 w_rx_09_fifo_empty
|
|
.sym 10784 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[2]
|
|
.sym 10785 rx_09_fifo.wr_addr[3]
|
|
.sym 10786 w_rx_09_fifo_data[7]
|
|
.sym 10787 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 10788 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 10789 w_rx_24_fifo_empty
|
|
.sym 10791 w_rx_09_fifo_push
|
|
.sym 10793 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 10795 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[8]
|
|
.sym 10800 smi_ctrl_ins.soe_and_reset
|
|
.sym 10802 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 10804 rx_24_fifo.wr_addr[9]
|
|
.sym 10805 w_rx_09_fifo_pulled_data[25]
|
|
.sym 10806 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
|
|
.sym 10807 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I3[3]
|
|
.sym 10808 rx_24_fifo.rd_addr[8]
|
|
.sym 10809 rx_24_fifo.rd_addr[9]
|
|
.sym 10810 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 10811 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 10812 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 10814 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[6]
|
|
.sym 10815 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[7]
|
|
.sym 10818 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[10]
|
|
.sym 10820 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 10821 rx_24_fifo.wr_addr[7]
|
|
.sym 10824 rx_24_fifo.wr_addr[4]
|
|
.sym 10825 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[9]
|
|
.sym 10826 w_rx_09_fifo_pulled_data[9]
|
|
.sym 10827 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
|
|
.sym 10828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
|
|
.sym 10829 rx_24_fifo.wr_addr[6]
|
|
.sym 10832 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[9]
|
|
.sym 10834 rx_24_fifo.rd_addr[8]
|
|
.sym 10836 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[8]
|
|
.sym 10838 $nextpnr_ICESTORM_LC_7$I3
|
|
.sym 10840 rx_24_fifo.rd_addr[9]
|
|
.sym 10842 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[9]
|
|
.sym 10848 $nextpnr_ICESTORM_LC_7$I3
|
|
.sym 10851 rx_24_fifo.wr_addr[4]
|
|
.sym 10852 rx_24_fifo.wr_addr[9]
|
|
.sym 10853 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 10854 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[9]
|
|
.sym 10857 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 10858 w_rx_09_fifo_pulled_data[25]
|
|
.sym 10859 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 10860 w_rx_09_fifo_pulled_data[9]
|
|
.sym 10863 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I3[3]
|
|
.sym 10864 rx_24_fifo.wr_addr[6]
|
|
.sym 10865 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[6]
|
|
.sym 10866 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[10]
|
|
.sym 10869 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
|
|
.sym 10870 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 10871 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
|
|
.sym 10872 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
|
|
.sym 10875 rx_24_fifo.wr_addr[7]
|
|
.sym 10876 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[7]
|
|
.sym 10877 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[6]
|
|
.sym 10878 rx_24_fifo.wr_addr[6]
|
|
.sym 10879 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 10880 smi_ctrl_ins.soe_and_reset
|
|
.sym 10883 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 10884 lvds_rx_24_inst.r_push
|
|
.sym 10885 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 10887 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3]
|
|
.sym 10893 lvds_rx_24_inst.r_data[11]
|
|
.sym 10895 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 10901 smi_ctrl_ins.soe_and_reset
|
|
.sym 10905 w_rx_09_fifo_data[5]
|
|
.sym 10906 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 10907 w_rx_09_fifo_push
|
|
.sym 10909 rx_09_fifo.rd_addr[9]
|
|
.sym 10910 rx_24_fifo.rd_addr[4]
|
|
.sym 10911 rx_09_fifo.rd_addr[8]
|
|
.sym 10912 rx_24_fifo.rd_addr[5]
|
|
.sym 10913 rx_09_fifo.rd_addr[5]
|
|
.sym 10914 rx_24_fifo.rd_addr[6]
|
|
.sym 10917 rx_09_fifo.rd_addr[7]
|
|
.sym 10923 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 10924 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[9]
|
|
.sym 10925 rx_24_fifo.wr_addr[9]
|
|
.sym 10926 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0]
|
|
.sym 10929 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 10930 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[3]
|
|
.sym 10931 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[8]
|
|
.sym 10932 rx_24_fifo.wr_addr[8]
|
|
.sym 10933 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 10934 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[0]
|
|
.sym 10935 rx_24_fifo.wr_addr[4]
|
|
.sym 10936 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[2]
|
|
.sym 10937 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1]
|
|
.sym 10938 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[1]
|
|
.sym 10939 smi_ctrl_ins.soe_and_reset
|
|
.sym 10941 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 10942 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[2]
|
|
.sym 10943 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 10944 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[2]
|
|
.sym 10945 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[5]
|
|
.sym 10947 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[3]
|
|
.sym 10948 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 10949 rx_24_fifo.wr_addr[5]
|
|
.sym 10950 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 10952 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2]
|
|
.sym 10953 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[0]
|
|
.sym 10956 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[0]
|
|
.sym 10957 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[3]
|
|
.sym 10958 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[1]
|
|
.sym 10959 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[2]
|
|
.sym 10968 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 10969 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1]
|
|
.sym 10970 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2]
|
|
.sym 10971 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0]
|
|
.sym 10974 rx_24_fifo.wr_addr[5]
|
|
.sym 10975 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 10976 rx_24_fifo.wr_addr[4]
|
|
.sym 10977 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[5]
|
|
.sym 10986 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[0]
|
|
.sym 10987 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 10988 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[3]
|
|
.sym 10989 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[2]
|
|
.sym 10992 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 10993 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[8]
|
|
.sym 10994 rx_24_fifo.wr_addr[8]
|
|
.sym 10995 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[2]
|
|
.sym 10998 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 10999 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 11000 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[9]
|
|
.sym 11001 rx_24_fifo.wr_addr[9]
|
|
.sym 11002 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 11003 smi_ctrl_ins.soe_and_reset
|
|
.sym 11005 w_tx_data_smi[2]
|
|
.sym 11006 w_tx_data_smi[3]
|
|
.sym 11008 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[3]
|
|
.sym 11009 w_tx_data_smi[0]
|
|
.sym 11010 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 11011 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 11012 w_tx_data_smi[1]
|
|
.sym 11017 rx_24_fifo.rd_addr[1]
|
|
.sym 11018 rx_24_fifo.rd_addr[4]
|
|
.sym 11019 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 11021 rx_24_fifo.wr_addr[9]
|
|
.sym 11028 rx_24_fifo.rd_addr[5]
|
|
.sym 11030 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 11031 rx_24_fifo.rd_addr[9]
|
|
.sym 11034 rx_24_fifo.wr_addr[9]
|
|
.sym 11035 rx_24_fifo.wr_addr[5]
|
|
.sym 11036 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11037 rx_24_fifo.rd_addr[1]
|
|
.sym 11038 rx_24_fifo.rd_addr[8]
|
|
.sym 11039 rx_24_fifo.wr_addr[8]
|
|
.sym 11048 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 11051 rx_24_fifo.rd_addr[1]
|
|
.sym 11052 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 11053 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 11059 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 11061 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 11062 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 11080 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 11086 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 11098 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 11099 rx_24_fifo.rd_addr[1]
|
|
.sym 11105 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 11122 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 11125 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 11126 lvds_clock_$glb_clk
|
|
.sym 11127 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 11130 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 11131 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 11132 w_cs[2]
|
|
.sym 11133 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
|
|
.sym 11135 w_cs[1]
|
|
.sym 11140 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 11141 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 11142 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 11144 rx_24_fifo.wr_addr[8]
|
|
.sym 11146 rx_24_fifo.rd_addr[7]
|
|
.sym 11147 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 11148 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 11149 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 11150 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 11153 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11156 rx_24_fifo.wr_addr[6]
|
|
.sym 11157 lvds_rx_24_inst.r_push
|
|
.sym 11159 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
|
|
.sym 11160 rx_24_fifo.wr_addr[7]
|
|
.sym 11161 w_rx_09_fifo_full
|
|
.sym 11162 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 11163 w_rx_24_fifo_full
|
|
.sym 11170 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 11172 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
|
|
.sym 11173 rx_24_fifo.rd_addr[7]
|
|
.sym 11174 rx_24_fifo.rd_addr[6]
|
|
.sym 11175 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 11176 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 11178 rx_24_fifo.rd_addr[4]
|
|
.sym 11180 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 11182 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 11183 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 11186 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 11190 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 11196 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 11198 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 11199 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 11200 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 11203 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 11208 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 11209 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 11210 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 11211 rx_24_fifo.rd_addr[4]
|
|
.sym 11214 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 11220 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 11221 rx_24_fifo.rd_addr[7]
|
|
.sym 11222 rx_24_fifo.rd_addr[6]
|
|
.sym 11223 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 11239 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 11244 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
|
|
.sym 11245 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 11246 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 11247 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 11248 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 11249 lvds_clock_$glb_clk
|
|
.sym 11250 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 11252 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
|
|
.sym 11253 w_rx_24_fifo_data[29]
|
|
.sym 11254 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 11256 w_rx_24_fifo_data[31]
|
|
.sym 11258 w_rx_24_fifo_data[28]
|
|
.sym 11267 rx_24_fifo.rd_addr[1]
|
|
.sym 11268 w_cs[1]
|
|
.sym 11271 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 11272 spi_if_ins.w_rx_data[6]
|
|
.sym 11275 w_rx_09_fifo_push
|
|
.sym 11276 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 11278 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 11281 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 11283 lvds_rx_24_inst.r_data[11]
|
|
.sym 11284 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 11286 lvds_rx_24_inst.r_data[26]
|
|
.sym 11293 lvds_rx_24_inst.r_data[26]
|
|
.sym 11294 rx_24_fifo.rd_addr[7]
|
|
.sym 11295 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 11296 rx_24_fifo.rd_addr[4]
|
|
.sym 11298 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
|
|
.sym 11299 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
|
|
.sym 11300 rx_24_fifo.rd_addr[6]
|
|
.sym 11301 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 11302 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
|
|
.sym 11303 rx_24_fifo.rd_addr[9]
|
|
.sym 11304 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 11305 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 11306 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 11307 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 11309 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
|
|
.sym 11310 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 11312 lvds_rx_24_inst.r_data[27]
|
|
.sym 11313 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
|
|
.sym 11314 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11317 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
|
|
.sym 11318 rx_24_fifo.rd_addr[5]
|
|
.sym 11320 lvds_rx_24_inst.r_data[9]
|
|
.sym 11322 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 11326 lvds_rx_24_inst.r_data[9]
|
|
.sym 11327 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11331 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 11332 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 11333 rx_24_fifo.rd_addr[5]
|
|
.sym 11334 rx_24_fifo.rd_addr[4]
|
|
.sym 11337 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 11338 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
|
|
.sym 11339 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 11340 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
|
|
.sym 11343 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
|
|
.sym 11344 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
|
|
.sym 11345 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
|
|
.sym 11346 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
|
|
.sym 11349 lvds_rx_24_inst.r_data[27]
|
|
.sym 11351 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11355 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 11356 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 11357 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 11358 rx_24_fifo.rd_addr[9]
|
|
.sym 11361 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 11362 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 11363 rx_24_fifo.rd_addr[7]
|
|
.sym 11364 rx_24_fifo.rd_addr[6]
|
|
.sym 11368 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11369 lvds_rx_24_inst.r_data[26]
|
|
.sym 11371 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 11372 lvds_clock_$glb_clk
|
|
.sym 11373 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 11376 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 11377 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 11378 w_rx_09_fifo_full
|
|
.sym 11379 w_rx_24_fifo_full
|
|
.sym 11380 w_rx_09_fifo_push
|
|
.sym 11381 w_rx_24_fifo_push
|
|
.sym 11386 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 11388 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 11391 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 11392 $PACKER_VCC_NET
|
|
.sym 11395 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 11396 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 11400 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11403 w_rx_09_fifo_push
|
|
.sym 11415 rx_24_fifo.wr_addr[7]
|
|
.sym 11418 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 11419 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 11420 rx_24_fifo.wr_addr[4]
|
|
.sym 11426 rx_24_fifo.wr_addr[5]
|
|
.sym 11427 rx_24_fifo.wr_addr[6]
|
|
.sym 11428 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 11441 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 11447 $nextpnr_ICESTORM_LC_2$O
|
|
.sym 11450 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 11453 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
|
|
.sym 11456 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 11457 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 11459 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
|
|
.sym 11462 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 11463 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
|
|
.sym 11465 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
|
|
.sym 11468 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 11469 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
|
|
.sym 11471 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
|
|
.sym 11473 rx_24_fifo.wr_addr[4]
|
|
.sym 11475 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
|
|
.sym 11477 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
|
|
.sym 11479 rx_24_fifo.wr_addr[5]
|
|
.sym 11481 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
|
|
.sym 11483 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
|
|
.sym 11485 rx_24_fifo.wr_addr[6]
|
|
.sym 11487 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
|
|
.sym 11489 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 11491 rx_24_fifo.wr_addr[7]
|
|
.sym 11493 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
|
|
.sym 11497 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
|
|
.sym 11498 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 11500 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 11501 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 11503 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 11504 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11510 rx_24_fifo.rd_addr[7]
|
|
.sym 11511 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
|
|
.sym 11512 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 11515 rx_24_fifo.rd_addr[8]
|
|
.sym 11516 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 11518 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 11522 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 11523 lvds_rx_09_inst.r_push
|
|
.sym 11524 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 11525 w_rx_09_fifo_full
|
|
.sym 11526 rx_24_fifo.wr_addr[9]
|
|
.sym 11527 rx_24_fifo.wr_addr[5]
|
|
.sym 11528 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11531 w_rx_24_fifo_push
|
|
.sym 11533 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 11540 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
|
|
.sym 11551 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
|
|
.sym 11553 rx_24_fifo.wr_addr[8]
|
|
.sym 11565 rx_24_fifo.wr_addr[9]
|
|
.sym 11566 $PACKER_VCC_NET
|
|
.sym 11570 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9]
|
|
.sym 11573 rx_24_fifo.wr_addr[8]
|
|
.sym 11574 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 11578 rx_24_fifo.wr_addr[9]
|
|
.sym 11580 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9]
|
|
.sym 11601 $PACKER_VCC_NET
|
|
.sym 11617 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
|
|
.sym 11618 r_counter_$glb_clk
|
|
.sym 11619 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
|
|
.sym 11621 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
|
|
.sym 11624 w_rx_24_fifo_data[22]
|
|
.sym 11625 w_rx_24_fifo_data[5]
|
|
.sym 11626 w_rx_24_fifo_data[21]
|
|
.sym 11633 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 11634 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 11635 rx_24_fifo.wr_addr[9]
|
|
.sym 11637 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11638 w_rx_24_fifo_data[20]
|
|
.sym 11639 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
|
|
.sym 11641 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 11643 rx_24_fifo.wr_addr[6]
|
|
.sym 11644 lvds_rx_24_inst.r_data[20]
|
|
.sym 11650 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 11652 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11654 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11666 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 11667 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 11670 lvds_rx_24_inst.r_data[4]
|
|
.sym 11675 lvds_rx_24_inst.r_data[21]
|
|
.sym 11679 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11684 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 11702 lvds_rx_24_inst.r_data[21]
|
|
.sym 11718 lvds_rx_24_inst.r_data[4]
|
|
.sym 11724 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 11725 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11726 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 11730 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 11732 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11733 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 11740 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 11741 lvds_clock_$glb_clk
|
|
.sym 11744 w_lvds_rx_24_d0_SB_LUT4_I1_O[1]
|
|
.sym 11745 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11746 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.sym 11755 rx_24_fifo.rd_addr[0]
|
|
.sym 11756 lvds_rx_24_inst.r_data[4]
|
|
.sym 11759 w_rx_24_fifo_data[23]
|
|
.sym 11762 w_cs[0]
|
|
.sym 11763 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 11764 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
|
|
.sym 11768 lvds_rx_24_inst.r_data[11]
|
|
.sym 11769 lvds_rx_24_inst.r_data[19]
|
|
.sym 11772 w_rx_24_fifo_data[6]
|
|
.sym 11778 lvds_rx_24_inst.r_data[26]
|
|
.sym 11786 sys_ctrl_ins.reset_cmd
|
|
.sym 11789 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 11791 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 11792 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 11795 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 11797 w_rx_09_fifo_full
|
|
.sym 11798 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 11802 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11806 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 11823 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 11825 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 11826 w_rx_09_fifo_full
|
|
.sym 11829 sys_ctrl_ins.reset_cmd
|
|
.sym 11835 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 11859 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 11860 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11861 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 11862 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 11863 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 11864 lvds_clock_$glb_clk
|
|
.sym 11865 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 11866 w_tx_data_sys[0]
|
|
.sym 11885 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 11889 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 11892 $PACKER_GND_NET
|
|
.sym 11911 lvds_rx_24_inst.r_data[12]
|
|
.sym 11916 lvds_rx_24_inst.r_data[14]
|
|
.sym 11920 lvds_rx_24_inst.r_data[16]
|
|
.sym 11921 lvds_rx_24_inst.r_data[22]
|
|
.sym 11922 w_lvds_rx_24_d0
|
|
.sym 11925 lvds_rx_24_inst.r_data[18]
|
|
.sym 11926 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11930 lvds_rx_24_inst.r_data[24]
|
|
.sym 11931 lvds_rx_24_inst.r_data[20]
|
|
.sym 11941 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11942 lvds_rx_24_inst.r_data[18]
|
|
.sym 11947 lvds_rx_24_inst.r_data[12]
|
|
.sym 11948 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11953 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11954 lvds_rx_24_inst.r_data[16]
|
|
.sym 11958 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11960 lvds_rx_24_inst.r_data[24]
|
|
.sym 11965 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11966 w_lvds_rx_24_d0
|
|
.sym 11971 lvds_rx_24_inst.r_data[14]
|
|
.sym 11972 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11977 lvds_rx_24_inst.r_data[20]
|
|
.sym 11979 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11982 lvds_rx_24_inst.r_data[22]
|
|
.sym 11984 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 11986 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 11987 lvds_clock_$glb_clk
|
|
.sym 11988 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 11989 w_rx_24_fifo_data[14]
|
|
.sym 11990 w_rx_24_fifo_data[13]
|
|
.sym 11992 w_rx_24_fifo_data[15]
|
|
.sym 11995 w_rx_24_fifo_data[4]
|
|
.sym 11996 w_rx_24_fifo_data[12]
|
|
.sym 12010 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 12012 rx_24_fifo.rd_addr[1]
|
|
.sym 12030 lvds_rx_24_inst.r_data[10]
|
|
.sym 12033 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 12034 lvds_rx_24_inst.r_data[0]
|
|
.sym 12040 lvds_rx_24_inst.r_data[13]
|
|
.sym 12041 lvds_rx_24_inst.r_data[8]
|
|
.sym 12057 lvds_rx_24_inst.r_data[2]
|
|
.sym 12058 lvds_rx_24_inst.r_data[11]
|
|
.sym 12063 lvds_rx_24_inst.r_data[8]
|
|
.sym 12064 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 12069 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 12071 lvds_rx_24_inst.r_data[13]
|
|
.sym 12076 lvds_rx_24_inst.r_data[11]
|
|
.sym 12078 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 12083 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 12084 lvds_rx_24_inst.r_data[0]
|
|
.sym 12088 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 12089 lvds_rx_24_inst.r_data[10]
|
|
.sym 12099 lvds_rx_24_inst.r_data[2]
|
|
.sym 12102 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 12109 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 12110 lvds_clock_$glb_clk
|
|
.sym 12111 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 12127 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 12130 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 12131 rx_24_fifo.wr_addr[9]
|
|
.sym 12248 rx_24_fifo.rd_addr[0]
|
|
.sym 12309 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 12310 w_smi_data_output[0]
|
|
.sym 12312 i_smi_a3$SB_IO_IN
|
|
.sym 12313 w_smi_data_output[7]
|
|
.sym 12315 i_smi_a3$SB_IO_IN
|
|
.sym 12323 i_smi_a3$SB_IO_IN
|
|
.sym 12325 w_smi_data_output[0]
|
|
.sym 12326 w_smi_data_output[7]
|
|
.sym 12331 i_smi_a3$SB_IO_IN
|
|
.sym 12333 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 12337 lvds_rx_09_inst.r_data[29]
|
|
.sym 12340 lvds_rx_09_inst.r_data[28]
|
|
.sym 12351 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 12367 i_sck$SB_IO_IN
|
|
.sym 12370 rx_09_fifo.rd_addr[9]
|
|
.sym 12464 lvds_rx_09_inst.r_data[27]
|
|
.sym 12466 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 12474 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 12492 smi_ctrl_ins.soe_and_reset
|
|
.sym 12513 w_rx_09_fifo_data[13]
|
|
.sym 12520 w_rx_09_fifo_data[15]
|
|
.sym 12525 w_rx_09_fifo_data[14]
|
|
.sym 12553 lvds_rx_09_inst.r_data[11]
|
|
.sym 12554 lvds_rx_09_inst.r_data[10]
|
|
.sym 12585 lvds_rx_09_inst.r_data[11]
|
|
.sym 12615 lvds_rx_09_inst.r_data[10]
|
|
.sym 12619 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 12620 lvds_clock_$glb_clk
|
|
.sym 12623 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 12624 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 12625 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 12626 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 12627 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 12628 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 12629 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 12634 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 12635 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 12636 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 12637 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 12638 w_smi_data_output[7]
|
|
.sym 12640 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 12641 lvds_rx_09_inst.r_data[11]
|
|
.sym 12642 lvds_rx_09_inst.r_data[10]
|
|
.sym 12643 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 12644 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 12646 rx_09_fifo.wr_addr[6]
|
|
.sym 12647 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 12648 rx_09_fifo.wr_addr[4]
|
|
.sym 12651 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 12655 rx_09_fifo.wr_addr[7]
|
|
.sym 12656 rx_09_fifo.wr_addr[9]
|
|
.sym 12657 rx_09_fifo.wr_addr[3]
|
|
.sym 12663 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 12664 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 12667 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 12668 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 12671 rx_09_fifo.rd_addr[8]
|
|
.sym 12672 rx_09_fifo.rd_addr[9]
|
|
.sym 12673 rx_09_fifo.rd_addr[1]
|
|
.sym 12676 w_rx_09_fifo_push
|
|
.sym 12677 rx_09_fifo.full_o_SB_LUT4_I3_O[3]
|
|
.sym 12679 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 12680 rx_09_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 12681 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 12683 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 12684 rx_09_fifo.rd_addr[5]
|
|
.sym 12685 rx_09_fifo.rd_addr[6]
|
|
.sym 12686 lvds_rx_09_inst.r_data[13]
|
|
.sym 12687 lvds_rx_09_inst.r_data[12]
|
|
.sym 12688 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 12689 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 12691 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 12692 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 12693 w_rx_09_fifo_full
|
|
.sym 12696 w_rx_09_fifo_push
|
|
.sym 12697 w_rx_09_fifo_full
|
|
.sym 12698 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 12699 rx_09_fifo.rd_addr[8]
|
|
.sym 12702 lvds_rx_09_inst.r_data[12]
|
|
.sym 12708 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 12709 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 12710 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 12711 rx_09_fifo.full_o_SB_LUT4_I3_O[3]
|
|
.sym 12720 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 12721 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 12722 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 12723 rx_09_fifo.rd_addr[1]
|
|
.sym 12726 rx_09_fifo.rd_addr[5]
|
|
.sym 12727 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 12728 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 12729 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 12732 rx_09_fifo.rd_addr[6]
|
|
.sym 12733 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 12734 rx_09_fifo.rd_addr[9]
|
|
.sym 12735 rx_09_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 12738 lvds_rx_09_inst.r_data[13]
|
|
.sym 12742 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 12743 lvds_clock_$glb_clk
|
|
.sym 12745 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 12746 rx_09_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 12747 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 12748 rx_09_fifo.wr_addr[9]
|
|
.sym 12749 rx_09_fifo.wr_addr[8]
|
|
.sym 12750 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[1]
|
|
.sym 12751 rx_09_fifo.wr_addr[6]
|
|
.sym 12752 rx_09_fifo.wr_addr[4]
|
|
.sym 12757 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0]
|
|
.sym 12758 w_rx_09_fifo_empty
|
|
.sym 12759 rx_09_fifo.rd_addr[1]
|
|
.sym 12761 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 12765 rx_09_fifo.rd_addr[6]
|
|
.sym 12766 w_rx_24_fifo_empty
|
|
.sym 12767 rx_09_fifo.rd_addr[7]
|
|
.sym 12768 w_rx_09_fifo_data[12]
|
|
.sym 12770 smi_ctrl_ins.soe_and_reset
|
|
.sym 12771 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 12772 w_rx_09_fifo_data[6]
|
|
.sym 12775 rx_09_fifo.rd_addr[5]
|
|
.sym 12779 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 12780 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 12787 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 12789 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 12793 rx_09_fifo.rd_addr[7]
|
|
.sym 12796 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 12799 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 12801 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 12802 rx_09_fifo.rd_addr[8]
|
|
.sym 12806 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 12808 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 12809 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 12813 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 12816 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 12820 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 12827 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 12828 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 12831 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 12837 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 12846 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 12852 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 12858 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 12861 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 12862 rx_09_fifo.rd_addr[8]
|
|
.sym 12863 rx_09_fifo.rd_addr[7]
|
|
.sym 12864 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 12865 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 12866 lvds_clock_$glb_clk
|
|
.sym 12867 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 12869 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 12870 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 12871 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 12872 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 12873 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 12874 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 12875 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 12880 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 12881 rx_09_fifo.wr_addr[6]
|
|
.sym 12882 rx_09_fifo.wr_addr[5]
|
|
.sym 12883 rx_09_fifo.rd_addr[6]
|
|
.sym 12884 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 12885 rx_09_fifo.wr_addr[4]
|
|
.sym 12886 rx_09_fifo.wr_addr[7]
|
|
.sym 12888 rx_09_fifo.wr_addr[3]
|
|
.sym 12889 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 12890 rx_09_fifo.wr_addr[2]
|
|
.sym 12893 w_tx_data_io[6]
|
|
.sym 12894 rx_09_fifo.wr_addr[9]
|
|
.sym 12896 rx_09_fifo.wr_addr[8]
|
|
.sym 12898 w_tx_data_io[5]
|
|
.sym 12899 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 12900 rx_09_fifo.wr_addr[6]
|
|
.sym 12901 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 12902 rx_09_fifo.wr_addr[4]
|
|
.sym 12903 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I1_O
|
|
.sym 12909 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 12911 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 12912 rx_09_fifo.wr_addr[3]
|
|
.sym 12913 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 12914 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3]
|
|
.sym 12916 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2]
|
|
.sym 12917 rx_09_fifo.rd_addr[6]
|
|
.sym 12918 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 12919 rx_09_fifo.rd_addr[7]
|
|
.sym 12921 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 12922 rx_09_fifo.wr_addr[5]
|
|
.sym 12923 rx_09_fifo.rd_addr[5]
|
|
.sym 12924 lvds_rx_09_inst.r_data[5]
|
|
.sym 12926 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 12927 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
|
|
.sym 12930 w_rx_09_fifo_push
|
|
.sym 12933 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
|
|
.sym 12934 lvds_rx_09_inst.r_data[4]
|
|
.sym 12935 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 12936 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 12938 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 12939 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 12942 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 12943 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3]
|
|
.sym 12944 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 12945 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2]
|
|
.sym 12948 rx_09_fifo.rd_addr[7]
|
|
.sym 12949 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 12950 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 12954 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 12955 rx_09_fifo.rd_addr[6]
|
|
.sym 12956 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 12957 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 12960 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
|
|
.sym 12961 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 12962 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 12963 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
|
|
.sym 12967 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 12969 w_rx_09_fifo_push
|
|
.sym 12975 lvds_rx_09_inst.r_data[5]
|
|
.sym 12978 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 12979 rx_09_fifo.wr_addr[3]
|
|
.sym 12980 rx_09_fifo.wr_addr[5]
|
|
.sym 12981 rx_09_fifo.rd_addr[5]
|
|
.sym 12987 lvds_rx_09_inst.r_data[4]
|
|
.sym 12988 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 12989 lvds_clock_$glb_clk
|
|
.sym 12991 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 12992 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 12993 r_tx_data[6]
|
|
.sym 12994 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 12995 r_tx_data[5]
|
|
.sym 12996 r_tx_data[2]
|
|
.sym 12997 r_tx_data[7]
|
|
.sym 12998 r_tx_data[3]
|
|
.sym 13003 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 13004 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 13005 rx_09_fifo.rd_addr[7]
|
|
.sym 13006 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
|
|
.sym 13007 rx_09_fifo.rd_addr[6]
|
|
.sym 13008 rx_09_fifo.rd_addr[8]
|
|
.sym 13009 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 13011 rx_09_fifo.rd_addr[5]
|
|
.sym 13012 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 13013 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 13023 spi_if_ins.w_rx_data[5]
|
|
.sym 13032 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13035 w_rx_24_fifo_full
|
|
.sym 13039 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 13040 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13041 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2]
|
|
.sym 13043 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 13044 w_rx_09_fifo_push
|
|
.sym 13048 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 13049 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 13050 rx_09_fifo.rd_addr[9]
|
|
.sym 13051 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13059 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 13071 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13073 w_rx_09_fifo_push
|
|
.sym 13077 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13078 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13080 w_rx_24_fifo_full
|
|
.sym 13084 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2]
|
|
.sym 13085 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 13086 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 13095 w_rx_09_fifo_push
|
|
.sym 13096 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 13097 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 13098 rx_09_fifo.rd_addr[9]
|
|
.sym 13111 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 13112 lvds_clock_$glb_clk
|
|
.sym 13113 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 13116 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 13117 smi_ctrl_ins.r_fifo_24_pull_1
|
|
.sym 13118 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 13119 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 13120 smi_ctrl_ins.r_fifo_24_pull
|
|
.sym 13121 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 13126 $PACKER_VCC_NET
|
|
.sym 13128 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 13130 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 13131 w_rx_24_fifo_full
|
|
.sym 13132 lvds_rx_24_inst.r_push
|
|
.sym 13136 w_rx_09_fifo_data[4]
|
|
.sym 13139 rx_24_fifo.rd_addr[9]
|
|
.sym 13141 w_cs[1]
|
|
.sym 13144 w_tx_data_smi[1]
|
|
.sym 13145 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13147 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13148 r_tx_data[3]
|
|
.sym 13156 w_rx_09_fifo_empty
|
|
.sym 13158 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
|
|
.sym 13159 rx_24_fifo.rd_addr[6]
|
|
.sym 13160 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
|
|
.sym 13161 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13162 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13164 rx_24_fifo.rd_addr[7]
|
|
.sym 13166 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[3]
|
|
.sym 13168 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 13170 w_rx_24_fifo_empty
|
|
.sym 13173 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I1_O
|
|
.sym 13176 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13177 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13178 w_rx_24_fifo_full
|
|
.sym 13179 rx_24_fifo.wr_addr[7]
|
|
.sym 13184 w_rx_09_fifo_full
|
|
.sym 13185 rx_24_fifo.wr_addr[6]
|
|
.sym 13188 w_rx_24_fifo_empty
|
|
.sym 13194 w_rx_24_fifo_full
|
|
.sym 13206 rx_24_fifo.wr_addr[6]
|
|
.sym 13207 rx_24_fifo.rd_addr[6]
|
|
.sym 13208 rx_24_fifo.wr_addr[7]
|
|
.sym 13209 rx_24_fifo.rd_addr[7]
|
|
.sym 13213 w_rx_09_fifo_empty
|
|
.sym 13218 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13219 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13220 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13221 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13224 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[3]
|
|
.sym 13225 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
|
|
.sym 13226 w_rx_24_fifo_empty
|
|
.sym 13227 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
|
|
.sym 13231 w_rx_09_fifo_full
|
|
.sym 13234 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I1_O
|
|
.sym 13235 r_counter_$glb_clk
|
|
.sym 13236 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 13237 spi_if_ins.r_tx_byte[3]
|
|
.sym 13238 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 13240 spi_if_ins.r_tx_byte[4]
|
|
.sym 13241 spi_if_ins.r_tx_byte[1]
|
|
.sym 13242 spi_if_ins.r_tx_byte[0]
|
|
.sym 13244 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3]
|
|
.sym 13249 w_tx_data_smi[2]
|
|
.sym 13250 w_rx_24_fifo_empty
|
|
.sym 13251 w_rx_09_fifo_data[21]
|
|
.sym 13252 rx_24_fifo.wr_addr[5]
|
|
.sym 13253 r_tx_data_SB_DFFE_Q_E
|
|
.sym 13258 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13259 w_rx_09_fifo_data[7]
|
|
.sym 13261 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 13262 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 13268 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 13271 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 13272 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 13280 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 13281 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 13283 rx_24_fifo.rd_addr[8]
|
|
.sym 13285 rx_24_fifo.rd_addr[5]
|
|
.sym 13287 rx_24_fifo.wr_addr[9]
|
|
.sym 13288 spi_if_ins.w_rx_data[6]
|
|
.sym 13291 rx_24_fifo.rd_addr[4]
|
|
.sym 13295 spi_if_ins.w_rx_data[5]
|
|
.sym 13296 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 13297 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 13298 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 13299 rx_24_fifo.rd_addr[9]
|
|
.sym 13303 rx_24_fifo.wr_addr[8]
|
|
.sym 13305 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 13306 rx_24_fifo.wr_addr[4]
|
|
.sym 13309 rx_24_fifo.wr_addr[5]
|
|
.sym 13323 rx_24_fifo.rd_addr[4]
|
|
.sym 13324 rx_24_fifo.wr_addr[4]
|
|
.sym 13325 rx_24_fifo.wr_addr[5]
|
|
.sym 13326 rx_24_fifo.rd_addr[5]
|
|
.sym 13329 rx_24_fifo.rd_addr[9]
|
|
.sym 13330 rx_24_fifo.wr_addr[8]
|
|
.sym 13331 rx_24_fifo.rd_addr[8]
|
|
.sym 13332 rx_24_fifo.wr_addr[9]
|
|
.sym 13336 spi_if_ins.w_rx_data[6]
|
|
.sym 13338 spi_if_ins.w_rx_data[5]
|
|
.sym 13341 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 13342 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 13343 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 13344 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 13353 spi_if_ins.w_rx_data[6]
|
|
.sym 13355 spi_if_ins.w_rx_data[5]
|
|
.sym 13357 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 13358 r_counter_$glb_clk
|
|
.sym 13359 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 13360 r_tx_data[4]
|
|
.sym 13363 r_tx_data[1]
|
|
.sym 13364 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 13373 rx_24_fifo.rd_addr[5]
|
|
.sym 13375 rx_24_fifo.rd_addr[4]
|
|
.sym 13376 rx_09_fifo.rd_addr[9]
|
|
.sym 13377 rx_24_fifo.rd_addr[6]
|
|
.sym 13379 spi_if_ins.r_tx_byte[3]
|
|
.sym 13383 rx_24_fifo.rd_addr[6]
|
|
.sym 13385 w_tx_data_sys[0]
|
|
.sym 13386 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 13387 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I1_O
|
|
.sym 13388 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 13389 w_cs[2]
|
|
.sym 13392 w_tx_data_io[6]
|
|
.sym 13393 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 13394 w_tx_data_io[5]
|
|
.sym 13401 lvds_rx_24_inst.r_data[27]
|
|
.sym 13402 rx_24_fifo.rd_addr[1]
|
|
.sym 13413 lvds_rx_24_inst.r_data[29]
|
|
.sym 13414 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13416 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 13418 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 13419 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 13427 lvds_rx_24_inst.r_data[26]
|
|
.sym 13431 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 13440 rx_24_fifo.rd_addr[1]
|
|
.sym 13441 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 13442 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 13443 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 13446 lvds_rx_24_inst.r_data[27]
|
|
.sym 13453 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13454 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 13466 lvds_rx_24_inst.r_data[29]
|
|
.sym 13476 lvds_rx_24_inst.r_data[26]
|
|
.sym 13480 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 13481 lvds_clock_$glb_clk
|
|
.sym 13483 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 13487 w_cs[0]
|
|
.sym 13488 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 13489 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 13495 lvds_rx_24_inst.r_data[27]
|
|
.sym 13497 w_rx_24_fifo_data[31]
|
|
.sym 13498 rx_24_fifo.wr_addr[8]
|
|
.sym 13499 rx_24_fifo.rd_addr[8]
|
|
.sym 13501 w_rx_24_fifo_data[29]
|
|
.sym 13502 rx_24_fifo.wr_addr[8]
|
|
.sym 13503 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 13504 rx_24_fifo.wr_addr[5]
|
|
.sym 13507 rx_24_fifo.wr_addr[7]
|
|
.sym 13510 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 13516 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 13525 rx_24_fifo.rd_addr[8]
|
|
.sym 13528 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 13531 w_rx_24_fifo_push
|
|
.sym 13532 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 13533 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 13534 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 13536 lvds_rx_24_inst.r_push
|
|
.sym 13537 w_rx_24_fifo_full
|
|
.sym 13539 w_rx_24_fifo_push
|
|
.sym 13540 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 13543 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 13546 lvds_rx_09_inst.r_push
|
|
.sym 13548 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13550 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 13551 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 13555 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 13571 w_rx_24_fifo_push
|
|
.sym 13572 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13575 w_rx_24_fifo_push
|
|
.sym 13576 w_rx_24_fifo_full
|
|
.sym 13577 rx_24_fifo.rd_addr[8]
|
|
.sym 13578 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 13581 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 13582 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 13583 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 13584 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 13587 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 13588 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 13589 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 13590 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 13593 lvds_rx_09_inst.r_push
|
|
.sym 13601 lvds_rx_24_inst.r_push
|
|
.sym 13604 lvds_clock_$glb_clk
|
|
.sym 13605 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 13607 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I1_O
|
|
.sym 13610 spi_if_ins.state_if_SB_DFFESR_Q_R
|
|
.sym 13611 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 13612 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 13614 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 13619 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 13621 rx_24_fifo.wr_addr[6]
|
|
.sym 13623 rx_24_fifo.wr_addr[7]
|
|
.sym 13624 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 13625 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 13631 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 13632 i_smi_a1$SB_IO_IN
|
|
.sym 13634 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13636 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 13640 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13641 w_cs[1]
|
|
.sym 13658 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 13659 w_cs[0]
|
|
.sym 13660 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13664 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13667 w_lvds_rx_24_d1
|
|
.sym 13670 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13673 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13674 w_lvds_rx_24_d0
|
|
.sym 13675 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 13677 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 13683 w_cs[0]
|
|
.sym 13686 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13687 w_lvds_rx_24_d0
|
|
.sym 13688 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13689 w_lvds_rx_24_d1
|
|
.sym 13700 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 13704 w_lvds_rx_24_d1
|
|
.sym 13705 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13706 w_lvds_rx_24_d0
|
|
.sym 13707 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13716 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13717 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 13719 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13722 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13723 w_lvds_rx_24_d0
|
|
.sym 13724 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13725 w_lvds_rx_24_d1
|
|
.sym 13726 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 13727 lvds_clock_$glb_clk
|
|
.sym 13728 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 13729 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 13730 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 13731 w_load
|
|
.sym 13732 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E
|
|
.sym 13733 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.sym 13734 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 13735 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 13736 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R_SB_LUT4_O_I3[2]
|
|
.sym 13740 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13741 w_ioc[2]
|
|
.sym 13756 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 13760 w_rx_data[2]
|
|
.sym 13764 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 13770 w_cs[0]
|
|
.sym 13778 w_fetch
|
|
.sym 13787 lvds_rx_24_inst.r_data[20]
|
|
.sym 13791 lvds_rx_24_inst.r_data[3]
|
|
.sym 13792 lvds_rx_24_inst.r_data[19]
|
|
.sym 13795 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 13796 w_load
|
|
.sym 13809 w_load
|
|
.sym 13810 w_cs[0]
|
|
.sym 13811 w_fetch
|
|
.sym 13812 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 13828 lvds_rx_24_inst.r_data[20]
|
|
.sym 13833 lvds_rx_24_inst.r_data[3]
|
|
.sym 13841 lvds_rx_24_inst.r_data[19]
|
|
.sym 13849 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 13850 lvds_clock_$glb_clk
|
|
.sym 13852 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 13853 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 13854 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 13855 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O
|
|
.sym 13856 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
|
|
.sym 13859 w_tx_data_io[2]
|
|
.sym 13864 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 13866 w_rx_24_fifo_data[5]
|
|
.sym 13869 $PACKER_GND_NET
|
|
.sym 13874 w_fetch
|
|
.sym 13878 w_tx_data_io[5]
|
|
.sym 13879 w_ioc[4]
|
|
.sym 13881 w_tx_data_sys[0]
|
|
.sym 13883 w_tx_data_io[6]
|
|
.sym 13885 w_rx_24_fifo_data[21]
|
|
.sym 13895 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
|
|
.sym 13897 w_lvds_rx_24_d1
|
|
.sym 13899 w_lvds_rx_24_d0
|
|
.sym 13903 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13905 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.sym 13912 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13915 $PACKER_GND_NET
|
|
.sym 13922 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 13932 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13933 w_lvds_rx_24_d0
|
|
.sym 13934 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 13935 w_lvds_rx_24_d1
|
|
.sym 13938 $PACKER_GND_NET
|
|
.sym 13944 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.sym 13972 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
|
|
.sym 13973 r_counter_$glb_clk
|
|
.sym 13974 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 13976 io_ctrl_ins.pmod_dir_state[2]
|
|
.sym 13979 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3]
|
|
.sym 13980 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 13981 io_ctrl_ins.pmod_dir_state[1]
|
|
.sym 13988 w_ioc[0]
|
|
.sym 13990 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13991 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 13993 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 13995 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 14007 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 14027 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.sym 14033 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 14050 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 14095 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.sym 14096 r_counter_$glb_clk
|
|
.sym 14103 w_tx_data_io[1]
|
|
.sym 14106 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 14113 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 14123 i_smi_a1$SB_IO_IN
|
|
.sym 14126 w_rx_24_fifo_data[4]
|
|
.sym 14139 lvds_rx_24_inst.r_data[10]
|
|
.sym 14142 lvds_rx_24_inst.r_data[2]
|
|
.sym 14143 lvds_rx_24_inst.r_data[12]
|
|
.sym 14147 lvds_rx_24_inst.r_data[11]
|
|
.sym 14149 lvds_rx_24_inst.r_data[13]
|
|
.sym 14172 lvds_rx_24_inst.r_data[12]
|
|
.sym 14180 lvds_rx_24_inst.r_data[11]
|
|
.sym 14192 lvds_rx_24_inst.r_data[13]
|
|
.sym 14211 lvds_rx_24_inst.r_data[2]
|
|
.sym 14215 lvds_rx_24_inst.r_data[10]
|
|
.sym 14218 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 14219 lvds_clock_$glb_clk
|
|
.sym 14233 w_rx_24_fifo_data[14]
|
|
.sym 14237 w_rx_24_fifo_data[13]
|
|
.sym 14239 w_rx_24_fifo_data[6]
|
|
.sym 14241 w_rx_24_fifo_data[15]
|
|
.sym 14344 i_smi_a1$SB_IO_IN
|
|
.sym 14352 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 14388 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 14410 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 14418 i_sck$SB_IO_IN
|
|
.sym 14419 w_smi_data_output[3]
|
|
.sym 14421 i_smi_a3$SB_IO_IN
|
|
.sym 14436 i_smi_a3$SB_IO_IN
|
|
.sym 14437 w_smi_data_output[3]
|
|
.sym 14440 i_sck$SB_IO_IN
|
|
.sym 14445 w_rx_09_fifo_data[30]
|
|
.sym 14446 w_rx_09_fifo_data[28]
|
|
.sym 14448 w_rx_09_fifo_data[29]
|
|
.sym 14449 w_rx_09_fifo_data[31]
|
|
.sym 14476 i_smi_a3$SB_IO_IN
|
|
.sym 14495 lvds_rx_09_inst.r_data[27]
|
|
.sym 14502 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 14515 lvds_rx_09_inst.r_data[26]
|
|
.sym 14531 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 14533 lvds_rx_09_inst.r_data[27]
|
|
.sym 14550 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 14552 lvds_rx_09_inst.r_data[26]
|
|
.sym 14565 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 14566 lvds_clock_$glb_clk
|
|
.sym 14567 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 14573 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 14577 w_smi_data_output[7]
|
|
.sym 14578 w_smi_data_output[4]
|
|
.sym 14579 w_smi_data_output[5]
|
|
.sym 14585 rx_09_fifo.wr_addr[7]
|
|
.sym 14586 rx_09_fifo.wr_addr[3]
|
|
.sym 14587 rx_09_fifo.wr_addr[9]
|
|
.sym 14589 rx_09_fifo.wr_addr[4]
|
|
.sym 14591 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 14592 rx_09_fifo.wr_addr[6]
|
|
.sym 14606 w_rx_09_fifo_data[30]
|
|
.sym 14620 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 14621 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 14633 rx_09_fifo.rd_addr[1]
|
|
.sym 14653 lvds_rx_09_inst.r_data[25]
|
|
.sym 14654 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 14666 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 14690 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 14691 lvds_rx_09_inst.r_data[25]
|
|
.sym 14702 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 14728 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce
|
|
.sym 14729 lvds_clock_$glb_clk
|
|
.sym 14730 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 14732 rx_09_fifo.rd_addr[1]
|
|
.sym 14733 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[2]
|
|
.sym 14734 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[3]
|
|
.sym 14735 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[4]
|
|
.sym 14736 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[5]
|
|
.sym 14737 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[6]
|
|
.sym 14738 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[7]
|
|
.sym 14743 smi_ctrl_ins.soe_and_reset
|
|
.sym 14747 rx_09_fifo.rd_addr[5]
|
|
.sym 14749 lvds_rx_09_inst.r_data[25]
|
|
.sym 14754 rx_09_fifo.rd_addr[7]
|
|
.sym 14756 rx_09_fifo.wr_addr[6]
|
|
.sym 14762 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 14766 rx_09_fifo.rd_addr[1]
|
|
.sym 14779 rx_09_fifo.wr_addr[4]
|
|
.sym 14786 rx_09_fifo.wr_addr[6]
|
|
.sym 14792 rx_09_fifo.wr_addr[2]
|
|
.sym 14793 rx_09_fifo.wr_addr[5]
|
|
.sym 14794 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 14796 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 14798 rx_09_fifo.wr_addr[7]
|
|
.sym 14799 rx_09_fifo.wr_addr[3]
|
|
.sym 14804 $nextpnr_ICESTORM_LC_8$O
|
|
.sym 14807 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 14810 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
|
|
.sym 14813 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 14814 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 14816 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
|
|
.sym 14819 rx_09_fifo.wr_addr[2]
|
|
.sym 14820 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
|
|
.sym 14822 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
|
|
.sym 14824 rx_09_fifo.wr_addr[3]
|
|
.sym 14826 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
|
|
.sym 14828 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
|
|
.sym 14830 rx_09_fifo.wr_addr[4]
|
|
.sym 14832 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
|
|
.sym 14834 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
|
|
.sym 14837 rx_09_fifo.wr_addr[5]
|
|
.sym 14838 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
|
|
.sym 14840 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
|
|
.sym 14842 rx_09_fifo.wr_addr[6]
|
|
.sym 14844 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
|
|
.sym 14846 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 14849 rx_09_fifo.wr_addr[7]
|
|
.sym 14850 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
|
|
.sym 14854 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[8]
|
|
.sym 14855 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[9]
|
|
.sym 14856 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[10]
|
|
.sym 14857 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[3]
|
|
.sym 14858 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[0]
|
|
.sym 14859 w_rx_24_fifo_data[30]
|
|
.sym 14860 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
|
|
.sym 14861 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[3]
|
|
.sym 14867 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 14869 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 14870 w_rx_09_fifo_data[13]
|
|
.sym 14872 rx_09_fifo.rd_addr[8]
|
|
.sym 14873 rx_09_fifo.wr_addr[8]
|
|
.sym 14874 rx_09_fifo.rd_addr[9]
|
|
.sym 14875 rx_09_fifo.rd_addr[1]
|
|
.sym 14878 rx_09_fifo.rd_addr[6]
|
|
.sym 14880 rx_09_fifo.rd_addr[7]
|
|
.sym 14881 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 14882 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 14883 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 14885 rx_09_fifo.rd_addr[6]
|
|
.sym 14886 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 14887 $PACKER_VCC_NET
|
|
.sym 14888 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 14890 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 14895 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 14898 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[3]
|
|
.sym 14899 rx_09_fifo.wr_addr[8]
|
|
.sym 14901 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 14903 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 14904 rx_09_fifo.rd_addr[1]
|
|
.sym 14906 rx_09_fifo.wr_addr[3]
|
|
.sym 14907 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 14912 rx_09_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 14914 rx_09_fifo.wr_addr[9]
|
|
.sym 14920 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[9]
|
|
.sym 14922 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 14927 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9]
|
|
.sym 14930 rx_09_fifo.wr_addr[8]
|
|
.sym 14931 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 14934 rx_09_fifo.wr_addr[9]
|
|
.sym 14937 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9]
|
|
.sym 14940 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 14942 rx_09_fifo.rd_addr[1]
|
|
.sym 14948 rx_09_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 14953 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 14958 rx_09_fifo.wr_addr[9]
|
|
.sym 14959 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[9]
|
|
.sym 14960 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[3]
|
|
.sym 14961 rx_09_fifo.wr_addr[3]
|
|
.sym 14964 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 14972 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 14974 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O
|
|
.sym 14975 lvds_clock_$glb_clk
|
|
.sym 14976 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 14977 smi_ctrl_ins.w_fifo_24_pull_trigger
|
|
.sym 14978 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[1]
|
|
.sym 14979 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[3]
|
|
.sym 14981 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
|
|
.sym 14982 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 14983 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 14984 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 14992 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 14993 w_rx_09_fifo_data[15]
|
|
.sym 14994 rx_24_fifo.rd_addr[7]
|
|
.sym 14997 w_rx_09_fifo_data[14]
|
|
.sym 14999 rx_09_fifo.wr_addr[8]
|
|
.sym 15001 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 15002 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 15004 rx_09_fifo.wr_addr[9]
|
|
.sym 15006 rx_09_fifo.wr_addr[8]
|
|
.sym 15008 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 15009 w_rx_09_fifo_empty
|
|
.sym 15010 smi_ctrl_ins.w_fifo_24_pull_trigger
|
|
.sym 15012 rx_09_fifo.rd_addr[8]
|
|
.sym 15022 rx_09_fifo.wr_addr[8]
|
|
.sym 15024 rx_09_fifo.wr_addr[6]
|
|
.sym 15025 rx_09_fifo.wr_addr[4]
|
|
.sym 15034 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 15037 rx_09_fifo.wr_addr[3]
|
|
.sym 15039 rx_09_fifo.wr_addr[5]
|
|
.sym 15042 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 15044 rx_09_fifo.wr_addr[7]
|
|
.sym 15046 rx_09_fifo.wr_addr[2]
|
|
.sym 15050 $nextpnr_ICESTORM_LC_15$O
|
|
.sym 15052 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 15056 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2]
|
|
.sym 15059 rx_09_fifo.wr_addr[2]
|
|
.sym 15060 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 15062 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3]
|
|
.sym 15064 rx_09_fifo.wr_addr[3]
|
|
.sym 15066 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2]
|
|
.sym 15068 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4]
|
|
.sym 15071 rx_09_fifo.wr_addr[4]
|
|
.sym 15072 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3]
|
|
.sym 15074 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5]
|
|
.sym 15076 rx_09_fifo.wr_addr[5]
|
|
.sym 15078 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4]
|
|
.sym 15080 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6]
|
|
.sym 15082 rx_09_fifo.wr_addr[6]
|
|
.sym 15084 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5]
|
|
.sym 15086 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7]
|
|
.sym 15088 rx_09_fifo.wr_addr[7]
|
|
.sym 15090 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6]
|
|
.sym 15092 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 15094 rx_09_fifo.wr_addr[8]
|
|
.sym 15096 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7]
|
|
.sym 15100 spi_if_ins.r_tx_byte[5]
|
|
.sym 15102 spi_if_ins.r_tx_byte[2]
|
|
.sym 15103 spi_if_ins.r_tx_byte[7]
|
|
.sym 15104 $PACKER_VCC_NET
|
|
.sym 15106 spi_if_ins.r_tx_byte[6]
|
|
.sym 15111 i_smi_a1$SB_IO_IN
|
|
.sym 15113 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 15117 rx_09_fifo.wr_addr[4]
|
|
.sym 15119 rx_09_fifo.wr_addr[9]
|
|
.sym 15120 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 15121 rx_24_fifo.rd_addr[9]
|
|
.sym 15122 rx_09_fifo.wr_addr[7]
|
|
.sym 15125 $PACKER_VCC_NET
|
|
.sym 15126 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 15128 i_glob_clock$SB_IO_IN
|
|
.sym 15130 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 15134 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 15136 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 15141 i_glob_clock$SB_IO_IN
|
|
.sym 15143 w_tx_data_io[5]
|
|
.sym 15144 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 15145 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 15146 w_tx_data_io[6]
|
|
.sym 15150 w_tx_data_io[3]
|
|
.sym 15151 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15153 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 15154 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 15156 rx_09_fifo.rd_addr[5]
|
|
.sym 15159 r_tx_data_SB_DFFE_Q_E
|
|
.sym 15162 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 15164 rx_09_fifo.wr_addr[9]
|
|
.sym 15165 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 15166 w_tx_data_smi[3]
|
|
.sym 15167 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1]
|
|
.sym 15172 w_tx_data_io[7]
|
|
.sym 15173 $nextpnr_ICESTORM_LC_16$I3
|
|
.sym 15175 rx_09_fifo.wr_addr[9]
|
|
.sym 15177 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 15183 $nextpnr_ICESTORM_LC_16$I3
|
|
.sym 15187 w_tx_data_io[6]
|
|
.sym 15189 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15192 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 15193 rx_09_fifo.rd_addr[5]
|
|
.sym 15194 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 15195 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 15198 w_tx_data_io[5]
|
|
.sym 15199 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 15201 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15204 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 15206 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1]
|
|
.sym 15211 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 15212 w_tx_data_io[7]
|
|
.sym 15213 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15216 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15217 w_tx_data_smi[3]
|
|
.sym 15218 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 15219 w_tx_data_io[3]
|
|
.sym 15220 r_tx_data_SB_DFFE_Q_E
|
|
.sym 15221 i_glob_clock$SB_IO_IN
|
|
.sym 15222 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 15223 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 15224 r_tx_data[0]
|
|
.sym 15225 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1]
|
|
.sym 15226 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 15227 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 15228 r_tx_data_SB_DFFE_Q_E
|
|
.sym 15230 w_cs[3]
|
|
.sym 15235 i_glob_clock$SB_IO_IN
|
|
.sym 15236 w_tx_data_io[3]
|
|
.sym 15238 spi_if_ins.r_tx_byte[7]
|
|
.sym 15242 w_rx_09_fifo_data[23]
|
|
.sym 15243 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 15245 w_rx_09_fifo_data[6]
|
|
.sym 15247 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 15251 $PACKER_VCC_NET
|
|
.sym 15252 w_cs[0]
|
|
.sym 15258 w_tx_data_io[7]
|
|
.sym 15268 w_cs[0]
|
|
.sym 15273 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 15275 smi_ctrl_ins.r_fifo_24_pull_1
|
|
.sym 15276 w_rx_24_fifo_empty
|
|
.sym 15278 smi_ctrl_ins.r_fifo_24_pull
|
|
.sym 15280 smi_ctrl_ins.w_fifo_24_pull_trigger
|
|
.sym 15287 w_cs[3]
|
|
.sym 15292 w_cs[2]
|
|
.sym 15295 w_cs[1]
|
|
.sym 15309 w_cs[1]
|
|
.sym 15310 w_cs[3]
|
|
.sym 15311 w_cs[0]
|
|
.sym 15312 w_cs[2]
|
|
.sym 15315 smi_ctrl_ins.r_fifo_24_pull
|
|
.sym 15321 w_cs[0]
|
|
.sym 15322 w_cs[3]
|
|
.sym 15323 w_cs[1]
|
|
.sym 15324 w_cs[2]
|
|
.sym 15328 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 15333 smi_ctrl_ins.w_fifo_24_pull_trigger
|
|
.sym 15339 smi_ctrl_ins.r_fifo_24_pull
|
|
.sym 15341 w_rx_24_fifo_empty
|
|
.sym 15342 smi_ctrl_ins.r_fifo_24_pull_1
|
|
.sym 15344 r_counter_$glb_clk
|
|
.sym 15345 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 15349 r_tx_data_SB_DFFE_Q_E
|
|
.sym 15351 spi_if_ins.w_rx_data[6]
|
|
.sym 15358 rx_24_fifo.wr_addr[4]
|
|
.sym 15360 spi_if_ins.w_rx_data[5]
|
|
.sym 15361 rx_09_fifo.wr_addr[4]
|
|
.sym 15362 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 15364 w_cs[2]
|
|
.sym 15365 w_tx_data_sys[0]
|
|
.sym 15366 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 15369 rx_09_fifo.wr_addr[6]
|
|
.sym 15371 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15372 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 15373 w_tx_data_io[2]
|
|
.sym 15376 r_tx_data_SB_DFFE_Q_E
|
|
.sym 15378 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 15379 $PACKER_VCC_NET
|
|
.sym 15387 r_tx_data[4]
|
|
.sym 15389 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15390 r_tx_data[1]
|
|
.sym 15391 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 15393 r_tx_data[3]
|
|
.sym 15394 w_cs[1]
|
|
.sym 15395 w_tx_data_io[0]
|
|
.sym 15396 r_tx_data[0]
|
|
.sym 15399 w_cs[2]
|
|
.sym 15402 w_cs[3]
|
|
.sym 15405 w_cs[0]
|
|
.sym 15414 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 15415 w_tx_data_smi[0]
|
|
.sym 15420 r_tx_data[3]
|
|
.sym 15426 w_cs[1]
|
|
.sym 15427 w_cs[0]
|
|
.sym 15428 w_cs[2]
|
|
.sym 15429 w_cs[3]
|
|
.sym 15439 r_tx_data[4]
|
|
.sym 15445 r_tx_data[1]
|
|
.sym 15451 r_tx_data[0]
|
|
.sym 15462 w_tx_data_io[0]
|
|
.sym 15463 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 15464 w_tx_data_smi[0]
|
|
.sym 15465 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15466 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 15467 r_counter_$glb_clk
|
|
.sym 15471 w_cs[0]
|
|
.sym 15472 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 15476 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 15479 w_tx_data_io[1]
|
|
.sym 15480 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 15481 w_tx_data_io[0]
|
|
.sym 15483 spi_if_ins.r_tx_byte[0]
|
|
.sym 15485 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 15486 w_rx_09_fifo_data[22]
|
|
.sym 15489 spi_if_ins.r_tx_byte[4]
|
|
.sym 15491 spi_if_ins.r_tx_byte[1]
|
|
.sym 15492 spi_if_ins.w_rx_data[5]
|
|
.sym 15493 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 15494 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15495 rx_24_fifo.wr_addr[5]
|
|
.sym 15498 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 15500 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 15510 i_glob_clock$SB_IO_IN
|
|
.sym 15517 w_tx_data_smi[1]
|
|
.sym 15518 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 15519 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 15521 r_tx_data_SB_DFFE_Q_E
|
|
.sym 15531 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15532 w_tx_data_io[1]
|
|
.sym 15534 w_tx_data_io[4]
|
|
.sym 15539 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 15541 rx_24_fifo.rd_addr[0]
|
|
.sym 15544 w_tx_data_io[4]
|
|
.sym 15546 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15561 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 15562 w_tx_data_io[1]
|
|
.sym 15563 w_tx_data_smi[1]
|
|
.sym 15564 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 15567 rx_24_fifo.rd_addr[0]
|
|
.sym 15568 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 15589 r_tx_data_SB_DFFE_Q_E
|
|
.sym 15590 i_glob_clock$SB_IO_IN
|
|
.sym 15591 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 15592 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
.sym 15593 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
|
|
.sym 15594 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 15596 spi_if_ins.state_if[1]
|
|
.sym 15598 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 15604 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 15612 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 15614 i_glob_clock$SB_IO_IN
|
|
.sym 15616 w_cs[0]
|
|
.sym 15617 $PACKER_VCC_NET
|
|
.sym 15618 $PACKER_VCC_NET
|
|
.sym 15620 w_tx_data_io[4]
|
|
.sym 15626 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 15638 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15639 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15643 w_cs[0]
|
|
.sym 15645 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 15653 spi_if_ins.state_if[1]
|
|
.sym 15661 spi_if_ins.state_if[0]
|
|
.sym 15666 spi_if_ins.state_if[1]
|
|
.sym 15667 spi_if_ins.state_if[0]
|
|
.sym 15668 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15669 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15693 w_cs[0]
|
|
.sym 15696 spi_if_ins.state_if[0]
|
|
.sym 15698 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15699 spi_if_ins.state_if[1]
|
|
.sym 15705 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 15713 r_counter_$glb_clk
|
|
.sym 15715 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[2]
|
|
.sym 15716 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15717 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 15718 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 15719 spi_if_ins.state_if[0]
|
|
.sym 15720 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 15721 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 15722 w_ioc[0]
|
|
.sym 15731 w_rx_data[4]
|
|
.sym 15733 w_rx_data[6]
|
|
.sym 15735 w_rx_data[2]
|
|
.sym 15736 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 15739 $PACKER_VCC_NET
|
|
.sym 15745 w_tx_data_io[7]
|
|
.sym 15748 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15760 spi_if_ins.state_if[1]
|
|
.sym 15761 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 15762 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 15767 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 15768 w_cs[2]
|
|
.sym 15769 w_ioc[2]
|
|
.sym 15770 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15776 spi_if_ins.state_if[0]
|
|
.sym 15777 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15785 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15786 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 15795 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 15796 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 15797 w_cs[2]
|
|
.sym 15798 w_ioc[2]
|
|
.sym 15814 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15821 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 15825 spi_if_ins.state_if[1]
|
|
.sym 15826 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15827 spi_if_ins.state_if[0]
|
|
.sym 15828 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 15835 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 15836 r_counter_$glb_clk
|
|
.sym 15837 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 15838 w_fetch
|
|
.sym 15839 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 15840 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 15841 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 15842 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_I1[0]
|
|
.sym 15843 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 15844 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 15845 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
|
|
.sym 15849 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 15851 w_rx_24_fifo_data[21]
|
|
.sym 15852 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 15853 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 15854 w_ioc[4]
|
|
.sym 15860 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 15861 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 15862 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 15864 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
|
|
.sym 15865 w_tx_data_io[2]
|
|
.sym 15866 w_rx_data[0]
|
|
.sym 15868 w_rx_data[1]
|
|
.sym 15870 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 15872 $PACKER_VCC_NET
|
|
.sym 15873 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 15880 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15881 w_load
|
|
.sym 15883 spi_if_ins.state_if_SB_DFFESR_Q_R
|
|
.sym 15885 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 15886 w_cs[1]
|
|
.sym 15888 w_cs[0]
|
|
.sym 15892 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 15894 w_ioc[0]
|
|
.sym 15895 w_fetch
|
|
.sym 15896 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 15897 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 15902 w_ioc[4]
|
|
.sym 15903 w_fetch
|
|
.sym 15905 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 15906 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 15907 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_I1[0]
|
|
.sym 15909 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 15910 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 15913 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_I1[0]
|
|
.sym 15914 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 15915 w_cs[1]
|
|
.sym 15918 w_cs[1]
|
|
.sym 15919 w_fetch
|
|
.sym 15921 w_load
|
|
.sym 15925 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 15930 w_cs[1]
|
|
.sym 15931 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 15932 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 15933 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 15936 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 15937 w_ioc[4]
|
|
.sym 15938 w_cs[0]
|
|
.sym 15939 w_fetch
|
|
.sym 15942 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 15943 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 15944 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 15948 w_fetch
|
|
.sym 15951 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 15955 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 15956 w_ioc[4]
|
|
.sym 15957 w_ioc[0]
|
|
.sym 15958 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 15959 r_counter_$glb_clk
|
|
.sym 15960 spi_if_ins.state_if_SB_DFFESR_Q_R
|
|
.sym 15961 io_ctrl_ins.debug_mode[1]
|
|
.sym 15962 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 15963 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 15964 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 15965 io_ctrl_ins.debug_mode[0]
|
|
.sym 15966 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 15967 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 15968 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
|
|
.sym 15973 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 15975 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 15976 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 15982 rx_24_fifo.wr_addr[7]
|
|
.sym 15984 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 15985 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 15989 w_ioc[2]
|
|
.sym 15991 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 15995 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 16003 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 16004 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 16005 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 16006 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
|
|
.sym 16007 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 16008 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 16009 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 16011 w_lvds_rx_24_d0_SB_LUT4_I1_O[1]
|
|
.sym 16013 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E
|
|
.sym 16014 w_ioc[0]
|
|
.sym 16015 w_ioc[2]
|
|
.sym 16016 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 16017 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R_SB_LUT4_O_I3[2]
|
|
.sym 16022 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 16027 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 16035 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 16036 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 16037 w_lvds_rx_24_d0_SB_LUT4_I1_O[1]
|
|
.sym 16041 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 16042 w_ioc[2]
|
|
.sym 16043 w_ioc[0]
|
|
.sym 16047 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 16048 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 16049 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 16054 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 16055 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 16056 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 16059 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R_SB_LUT4_O_I3[2]
|
|
.sym 16061 w_ioc[2]
|
|
.sym 16062 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 16079 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 16080 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 16081 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E
|
|
.sym 16082 r_counter_$glb_clk
|
|
.sym 16083 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
|
|
.sym 16084 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 16085 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 16086 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 16088 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 16089 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 16090 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 16091 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 16097 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 16098 w_rx_24_fifo_data[4]
|
|
.sym 16099 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 16100 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 16102 io_ctrl_ins.o_pmod[3]
|
|
.sym 16103 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 16104 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 16107 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 16108 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 16113 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 16114 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 16117 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 16118 $PACKER_VCC_NET
|
|
.sym 16126 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 16127 io_ctrl_ins.o_pmod[2]
|
|
.sym 16131 w_rx_data[2]
|
|
.sym 16133 io_ctrl_ins.debug_mode[1]
|
|
.sym 16134 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 16136 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
|
|
.sym 16139 io_ctrl_ins.pmod_dir_state[1]
|
|
.sym 16140 w_rx_data[1]
|
|
.sym 16142 io_ctrl_ins.pmod_dir_state[2]
|
|
.sym 16145 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 16167 w_rx_data[2]
|
|
.sym 16182 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 16183 io_ctrl_ins.debug_mode[1]
|
|
.sym 16184 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 16185 io_ctrl_ins.pmod_dir_state[1]
|
|
.sym 16188 io_ctrl_ins.pmod_dir_state[2]
|
|
.sym 16189 io_ctrl_ins.o_pmod[2]
|
|
.sym 16190 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 16191 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 16194 w_rx_data[1]
|
|
.sym 16204 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
|
|
.sym 16205 r_counter_$glb_clk
|
|
.sym 16208 i_button_SB_LUT4_I3_O[1]
|
|
.sym 16209 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2]
|
|
.sym 16213 w_tx_data_io[7]
|
|
.sym 16220 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 16221 io_ctrl_ins.o_pmod[2]
|
|
.sym 16225 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 16236 w_tx_data_io[7]
|
|
.sym 16237 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 16241 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 16249 o_led1$SB_IO_OUT
|
|
.sym 16260 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3]
|
|
.sym 16263 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 16266 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2]
|
|
.sym 16268 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 16275 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 16311 o_led1$SB_IO_OUT
|
|
.sym 16312 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 16313 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3]
|
|
.sym 16314 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2]
|
|
.sym 16327 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 16328 r_counter_$glb_clk
|
|
.sym 16329 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 16331 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 16334 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 16344 w_tx_data_io[5]
|
|
.sym 16350 w_tx_data_io[6]
|
|
.sym 16353 o_led1$SB_IO_OUT
|
|
.sym 16354 i_button$SB_IO_IN
|
|
.sym 16361 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 16453 i_config[3]$SB_IO_IN
|
|
.sym 16455 i_button$SB_IO_IN
|
|
.sym 16474 i_config[3]$SB_IO_IN
|
|
.sym 16497 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 16519 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
|
|
.sym 16523 i_smi_a3$SB_IO_IN
|
|
.sym 16553 w_rx_09_fifo_data[31]
|
|
.sym 16554 w_smi_data_output[5]
|
|
.sym 16603 lvds_rx_09_inst.r_data[26]
|
|
.sym 16605 lvds_rx_09_inst.r_data[29]
|
|
.sym 16608 lvds_rx_09_inst.r_data[28]
|
|
.sym 16620 lvds_rx_09_inst.r_data[27]
|
|
.sym 16635 lvds_rx_09_inst.r_data[28]
|
|
.sym 16643 lvds_rx_09_inst.r_data[26]
|
|
.sym 16652 lvds_rx_09_inst.r_data[27]
|
|
.sym 16660 lvds_rx_09_inst.r_data[29]
|
|
.sym 16674 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 16675 lvds_clock_$glb_clk
|
|
.sym 16682 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1]
|
|
.sym 16683 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1]
|
|
.sym 16684 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 16685 smi_ctrl_ins.soe_and_reset
|
|
.sym 16686 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 16687 smi_ctrl_ins.w_fifo_09_pull_trigger
|
|
.sym 16688 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1]
|
|
.sym 16689 w_rx_09_fifo_data[29]
|
|
.sym 16699 w_rx_09_fifo_data[28]
|
|
.sym 16703 lvds_rx_09_inst.r_data[26]
|
|
.sym 16711 w_smi_data_output[4]
|
|
.sym 16715 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 16716 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 16719 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 16721 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
|
|
.sym 16729 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 16734 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2]
|
|
.sym 16736 smi_ctrl_ins.soe_and_reset
|
|
.sym 16738 rx_09_fifo.rd_addr[5]
|
|
.sym 16743 rx_09_fifo.rd_addr[1]
|
|
.sym 16744 rx_09_fifo.wr_addr[7]
|
|
.sym 16747 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1]
|
|
.sym 16758 smi_ctrl_ins.soe_and_reset
|
|
.sym 16769 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 16773 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 16774 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 16776 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
|
|
.sym 16778 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 16779 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 16780 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 16781 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1]
|
|
.sym 16782 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 16784 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1]
|
|
.sym 16785 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0]
|
|
.sym 16786 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 16787 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
|
|
.sym 16788 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2]
|
|
.sym 16799 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 16800 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 16821 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 16822 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 16823 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 16824 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 16827 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0]
|
|
.sym 16828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1]
|
|
.sym 16829 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
|
|
.sym 16830 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 16833 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2]
|
|
.sym 16834 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 16835 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1]
|
|
.sym 16836 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
|
|
.sym 16837 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 16838 smi_ctrl_ins.soe_and_reset
|
|
.sym 16840 w_smi_read_req
|
|
.sym 16841 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 16842 w_rx_09_fifo_empty
|
|
.sym 16843 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
|
|
.sym 16844 smi_ctrl_ins.r_fifo_09_pull_1
|
|
.sym 16845 w_rx_24_fifo_empty
|
|
.sym 16846 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 16847 smi_ctrl_ins.r_fifo_09_pull
|
|
.sym 16850 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 16853 w_rx_09_fifo_data[30]
|
|
.sym 16855 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 16856 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 16857 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 16858 rx_09_fifo.rd_addr[6]
|
|
.sym 16860 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 16866 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 16867 w_rx_24_fifo_empty
|
|
.sym 16868 smi_ctrl_ins.soe_and_reset
|
|
.sym 16869 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 16871 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0]
|
|
.sym 16872 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 16873 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
|
|
.sym 16897 rx_09_fifo.rd_addr[7]
|
|
.sym 16898 rx_09_fifo.rd_addr[1]
|
|
.sym 16899 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 16901 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 16904 rx_09_fifo.rd_addr[5]
|
|
.sym 16906 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 16908 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 16910 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 16911 rx_09_fifo.rd_addr[6]
|
|
.sym 16913 $nextpnr_ICESTORM_LC_3$O
|
|
.sym 16916 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 16919 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 16922 rx_09_fifo.rd_addr[1]
|
|
.sym 16923 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 16925 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 16928 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 16929 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 16931 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[4]
|
|
.sym 16933 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 16935 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 16937 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[5]
|
|
.sym 16940 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 16941 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[4]
|
|
.sym 16943 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[6]
|
|
.sym 16946 rx_09_fifo.rd_addr[5]
|
|
.sym 16947 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[5]
|
|
.sym 16949 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[7]
|
|
.sym 16951 rx_09_fifo.rd_addr[6]
|
|
.sym 16953 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[6]
|
|
.sym 16955 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[8]
|
|
.sym 16957 rx_09_fifo.rd_addr[7]
|
|
.sym 16959 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[7]
|
|
.sym 16960 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 16961 r_counter_$glb_clk
|
|
.sym 16962 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 16965 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 16966 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 16967 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 16968 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 16969 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 16970 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 16980 smi_ctrl_ins.r_fifo_09_pull
|
|
.sym 16981 rx_09_fifo.wr_addr[8]
|
|
.sym 16982 w_smi_read_req
|
|
.sym 16983 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 16984 rx_09_fifo.wr_addr[9]
|
|
.sym 16986 w_rx_09_fifo_empty
|
|
.sym 16987 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 16988 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 16989 w_rx_24_fifo_data[30]
|
|
.sym 16990 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
|
|
.sym 16992 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 16993 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 16994 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 16995 $PACKER_VCC_NET
|
|
.sym 16996 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 16998 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 16999 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[8]
|
|
.sym 17006 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[3]
|
|
.sym 17008 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[4]
|
|
.sym 17009 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[1]
|
|
.sym 17010 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[6]
|
|
.sym 17011 rx_09_fifo.wr_addr[4]
|
|
.sym 17013 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[1]
|
|
.sym 17014 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[2]
|
|
.sym 17015 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[3]
|
|
.sym 17016 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
|
|
.sym 17018 rx_09_fifo.wr_addr[6]
|
|
.sym 17020 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 17022 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 17024 rx_09_fifo.rd_addr[9]
|
|
.sym 17028 rx_09_fifo.wr_addr[2]
|
|
.sym 17029 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 17030 lvds_rx_24_inst.r_data[28]
|
|
.sym 17032 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[0]
|
|
.sym 17035 rx_09_fifo.rd_addr[8]
|
|
.sym 17036 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[9]
|
|
.sym 17039 rx_09_fifo.rd_addr[8]
|
|
.sym 17040 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[8]
|
|
.sym 17042 $nextpnr_ICESTORM_LC_4$I3
|
|
.sym 17044 rx_09_fifo.rd_addr[9]
|
|
.sym 17046 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[9]
|
|
.sym 17052 $nextpnr_ICESTORM_LC_4$I3
|
|
.sym 17055 rx_09_fifo.wr_addr[6]
|
|
.sym 17056 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[6]
|
|
.sym 17057 rx_09_fifo.wr_addr[4]
|
|
.sym 17058 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[4]
|
|
.sym 17061 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 17062 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[2]
|
|
.sym 17063 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[1]
|
|
.sym 17064 rx_09_fifo.wr_addr[2]
|
|
.sym 17069 lvds_rx_24_inst.r_data[28]
|
|
.sym 17073 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[3]
|
|
.sym 17074 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[1]
|
|
.sym 17075 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 17076 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[0]
|
|
.sym 17079 rx_09_fifo.wr_addr[2]
|
|
.sym 17080 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[3]
|
|
.sym 17081 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
|
|
.sym 17082 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 17083 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce
|
|
.sym 17084 lvds_clock_$glb_clk
|
|
.sym 17088 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 17089 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0]
|
|
.sym 17090 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 17091 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 17092 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
|
|
.sym 17093 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
|
|
.sym 17097 rx_24_fifo.rd_addr[4]
|
|
.sym 17099 i_ss$SB_IO_IN
|
|
.sym 17101 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 17102 i_ss$SB_IO_IN
|
|
.sym 17105 $PACKER_VCC_NET
|
|
.sym 17106 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 17110 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 17111 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 17112 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 17113 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
|
|
.sym 17115 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 17116 rx_09_fifo.rd_addr[9]
|
|
.sym 17119 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 17129 rx_09_fifo.rd_addr[1]
|
|
.sym 17130 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 17131 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 17132 rx_09_fifo.wr_addr[7]
|
|
.sym 17133 rx_09_fifo.rd_addr[7]
|
|
.sym 17134 rx_09_fifo.rd_addr[9]
|
|
.sym 17137 w_rx_24_fifo_empty
|
|
.sym 17138 rx_09_fifo.rd_addr[6]
|
|
.sym 17139 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 17141 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 17142 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 17143 smi_ctrl_ins.soe_and_reset
|
|
.sym 17144 w_rx_09_fifo_empty
|
|
.sym 17145 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 17146 rx_09_fifo.wr_addr[9]
|
|
.sym 17147 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 17149 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 17152 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 17153 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 17154 rx_09_fifo.rd_addr[8]
|
|
.sym 17155 rx_09_fifo.wr_addr[8]
|
|
.sym 17156 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 17157 rx_09_fifo.wr_addr[6]
|
|
.sym 17158 rx_09_fifo.wr_addr[4]
|
|
.sym 17161 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 17162 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 17163 w_rx_24_fifo_empty
|
|
.sym 17166 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 17167 rx_09_fifo.rd_addr[1]
|
|
.sym 17172 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 17173 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 17174 rx_09_fifo.rd_addr[7]
|
|
.sym 17175 rx_09_fifo.wr_addr[7]
|
|
.sym 17184 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 17185 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 17186 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 17187 w_rx_09_fifo_empty
|
|
.sym 17191 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 17196 rx_09_fifo.rd_addr[8]
|
|
.sym 17197 rx_09_fifo.wr_addr[6]
|
|
.sym 17198 rx_09_fifo.rd_addr[6]
|
|
.sym 17199 rx_09_fifo.wr_addr[8]
|
|
.sym 17202 rx_09_fifo.rd_addr[9]
|
|
.sym 17203 rx_09_fifo.wr_addr[4]
|
|
.sym 17204 rx_09_fifo.wr_addr[9]
|
|
.sym 17205 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 17206 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 17207 smi_ctrl_ins.soe_and_reset
|
|
.sym 17209 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 17210 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
|
|
.sym 17211 w_cs[3]
|
|
.sym 17212 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1]
|
|
.sym 17213 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 17214 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[3]
|
|
.sym 17215 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0]
|
|
.sym 17216 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 17218 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
|
|
.sym 17220 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 17221 rx_09_fifo.wr_addr[6]
|
|
.sym 17227 spi_if_ins.spi.SCKr[2]
|
|
.sym 17228 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 17233 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 17234 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 17235 w_cs[1]
|
|
.sym 17236 rx_09_fifo.rd_addr[1]
|
|
.sym 17237 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 17238 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 17240 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 17241 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 17242 spi_if_ins.spi.SCKr[1]
|
|
.sym 17243 spi_if_ins.w_rx_data[6]
|
|
.sym 17244 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 17256 r_tx_data[7]
|
|
.sym 17260 r_tx_data[6]
|
|
.sym 17261 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 17262 r_tx_data[5]
|
|
.sym 17263 r_tx_data[2]
|
|
.sym 17286 r_tx_data[5]
|
|
.sym 17295 r_tx_data[2]
|
|
.sym 17302 r_tx_data[7]
|
|
.sym 17320 r_tx_data[6]
|
|
.sym 17329 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 17330 r_counter_$glb_clk
|
|
.sym 17332 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
|
|
.sym 17333 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
|
|
.sym 17334 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 17335 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 17336 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 17337 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 17338 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 17339 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 17340 $PACKER_VCC_NET
|
|
.sym 17347 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 17348 w_rx_09_fifo_pulled_data[31]
|
|
.sym 17349 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 17351 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 17352 spi_if_ins.w_rx_data[5]
|
|
.sym 17353 rx_09_fifo.rd_addr[6]
|
|
.sym 17354 $PACKER_VCC_NET
|
|
.sym 17361 $PACKER_VCC_NET
|
|
.sym 17362 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 17363 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 17365 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
|
|
.sym 17373 i_glob_clock$SB_IO_IN
|
|
.sym 17375 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 17377 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 17378 spi_if_ins.w_rx_data[6]
|
|
.sym 17381 w_tx_data_sys[0]
|
|
.sym 17382 w_cs[2]
|
|
.sym 17383 w_cs[3]
|
|
.sym 17388 spi_if_ins.w_rx_data[5]
|
|
.sym 17389 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 17390 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 17391 r_tx_data_SB_DFFE_Q_E
|
|
.sym 17395 w_cs[1]
|
|
.sym 17396 w_tx_data_io[2]
|
|
.sym 17397 w_tx_data_smi[2]
|
|
.sym 17400 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 17401 w_cs[0]
|
|
.sym 17404 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3]
|
|
.sym 17406 w_cs[2]
|
|
.sym 17407 w_cs[3]
|
|
.sym 17408 w_cs[1]
|
|
.sym 17409 w_cs[0]
|
|
.sym 17412 w_tx_data_sys[0]
|
|
.sym 17413 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3]
|
|
.sym 17414 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 17415 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 17418 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 17419 w_tx_data_smi[2]
|
|
.sym 17420 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 17421 w_tx_data_io[2]
|
|
.sym 17424 spi_if_ins.w_rx_data[6]
|
|
.sym 17425 spi_if_ins.w_rx_data[5]
|
|
.sym 17432 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 17436 w_cs[0]
|
|
.sym 17437 w_cs[2]
|
|
.sym 17438 w_cs[3]
|
|
.sym 17439 w_cs[1]
|
|
.sym 17448 w_cs[3]
|
|
.sym 17452 r_tx_data_SB_DFFE_Q_E
|
|
.sym 17453 i_glob_clock$SB_IO_IN
|
|
.sym 17456 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 17457 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 17460 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 17461 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 17469 rx_09_fifo.wr_addr[8]
|
|
.sym 17477 rx_09_fifo.wr_addr[9]
|
|
.sym 17479 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 17480 w_rx_data[0]
|
|
.sym 17481 spi_if_ins.w_rx_data[6]
|
|
.sym 17482 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 17483 rx_24_fifo.rd_addr[1]
|
|
.sym 17484 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 17485 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 17486 rx_24_fifo.rd_addr[4]
|
|
.sym 17487 rx_24_fifo.rd_addr[5]
|
|
.sym 17489 w_rx_24_fifo_data[30]
|
|
.sym 17498 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 17507 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 17509 r_tx_data_SB_DFFE_Q_E
|
|
.sym 17548 r_tx_data_SB_DFFE_Q_E
|
|
.sym 17562 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 17575 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 17576 r_counter_$glb_clk
|
|
.sym 17579 rx_24_fifo.rd_addr[0]
|
|
.sym 17580 spi_if_ins.r_tx_data_valid
|
|
.sym 17581 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2]
|
|
.sym 17582 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
|
|
.sym 17590 i_glob_clock$SB_IO_IN
|
|
.sym 17594 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 17595 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 17596 i_ss$SB_IO_IN
|
|
.sym 17601 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 17603 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 17604 w_rx_data[2]
|
|
.sym 17605 rx_24_fifo.wr_addr[8]
|
|
.sym 17606 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 17625 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 17628 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
|
|
.sym 17633 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 17637 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 17649 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17664 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 17672 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 17694 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17695 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
|
|
.sym 17698 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 17699 r_counter_$glb_clk
|
|
.sym 17701 w_rx_data[0]
|
|
.sym 17702 w_rx_data[5]
|
|
.sym 17703 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 17704 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 17705 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 17706 w_rx_data[4]
|
|
.sym 17707 w_rx_data[6]
|
|
.sym 17708 w_rx_data[2]
|
|
.sym 17711 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 17714 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17717 rx_24_fifo.wr_addr[9]
|
|
.sym 17720 $PACKER_VCC_NET
|
|
.sym 17721 w_rx_24_fifo_data[28]
|
|
.sym 17726 w_cs[0]
|
|
.sym 17728 rx_24_fifo.rd_addr[1]
|
|
.sym 17730 w_rx_data[6]
|
|
.sym 17732 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 17733 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 17734 w_rx_data[0]
|
|
.sym 17736 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 17744 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 17747 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 17748 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17750 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
.sym 17753 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 17754 spi_if_ins.state_if[0]
|
|
.sym 17756 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17762 spi_if_ins.state_if[1]
|
|
.sym 17770 spi_if_ins.state_if[1]
|
|
.sym 17771 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 17776 spi_if_ins.state_if[1]
|
|
.sym 17777 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 17778 spi_if_ins.state_if[0]
|
|
.sym 17781 spi_if_ins.state_if[0]
|
|
.sym 17783 spi_if_ins.state_if[1]
|
|
.sym 17784 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 17787 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17788 spi_if_ins.state_if[1]
|
|
.sym 17789 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 17790 spi_if_ins.state_if[0]
|
|
.sym 17799 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 17800 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 17801 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17802 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
.sym 17811 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 17812 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17813 spi_if_ins.state_if[1]
|
|
.sym 17814 spi_if_ins.state_if[0]
|
|
.sym 17821 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 17822 r_counter_$glb_clk
|
|
.sym 17824 w_ioc[3]
|
|
.sym 17826 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 17827 w_ioc[2]
|
|
.sym 17828 w_ioc[0]
|
|
.sym 17829 w_ioc[4]
|
|
.sym 17830 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 17831 w_ioc[1]
|
|
.sym 17836 spi_if_ins.w_rx_data[5]
|
|
.sym 17837 w_rx_data[1]
|
|
.sym 17840 spi_if_ins.w_rx_data[4]
|
|
.sym 17841 spi_if_ins.w_rx_data[2]
|
|
.sym 17843 w_rx_data[0]
|
|
.sym 17845 w_rx_data[5]
|
|
.sym 17848 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 17850 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 17854 w_rx_data[4]
|
|
.sym 17855 spi_if_ins.w_rx_data[0]
|
|
.sym 17856 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 17858 w_rx_data[2]
|
|
.sym 17865 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[2]
|
|
.sym 17867 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 17868 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 17869 spi_if_ins.state_if_SB_DFFESR_Q_R
|
|
.sym 17870 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 17871 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 17872 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 17873 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
.sym 17874 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17877 spi_if_ins.state_if[1]
|
|
.sym 17881 w_ioc[3]
|
|
.sym 17885 spi_if_ins.state_if[0]
|
|
.sym 17887 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17892 w_ioc[2]
|
|
.sym 17893 w_ioc[0]
|
|
.sym 17894 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 17895 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17898 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17900 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 17901 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17906 spi_if_ins.state_if[1]
|
|
.sym 17907 spi_if_ins.state_if[0]
|
|
.sym 17910 w_ioc[2]
|
|
.sym 17911 w_ioc[0]
|
|
.sym 17912 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 17916 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 17917 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 17919 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17923 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
.sym 17929 w_ioc[2]
|
|
.sym 17931 w_ioc[3]
|
|
.sym 17935 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 17936 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[2]
|
|
.sym 17937 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 17940 w_ioc[0]
|
|
.sym 17944 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 17945 r_counter_$glb_clk
|
|
.sym 17946 spi_if_ins.state_if_SB_DFFESR_Q_R
|
|
.sym 17947 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 17948 io_ctrl_ins.pmod_dir_state[0]
|
|
.sym 17949 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 17950 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[3]
|
|
.sym 17951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 17952 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 17953 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 17954 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 17960 spi_if_ins.w_rx_data[0]
|
|
.sym 17961 spi_if_ins.state_if_SB_DFFE_Q_E
|
|
.sym 17962 w_ioc[2]
|
|
.sym 17964 spi_if_ins.w_rx_data[3]
|
|
.sym 17968 spi_if_ins.w_rx_data[4]
|
|
.sym 17970 rx_24_fifo.wr_addr[5]
|
|
.sym 17972 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 17973 w_rx_data[0]
|
|
.sym 17974 w_rx_data[7]
|
|
.sym 17975 w_ioc[0]
|
|
.sym 17976 rx_24_fifo.rd_addr[8]
|
|
.sym 17977 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 17978 rx_24_fifo.rd_addr[4]
|
|
.sym 17979 rx_24_fifo.rd_addr[5]
|
|
.sym 17980 w_rx_data[3]
|
|
.sym 17981 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 17988 w_ioc[3]
|
|
.sym 17989 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 17992 w_ioc[0]
|
|
.sym 17993 w_ioc[4]
|
|
.sym 17995 w_ioc[1]
|
|
.sym 17997 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 17999 w_ioc[2]
|
|
.sym 18000 w_ioc[0]
|
|
.sym 18001 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 18005 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18008 spi_if_ins.state_if_SB_DFFESR_Q_R
|
|
.sym 18009 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 18010 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 18015 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 18016 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18017 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 18023 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 18024 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 18027 w_ioc[4]
|
|
.sym 18028 w_ioc[3]
|
|
.sym 18029 w_ioc[1]
|
|
.sym 18030 w_ioc[2]
|
|
.sym 18033 w_ioc[0]
|
|
.sym 18034 w_ioc[4]
|
|
.sym 18035 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 18036 w_ioc[1]
|
|
.sym 18040 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 18041 w_ioc[0]
|
|
.sym 18042 w_ioc[2]
|
|
.sym 18045 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 18048 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18051 w_ioc[4]
|
|
.sym 18052 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 18053 w_ioc[1]
|
|
.sym 18054 w_ioc[0]
|
|
.sym 18057 w_ioc[3]
|
|
.sym 18058 w_ioc[4]
|
|
.sym 18060 w_ioc[1]
|
|
.sym 18063 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 18065 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18066 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 18067 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
|
|
.sym 18068 r_counter_$glb_clk
|
|
.sym 18069 spi_if_ins.state_if_SB_DFFESR_Q_R
|
|
.sym 18070 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 18071 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 18072 io_ctrl_ins.o_pmod[5]
|
|
.sym 18073 i_button_SB_LUT4_I3_O[0]
|
|
.sym 18074 io_ctrl_ins.o_pmod[4]
|
|
.sym 18075 io_ctrl_ins.o_pmod[0]
|
|
.sym 18076 io_ctrl_ins.o_pmod[3]
|
|
.sym 18077 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
|
|
.sym 18084 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 18087 w_rx_data[7]
|
|
.sym 18088 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 18089 w_tx_data_io[4]
|
|
.sym 18092 w_rx_24_fifo_data[22]
|
|
.sym 18093 w_rx_data[3]
|
|
.sym 18094 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 18095 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 18096 w_rx_data[2]
|
|
.sym 18097 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 18098 rx_24_fifo.wr_addr[8]
|
|
.sym 18100 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
|
|
.sym 18101 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 18102 rx_24_fifo.wr_addr[6]
|
|
.sym 18103 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 18104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 18105 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
|
|
.sym 18111 w_rx_data[0]
|
|
.sym 18113 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 18114 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 18115 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 18120 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18121 w_rx_data[1]
|
|
.sym 18122 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O
|
|
.sym 18126 w_rx_data[4]
|
|
.sym 18130 w_rx_data[2]
|
|
.sym 18136 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 18139 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18140 w_rx_data[3]
|
|
.sym 18147 w_rx_data[1]
|
|
.sym 18151 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 18156 w_rx_data[3]
|
|
.sym 18162 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18165 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 18168 w_rx_data[0]
|
|
.sym 18177 w_rx_data[4]
|
|
.sym 18181 w_rx_data[2]
|
|
.sym 18187 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 18188 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 18190 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O
|
|
.sym 18191 r_counter_$glb_clk
|
|
.sym 18192 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 18193 io_ctrl_ins.o_pmod[7]
|
|
.sym 18194 io_ctrl_ins.o_pmod[2]
|
|
.sym 18197 io_ctrl_ins.o_pmod[6]
|
|
.sym 18199 io_ctrl_ins.o_pmod[1]
|
|
.sym 18200 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
|
|
.sym 18207 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 18209 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 18212 rx_24_fifo.wr_addr[9]
|
|
.sym 18219 i_button_SB_LUT4_I3_O[0]
|
|
.sym 18221 rx_24_fifo.rd_addr[1]
|
|
.sym 18225 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 18226 i_config[1]$SB_IO_IN
|
|
.sym 18227 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
|
|
.sym 18234 io_ctrl_ins.debug_mode[1]
|
|
.sym 18235 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 18236 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 18238 io_ctrl_ins.debug_mode[0]
|
|
.sym 18239 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 18240 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 18243 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 18244 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 18247 w_ioc[0]
|
|
.sym 18249 w_rx_data[1]
|
|
.sym 18253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18256 w_rx_data[2]
|
|
.sym 18257 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 18261 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 18269 w_rx_data[2]
|
|
.sym 18273 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 18274 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 18275 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 18276 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 18279 io_ctrl_ins.debug_mode[1]
|
|
.sym 18281 io_ctrl_ins.debug_mode[0]
|
|
.sym 18292 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18298 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 18299 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18300 w_ioc[0]
|
|
.sym 18303 io_ctrl_ins.debug_mode[0]
|
|
.sym 18304 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 18305 io_ctrl_ins.debug_mode[1]
|
|
.sym 18306 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 18310 w_rx_data[1]
|
|
.sym 18313 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 18314 r_counter_$glb_clk
|
|
.sym 18317 w_tx_data_io[5]
|
|
.sym 18321 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0]
|
|
.sym 18322 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
|
|
.sym 18323 w_tx_data_io[6]
|
|
.sym 18328 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 18334 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 18335 $PACKER_VCC_NET
|
|
.sym 18337 w_rx_data[1]
|
|
.sym 18341 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 18347 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 18357 io_ctrl_ins.o_pmod[7]
|
|
.sym 18358 i_button_SB_LUT4_I3_O[1]
|
|
.sym 18360 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 18363 io_ctrl_ins.o_pmod[1]
|
|
.sym 18366 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 18367 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 18371 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 18377 i_button$SB_IO_IN
|
|
.sym 18379 i_button_SB_LUT4_I3_O[0]
|
|
.sym 18384 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 18386 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18396 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 18397 io_ctrl_ins.o_pmod[7]
|
|
.sym 18398 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 18399 i_button$SB_IO_IN
|
|
.sym 18402 io_ctrl_ins.o_pmod[1]
|
|
.sym 18403 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 18404 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 18405 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 18426 i_button_SB_LUT4_I3_O[0]
|
|
.sym 18427 i_button_SB_LUT4_I3_O[1]
|
|
.sym 18436 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 18437 r_counter_$glb_clk
|
|
.sym 18438 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 18451 i_config[3]$SB_IO_IN
|
|
.sym 18455 o_tr_vc1$SB_IO_OUT
|
|
.sym 18458 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 18459 w_rx_24_fifo_data[12]
|
|
.sym 18463 i_config[2]$SB_IO_IN
|
|
.sym 18469 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 18480 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 18481 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 18482 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 18486 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 18495 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 18501 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 18519 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 18521 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 18522 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 18537 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 18538 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 18539 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 18540 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 18559 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 18560 r_counter_$glb_clk
|
|
.sym 18562 i_config[1]$SB_IO_IN
|
|
.sym 18564 i_config[2]$SB_IO_IN
|
|
.sym 18566 rx_24_fifo.rd_addr[4]
|
|
.sym 18572 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 18577 $PACKER_VCC_NET
|
|
.sym 18633 o_led1$SB_IO_OUT
|
|
.sym 18636 w_smi_data_output[4]
|
|
.sym 18638 i_smi_a3$SB_IO_IN
|
|
.sym 18641 i_smi_a3$SB_IO_IN
|
|
.sym 18645 i_smi_a3$SB_IO_IN
|
|
.sym 18651 w_smi_data_output[4]
|
|
.sym 18653 i_smi_a3$SB_IO_IN
|
|
.sym 18662 w_rx_09_fifo_pulled_data[4]
|
|
.sym 18666 w_rx_09_fifo_pulled_data[5]
|
|
.sym 18684 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2]
|
|
.sym 18696 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 18716 w_rx_09_fifo_data[31]
|
|
.sym 18734 w_smi_data_output[5]
|
|
.sym 18738 w_rx_09_fifo_data[31]
|
|
.sym 18745 w_smi_data_output[5]
|
|
.sym 18785 i_smi_soe_se$SB_IO_IN
|
|
.sym 18790 w_rx_09_fifo_pulled_data[6]
|
|
.sym 18794 w_rx_09_fifo_pulled_data[7]
|
|
.sym 18818 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18821 i_smi_soe_se$SB_IO_IN
|
|
.sym 18823 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 18824 rx_09_fifo.rd_addr[9]
|
|
.sym 18827 $PACKER_VCC_NET
|
|
.sym 18833 w_rx_09_fifo_pulled_data[23]
|
|
.sym 18841 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 18844 rx_09_fifo.wr_addr[3]
|
|
.sym 18845 rx_09_fifo.wr_addr[4]
|
|
.sym 18846 rx_09_fifo.wr_addr[2]
|
|
.sym 18849 rx_09_fifo.wr_addr[5]
|
|
.sym 18850 rx_09_fifo.wr_addr[6]
|
|
.sym 18851 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 18853 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 18855 rx_09_fifo.wr_addr[7]
|
|
.sym 18856 i_smi_a3$SB_IO_IN
|
|
.sym 18866 smi_ctrl_ins.soe_and_reset
|
|
.sym 18868 w_rx_09_fifo_empty
|
|
.sym 18869 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 18871 w_rx_09_fifo_pulled_data[5]
|
|
.sym 18872 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 18874 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18875 w_rx_09_fifo_pulled_data[4]
|
|
.sym 18877 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 18879 i_smi_soe_se$SB_IO_IN
|
|
.sym 18880 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 18881 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 18883 w_rx_09_fifo_pulled_data[20]
|
|
.sym 18887 w_rx_09_fifo_pulled_data[7]
|
|
.sym 18888 w_rx_09_fifo_pulled_data[23]
|
|
.sym 18891 w_rx_09_fifo_pulled_data[6]
|
|
.sym 18892 w_rx_09_fifo_pulled_data[22]
|
|
.sym 18895 w_rx_09_fifo_pulled_data[21]
|
|
.sym 18905 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 18906 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 18907 w_rx_09_fifo_pulled_data[22]
|
|
.sym 18908 w_rx_09_fifo_pulled_data[6]
|
|
.sym 18911 w_rx_09_fifo_pulled_data[21]
|
|
.sym 18912 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 18913 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 18914 w_rx_09_fifo_pulled_data[5]
|
|
.sym 18919 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18920 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 18924 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 18925 i_smi_soe_se$SB_IO_IN
|
|
.sym 18929 w_rx_09_fifo_pulled_data[7]
|
|
.sym 18930 w_rx_09_fifo_pulled_data[23]
|
|
.sym 18931 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 18932 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 18935 w_rx_09_fifo_empty
|
|
.sym 18936 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 18938 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 18941 w_rx_09_fifo_pulled_data[20]
|
|
.sym 18942 w_rx_09_fifo_pulled_data[4]
|
|
.sym 18943 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 18944 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 18945 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
|
|
.sym 18946 smi_ctrl_ins.soe_and_reset
|
|
.sym 18949 w_rx_09_fifo_pulled_data[20]
|
|
.sym 18953 w_rx_09_fifo_pulled_data[21]
|
|
.sym 18960 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 18962 rx_09_fifo.rd_addr[5]
|
|
.sym 18963 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 18968 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 18970 smi_ctrl_ins.soe_and_reset
|
|
.sym 18971 $PACKER_VCC_NET
|
|
.sym 18973 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 18974 rx_09_fifo.rd_addr[8]
|
|
.sym 18975 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 18976 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
|
|
.sym 18977 rx_09_fifo.rd_addr[7]
|
|
.sym 18978 w_rx_09_fifo_pulled_data[22]
|
|
.sym 18979 rx_09_fifo.rd_addr[5]
|
|
.sym 18980 i_smi_a3$SB_IO_IN
|
|
.sym 18983 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 18990 rx_09_fifo.wr_addr[8]
|
|
.sym 18991 w_rx_09_fifo_empty
|
|
.sym 18995 smi_ctrl_ins.r_fifo_09_pull
|
|
.sym 18996 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 18998 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 19000 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 19001 rx_09_fifo.wr_addr[7]
|
|
.sym 19002 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[5]
|
|
.sym 19003 smi_ctrl_ins.w_fifo_09_pull_trigger
|
|
.sym 19004 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[7]
|
|
.sym 19006 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 19008 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
|
|
.sym 19010 w_rx_24_fifo_empty
|
|
.sym 19011 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
|
|
.sym 19012 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 19013 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[8]
|
|
.sym 19014 rx_09_fifo.wr_addr[5]
|
|
.sym 19015 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[10]
|
|
.sym 19017 smi_ctrl_ins.r_fifo_09_pull_1
|
|
.sym 19018 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 19020 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[3]
|
|
.sym 19022 w_rx_09_fifo_empty
|
|
.sym 19023 w_rx_24_fifo_empty
|
|
.sym 19028 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[8]
|
|
.sym 19029 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[5]
|
|
.sym 19030 rx_09_fifo.wr_addr[8]
|
|
.sym 19031 rx_09_fifo.wr_addr[5]
|
|
.sym 19034 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
|
|
.sym 19035 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
|
|
.sym 19036 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[3]
|
|
.sym 19037 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[10]
|
|
.sym 19040 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 19041 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 19042 rx_09_fifo.wr_addr[7]
|
|
.sym 19043 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[7]
|
|
.sym 19048 smi_ctrl_ins.r_fifo_09_pull
|
|
.sym 19052 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 19053 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 19054 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 19055 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 19058 smi_ctrl_ins.r_fifo_09_pull
|
|
.sym 19059 smi_ctrl_ins.r_fifo_09_pull_1
|
|
.sym 19060 w_rx_09_fifo_empty
|
|
.sym 19066 smi_ctrl_ins.w_fifo_09_pull_trigger
|
|
.sym 19069 r_counter_$glb_clk
|
|
.sym 19070 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 19072 w_rx_09_fifo_pulled_data[22]
|
|
.sym 19076 w_rx_09_fifo_pulled_data[23]
|
|
.sym 19084 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 19096 $PACKER_VCC_NET
|
|
.sym 19098 w_rx_09_fifo_data[4]
|
|
.sym 19100 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 19101 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 19102 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 19103 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 19104 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 19114 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 19116 i_ss$SB_IO_IN
|
|
.sym 19117 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 19119 i_ss$SB_IO_IN
|
|
.sym 19121 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[1]
|
|
.sym 19123 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 19124 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 19126 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 19132 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 19144 $nextpnr_ICESTORM_LC_14$O
|
|
.sym 19146 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 19150 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 19152 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 19159 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 19160 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 19163 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 19164 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 19166 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 19170 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 19171 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 19177 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 19181 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 19182 i_ss$SB_IO_IN
|
|
.sym 19183 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 19184 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 19187 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 19188 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[1]
|
|
.sym 19189 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 19190 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 19192 i_sck$SB_IO_IN_$glb_clk
|
|
.sym 19193 i_ss$SB_IO_IN
|
|
.sym 19195 w_rx_09_fifo_pulled_data[28]
|
|
.sym 19199 w_rx_09_fifo_pulled_data[29]
|
|
.sym 19204 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 19205 w_rx_data[6]
|
|
.sym 19206 rx_09_fifo.rd_addr[1]
|
|
.sym 19207 rx_09_fifo.rd_addr[9]
|
|
.sym 19210 spi_if_ins.spi.SCKr[1]
|
|
.sym 19214 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 19217 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[1]
|
|
.sym 19219 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0]
|
|
.sym 19220 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19221 w_rx_09_fifo_pulled_data[12]
|
|
.sym 19224 w_rx_09_fifo_pulled_data[23]
|
|
.sym 19225 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 19227 w_rx_09_fifo_data[7]
|
|
.sym 19235 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 19237 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
|
|
.sym 19239 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19240 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19244 spi_if_ins.spi.SCKr[2]
|
|
.sym 19245 w_rx_09_fifo_pulled_data[12]
|
|
.sym 19248 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
|
|
.sym 19252 w_rx_09_fifo_pulled_data[28]
|
|
.sym 19255 $PACKER_VCC_NET
|
|
.sym 19256 spi_if_ins.spi.SCKr[1]
|
|
.sym 19260 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19261 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19264 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 19267 $nextpnr_ICESTORM_LC_12$O
|
|
.sym 19270 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19273 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 19275 $PACKER_VCC_NET
|
|
.sym 19276 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19280 $PACKER_VCC_NET
|
|
.sym 19281 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19283 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 19286 w_rx_09_fifo_pulled_data[28]
|
|
.sym 19287 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 19288 w_rx_09_fifo_pulled_data[12]
|
|
.sym 19289 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 19292 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19298 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19299 $PACKER_VCC_NET
|
|
.sym 19301 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19304 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19305 spi_if_ins.spi.SCKr[1]
|
|
.sym 19306 spi_if_ins.spi.SCKr[2]
|
|
.sym 19307 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19313 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19314 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
|
|
.sym 19315 r_counter_$glb_clk
|
|
.sym 19316 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
|
|
.sym 19318 w_rx_09_fifo_pulled_data[30]
|
|
.sym 19322 w_rx_09_fifo_pulled_data[31]
|
|
.sym 19336 w_rx_09_fifo_data[5]
|
|
.sym 19341 rx_09_fifo.wr_addr[2]
|
|
.sym 19342 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 19343 rx_09_fifo.wr_addr[5]
|
|
.sym 19344 w_rx_09_fifo_pulled_data[14]
|
|
.sym 19345 spi_if_ins.r_tx_byte[3]
|
|
.sym 19346 rx_09_fifo.wr_addr[7]
|
|
.sym 19348 rx_09_fifo.wr_addr[3]
|
|
.sym 19352 w_rx_09_fifo_pulled_data[15]
|
|
.sym 19358 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 19359 w_rx_09_fifo_pulled_data[15]
|
|
.sym 19360 w_rx_09_fifo_pulled_data[14]
|
|
.sym 19361 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1]
|
|
.sym 19362 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19363 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 19364 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
|
|
.sym 19365 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
|
|
.sym 19366 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
|
|
.sym 19367 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 19368 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19369 spi_if_ins.w_rx_data[5]
|
|
.sym 19370 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 19371 w_rx_09_fifo_pulled_data[29]
|
|
.sym 19372 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 19373 w_rx_09_fifo_pulled_data[31]
|
|
.sym 19375 w_rx_09_fifo_pulled_data[30]
|
|
.sym 19376 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 19377 spi_if_ins.w_rx_data[6]
|
|
.sym 19378 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 19379 w_rx_09_fifo_pulled_data[13]
|
|
.sym 19380 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19386 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19387 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[3]
|
|
.sym 19391 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 19392 w_rx_09_fifo_pulled_data[15]
|
|
.sym 19393 w_rx_09_fifo_pulled_data[31]
|
|
.sym 19394 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 19397 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 19398 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 19399 w_rx_09_fifo_pulled_data[13]
|
|
.sym 19400 w_rx_09_fifo_pulled_data[29]
|
|
.sym 19403 spi_if_ins.w_rx_data[5]
|
|
.sym 19404 spi_if_ins.w_rx_data[6]
|
|
.sym 19409 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19410 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 19411 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 19415 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19416 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19417 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
|
|
.sym 19421 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1]
|
|
.sym 19422 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19423 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
|
|
.sym 19424 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19427 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 19428 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 19429 w_rx_09_fifo_pulled_data[14]
|
|
.sym 19430 w_rx_09_fifo_pulled_data[30]
|
|
.sym 19433 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 19434 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[3]
|
|
.sym 19435 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
|
|
.sym 19436 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 19437 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 19438 r_counter_$glb_clk
|
|
.sym 19439 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 19441 w_rx_09_fifo_pulled_data[12]
|
|
.sym 19445 w_rx_09_fifo_pulled_data[13]
|
|
.sym 19456 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 19460 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 19462 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 19464 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 19465 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 19466 rx_09_fifo.rd_addr[8]
|
|
.sym 19467 rx_09_fifo.rd_addr[6]
|
|
.sym 19470 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 19471 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 19472 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 19473 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19474 rx_09_fifo.rd_addr[5]
|
|
.sym 19475 rx_09_fifo.rd_addr[7]
|
|
.sym 19485 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19487 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 19489 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19490 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 19492 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 19493 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19494 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 19496 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 19497 spi_if_ins.r_tx_byte[5]
|
|
.sym 19500 spi_if_ins.r_tx_byte[7]
|
|
.sym 19503 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 19505 spi_if_ins.r_tx_byte[3]
|
|
.sym 19507 spi_if_ins.r_tx_byte[2]
|
|
.sym 19508 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 19511 spi_if_ins.r_tx_byte[6]
|
|
.sym 19514 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 19515 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19516 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 19517 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19520 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19521 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 19523 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 19527 spi_if_ins.r_tx_byte[3]
|
|
.sym 19534 spi_if_ins.r_tx_byte[2]
|
|
.sym 19541 spi_if_ins.r_tx_byte[7]
|
|
.sym 19544 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 19545 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 19546 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 19547 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 19550 spi_if_ins.r_tx_byte[5]
|
|
.sym 19556 spi_if_ins.r_tx_byte[6]
|
|
.sym 19560 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 19561 r_counter_$glb_clk
|
|
.sym 19562 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19564 w_rx_09_fifo_pulled_data[14]
|
|
.sym 19568 w_rx_09_fifo_pulled_data[15]
|
|
.sym 19573 w_rx_data[5]
|
|
.sym 19582 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 19588 $PACKER_VCC_NET
|
|
.sym 19591 $PACKER_VCC_NET
|
|
.sym 19593 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 19595 rx_24_fifo.wr_addr[7]
|
|
.sym 19596 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 19597 rx_24_fifo.wr_addr[6]
|
|
.sym 19606 spi_if_ins.r_tx_data_valid
|
|
.sym 19608 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19613 i_ss$SB_IO_IN
|
|
.sym 19622 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 19626 spi_if_ins.r_tx_byte[4]
|
|
.sym 19628 spi_if_ins.r_tx_byte[1]
|
|
.sym 19630 spi_if_ins.r_tx_byte[0]
|
|
.sym 19646 spi_if_ins.r_tx_byte[4]
|
|
.sym 19649 spi_if_ins.r_tx_data_valid
|
|
.sym 19651 i_ss$SB_IO_IN
|
|
.sym 19667 spi_if_ins.r_tx_byte[1]
|
|
.sym 19676 spi_if_ins.r_tx_byte[0]
|
|
.sym 19683 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 19684 r_counter_$glb_clk
|
|
.sym 19685 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19687 w_rx_24_fifo_pulled_data[4]
|
|
.sym 19691 w_rx_24_fifo_pulled_data[5]
|
|
.sym 19704 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 19706 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
|
|
.sym 19708 rx_09_fifo.rd_addr[1]
|
|
.sym 19714 w_rx_24_fifo_pulled_data[20]
|
|
.sym 19715 w_rx_data[0]
|
|
.sym 19716 w_ioc[2]
|
|
.sym 19720 rx_24_fifo.wr_addr[5]
|
|
.sym 19721 w_rx_24_fifo_pulled_data[21]
|
|
.sym 19728 w_rx_24_fifo_pulled_data[21]
|
|
.sym 19729 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19730 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 19731 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 19732 rx_24_fifo.rd_addr[0]
|
|
.sym 19737 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19739 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 19740 w_rx_24_fifo_pulled_data[20]
|
|
.sym 19744 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
|
|
.sym 19745 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 19752 w_rx_24_fifo_pulled_data[4]
|
|
.sym 19756 w_rx_24_fifo_pulled_data[5]
|
|
.sym 19768 rx_24_fifo.rd_addr[0]
|
|
.sym 19773 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
|
|
.sym 19778 w_rx_24_fifo_pulled_data[21]
|
|
.sym 19779 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 19781 w_rx_24_fifo_pulled_data[5]
|
|
.sym 19784 w_rx_24_fifo_pulled_data[4]
|
|
.sym 19785 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 19786 w_rx_24_fifo_pulled_data[20]
|
|
.sym 19787 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19806 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
|
|
.sym 19807 r_counter_$glb_clk
|
|
.sym 19808 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 19810 w_rx_24_fifo_pulled_data[6]
|
|
.sym 19814 w_rx_24_fifo_pulled_data[7]
|
|
.sym 19821 spi_if_ins.w_rx_data[0]
|
|
.sym 19823 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 19824 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 19827 $PACKER_VCC_NET
|
|
.sym 19829 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 19833 rx_24_fifo.rd_addr[5]
|
|
.sym 19834 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 19835 w_rx_data[4]
|
|
.sym 19837 w_rx_24_fifo_pulled_data[22]
|
|
.sym 19838 rx_24_fifo.rd_addr[4]
|
|
.sym 19840 rx_24_fifo.rd_addr[5]
|
|
.sym 19841 rx_24_fifo.rd_addr[6]
|
|
.sym 19842 rx_24_fifo.rd_addr[6]
|
|
.sym 19843 w_rx_data[5]
|
|
.sym 19844 w_rx_24_fifo_pulled_data[23]
|
|
.sym 19851 w_rx_24_fifo_pulled_data[23]
|
|
.sym 19856 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 19857 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 19859 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19861 spi_if_ins.w_rx_data[6]
|
|
.sym 19863 spi_if_ins.w_rx_data[5]
|
|
.sym 19864 spi_if_ins.w_rx_data[2]
|
|
.sym 19865 spi_if_ins.w_rx_data[4]
|
|
.sym 19866 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19869 spi_if_ins.w_rx_data[0]
|
|
.sym 19871 w_rx_24_fifo_pulled_data[7]
|
|
.sym 19873 w_rx_24_fifo_pulled_data[28]
|
|
.sym 19874 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19875 w_rx_24_fifo_pulled_data[12]
|
|
.sym 19877 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 19879 w_rx_24_fifo_pulled_data[13]
|
|
.sym 19881 w_rx_24_fifo_pulled_data[29]
|
|
.sym 19884 spi_if_ins.w_rx_data[0]
|
|
.sym 19890 spi_if_ins.w_rx_data[5]
|
|
.sym 19895 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 19896 w_rx_24_fifo_pulled_data[23]
|
|
.sym 19897 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19898 w_rx_24_fifo_pulled_data[7]
|
|
.sym 19901 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 19902 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19903 w_rx_24_fifo_pulled_data[28]
|
|
.sym 19904 w_rx_24_fifo_pulled_data[12]
|
|
.sym 19907 w_rx_24_fifo_pulled_data[29]
|
|
.sym 19908 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19909 w_rx_24_fifo_pulled_data[13]
|
|
.sym 19910 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 19916 spi_if_ins.w_rx_data[4]
|
|
.sym 19921 spi_if_ins.w_rx_data[6]
|
|
.sym 19927 spi_if_ins.w_rx_data[2]
|
|
.sym 19929 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 19930 r_counter_$glb_clk
|
|
.sym 19933 w_rx_24_fifo_pulled_data[12]
|
|
.sym 19937 w_rx_24_fifo_pulled_data[13]
|
|
.sym 19947 w_rx_24_fifo_data[30]
|
|
.sym 19948 w_rx_data[7]
|
|
.sym 19949 rx_24_fifo.rd_addr[5]
|
|
.sym 19950 rx_24_fifo.rd_addr[8]
|
|
.sym 19951 rx_24_fifo.rd_addr[1]
|
|
.sym 19952 rx_24_fifo.rd_addr[4]
|
|
.sym 19953 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 19954 w_rx_data[3]
|
|
.sym 19955 rx_24_fifo.rd_addr[7]
|
|
.sym 19956 w_ioc[0]
|
|
.sym 19957 rx_24_fifo.wr_addr[5]
|
|
.sym 19958 w_rx_24_fifo_data[31]
|
|
.sym 19959 w_rx_24_fifo_pulled_data[28]
|
|
.sym 19961 rx_24_fifo.wr_addr[8]
|
|
.sym 19962 rx_24_fifo.rd_addr[8]
|
|
.sym 19963 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 19964 spi_if_ins.w_rx_data[1]
|
|
.sym 19966 spi_if_ins.w_rx_data[2]
|
|
.sym 19967 w_rx_24_fifo_pulled_data[29]
|
|
.sym 19975 spi_if_ins.w_rx_data[4]
|
|
.sym 19977 spi_if_ins.w_rx_data[0]
|
|
.sym 19982 w_rx_24_fifo_pulled_data[6]
|
|
.sym 19984 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 19985 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 19987 spi_if_ins.w_rx_data[3]
|
|
.sym 19990 spi_if_ins.w_rx_data[1]
|
|
.sym 19991 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 19992 spi_if_ins.w_rx_data[2]
|
|
.sym 19994 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 19997 w_rx_24_fifo_pulled_data[22]
|
|
.sym 19999 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 20002 w_rx_24_fifo_pulled_data[15]
|
|
.sym 20004 w_rx_24_fifo_pulled_data[31]
|
|
.sym 20009 spi_if_ins.w_rx_data[3]
|
|
.sym 20018 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 20019 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 20020 w_rx_24_fifo_pulled_data[6]
|
|
.sym 20021 w_rx_24_fifo_pulled_data[22]
|
|
.sym 20026 spi_if_ins.w_rx_data[2]
|
|
.sym 20030 spi_if_ins.w_rx_data[0]
|
|
.sym 20039 spi_if_ins.w_rx_data[4]
|
|
.sym 20042 w_rx_24_fifo_pulled_data[15]
|
|
.sym 20043 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 20044 w_rx_24_fifo_pulled_data[31]
|
|
.sym 20045 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 20050 spi_if_ins.w_rx_data[1]
|
|
.sym 20052 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 20053 r_counter_$glb_clk
|
|
.sym 20056 w_rx_24_fifo_pulled_data[14]
|
|
.sym 20060 w_rx_24_fifo_pulled_data[15]
|
|
.sym 20068 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 20069 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
|
|
.sym 20071 rx_24_fifo.wr_addr[8]
|
|
.sym 20072 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 20073 w_rx_24_fifo_data[20]
|
|
.sym 20074 rx_24_fifo.wr_addr[6]
|
|
.sym 20075 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 20076 rx_24_fifo.wr_addr[9]
|
|
.sym 20080 $PACKER_VCC_NET
|
|
.sym 20081 rx_24_fifo.wr_addr[7]
|
|
.sym 20082 w_rx_24_fifo_pulled_data[30]
|
|
.sym 20083 $PACKER_VCC_NET
|
|
.sym 20084 rx_24_fifo.wr_addr[6]
|
|
.sym 20085 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 20086 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 20087 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 20088 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 20090 w_rx_24_fifo_pulled_data[31]
|
|
.sym 20098 w_rx_24_fifo_pulled_data[30]
|
|
.sym 20100 w_rx_data[3]
|
|
.sym 20104 w_rx_data[0]
|
|
.sym 20106 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 20107 w_rx_data[4]
|
|
.sym 20108 w_rx_data[6]
|
|
.sym 20110 w_rx_data[7]
|
|
.sym 20113 w_rx_24_fifo_pulled_data[14]
|
|
.sym 20114 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
|
|
.sym 20115 w_rx_data[5]
|
|
.sym 20116 io_ctrl_ins.debug_mode[0]
|
|
.sym 20117 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 20121 io_ctrl_ins.pmod_dir_state[0]
|
|
.sym 20122 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 20127 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 20130 w_rx_data[6]
|
|
.sym 20137 w_rx_data[0]
|
|
.sym 20143 w_rx_data[3]
|
|
.sym 20147 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 20148 io_ctrl_ins.pmod_dir_state[0]
|
|
.sym 20149 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 20150 io_ctrl_ins.debug_mode[0]
|
|
.sym 20153 w_rx_24_fifo_pulled_data[30]
|
|
.sym 20154 w_rx_24_fifo_pulled_data[14]
|
|
.sym 20155 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 20156 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 20160 w_rx_data[4]
|
|
.sym 20166 w_rx_data[5]
|
|
.sym 20173 w_rx_data[7]
|
|
.sym 20175 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
|
|
.sym 20176 r_counter_$glb_clk
|
|
.sym 20179 w_rx_24_fifo_pulled_data[28]
|
|
.sym 20183 w_rx_24_fifo_pulled_data[29]
|
|
.sym 20190 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 20192 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 20194 rx_24_fifo.rd_addr[1]
|
|
.sym 20195 rx_24_fifo.rd_addr[0]
|
|
.sym 20196 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 20197 w_rx_24_fifo_data[23]
|
|
.sym 20198 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[3]
|
|
.sym 20200 i_config[1]$SB_IO_IN
|
|
.sym 20205 w_rx_24_fifo_pulled_data[20]
|
|
.sym 20207 w_rx_24_fifo_data[6]
|
|
.sym 20208 rx_24_fifo.wr_addr[5]
|
|
.sym 20210 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 20213 w_rx_24_fifo_pulled_data[21]
|
|
.sym 20221 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 20224 w_rx_data[3]
|
|
.sym 20225 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 20226 w_rx_data[4]
|
|
.sym 20229 io_ctrl_ins.o_pmod[5]
|
|
.sym 20230 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 20233 w_rx_data[0]
|
|
.sym 20234 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 20237 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 20238 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 20240 w_rx_data[5]
|
|
.sym 20245 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 20248 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 20252 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 20254 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 20259 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 20260 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 20267 w_rx_data[5]
|
|
.sym 20270 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 20271 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 20272 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 20273 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 20277 w_rx_data[4]
|
|
.sym 20282 w_rx_data[0]
|
|
.sym 20289 w_rx_data[3]
|
|
.sym 20294 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 20295 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 20296 io_ctrl_ins.o_pmod[5]
|
|
.sym 20297 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 20298 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 20299 r_counter_$glb_clk
|
|
.sym 20302 w_rx_24_fifo_pulled_data[30]
|
|
.sym 20306 w_rx_24_fifo_pulled_data[31]
|
|
.sym 20313 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 20314 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 20315 io_ctrl_ins.o_pmod[0]
|
|
.sym 20317 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 20318 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 20323 io_ctrl_ins.o_pmod[4]
|
|
.sym 20327 w_rx_24_fifo_data[5]
|
|
.sym 20328 w_rx_24_fifo_pulled_data[22]
|
|
.sym 20333 rx_24_fifo.rd_addr[5]
|
|
.sym 20334 rx_24_fifo.rd_addr[6]
|
|
.sym 20336 w_rx_24_fifo_pulled_data[23]
|
|
.sym 20344 w_rx_data[7]
|
|
.sym 20349 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 20351 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 20352 w_rx_data[1]
|
|
.sym 20355 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 20356 w_rx_data[2]
|
|
.sym 20359 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 20369 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 20370 w_rx_data[6]
|
|
.sym 20375 w_rx_data[7]
|
|
.sym 20383 w_rx_data[2]
|
|
.sym 20402 w_rx_data[6]
|
|
.sym 20412 w_rx_data[1]
|
|
.sym 20417 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 20418 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 20419 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 20420 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 20421 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
|
|
.sym 20422 r_counter_$glb_clk
|
|
.sym 20425 w_rx_24_fifo_pulled_data[20]
|
|
.sym 20429 w_rx_24_fifo_pulled_data[21]
|
|
.sym 20436 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 20438 rx_24_fifo.rd_addr[8]
|
|
.sym 20441 rx_24_fifo.rd_addr[5]
|
|
.sym 20443 rx_24_fifo.rd_addr[1]
|
|
.sym 20444 rx_24_fifo.rd_addr[4]
|
|
.sym 20447 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 20455 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 20459 rx_24_fifo.rd_addr[8]
|
|
.sym 20469 io_ctrl_ins.o_pmod[6]
|
|
.sym 20470 i_config[3]$SB_IO_IN
|
|
.sym 20471 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 20472 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
|
|
.sym 20473 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 20475 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 20478 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0]
|
|
.sym 20479 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
|
|
.sym 20480 o_tr_vc1$SB_IO_OUT
|
|
.sym 20483 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 20485 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 20487 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
|
|
.sym 20493 i_config[2]$SB_IO_IN
|
|
.sym 20504 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
|
|
.sym 20505 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
|
|
.sym 20528 i_config[3]$SB_IO_IN
|
|
.sym 20529 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 20530 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 20531 io_ctrl_ins.o_pmod[6]
|
|
.sym 20534 o_tr_vc1$SB_IO_OUT
|
|
.sym 20535 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 20536 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 20537 i_config[2]$SB_IO_IN
|
|
.sym 20541 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0]
|
|
.sym 20542 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
|
|
.sym 20544 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
|
|
.sym 20545 r_counter_$glb_clk
|
|
.sym 20546 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 20548 w_rx_24_fifo_pulled_data[22]
|
|
.sym 20552 w_rx_24_fifo_pulled_data[23]
|
|
.sym 20562 rx_24_fifo.wr_addr[8]
|
|
.sym 20563 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 20566 rx_24_fifo.wr_addr[9]
|
|
.sym 20568 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 20569 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 20570 rx_24_fifo.wr_addr[6]
|
|
.sym 20572 $PACKER_VCC_NET
|
|
.sym 20672 i_config[0]$SB_IO_IN
|
|
.sym 20675 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 20683 rx_24_fifo.rd_addr[0]
|
|
.sym 20685 rx_24_fifo.rd_addr[1]
|
|
.sym 20694 w_rx_24_fifo_data[14]
|
|
.sym 20700 w_rx_24_fifo_data[15]
|
|
.sym 20706 i_config[1]$SB_IO_IN
|
|
.sym 20742 i_config[0]$SB_IO_IN
|
|
.sym 20748 w_smi_data_output[5]
|
|
.sym 20750 i_smi_a3$SB_IO_IN
|
|
.sym 20755 w_smi_data_output[5]
|
|
.sym 20767 i_smi_a3$SB_IO_IN
|
|
.sym 20802 i_sck$SB_IO_IN
|
|
.sym 20812 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 20814 w_rx_09_fifo_data[29]
|
|
.sym 20823 $PACKER_VCC_NET
|
|
.sym 20826 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 20827 rx_09_fifo.wr_addr[5]
|
|
.sym 20829 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 20830 w_rx_09_fifo_data[28]
|
|
.sym 20832 rx_09_fifo.wr_addr[4]
|
|
.sym 20833 rx_09_fifo.wr_addr[3]
|
|
.sym 20837 rx_09_fifo.wr_addr[6]
|
|
.sym 20838 rx_09_fifo.wr_addr[7]
|
|
.sym 20839 rx_09_fifo.wr_addr[8]
|
|
.sym 20840 rx_09_fifo.wr_addr[9]
|
|
.sym 20841 rx_09_fifo.wr_addr[2]
|
|
.sym 20844 i_mosi$SB_IO_IN
|
|
.sym 20862 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 20863 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 20865 rx_09_fifo.wr_addr[2]
|
|
.sym 20866 rx_09_fifo.wr_addr[3]
|
|
.sym 20867 rx_09_fifo.wr_addr[4]
|
|
.sym 20868 rx_09_fifo.wr_addr[5]
|
|
.sym 20869 rx_09_fifo.wr_addr[6]
|
|
.sym 20870 rx_09_fifo.wr_addr[7]
|
|
.sym 20871 rx_09_fifo.wr_addr[8]
|
|
.sym 20872 rx_09_fifo.wr_addr[9]
|
|
.sym 20873 lvds_clock_$glb_clk
|
|
.sym 20874 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 20876 w_rx_09_fifo_data[28]
|
|
.sym 20880 w_rx_09_fifo_data[29]
|
|
.sym 20883 $PACKER_VCC_NET
|
|
.sym 20925 rx_09_fifo.rd_addr[1]
|
|
.sym 20928 rx_09_fifo.rd_addr[8]
|
|
.sym 20940 rx_09_fifo.wr_addr[8]
|
|
.sym 20944 o_miso_$_TBUF__Y_E
|
|
.sym 20955 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 20956 $PACKER_VCC_NET
|
|
.sym 20958 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 20959 rx_09_fifo.rd_addr[5]
|
|
.sym 20963 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 20965 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 20966 rx_09_fifo.rd_addr[9]
|
|
.sym 20967 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 20968 w_rx_09_fifo_data[31]
|
|
.sym 20972 rx_09_fifo.rd_addr[6]
|
|
.sym 20977 w_rx_09_fifo_data[30]
|
|
.sym 20978 rx_09_fifo.rd_addr[1]
|
|
.sym 20980 rx_09_fifo.rd_addr[7]
|
|
.sym 20983 rx_09_fifo.rd_addr[8]
|
|
.sym 21000 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21001 rx_09_fifo.rd_addr[1]
|
|
.sym 21003 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 21004 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 21005 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21006 rx_09_fifo.rd_addr[5]
|
|
.sym 21007 rx_09_fifo.rd_addr[6]
|
|
.sym 21008 rx_09_fifo.rd_addr[7]
|
|
.sym 21009 rx_09_fifo.rd_addr[8]
|
|
.sym 21010 rx_09_fifo.rd_addr[9]
|
|
.sym 21011 r_counter_$glb_clk
|
|
.sym 21012 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21013 $PACKER_VCC_NET
|
|
.sym 21017 w_rx_09_fifo_data[31]
|
|
.sym 21021 w_rx_09_fifo_data[30]
|
|
.sym 21035 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21040 o_miso_$_TBUF__Y_E
|
|
.sym 21055 rx_09_fifo.wr_addr[5]
|
|
.sym 21056 rx_09_fifo.wr_addr[6]
|
|
.sym 21057 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21059 rx_09_fifo.wr_addr[3]
|
|
.sym 21060 rx_09_fifo.wr_addr[4]
|
|
.sym 21061 rx_09_fifo.wr_addr[7]
|
|
.sym 21067 w_rx_09_fifo_data[12]
|
|
.sym 21069 rx_09_fifo.wr_addr[2]
|
|
.sym 21070 rx_09_fifo.wr_addr[8]
|
|
.sym 21072 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21074 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21077 rx_09_fifo.wr_addr[9]
|
|
.sym 21083 $PACKER_VCC_NET
|
|
.sym 21085 w_rx_09_fifo_data[13]
|
|
.sym 21086 spi_if_ins.spi.SCKr[2]
|
|
.sym 21088 spi_if_ins.spi.SCKr[0]
|
|
.sym 21091 spi_if_ins.spi.SCKr[1]
|
|
.sym 21093 o_miso_$_TBUF__Y_E
|
|
.sym 21102 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21103 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21105 rx_09_fifo.wr_addr[2]
|
|
.sym 21106 rx_09_fifo.wr_addr[3]
|
|
.sym 21107 rx_09_fifo.wr_addr[4]
|
|
.sym 21108 rx_09_fifo.wr_addr[5]
|
|
.sym 21109 rx_09_fifo.wr_addr[6]
|
|
.sym 21110 rx_09_fifo.wr_addr[7]
|
|
.sym 21111 rx_09_fifo.wr_addr[8]
|
|
.sym 21112 rx_09_fifo.wr_addr[9]
|
|
.sym 21113 lvds_clock_$glb_clk
|
|
.sym 21114 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21116 w_rx_09_fifo_data[12]
|
|
.sym 21120 w_rx_09_fifo_data[13]
|
|
.sym 21123 $PACKER_VCC_NET
|
|
.sym 21135 w_rx_09_fifo_data[12]
|
|
.sym 21142 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
|
|
.sym 21143 rx_09_fifo.rd_addr[5]
|
|
.sym 21148 rx_09_fifo.rd_addr[7]
|
|
.sym 21157 rx_09_fifo.rd_addr[7]
|
|
.sym 21158 rx_09_fifo.rd_addr[6]
|
|
.sym 21159 rx_09_fifo.rd_addr[5]
|
|
.sym 21161 rx_09_fifo.rd_addr[1]
|
|
.sym 21162 rx_09_fifo.rd_addr[8]
|
|
.sym 21167 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21168 rx_09_fifo.rd_addr[9]
|
|
.sym 21171 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21178 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 21181 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21183 w_rx_09_fifo_data[14]
|
|
.sym 21184 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 21185 $PACKER_VCC_NET
|
|
.sym 21187 w_rx_09_fifo_data[15]
|
|
.sym 21190 spi_if_ins.spi.r_rx_done
|
|
.sym 21195 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
|
|
.sym 21204 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21205 rx_09_fifo.rd_addr[1]
|
|
.sym 21207 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 21208 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 21209 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21210 rx_09_fifo.rd_addr[5]
|
|
.sym 21211 rx_09_fifo.rd_addr[6]
|
|
.sym 21212 rx_09_fifo.rd_addr[7]
|
|
.sym 21213 rx_09_fifo.rd_addr[8]
|
|
.sym 21214 rx_09_fifo.rd_addr[9]
|
|
.sym 21215 r_counter_$glb_clk
|
|
.sym 21216 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21217 $PACKER_VCC_NET
|
|
.sym 21221 w_rx_09_fifo_data[15]
|
|
.sym 21225 w_rx_09_fifo_data[14]
|
|
.sym 21229 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 21234 rx_09_fifo.rd_addr[6]
|
|
.sym 21239 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21247 rx_09_fifo.rd_addr[8]
|
|
.sym 21248 rx_09_fifo.rd_addr[1]
|
|
.sym 21252 rx_09_fifo.rd_addr[9]
|
|
.sym 21258 w_rx_09_fifo_data[5]
|
|
.sym 21260 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21271 $PACKER_VCC_NET
|
|
.sym 21273 w_rx_09_fifo_data[4]
|
|
.sym 21274 rx_09_fifo.wr_addr[6]
|
|
.sym 21275 rx_09_fifo.wr_addr[7]
|
|
.sym 21277 rx_09_fifo.wr_addr[3]
|
|
.sym 21278 rx_09_fifo.wr_addr[2]
|
|
.sym 21279 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21280 rx_09_fifo.wr_addr[4]
|
|
.sym 21282 rx_09_fifo.wr_addr[9]
|
|
.sym 21285 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21287 rx_09_fifo.wr_addr[8]
|
|
.sym 21288 rx_09_fifo.wr_addr[5]
|
|
.sym 21290 int_miso
|
|
.sym 21293 w_rx_09_fifo_data[20]
|
|
.sym 21306 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21307 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21309 rx_09_fifo.wr_addr[2]
|
|
.sym 21310 rx_09_fifo.wr_addr[3]
|
|
.sym 21311 rx_09_fifo.wr_addr[4]
|
|
.sym 21312 rx_09_fifo.wr_addr[5]
|
|
.sym 21313 rx_09_fifo.wr_addr[6]
|
|
.sym 21314 rx_09_fifo.wr_addr[7]
|
|
.sym 21315 rx_09_fifo.wr_addr[8]
|
|
.sym 21316 rx_09_fifo.wr_addr[9]
|
|
.sym 21317 lvds_clock_$glb_clk
|
|
.sym 21318 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21320 w_rx_09_fifo_data[4]
|
|
.sym 21324 w_rx_09_fifo_data[5]
|
|
.sym 21327 $PACKER_VCC_NET
|
|
.sym 21333 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 21334 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 21340 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 21343 i_smi_a3$SB_IO_IN
|
|
.sym 21346 rx_24_fifo.rd_addr[7]
|
|
.sym 21353 rx_09_fifo.wr_addr[8]
|
|
.sym 21354 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 21362 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21363 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 21364 $PACKER_VCC_NET
|
|
.sym 21366 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 21370 rx_09_fifo.rd_addr[5]
|
|
.sym 21371 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21373 w_rx_09_fifo_data[7]
|
|
.sym 21375 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21377 rx_09_fifo.rd_addr[7]
|
|
.sym 21385 rx_09_fifo.rd_addr[8]
|
|
.sym 21386 rx_09_fifo.rd_addr[1]
|
|
.sym 21389 w_rx_09_fifo_data[6]
|
|
.sym 21390 rx_09_fifo.rd_addr[9]
|
|
.sym 21391 rx_09_fifo.rd_addr[6]
|
|
.sym 21392 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 21393 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 21394 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 21395 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 21396 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 21397 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 21398 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 21399 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 21408 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21409 rx_09_fifo.rd_addr[1]
|
|
.sym 21411 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 21412 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 21413 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21414 rx_09_fifo.rd_addr[5]
|
|
.sym 21415 rx_09_fifo.rd_addr[6]
|
|
.sym 21416 rx_09_fifo.rd_addr[7]
|
|
.sym 21417 rx_09_fifo.rd_addr[8]
|
|
.sym 21418 rx_09_fifo.rd_addr[9]
|
|
.sym 21419 r_counter_$glb_clk
|
|
.sym 21420 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21421 $PACKER_VCC_NET
|
|
.sym 21425 w_rx_09_fifo_data[7]
|
|
.sym 21429 w_rx_09_fifo_data[6]
|
|
.sym 21436 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21438 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21444 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 21447 rx_24_fifo.rd_addr[9]
|
|
.sym 21463 rx_09_fifo.wr_addr[7]
|
|
.sym 21465 rx_09_fifo.wr_addr[3]
|
|
.sym 21466 rx_09_fifo.wr_addr[2]
|
|
.sym 21467 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21468 w_rx_09_fifo_data[21]
|
|
.sym 21473 w_rx_09_fifo_data[20]
|
|
.sym 21476 rx_09_fifo.wr_addr[5]
|
|
.sym 21480 rx_09_fifo.wr_addr[8]
|
|
.sym 21482 rx_09_fifo.wr_addr[6]
|
|
.sym 21484 rx_09_fifo.wr_addr[4]
|
|
.sym 21486 rx_09_fifo.wr_addr[9]
|
|
.sym 21489 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21491 $PACKER_VCC_NET
|
|
.sym 21493 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21494 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 21495 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 21496 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 21497 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 21498 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 21499 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 21500 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 21501 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 21510 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21511 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21513 rx_09_fifo.wr_addr[2]
|
|
.sym 21514 rx_09_fifo.wr_addr[3]
|
|
.sym 21515 rx_09_fifo.wr_addr[4]
|
|
.sym 21516 rx_09_fifo.wr_addr[5]
|
|
.sym 21517 rx_09_fifo.wr_addr[6]
|
|
.sym 21518 rx_09_fifo.wr_addr[7]
|
|
.sym 21519 rx_09_fifo.wr_addr[8]
|
|
.sym 21520 rx_09_fifo.wr_addr[9]
|
|
.sym 21521 lvds_clock_$glb_clk
|
|
.sym 21522 rx_09_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21524 w_rx_09_fifo_data[20]
|
|
.sym 21528 w_rx_09_fifo_data[21]
|
|
.sym 21531 $PACKER_VCC_NET
|
|
.sym 21544 w_rx_09_fifo_data[21]
|
|
.sym 21548 w_tx_data_io[3]
|
|
.sym 21554 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 21559 w_rx_09_fifo_data[23]
|
|
.sym 21566 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21568 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21569 rx_09_fifo.rd_addr[1]
|
|
.sym 21570 rx_09_fifo.rd_addr[8]
|
|
.sym 21571 rx_09_fifo.rd_addr[7]
|
|
.sym 21574 rx_09_fifo.rd_addr[9]
|
|
.sym 21575 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21576 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 21577 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 21578 rx_09_fifo.rd_addr[5]
|
|
.sym 21579 rx_09_fifo.rd_addr[6]
|
|
.sym 21582 w_rx_09_fifo_data[23]
|
|
.sym 21586 w_rx_09_fifo_data[22]
|
|
.sym 21593 $PACKER_VCC_NET
|
|
.sym 21597 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 21598 spi_if_ins.w_rx_data[1]
|
|
.sym 21599 spi_if_ins.w_rx_data[2]
|
|
.sym 21600 spi_if_ins.w_rx_data[0]
|
|
.sym 21601 spi_if_ins.w_rx_data[3]
|
|
.sym 21602 spi_if_ins.w_rx_data[5]
|
|
.sym 21603 spi_if_ins.w_rx_data[4]
|
|
.sym 21612 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 21613 rx_09_fifo.rd_addr[1]
|
|
.sym 21615 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 21616 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 21617 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 21618 rx_09_fifo.rd_addr[5]
|
|
.sym 21619 rx_09_fifo.rd_addr[6]
|
|
.sym 21620 rx_09_fifo.rd_addr[7]
|
|
.sym 21621 rx_09_fifo.rd_addr[8]
|
|
.sym 21622 rx_09_fifo.rd_addr[9]
|
|
.sym 21623 r_counter_$glb_clk
|
|
.sym 21624 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21625 $PACKER_VCC_NET
|
|
.sym 21629 w_rx_09_fifo_data[23]
|
|
.sym 21633 w_rx_09_fifo_data[22]
|
|
.sym 21640 rx_09_fifo.rd_addr[9]
|
|
.sym 21651 rx_24_fifo.wr_addr[4]
|
|
.sym 21654 rx_24_fifo.wr_addr[4]
|
|
.sym 21655 spi_if_ins.w_rx_data[5]
|
|
.sym 21659 o_led1$SB_IO_OUT
|
|
.sym 21661 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 21666 rx_24_fifo.wr_addr[4]
|
|
.sym 21668 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21669 rx_24_fifo.wr_addr[5]
|
|
.sym 21672 rx_24_fifo.wr_addr[6]
|
|
.sym 21673 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 21675 rx_24_fifo.wr_addr[8]
|
|
.sym 21677 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 21678 rx_24_fifo.wr_addr[7]
|
|
.sym 21679 $PACKER_VCC_NET
|
|
.sym 21680 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21681 w_rx_24_fifo_data[29]
|
|
.sym 21688 w_rx_24_fifo_data[28]
|
|
.sym 21692 rx_24_fifo.wr_addr[9]
|
|
.sym 21695 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21698 w_rx_data[3]
|
|
.sym 21700 w_rx_data[1]
|
|
.sym 21703 w_rx_data[7]
|
|
.sym 21714 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21715 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21717 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 21718 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 21719 rx_24_fifo.wr_addr[4]
|
|
.sym 21720 rx_24_fifo.wr_addr[5]
|
|
.sym 21721 rx_24_fifo.wr_addr[6]
|
|
.sym 21722 rx_24_fifo.wr_addr[7]
|
|
.sym 21723 rx_24_fifo.wr_addr[8]
|
|
.sym 21724 rx_24_fifo.wr_addr[9]
|
|
.sym 21725 lvds_clock_$glb_clk
|
|
.sym 21726 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21728 w_rx_24_fifo_data[28]
|
|
.sym 21732 w_rx_24_fifo_data[29]
|
|
.sym 21735 $PACKER_VCC_NET
|
|
.sym 21741 rx_24_fifo.wr_addr[8]
|
|
.sym 21743 spi_if_ins.w_rx_data[2]
|
|
.sym 21745 rx_24_fifo.wr_addr[5]
|
|
.sym 21749 w_rx_24_fifo_data[29]
|
|
.sym 21751 spi_if_ins.w_rx_data[1]
|
|
.sym 21753 w_tx_data_io[0]
|
|
.sym 21755 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 21757 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 21760 spi_if_ins.w_rx_data[5]
|
|
.sym 21762 rx_24_fifo.rd_addr[7]
|
|
.sym 21774 w_rx_24_fifo_data[30]
|
|
.sym 21776 rx_24_fifo.rd_addr[1]
|
|
.sym 21777 rx_24_fifo.rd_addr[8]
|
|
.sym 21778 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 21779 rx_24_fifo.rd_addr[4]
|
|
.sym 21780 rx_24_fifo.rd_addr[7]
|
|
.sym 21781 $PACKER_VCC_NET
|
|
.sym 21782 rx_24_fifo.rd_addr[5]
|
|
.sym 21784 rx_24_fifo.rd_addr[6]
|
|
.sym 21788 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 21789 rx_24_fifo.rd_addr[9]
|
|
.sym 21790 w_rx_24_fifo_data[31]
|
|
.sym 21793 rx_24_fifo.rd_addr[0]
|
|
.sym 21795 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21801 o_led0$SB_IO_OUT
|
|
.sym 21804 o_led1$SB_IO_OUT
|
|
.sym 21816 rx_24_fifo.rd_addr[0]
|
|
.sym 21817 rx_24_fifo.rd_addr[1]
|
|
.sym 21819 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 21820 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 21821 rx_24_fifo.rd_addr[4]
|
|
.sym 21822 rx_24_fifo.rd_addr[5]
|
|
.sym 21823 rx_24_fifo.rd_addr[6]
|
|
.sym 21824 rx_24_fifo.rd_addr[7]
|
|
.sym 21825 rx_24_fifo.rd_addr[8]
|
|
.sym 21826 rx_24_fifo.rd_addr[9]
|
|
.sym 21827 r_counter_$glb_clk
|
|
.sym 21828 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21829 $PACKER_VCC_NET
|
|
.sym 21833 w_rx_24_fifo_data[31]
|
|
.sym 21837 w_rx_24_fifo_data[30]
|
|
.sym 21851 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21855 rx_24_fifo.rd_addr[9]
|
|
.sym 21856 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 21861 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 21864 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 21870 rx_24_fifo.wr_addr[6]
|
|
.sym 21873 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21874 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21876 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 21879 w_rx_24_fifo_data[20]
|
|
.sym 21880 rx_24_fifo.wr_addr[9]
|
|
.sym 21883 rx_24_fifo.wr_addr[4]
|
|
.sym 21885 rx_24_fifo.wr_addr[8]
|
|
.sym 21887 rx_24_fifo.wr_addr[5]
|
|
.sym 21888 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21889 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 21890 w_rx_24_fifo_data[21]
|
|
.sym 21899 $PACKER_VCC_NET
|
|
.sym 21900 rx_24_fifo.wr_addr[7]
|
|
.sym 21902 w_tx_data_io[0]
|
|
.sym 21903 w_tx_data_io[3]
|
|
.sym 21904 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
|
|
.sym 21905 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 21906 w_tx_data_io[4]
|
|
.sym 21918 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 21919 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 21921 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 21922 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 21923 rx_24_fifo.wr_addr[4]
|
|
.sym 21924 rx_24_fifo.wr_addr[5]
|
|
.sym 21925 rx_24_fifo.wr_addr[6]
|
|
.sym 21926 rx_24_fifo.wr_addr[7]
|
|
.sym 21927 rx_24_fifo.wr_addr[8]
|
|
.sym 21928 rx_24_fifo.wr_addr[9]
|
|
.sym 21929 lvds_clock_$glb_clk
|
|
.sym 21930 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 21932 w_rx_24_fifo_data[20]
|
|
.sym 21936 w_rx_24_fifo_data[21]
|
|
.sym 21939 $PACKER_VCC_NET
|
|
.sym 21950 w_rx_data[0]
|
|
.sym 21957 w_rx_data[3]
|
|
.sym 21959 w_rx_data[4]
|
|
.sym 21961 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 21964 w_rx_data[6]
|
|
.sym 21967 w_tx_data_io[3]
|
|
.sym 21972 w_rx_24_fifo_data[23]
|
|
.sym 21974 rx_24_fifo.rd_addr[8]
|
|
.sym 21976 rx_24_fifo.rd_addr[4]
|
|
.sym 21978 rx_24_fifo.rd_addr[0]
|
|
.sym 21979 rx_24_fifo.rd_addr[1]
|
|
.sym 21981 rx_24_fifo.rd_addr[6]
|
|
.sym 21982 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 21983 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 21985 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 21986 rx_24_fifo.rd_addr[5]
|
|
.sym 21988 w_rx_24_fifo_data[22]
|
|
.sym 21991 rx_24_fifo.rd_addr[7]
|
|
.sym 21993 rx_24_fifo.rd_addr[9]
|
|
.sym 22001 $PACKER_VCC_NET
|
|
.sym 22004 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 22005 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[2]
|
|
.sym 22006 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
|
|
.sym 22007 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 22008 io_ctrl_ins.rf_pin_state[5]
|
|
.sym 22009 io_ctrl_ins.rf_pin_state[4]
|
|
.sym 22010 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 22011 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 22020 rx_24_fifo.rd_addr[0]
|
|
.sym 22021 rx_24_fifo.rd_addr[1]
|
|
.sym 22023 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 22024 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 22025 rx_24_fifo.rd_addr[4]
|
|
.sym 22026 rx_24_fifo.rd_addr[5]
|
|
.sym 22027 rx_24_fifo.rd_addr[6]
|
|
.sym 22028 rx_24_fifo.rd_addr[7]
|
|
.sym 22029 rx_24_fifo.rd_addr[8]
|
|
.sym 22030 rx_24_fifo.rd_addr[9]
|
|
.sym 22031 r_counter_$glb_clk
|
|
.sym 22032 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 22033 $PACKER_VCC_NET
|
|
.sym 22037 w_rx_24_fifo_data[23]
|
|
.sym 22041 w_rx_24_fifo_data[22]
|
|
.sym 22045 w_rx_24_fifo_data[7]
|
|
.sym 22046 $PACKER_GND_NET
|
|
.sym 22059 o_tr_vc2$SB_IO_OUT
|
|
.sym 22060 rx_24_fifo.wr_addr[4]
|
|
.sym 22061 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 22063 o_led1$SB_IO_OUT
|
|
.sym 22067 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 22069 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 22078 rx_24_fifo.wr_addr[8]
|
|
.sym 22080 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 22082 rx_24_fifo.wr_addr[5]
|
|
.sym 22083 rx_24_fifo.wr_addr[6]
|
|
.sym 22085 rx_24_fifo.wr_addr[4]
|
|
.sym 22086 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 22087 $PACKER_VCC_NET
|
|
.sym 22088 rx_24_fifo.wr_addr[7]
|
|
.sym 22094 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 22095 rx_24_fifo.wr_addr[9]
|
|
.sym 22096 w_rx_24_fifo_data[5]
|
|
.sym 22101 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 22104 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 22105 w_rx_24_fifo_data[4]
|
|
.sym 22107 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 22109 io_ctrl_ins.rf_pin_state[7]
|
|
.sym 22111 io_ctrl_ins.rf_pin_state[6]
|
|
.sym 22113 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 22122 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 22123 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 22125 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 22126 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 22127 rx_24_fifo.wr_addr[4]
|
|
.sym 22128 rx_24_fifo.wr_addr[5]
|
|
.sym 22129 rx_24_fifo.wr_addr[6]
|
|
.sym 22130 rx_24_fifo.wr_addr[7]
|
|
.sym 22131 rx_24_fifo.wr_addr[8]
|
|
.sym 22132 rx_24_fifo.wr_addr[9]
|
|
.sym 22133 lvds_clock_$glb_clk
|
|
.sym 22134 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 22136 w_rx_24_fifo_data[4]
|
|
.sym 22140 w_rx_24_fifo_data[5]
|
|
.sym 22143 $PACKER_VCC_NET
|
|
.sym 22151 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 22159 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 22161 rx_24_fifo.wr_addr[7]
|
|
.sym 22162 rx_24_fifo.rd_addr[9]
|
|
.sym 22165 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 22170 rx_24_fifo.rd_addr[7]
|
|
.sym 22179 rx_24_fifo.rd_addr[9]
|
|
.sym 22180 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 22184 rx_24_fifo.rd_addr[1]
|
|
.sym 22185 w_rx_24_fifo_data[6]
|
|
.sym 22187 rx_24_fifo.rd_addr[4]
|
|
.sym 22189 rx_24_fifo.rd_addr[0]
|
|
.sym 22190 rx_24_fifo.rd_addr[5]
|
|
.sym 22191 rx_24_fifo.rd_addr[8]
|
|
.sym 22192 rx_24_fifo.rd_addr[6]
|
|
.sym 22195 rx_24_fifo.rd_addr[7]
|
|
.sym 22196 w_rx_24_fifo_data[7]
|
|
.sym 22200 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 22203 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 22205 $PACKER_VCC_NET
|
|
.sym 22208 o_tr_vc2$SB_IO_OUT
|
|
.sym 22209 io_ctrl_ins.mixer_en_state
|
|
.sym 22224 rx_24_fifo.rd_addr[0]
|
|
.sym 22225 rx_24_fifo.rd_addr[1]
|
|
.sym 22227 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 22228 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 22229 rx_24_fifo.rd_addr[4]
|
|
.sym 22230 rx_24_fifo.rd_addr[5]
|
|
.sym 22231 rx_24_fifo.rd_addr[6]
|
|
.sym 22232 rx_24_fifo.rd_addr[7]
|
|
.sym 22233 rx_24_fifo.rd_addr[8]
|
|
.sym 22234 rx_24_fifo.rd_addr[9]
|
|
.sym 22235 r_counter_$glb_clk
|
|
.sym 22236 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 22237 $PACKER_VCC_NET
|
|
.sym 22241 w_rx_24_fifo_data[7]
|
|
.sym 22245 w_rx_24_fifo_data[6]
|
|
.sym 22258 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 22260 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 22263 rx_24_fifo.rd_addr[9]
|
|
.sym 22265 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 22267 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 22270 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 22280 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 22282 rx_24_fifo.wr_addr[6]
|
|
.sym 22283 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 22284 rx_24_fifo.wr_addr[8]
|
|
.sym 22285 rx_24_fifo.wr_addr[5]
|
|
.sym 22286 rx_24_fifo.wr_addr[9]
|
|
.sym 22289 rx_24_fifo.wr_addr[4]
|
|
.sym 22290 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 22291 w_rx_24_fifo_data[13]
|
|
.sym 22293 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 22296 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 22299 rx_24_fifo.wr_addr[7]
|
|
.sym 22300 w_rx_24_fifo_data[12]
|
|
.sym 22307 $PACKER_VCC_NET
|
|
.sym 22326 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 22327 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 22329 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 22330 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 22331 rx_24_fifo.wr_addr[4]
|
|
.sym 22332 rx_24_fifo.wr_addr[5]
|
|
.sym 22333 rx_24_fifo.wr_addr[6]
|
|
.sym 22334 rx_24_fifo.wr_addr[7]
|
|
.sym 22335 rx_24_fifo.wr_addr[8]
|
|
.sym 22336 rx_24_fifo.wr_addr[9]
|
|
.sym 22337 lvds_clock_$glb_clk
|
|
.sym 22338 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 22340 w_rx_24_fifo_data[12]
|
|
.sym 22344 w_rx_24_fifo_data[13]
|
|
.sym 22347 $PACKER_VCC_NET
|
|
.sym 22359 w_rx_24_fifo_data[13]
|
|
.sym 22371 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 22372 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 22380 rx_24_fifo.rd_addr[6]
|
|
.sym 22381 rx_24_fifo.rd_addr[5]
|
|
.sym 22382 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 22384 rx_24_fifo.rd_addr[4]
|
|
.sym 22386 rx_24_fifo.rd_addr[0]
|
|
.sym 22388 rx_24_fifo.rd_addr[1]
|
|
.sym 22390 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 22391 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 22395 rx_24_fifo.rd_addr[8]
|
|
.sym 22396 w_rx_24_fifo_data[14]
|
|
.sym 22399 rx_24_fifo.rd_addr[7]
|
|
.sym 22401 rx_24_fifo.rd_addr[9]
|
|
.sym 22402 w_rx_24_fifo_data[15]
|
|
.sym 22409 $PACKER_VCC_NET
|
|
.sym 22424 rx_24_fifo.rd_addr[0]
|
|
.sym 22425 rx_24_fifo.rd_addr[1]
|
|
.sym 22427 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 22428 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 22429 rx_24_fifo.rd_addr[4]
|
|
.sym 22430 rx_24_fifo.rd_addr[5]
|
|
.sym 22431 rx_24_fifo.rd_addr[6]
|
|
.sym 22432 rx_24_fifo.rd_addr[7]
|
|
.sym 22433 rx_24_fifo.rd_addr[8]
|
|
.sym 22434 rx_24_fifo.rd_addr[9]
|
|
.sym 22435 r_counter_$glb_clk
|
|
.sym 22436 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O
|
|
.sym 22437 $PACKER_VCC_NET
|
|
.sym 22441 w_rx_24_fifo_data[15]
|
|
.sym 22445 w_rx_24_fifo_data[14]
|
|
.sym 22487 o_led1$SB_IO_OUT
|
|
.sym 22498 o_led1$SB_IO_OUT
|
|
.sym 22517 int_miso
|
|
.sym 22519 o_miso_$_TBUF__Y_E
|
|
.sym 22537 int_miso
|
|
.sym 22540 o_miso_$_TBUF__Y_E
|
|
.sym 22553 int_miso
|
|
.sym 22554 i_mosi$SB_IO_IN
|
|
.sym 22563 i_mosi$SB_IO_IN
|
|
.sym 22666 i_sck$SB_IO_IN
|
|
.sym 22668 i_ss$SB_IO_IN
|
|
.sym 22681 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 22698 i_ss$SB_IO_IN
|
|
.sym 22724 i_ss$SB_IO_IN
|
|
.sym 22729 i_sck$SB_IO_IN
|
|
.sym 22733 i_ss$SB_IO_IN
|
|
.sym 22858 spi_if_ins.spi.SCKr[2]
|
|
.sym 22962 w_rx_data[7]
|
|
.sym 22976 i_ss$SB_IO_IN
|
|
.sym 22998 spi_if_ins.spi.SCKr[1]
|
|
.sym 23002 i_ss$SB_IO_IN
|
|
.sym 23006 i_sck$SB_IO_IN
|
|
.sym 23019 spi_if_ins.spi.SCKr[0]
|
|
.sym 23029 spi_if_ins.spi.SCKr[1]
|
|
.sym 23040 i_sck$SB_IO_IN
|
|
.sym 23058 spi_if_ins.spi.SCKr[0]
|
|
.sym 23071 i_ss$SB_IO_IN
|
|
.sym 23073 r_counter_$glb_clk
|
|
.sym 23078 spi_if_ins.spi.r2_rx_done
|
|
.sym 23110 o_miso_$_TBUF__Y_E
|
|
.sym 23120 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 23121 spi_if_ins.spi.SCKr[1]
|
|
.sym 23124 spi_if_ins.spi.SCKr[2]
|
|
.sym 23127 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 23131 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 23136 i_ss$SB_IO_IN
|
|
.sym 23161 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 23191 spi_if_ins.spi.SCKr[1]
|
|
.sym 23192 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 23193 spi_if_ins.spi.SCKr[2]
|
|
.sym 23195 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
|
|
.sym 23196 i_sck$SB_IO_IN_$glb_clk
|
|
.sym 23197 i_ss$SB_IO_IN
|
|
.sym 23198 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 23202 spi_if_ins.spi.r3_rx_done
|
|
.sym 23208 rx_24_fifo.rd_addr[9]
|
|
.sym 23224 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 23227 i_ss$SB_IO_IN
|
|
.sym 23231 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 23232 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 23242 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 23245 w_rx_09_fifo_data[20]
|
|
.sym 23250 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
|
|
.sym 23254 spi_if_ins.r_tx_byte[7]
|
|
.sym 23269 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 23272 spi_if_ins.r_tx_byte[7]
|
|
.sym 23273 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 23275 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 23291 w_rx_09_fifo_data[20]
|
|
.sym 23318 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
|
|
.sym 23319 r_counter_$glb_clk
|
|
.sym 23333 i_glob_clock$SB_IO_IN
|
|
.sym 23342 spi_if_ins.r_tx_byte[7]
|
|
.sym 23363 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23364 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 23367 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 23373 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 23378 i_mosi$SB_IO_IN
|
|
.sym 23380 o_miso_$_TBUF__Y_E
|
|
.sym 23386 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 23387 i_ss$SB_IO_IN
|
|
.sym 23390 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 23392 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 23398 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 23404 i_mosi$SB_IO_IN
|
|
.sym 23408 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 23413 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23421 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 23428 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 23431 i_ss$SB_IO_IN
|
|
.sym 23432 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 23437 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 23441 o_miso_$_TBUF__Y_E
|
|
.sym 23442 i_sck$SB_IO_IN_$glb_clk
|
|
.sym 23469 spi_if_ins.w_rx_data[5]
|
|
.sym 23471 spi_if_ins.w_rx_data[4]
|
|
.sym 23475 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 23479 spi_if_ins.w_rx_data[2]
|
|
.sym 23486 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23487 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 23488 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 23490 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 23492 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 23493 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 23497 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 23512 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 23516 i_mosi$SB_IO_IN
|
|
.sym 23518 i_mosi$SB_IO_IN
|
|
.sym 23524 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 23530 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 23536 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 23543 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 23550 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 23555 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 23560 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 23564 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
|
|
.sym 23565 i_sck$SB_IO_IN_$glb_clk
|
|
.sym 23568 r_counter
|
|
.sym 23577 o_led0$SB_IO_OUT
|
|
.sym 23585 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 23591 spi_if_ins.w_rx_data[0]
|
|
.sym 23593 spi_if_ins.w_rx_data[3]
|
|
.sym 23597 spi_if_ins.w_rx_data[4]
|
|
.sym 23608 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 23610 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 23612 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 23613 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 23617 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 23622 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 23623 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 23635 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 23650 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 23655 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 23659 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 23667 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 23671 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 23677 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 23684 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 23687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 23688 r_counter_$glb_clk
|
|
.sym 23702 i_glob_clock$SB_IO_IN
|
|
.sym 23716 w_rx_data[7]
|
|
.sym 23719 i_glob_clock$SB_IO_IN
|
|
.sym 23722 w_rx_data[3]
|
|
.sym 23732 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 23733 spi_if_ins.w_rx_data[1]
|
|
.sym 23742 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 23744 spi_if_ins.w_rx_data[3]
|
|
.sym 23764 spi_if_ins.w_rx_data[3]
|
|
.sym 23776 spi_if_ins.w_rx_data[1]
|
|
.sym 23794 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 23810 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 23811 r_counter_$glb_clk
|
|
.sym 23825 w_rx_data[3]
|
|
.sym 23842 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 23846 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 23848 $PACKER_VCC_NET
|
|
.sym 23855 w_rx_data[0]
|
|
.sym 23864 w_rx_data[1]
|
|
.sym 23872 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
|
|
.sym 23893 w_rx_data[0]
|
|
.sym 23914 w_rx_data[1]
|
|
.sym 23933 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
|
|
.sym 23934 r_counter_$glb_clk
|
|
.sym 23935 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 23940 $PACKER_GND_NET
|
|
.sym 23954 rx_24_fifo.mem_i.0.0.0_WCLKE
|
|
.sym 23961 w_rx_data[5]
|
|
.sym 23965 o_led1$SB_IO_OUT
|
|
.sym 23971 w_rx_data[0]
|
|
.sym 23977 i_config[0]$SB_IO_IN
|
|
.sym 23978 o_led0$SB_IO_OUT
|
|
.sym 23980 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 23983 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 23984 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 23986 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[2]
|
|
.sym 23987 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
|
|
.sym 23988 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 23993 i_config[1]$SB_IO_IN
|
|
.sym 23994 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 23995 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 23997 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 24000 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 24002 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24003 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
|
|
.sym 24006 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 24007 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[3]
|
|
.sym 24008 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 24010 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 24011 o_led0$SB_IO_OUT
|
|
.sym 24012 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[2]
|
|
.sym 24013 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[3]
|
|
.sym 24016 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 24017 i_config[0]$SB_IO_IN
|
|
.sym 24018 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 24019 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 24022 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24023 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 24024 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 24025 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 24028 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 24029 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24030 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 24031 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 24034 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 24035 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
|
|
.sym 24036 i_config[1]$SB_IO_IN
|
|
.sym 24037 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
|
|
.sym 24056 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 24057 r_counter_$glb_clk
|
|
.sym 24058 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
|
|
.sym 24060 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1]
|
|
.sym 24061 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2]
|
|
.sym 24062 lvds_rx_24_inst.r_phase_count[1]
|
|
.sym 24063 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 24064 lvds_rx_24_inst.r_phase_count[0]
|
|
.sym 24065 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 24066 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 24071 i_config[0]$SB_IO_IN
|
|
.sym 24076 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 24085 io_ctrl_ins.mixer_en_state
|
|
.sym 24091 o_tr_vc1$SB_IO_OUT
|
|
.sym 24101 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 24102 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 24104 io_ctrl_ins.o_pmod[3]
|
|
.sym 24111 io_ctrl_ins.mixer_en_state
|
|
.sym 24113 w_rx_data[3]
|
|
.sym 24115 w_rx_data[4]
|
|
.sym 24116 io_ctrl_ins.o_pmod[4]
|
|
.sym 24117 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 24118 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 24120 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 24121 w_rx_data[5]
|
|
.sym 24122 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 24123 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 24124 o_tr_vc2$SB_IO_OUT
|
|
.sym 24126 io_ctrl_ins.o_pmod[0]
|
|
.sym 24128 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 24131 w_rx_data[0]
|
|
.sym 24133 w_rx_data[3]
|
|
.sym 24139 io_ctrl_ins.o_pmod[0]
|
|
.sym 24140 io_ctrl_ins.mixer_en_state
|
|
.sym 24141 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 24142 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 24145 io_ctrl_ins.o_pmod[4]
|
|
.sym 24146 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 24147 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 24148 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 24151 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 24152 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 24153 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 24154 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 24158 w_rx_data[5]
|
|
.sym 24166 w_rx_data[4]
|
|
.sym 24171 w_rx_data[0]
|
|
.sym 24175 o_tr_vc2$SB_IO_OUT
|
|
.sym 24176 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 24177 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 24178 io_ctrl_ins.o_pmod[3]
|
|
.sym 24179 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 24180 r_counter_$glb_clk
|
|
.sym 24182 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 24184 o_tr_vc1$SB_IO_OUT
|
|
.sym 24186 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 24188 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 24195 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 24198 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 24200 io_ctrl_ins.o_pmod[3]
|
|
.sym 24215 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 24232 w_rx_data[6]
|
|
.sym 24234 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 24246 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24247 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 24248 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 24249 w_rx_data[7]
|
|
.sym 24254 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24262 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 24263 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24264 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24265 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 24274 w_rx_data[7]
|
|
.sym 24287 w_rx_data[6]
|
|
.sym 24298 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 24299 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24300 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24301 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 24302 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
|
|
.sym 24303 r_counter_$glb_clk
|
|
.sym 24326 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 24328 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 24340 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24346 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 24347 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24364 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24371 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24372 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24373 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 24374 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 24375 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 24379 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24380 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 24381 io_ctrl_ins.rf_pin_state[3]
|
|
.sym 24382 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24385 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 24386 io_ctrl_ins.rf_pin_state[0]
|
|
.sym 24387 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 24388 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 24425 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 24426 r_counter_$glb_clk
|
|
.sym 24440 o_tr_vc2$SB_IO_OUT
|
|
.sym 24453 o_led1$SB_IO_OUT
|
|
.sym 24460 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 24596 o_led0$SB_IO_OUT
|
|
.sym 24611 o_led0$SB_IO_OUT
|
|
.sym 24621 i_smi_a3$SB_IO_IN
|
|
.sym 25107 w_smi_read_req
|
|
.sym 25327 spi_if_ins.spi.r_rx_done
|
|
.sym 25368 spi_if_ins.spi.r_rx_done
|
|
.sym 25397 r_counter_$glb_clk
|
|
.sym 25483 spi_if_ins.spi.r2_rx_done
|
|
.sym 25492 spi_if_ins.spi.r3_rx_done
|
|
.sym 25505 spi_if_ins.spi.r3_rx_done
|
|
.sym 25507 spi_if_ins.spi.r2_rx_done
|
|
.sym 25531 spi_if_ins.spi.r2_rx_done
|
|
.sym 25552 r_counter_$glb_clk
|
|
.sym 25562 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 25711 i_glob_clock$SB_IO_IN
|
|
.sym 25876 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 25878 i_glob_clock$SB_IO_IN
|
|
.sym 25946 r_counter
|
|
.sym 25962 i_glob_clock$SB_IO_IN
|
|
.sym 25977 r_counter
|
|
.sym 26017 i_glob_clock$SB_IO_IN
|
|
.sym 26558 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1]
|
|
.sym 26559 $PACKER_VCC_NET
|
|
.sym 26560 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 26561 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 26567 $PACKER_VCC_NET
|
|
.sym 26568 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 26570 lvds_rx_24_inst.r_phase_count[0]
|
|
.sym 26571 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 26574 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 26575 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2]
|
|
.sym 26580 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 26582 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 26584 lvds_rx_24_inst.r_phase_count[1]
|
|
.sym 26585 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 26589 $nextpnr_ICESTORM_LC_5$O
|
|
.sym 26592 lvds_rx_24_inst.r_phase_count[0]
|
|
.sym 26595 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2]
|
|
.sym 26597 lvds_rx_24_inst.r_phase_count[1]
|
|
.sym 26598 $PACKER_VCC_NET
|
|
.sym 26599 lvds_rx_24_inst.r_phase_count[0]
|
|
.sym 26602 $PACKER_VCC_NET
|
|
.sym 26603 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 26605 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2]
|
|
.sym 26608 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 26614 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 26615 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 26616 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 26617 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 26622 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 26626 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 26627 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 26628 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2]
|
|
.sym 26629 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 26632 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
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.sym 26633 lvds_rx_24_inst.o_debug_state[1]
|
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.sym 26634 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1]
|
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.sym 26635 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 26636 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E
|
|
.sym 26637 lvds_clock_$glb_clk
|
|
.sym 26638 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr
|
|
.sym 26713 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26714 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
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.sym 26719 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 26723 io_ctrl_ins.rf_pin_state[7]
|
|
.sym 26725 io_ctrl_ins.rf_pin_state[6]
|
|
.sym 26727 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26740 io_ctrl_ins.rf_pin_state[5]
|
|
.sym 26741 io_ctrl_ins.rf_pin_state[4]
|
|
.sym 26746 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26747 io_ctrl_ins.rf_pin_state[7]
|
|
.sym 26748 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 26757 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26758 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 26760 io_ctrl_ins.rf_pin_state[5]
|
|
.sym 26769 io_ctrl_ins.rf_pin_state[4]
|
|
.sym 26770 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 26771 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26782 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 26783 io_ctrl_ins.rf_pin_state[6]
|
|
.sym 26784 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 26791 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
|
|
.sym 26792 r_counter_$glb_clk
|
|
.sym 26811 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 27275 i_smi_a3$SB_IO_IN
|
|
.sym 27283 w_smi_read_req
|
|
.sym 27285 i_smi_a3$SB_IO_IN
|
|
.sym 27293 i_smi_a3$SB_IO_IN
|
|
.sym 27297 w_smi_read_req
|
|
.sym 27367 i_glob_clock$SB_IO_IN
|
|
.sym 27395 i_smi_a3$SB_IO_IN
|
|
.sym 27397 i_glob_clock$SB_IO_IN
|
|
.sym 27429 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 27440 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 27459 r_counter
|
|
.sym 27460 $PACKER_VCC_NET
|
|
.sym 27470 r_counter
|
|
.sym 27478 $PACKER_VCC_NET
|
|
.sym 27514 i_smi_a3$SB_IO_IN
|
|
.sym 27546 o_tr_vc2$SB_IO_OUT
|
|
.sym 27552 $PACKER_GND_NET
|
|
.sym 27570 $PACKER_GND_NET
|
|
.sym 27576 i_config[0]$SB_IO_IN
|
|
.sym 27582 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 27596 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 27605 o_tr_vc1$SB_IO_OUT
|
|
.sym 27608 o_tr_vc2$SB_IO_OUT
|
|
.sym 27616 o_tr_vc1$SB_IO_OUT
|
|
.sym 27628 o_tr_vc2$SB_IO_OUT
|
|
.sym 27631 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 27634 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 27646 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 27652 o_tr_vc1_b$SB_IO_OUT
|
|
.sym 27800 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 27801 lvds_rx_09_inst.r_data[12]
|
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.sym 27812 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 27813 lvds_rx_09_inst.r_data[14]
|
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.sym 27816 lvds_rx_09_inst.o_debug_state[0]
|
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.sym 27817 lvds_rx_09_inst.r_data[16]
|
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.sym 27828 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 27829 lvds_rx_09_inst.r_data[18]
|
|
.sym 27862 lvds_rx_09_inst.r_data[18]
|
|
.sym 27876 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 27877 w_lvds_rx_09_d1
|
|
.sym 27892 w_lvds_rx_09_d0
|
|
.sym 27893 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28039 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 28040 w_lvds_rx_09_d1_SB_LUT4_I1_O[1]
|
|
.sym 28041 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]
|
|
.sym 28046 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 28047 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28048 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 28049 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 28062 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 28063 w_lvds_rx_09_d1
|
|
.sym 28064 w_lvds_rx_09_d0
|
|
.sym 28065 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 28070 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 28071 w_lvds_rx_09_d1
|
|
.sym 28072 w_lvds_rx_09_d0
|
|
.sym 28073 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28074 w_lvds_rx_09_d0
|
|
.sym 28075 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 28076 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28077 w_lvds_rx_09_d1
|
|
.sym 28081 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E
|
|
.sym 28091 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 28092 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 28093 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 28094 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 28095 w_lvds_rx_09_d1
|
|
.sym 28096 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28097 w_lvds_rx_09_d0
|
|
.sym 28194 lvds_rx_09_inst.r_data[9]
|
|
.sym 28198 lvds_rx_09_inst.r_data[6]
|
|
.sym 28202 lvds_rx_09_inst.r_data[7]
|
|
.sym 28210 lvds_rx_09_inst.r_data[8]
|
|
.sym 28228 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28229 lvds_rx_09_inst.r_data[10]
|
|
.sym 28232 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28233 lvds_rx_09_inst.r_data[9]
|
|
.sym 28236 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28237 lvds_rx_09_inst.r_data[5]
|
|
.sym 28240 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28241 lvds_rx_09_inst.r_data[8]
|
|
.sym 28244 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28245 lvds_rx_09_inst.r_data[6]
|
|
.sym 28248 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28249 lvds_rx_09_inst.r_data[4]
|
|
.sym 28252 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28253 lvds_rx_09_inst.r_data[7]
|
|
.sym 28256 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28257 lvds_rx_09_inst.r_data[11]
|
|
.sym 28266 lvds_rx_09_inst.r_data[22]
|
|
.sym 28274 lvds_rx_09_inst.r_data[23]
|
|
.sym 28278 lvds_rx_09_inst.r_data[24]
|
|
.sym 28282 lvds_rx_09_inst.r_data[25]
|
|
.sym 28292 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28293 lvds_rx_09_inst.r_data[21]
|
|
.sym 28296 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28297 lvds_rx_09_inst.r_data[20]
|
|
.sym 28300 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28301 lvds_rx_09_inst.r_data[22]
|
|
.sym 28304 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28305 lvds_rx_09_inst.r_data[2]
|
|
.sym 28308 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28309 lvds_rx_09_inst.r_data[23]
|
|
.sym 28312 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28313 lvds_rx_09_inst.r_data[13]
|
|
.sym 28326 lvds_rx_09_inst.r_data[17]
|
|
.sym 28330 lvds_rx_09_inst.r_data[20]
|
|
.sym 28334 lvds_rx_09_inst.r_data[15]
|
|
.sym 28338 lvds_rx_09_inst.r_data[14]
|
|
.sym 28342 lvds_rx_09_inst.r_data[16]
|
|
.sym 28346 lvds_rx_09_inst.r_data[3]
|
|
.sym 28360 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28361 lvds_rx_09_inst.r_data[19]
|
|
.sym 28364 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28365 lvds_rx_09_inst.r_data[3]
|
|
.sym 28368 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28369 lvds_rx_09_inst.r_data[15]
|
|
.sym 28372 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28373 lvds_rx_09_inst.r_data[0]
|
|
.sym 28376 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28377 lvds_rx_09_inst.r_data[1]
|
|
.sym 28380 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28381 lvds_rx_09_inst.r_data[17]
|
|
.sym 28386 lvds_rx_09_inst.r_data[0]
|
|
.sym 28398 w_lvds_rx_09_d0
|
|
.sym 28402 w_lvds_rx_09_d1
|
|
.sym 28406 lvds_rx_09_inst.r_data[19]
|
|
.sym 28414 lvds_rx_09_inst.r_data[1]
|
|
.sym 28482 w_rx_24_fifo_pulled_data[0]
|
|
.sym 28483 w_rx_24_fifo_pulled_data[16]
|
|
.sym 28484 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28485 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 28489 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28490 w_rx_24_fifo_pulled_data[8]
|
|
.sym 28491 w_rx_24_fifo_pulled_data[24]
|
|
.sym 28492 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28493 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 28494 w_rx_24_fifo_pulled_data[1]
|
|
.sym 28495 w_rx_24_fifo_pulled_data[17]
|
|
.sym 28496 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28497 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 28498 w_rx_24_fifo_pulled_data[11]
|
|
.sym 28499 w_rx_24_fifo_pulled_data[27]
|
|
.sym 28500 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28501 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 28502 w_rx_24_fifo_pulled_data[9]
|
|
.sym 28503 w_rx_24_fifo_pulled_data[25]
|
|
.sym 28504 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28505 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 28512 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28513 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 28516 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28517 lvds_rx_24_inst.r_data[3]
|
|
.sym 28520 w_lvds_rx_24_d1
|
|
.sym 28521 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28524 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28525 lvds_rx_24_inst.r_data[15]
|
|
.sym 28536 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28537 lvds_rx_24_inst.r_data[17]
|
|
.sym 28540 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28541 lvds_rx_24_inst.r_data[1]
|
|
.sym 28542 w_rx_24_fifo_pulled_data[3]
|
|
.sym 28543 w_rx_24_fifo_pulled_data[19]
|
|
.sym 28544 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 28545 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 28547 lvds_rx_09_inst.r_phase_count[0]
|
|
.sym 28551 lvds_rx_09_inst.r_phase_count[1]
|
|
.sym 28552 $PACKER_VCC_NET
|
|
.sym 28553 lvds_rx_09_inst.r_phase_count[0]
|
|
.sym 28554 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 28556 $PACKER_VCC_NET
|
|
.sym 28557 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2]
|
|
.sym 28561 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 28565 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 28566 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 28567 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 28568 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2]
|
|
.sym 28569 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28570 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 28571 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 28572 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1]
|
|
.sym 28573 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28574 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0]
|
|
.sym 28575 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
|
|
.sym 28576 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2]
|
|
.sym 28577 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28580 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28581 lvds_rx_24_inst.r_data[19]
|
|
.sym 28588 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28589 lvds_rx_24_inst.r_data[25]
|
|
.sym 28616 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28617 lvds_rx_24_inst.r_data[23]
|
|
.sym 28624 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28625 lvds_rx_24_inst.r_data[21]
|
|
.sym 28662 lvds_rx_24_inst.r_data[23]
|
|
.sym 28670 lvds_rx_24_inst.r_data[25]
|
|
.sym 28708 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 28709 lvds_rx_09_inst.r_data[24]
|
|
.sym 28740 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28741 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28742 w_rx_09_fifo_pulled_data[1]
|
|
.sym 28743 w_rx_09_fifo_pulled_data[17]
|
|
.sym 28744 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28745 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28749 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 28753 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28768 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 28769 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 28770 w_rx_09_fifo_pulled_data[3]
|
|
.sym 28771 w_rx_09_fifo_pulled_data[19]
|
|
.sym 28772 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28773 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28777 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 28778 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
|
|
.sym 28779 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1]
|
|
.sym 28780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
|
|
.sym 28781 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 28782 w_rx_09_fifo_pulled_data[0]
|
|
.sym 28783 w_rx_09_fifo_pulled_data[16]
|
|
.sym 28784 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28785 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28786 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0]
|
|
.sym 28787 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1]
|
|
.sym 28788 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2]
|
|
.sym 28789 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 28790 w_rx_09_fifo_pulled_data[2]
|
|
.sym 28791 w_rx_09_fifo_pulled_data[18]
|
|
.sym 28792 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28793 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28794 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
|
|
.sym 28795 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1]
|
|
.sym 28796 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
|
|
.sym 28797 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 28801 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 28803 rx_24_fifo.rd_addr[0]
|
|
.sym 28808 rx_24_fifo.rd_addr[1]
|
|
.sym 28812 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 28813 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 28816 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 28817 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 28820 rx_24_fifo.rd_addr[4]
|
|
.sym 28821 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
|
|
.sym 28824 rx_24_fifo.rd_addr[5]
|
|
.sym 28825 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
|
|
.sym 28828 rx_24_fifo.rd_addr[6]
|
|
.sym 28829 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
|
|
.sym 28832 rx_24_fifo.rd_addr[7]
|
|
.sym 28833 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
|
|
.sym 28836 rx_24_fifo.rd_addr[8]
|
|
.sym 28837 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 28840 rx_24_fifo.rd_addr[9]
|
|
.sym 28841 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9]
|
|
.sym 28843 i_smi_a2$SB_IO_IN
|
|
.sym 28844 i_smi_a1$SB_IO_IN
|
|
.sym 28845 i_smi_a3$SB_IO_IN
|
|
.sym 28849 i_smi_a1_SB_LUT4_I1_O
|
|
.sym 28850 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 28851 i_smi_a1$SB_IO_IN
|
|
.sym 28852 i_smi_a2$SB_IO_IN
|
|
.sym 28853 i_smi_a3$SB_IO_IN
|
|
.sym 28854 w_rx_09_fifo_pulled_data[11]
|
|
.sym 28855 w_rx_09_fifo_pulled_data[27]
|
|
.sym 28856 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28857 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28860 rx_24_fifo.rd_addr[1]
|
|
.sym 28861 rx_24_fifo.rd_addr[0]
|
|
.sym 28862 w_rx_09_fifo_pulled_data[8]
|
|
.sym 28863 w_rx_09_fifo_pulled_data[24]
|
|
.sym 28864 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28865 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28874 lvds_rx_09_inst.r_data[21]
|
|
.sym 28878 w_rx_09_fifo_pulled_data[10]
|
|
.sym 28879 w_rx_09_fifo_pulled_data[26]
|
|
.sym 28880 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 28881 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 28882 lvds_rx_09_inst.r_data[2]
|
|
.sym 28892 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 28893 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 28894 rx_24_fifo.wr_addr[8]
|
|
.sym 28895 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[8]
|
|
.sym 28896 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 28897 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 28901 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 28924 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28925 lvds_rx_24_inst.r_data[5]
|
|
.sym 28928 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 28929 lvds_rx_24_inst.r_data[7]
|
|
.sym 28931 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 28936 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 28937 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 28940 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 28941 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[2]
|
|
.sym 28944 rx_24_fifo.wr_addr[4]
|
|
.sym 28945 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[3]
|
|
.sym 28948 rx_24_fifo.wr_addr[5]
|
|
.sym 28949 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[4]
|
|
.sym 28952 rx_24_fifo.wr_addr[6]
|
|
.sym 28953 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5]
|
|
.sym 28956 rx_24_fifo.wr_addr[7]
|
|
.sym 28957 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[6]
|
|
.sym 28960 rx_24_fifo.wr_addr[8]
|
|
.sym 28961 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[7]
|
|
.sym 28964 rx_24_fifo.wr_addr[9]
|
|
.sym 28965 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 28969 $nextpnr_ICESTORM_LC_1$I3
|
|
.sym 28970 rx_24_fifo.rd_addr[5]
|
|
.sym 28971 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 28972 rx_24_fifo.rd_addr[8]
|
|
.sym 28973 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 28974 i_smi_a1$SB_IO_IN
|
|
.sym 28975 i_smi_a3$SB_IO_IN
|
|
.sym 28976 i_smi_a2$SB_IO_IN
|
|
.sym 28977 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 28985 rx_24_fifo.rd_addr[0]
|
|
.sym 28988 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 28989 w_rx_24_fifo_push
|
|
.sym 28990 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 28991 rx_24_fifo.rd_addr[9]
|
|
.sym 28992 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 28993 w_rx_24_fifo_push
|
|
.sym 28995 sys_ctrl_ins.reset_count[0]
|
|
.sym 29000 sys_ctrl_ins.reset_count[1]
|
|
.sym 29002 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 29004 sys_ctrl_ins.reset_count[2]
|
|
.sym 29005 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 29006 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 29008 sys_ctrl_ins.reset_count[3]
|
|
.sym 29009 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 29013 sys_ctrl_ins.reset_count[0]
|
|
.sym 29014 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 29016 sys_ctrl_ins.reset_count[1]
|
|
.sym 29017 sys_ctrl_ins.reset_count[0]
|
|
.sym 29020 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
|
|
.sym 29021 sys_ctrl_ins.reset_cmd
|
|
.sym 29022 sys_ctrl_ins.reset_count[3]
|
|
.sym 29023 sys_ctrl_ins.reset_count[1]
|
|
.sym 29024 sys_ctrl_ins.reset_count[2]
|
|
.sym 29025 sys_ctrl_ins.reset_count[0]
|
|
.sym 29026 lvds_rx_24_inst.r_data[9]
|
|
.sym 29034 w_rx_24_fifo_pulled_data[10]
|
|
.sym 29035 w_rx_24_fifo_pulled_data[26]
|
|
.sym 29036 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 29037 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 29038 lvds_rx_24_inst.r_data[15]
|
|
.sym 29042 lvds_rx_24_inst.r_data[17]
|
|
.sym 29049 w_lvds_rx_24_d0
|
|
.sym 29050 lvds_rx_24_inst.r_data[1]
|
|
.sym 29057 w_lvds_rx_24_d1
|
|
.sym 29062 lvds_rx_24_inst.r_data[0]
|
|
.sym 29066 lvds_rx_24_inst.r_data[5]
|
|
.sym 29074 w_rx_24_fifo_pulled_data[2]
|
|
.sym 29075 w_rx_24_fifo_pulled_data[18]
|
|
.sym 29076 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 29077 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 29082 lvds_rx_24_inst.r_data[7]
|
|
.sym 29094 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 29102 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 29117 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 29121 w_rx_24_fifo_data[18]
|
|
.sym 29122 lvds_rx_24_inst.r_data[18]
|
|
.sym 29130 lvds_rx_24_inst.r_data[14]
|
|
.sym 29134 lvds_rx_24_inst.r_data[22]
|
|
.sym 29138 lvds_rx_24_inst.r_data[6]
|
|
.sym 29142 lvds_rx_24_inst.r_data[24]
|
|
.sym 29146 lvds_rx_24_inst.r_data[16]
|
|
.sym 29150 lvds_rx_24_inst.r_data[8]
|
|
.sym 29168 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29169 lvds_rx_24_inst.r_data[6]
|
|
.sym 29184 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29185 lvds_rx_24_inst.r_data[4]
|
|
.sym 29251 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 29256 rx_09_fifo.rd_addr[1]
|
|
.sym 29260 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 29261 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 29264 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 29265 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 29268 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 29269 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
|
|
.sym 29272 rx_09_fifo.rd_addr[5]
|
|
.sym 29273 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
|
|
.sym 29276 rx_09_fifo.rd_addr[6]
|
|
.sym 29277 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
|
|
.sym 29280 rx_09_fifo.rd_addr[7]
|
|
.sym 29281 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
|
|
.sym 29284 rx_09_fifo.rd_addr[8]
|
|
.sym 29285 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
|
|
.sym 29288 rx_09_fifo.rd_addr[9]
|
|
.sym 29289 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9]
|
|
.sym 29293 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
|
|
.sym 29301 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 29315 rx_24_fifo.rd_addr[0]
|
|
.sym 29320 rx_24_fifo.rd_addr[1]
|
|
.sym 29321 rx_24_fifo.rd_addr[0]
|
|
.sym 29324 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 29325 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[2]
|
|
.sym 29328 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 29329 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[3]
|
|
.sym 29332 rx_24_fifo.rd_addr[4]
|
|
.sym 29333 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[4]
|
|
.sym 29336 rx_24_fifo.rd_addr[5]
|
|
.sym 29337 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[5]
|
|
.sym 29340 rx_24_fifo.rd_addr[6]
|
|
.sym 29341 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[6]
|
|
.sym 29344 rx_24_fifo.rd_addr[7]
|
|
.sym 29345 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[7]
|
|
.sym 29348 rx_24_fifo.rd_addr[8]
|
|
.sym 29349 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[8]
|
|
.sym 29352 rx_24_fifo.rd_addr[9]
|
|
.sym 29353 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I2[9]
|
|
.sym 29357 $nextpnr_ICESTORM_LC_7$I3
|
|
.sym 29358 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[9]
|
|
.sym 29359 rx_24_fifo.wr_addr[9]
|
|
.sym 29360 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 29361 rx_24_fifo.wr_addr[4]
|
|
.sym 29362 w_rx_09_fifo_pulled_data[9]
|
|
.sym 29363 w_rx_09_fifo_pulled_data[25]
|
|
.sym 29364 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 29365 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 29366 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[6]
|
|
.sym 29367 rx_24_fifo.wr_addr[6]
|
|
.sym 29368 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[10]
|
|
.sym 29369 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_2_I3[3]
|
|
.sym 29370 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
|
|
.sym 29371 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
|
|
.sym 29372 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
|
|
.sym 29373 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 29374 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[6]
|
|
.sym 29375 rx_24_fifo.wr_addr[6]
|
|
.sym 29376 rx_24_fifo.wr_addr[7]
|
|
.sym 29377 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[7]
|
|
.sym 29378 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[0]
|
|
.sym 29379 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[1]
|
|
.sym 29380 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[2]
|
|
.sym 29381 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0_SB_LUT4_O_I0[3]
|
|
.sym 29386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0]
|
|
.sym 29387 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1]
|
|
.sym 29388 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2]
|
|
.sym 29389 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 29390 rx_24_fifo.wr_addr[4]
|
|
.sym 29391 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[4]
|
|
.sym 29392 rx_24_fifo.wr_addr[5]
|
|
.sym 29393 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[5]
|
|
.sym 29398 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[0]
|
|
.sym 29399 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 29400 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[2]
|
|
.sym 29401 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_I0[3]
|
|
.sym 29402 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[8]
|
|
.sym 29403 rx_24_fifo.wr_addr[8]
|
|
.sym 29404 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 29405 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[2]
|
|
.sym 29406 rx_24_fifo.wr_addr[9]
|
|
.sym 29407 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[9]
|
|
.sym 29408 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_I1[1]
|
|
.sym 29409 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 29410 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 29414 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 29424 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 29425 rx_24_fifo.rd_addr[1]
|
|
.sym 29426 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 29438 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 29442 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 29446 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 29447 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 29448 rx_24_fifo.rd_addr[4]
|
|
.sym 29449 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 29450 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 29454 rx_24_fifo.rd_addr[6]
|
|
.sym 29455 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 29456 rx_24_fifo.rd_addr[7]
|
|
.sym 29457 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 29466 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 29470 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
|
|
.sym 29471 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 29472 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 29473 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 29476 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29477 lvds_rx_24_inst.r_data[9]
|
|
.sym 29478 rx_24_fifo.rd_addr[4]
|
|
.sym 29479 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 29480 rx_24_fifo.rd_addr[5]
|
|
.sym 29481 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 29482 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 29483 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 29484 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2]
|
|
.sym 29485 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3]
|
|
.sym 29486 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
|
|
.sym 29487 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
|
|
.sym 29488 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
|
|
.sym 29489 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
|
|
.sym 29492 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29493 lvds_rx_24_inst.r_data[27]
|
|
.sym 29494 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 29495 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
|
|
.sym 29496 rx_24_fifo.rd_addr[9]
|
|
.sym 29497 rx_24_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 29498 rx_24_fifo.rd_addr[6]
|
|
.sym 29499 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 29500 rx_24_fifo.rd_addr[7]
|
|
.sym 29501 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 29504 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29505 lvds_rx_24_inst.r_data[26]
|
|
.sym 29507 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 29512 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 29513 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 29516 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 29517 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
|
|
.sym 29520 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 29521 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
|
|
.sym 29524 rx_24_fifo.wr_addr[4]
|
|
.sym 29525 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
|
|
.sym 29528 rx_24_fifo.wr_addr[5]
|
|
.sym 29529 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
|
|
.sym 29532 rx_24_fifo.wr_addr[6]
|
|
.sym 29533 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
|
|
.sym 29536 rx_24_fifo.wr_addr[7]
|
|
.sym 29537 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
|
|
.sym 29540 rx_24_fifo.wr_addr[8]
|
|
.sym 29541 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 29544 rx_24_fifo.wr_addr[9]
|
|
.sym 29545 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9]
|
|
.sym 29558 $PACKER_VCC_NET
|
|
.sym 29574 lvds_rx_24_inst.r_data[21]
|
|
.sym 29586 lvds_rx_24_inst.r_data[4]
|
|
.sym 29591 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 29592 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 29593 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 29595 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 29596 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 29597 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 29607 w_rx_09_fifo_full
|
|
.sym 29608 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 29609 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 29613 sys_ctrl_ins.reset_cmd
|
|
.sym 29617 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E
|
|
.sym 29630 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 29631 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 29632 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 29633 lvds_rx_09_inst.o_debug_state[1]
|
|
.sym 29636 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29637 lvds_rx_24_inst.r_data[18]
|
|
.sym 29640 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29641 lvds_rx_24_inst.r_data[12]
|
|
.sym 29644 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29645 lvds_rx_24_inst.r_data[16]
|
|
.sym 29648 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29649 lvds_rx_24_inst.r_data[24]
|
|
.sym 29652 w_lvds_rx_24_d0
|
|
.sym 29653 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29656 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29657 lvds_rx_24_inst.r_data[14]
|
|
.sym 29660 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29661 lvds_rx_24_inst.r_data[20]
|
|
.sym 29664 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29665 lvds_rx_24_inst.r_data[22]
|
|
.sym 29668 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29669 lvds_rx_24_inst.r_data[8]
|
|
.sym 29672 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29673 lvds_rx_24_inst.r_data[13]
|
|
.sym 29676 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29677 lvds_rx_24_inst.r_data[11]
|
|
.sym 29680 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29681 lvds_rx_24_inst.r_data[0]
|
|
.sym 29684 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29685 lvds_rx_24_inst.r_data[10]
|
|
.sym 29692 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29693 lvds_rx_24_inst.r_data[2]
|
|
.sym 29770 lvds_rx_09_inst.r_data[11]
|
|
.sym 29790 lvds_rx_09_inst.r_data[10]
|
|
.sym 29794 w_rx_09_fifo_push
|
|
.sym 29795 rx_09_fifo.rd_addr[8]
|
|
.sym 29796 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 29797 w_rx_09_fifo_full
|
|
.sym 29798 lvds_rx_09_inst.r_data[12]
|
|
.sym 29802 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 29803 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 29804 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 29805 rx_09_fifo.full_o_SB_LUT4_I3_O[3]
|
|
.sym 29810 rx_09_fifo.rd_addr[1]
|
|
.sym 29811 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 29812 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 29813 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 29814 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 29815 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 29816 rx_09_fifo.rd_addr[5]
|
|
.sym 29817 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 29818 rx_09_fifo.rd_addr[6]
|
|
.sym 29819 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 29820 rx_09_fifo.rd_addr[9]
|
|
.sym 29821 rx_09_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 29822 lvds_rx_09_inst.r_data[13]
|
|
.sym 29826 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 29832 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 29833 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 29834 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 29838 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 29842 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 29846 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
|
|
.sym 29853 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 29854 rx_09_fifo.rd_addr[7]
|
|
.sym 29855 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6]
|
|
.sym 29856 rx_09_fifo.rd_addr[8]
|
|
.sym 29857 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7]
|
|
.sym 29858 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 29859 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3]
|
|
.sym 29860 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2]
|
|
.sym 29861 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3]
|
|
.sym 29863 rx_09_fifo.rd_addr[7]
|
|
.sym 29864 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
|
|
.sym 29865 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 29866 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 29867 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2]
|
|
.sym 29868 rx_09_fifo.rd_addr[6]
|
|
.sym 29869 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5]
|
|
.sym 29870 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 29871 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1]
|
|
.sym 29872 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
|
|
.sym 29873 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
|
|
.sym 29876 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 29877 w_rx_09_fifo_push
|
|
.sym 29878 lvds_rx_09_inst.r_data[5]
|
|
.sym 29882 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 29883 rx_09_fifo.wr_addr[3]
|
|
.sym 29884 rx_09_fifo.rd_addr[5]
|
|
.sym 29885 rx_09_fifo.wr_addr[5]
|
|
.sym 29886 lvds_rx_09_inst.r_data[4]
|
|
.sym 29896 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 29897 w_rx_09_fifo_push
|
|
.sym 29899 w_rx_24_fifo_full
|
|
.sym 29900 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29901 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 29903 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 29904 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1]
|
|
.sym 29905 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2]
|
|
.sym 29910 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9]
|
|
.sym 29911 rx_09_fifo.rd_addr[9]
|
|
.sym 29912 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8]
|
|
.sym 29913 w_rx_09_fifo_push
|
|
.sym 29922 w_rx_24_fifo_empty
|
|
.sym 29926 w_rx_24_fifo_full
|
|
.sym 29934 rx_24_fifo.rd_addr[6]
|
|
.sym 29935 rx_24_fifo.wr_addr[6]
|
|
.sym 29936 rx_24_fifo.rd_addr[7]
|
|
.sym 29937 rx_24_fifo.wr_addr[7]
|
|
.sym 29938 w_rx_09_fifo_empty
|
|
.sym 29942 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 29943 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 29944 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 29945 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 29946 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
|
|
.sym 29947 w_rx_24_fifo_empty
|
|
.sym 29948 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
|
|
.sym 29949 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0[3]
|
|
.sym 29950 w_rx_09_fifo_full
|
|
.sym 29962 rx_24_fifo.rd_addr[4]
|
|
.sym 29963 rx_24_fifo.wr_addr[4]
|
|
.sym 29964 rx_24_fifo.rd_addr[5]
|
|
.sym 29965 rx_24_fifo.wr_addr[5]
|
|
.sym 29966 rx_24_fifo.rd_addr[8]
|
|
.sym 29967 rx_24_fifo.wr_addr[8]
|
|
.sym 29968 rx_24_fifo.rd_addr[9]
|
|
.sym 29969 rx_24_fifo.wr_addr[9]
|
|
.sym 29972 spi_if_ins.w_rx_data[5]
|
|
.sym 29973 spi_if_ins.w_rx_data[6]
|
|
.sym 29974 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 29975 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1]
|
|
.sym 29976 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2]
|
|
.sym 29977 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3]
|
|
.sym 29984 spi_if_ins.w_rx_data[6]
|
|
.sym 29985 spi_if_ins.w_rx_data[5]
|
|
.sym 29990 rx_24_fifo.rd_addr[1]
|
|
.sym 29991 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
|
|
.sym 29992 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]
|
|
.sym 29993 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
|
|
.sym 29994 lvds_rx_24_inst.r_data[27]
|
|
.sym 30000 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30001 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 30006 lvds_rx_24_inst.r_data[29]
|
|
.sym 30014 lvds_rx_24_inst.r_data[26]
|
|
.sym 30028 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30029 w_rx_24_fifo_push
|
|
.sym 30030 w_rx_24_fifo_push
|
|
.sym 30031 rx_24_fifo.rd_addr[8]
|
|
.sym 30032 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 30033 w_rx_24_fifo_full
|
|
.sym 30034 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 30035 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 30036 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 30037 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 30038 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
|
|
.sym 30039 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
|
|
.sym 30040 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
|
|
.sym 30041 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 30042 lvds_rx_09_inst.r_push
|
|
.sym 30046 lvds_rx_24_inst.r_push
|
|
.sym 30053 w_cs[0]
|
|
.sym 30054 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 30055 w_lvds_rx_24_d0
|
|
.sym 30056 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 30057 w_lvds_rx_24_d1
|
|
.sym 30065 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
|
|
.sym 30066 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 30067 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 30068 w_lvds_rx_24_d1
|
|
.sym 30069 w_lvds_rx_24_d0
|
|
.sym 30075 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 30076 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1]
|
|
.sym 30077 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30078 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 30079 w_lvds_rx_24_d0
|
|
.sym 30080 w_lvds_rx_24_d1
|
|
.sym 30081 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 30086 w_fetch
|
|
.sym 30087 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 30088 w_load
|
|
.sym 30089 w_cs[0]
|
|
.sym 30098 lvds_rx_24_inst.r_data[20]
|
|
.sym 30102 lvds_rx_24_inst.r_data[3]
|
|
.sym 30106 lvds_rx_24_inst.r_data[19]
|
|
.sym 30118 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 30119 w_lvds_rx_24_d0
|
|
.sym 30120 w_lvds_rx_24_d1
|
|
.sym 30121 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 30122 $PACKER_GND_NET
|
|
.sym 30129 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
|
|
.sym 30146 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 30178 lvds_rx_24_inst.r_data[12]
|
|
.sym 30182 lvds_rx_24_inst.r_data[11]
|
|
.sym 30190 lvds_rx_24_inst.r_data[13]
|
|
.sym 30202 lvds_rx_24_inst.r_data[2]
|
|
.sym 30206 lvds_rx_24_inst.r_data[10]
|
|
.sym 30252 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 30253 lvds_rx_09_inst.r_data[27]
|
|
.sym 30264 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 30265 lvds_rx_09_inst.r_data[26]
|
|
.sym 30280 lvds_rx_09_inst.o_debug_state[0]
|
|
.sym 30281 lvds_rx_09_inst.r_data[25]
|
|
.sym 30289 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_1_O
|
|
.sym 30307 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 30312 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 30313 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 30316 rx_09_fifo.wr_addr[2]
|
|
.sym 30317 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
|
|
.sym 30320 rx_09_fifo.wr_addr[3]
|
|
.sym 30321 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
|
|
.sym 30324 rx_09_fifo.wr_addr[4]
|
|
.sym 30325 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
|
|
.sym 30328 rx_09_fifo.wr_addr[5]
|
|
.sym 30329 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
|
|
.sym 30332 rx_09_fifo.wr_addr[6]
|
|
.sym 30333 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
|
|
.sym 30336 rx_09_fifo.wr_addr[7]
|
|
.sym 30337 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
|
|
.sym 30340 rx_09_fifo.wr_addr[8]
|
|
.sym 30341 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
|
|
.sym 30344 rx_09_fifo.wr_addr[9]
|
|
.sym 30345 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9]
|
|
.sym 30348 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 30349 rx_09_fifo.rd_addr[1]
|
|
.sym 30350 rx_09_fifo.full_o_SB_LUT4_I3_I2[9]
|
|
.sym 30354 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
|
|
.sym 30358 rx_09_fifo.wr_addr[3]
|
|
.sym 30359 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[3]
|
|
.sym 30360 rx_09_fifo.wr_addr[9]
|
|
.sym 30361 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[9]
|
|
.sym 30362 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
|
|
.sym 30366 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
|
|
.sym 30371 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 30376 rx_09_fifo.wr_addr[2]
|
|
.sym 30377 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 30380 rx_09_fifo.wr_addr[3]
|
|
.sym 30381 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2]
|
|
.sym 30384 rx_09_fifo.wr_addr[4]
|
|
.sym 30385 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3]
|
|
.sym 30388 rx_09_fifo.wr_addr[5]
|
|
.sym 30389 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4]
|
|
.sym 30392 rx_09_fifo.wr_addr[6]
|
|
.sym 30393 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5]
|
|
.sym 30396 rx_09_fifo.wr_addr[7]
|
|
.sym 30397 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6]
|
|
.sym 30400 rx_09_fifo.wr_addr[8]
|
|
.sym 30401 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7]
|
|
.sym 30404 rx_09_fifo.wr_addr[9]
|
|
.sym 30405 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8]
|
|
.sym 30409 $nextpnr_ICESTORM_LC_16$I3
|
|
.sym 30412 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30413 w_tx_data_io[6]
|
|
.sym 30414 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 30415 rx_09_fifo.rd_addr[5]
|
|
.sym 30416 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4]
|
|
.sym 30417 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 30419 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30420 w_tx_data_io[5]
|
|
.sym 30421 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 30424 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 30425 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1]
|
|
.sym 30427 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30428 w_tx_data_io[7]
|
|
.sym 30429 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 30430 w_tx_data_smi[3]
|
|
.sym 30431 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 30432 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30433 w_tx_data_io[3]
|
|
.sym 30442 w_cs[0]
|
|
.sym 30443 w_cs[2]
|
|
.sym 30444 w_cs[3]
|
|
.sym 30445 w_cs[1]
|
|
.sym 30446 smi_ctrl_ins.r_fifo_24_pull
|
|
.sym 30450 w_cs[0]
|
|
.sym 30451 w_cs[1]
|
|
.sym 30452 w_cs[3]
|
|
.sym 30453 w_cs[2]
|
|
.sym 30457 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 30458 smi_ctrl_ins.w_fifo_24_pull_trigger
|
|
.sym 30463 smi_ctrl_ins.r_fifo_24_pull_1
|
|
.sym 30464 w_rx_24_fifo_empty
|
|
.sym 30465 smi_ctrl_ins.r_fifo_24_pull
|
|
.sym 30466 r_tx_data[3]
|
|
.sym 30470 w_cs[1]
|
|
.sym 30471 w_cs[2]
|
|
.sym 30472 w_cs[3]
|
|
.sym 30473 w_cs[0]
|
|
.sym 30478 r_tx_data[4]
|
|
.sym 30482 r_tx_data[1]
|
|
.sym 30486 r_tx_data[0]
|
|
.sym 30494 w_tx_data_smi[0]
|
|
.sym 30495 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 30496 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30497 w_tx_data_io[0]
|
|
.sym 30500 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30501 w_tx_data_io[4]
|
|
.sym 30510 w_tx_data_smi[1]
|
|
.sym 30511 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 30512 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30513 w_tx_data_io[1]
|
|
.sym 30516 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
|
|
.sym 30517 rx_24_fifo.rd_addr[0]
|
|
.sym 30530 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30531 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 30532 spi_if_ins.state_if[0]
|
|
.sym 30533 spi_if_ins.state_if[1]
|
|
.sym 30549 w_cs[0]
|
|
.sym 30551 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30552 spi_if_ins.state_if[1]
|
|
.sym 30553 spi_if_ins.state_if[0]
|
|
.sym 30554 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
|
|
.sym 30566 w_ioc[2]
|
|
.sym 30567 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 30568 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 30569 w_cs[2]
|
|
.sym 30581 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 30582 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 30586 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 30587 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 30588 spi_if_ins.state_if[0]
|
|
.sym 30589 spi_if_ins.state_if[1]
|
|
.sym 30595 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_I1[0]
|
|
.sym 30596 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 30597 w_cs[1]
|
|
.sym 30599 w_fetch
|
|
.sym 30600 w_cs[1]
|
|
.sym 30601 w_load
|
|
.sym 30602 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 30606 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 30607 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 30608 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[2]
|
|
.sym 30609 w_cs[1]
|
|
.sym 30610 w_ioc[4]
|
|
.sym 30611 w_cs[0]
|
|
.sym 30612 w_fetch
|
|
.sym 30613 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 30615 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30616 lvds_rx_24_inst.o_debug_state[0]
|
|
.sym 30617 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 30620 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30621 w_fetch
|
|
.sym 30623 w_ioc[4]
|
|
.sym 30624 w_ioc[0]
|
|
.sym 30625 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 30627 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30628 w_lvds_rx_24_d0_SB_LUT4_I1_O[1]
|
|
.sym 30629 w_lvds_rx_24_d0_SB_LUT4_I1_O[2]
|
|
.sym 30631 w_ioc[0]
|
|
.sym 30632 w_ioc[2]
|
|
.sym 30633 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 30635 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30636 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
|
|
.sym 30637 lvds_rx_24_inst.o_debug_state[1]
|
|
.sym 30639 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 30640 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 30641 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30643 w_ioc[2]
|
|
.sym 30644 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 30645 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R_SB_LUT4_O_I3[2]
|
|
.sym 30656 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0]
|
|
.sym 30657 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1]
|
|
.sym 30662 w_rx_data[2]
|
|
.sym 30674 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 30675 io_ctrl_ins.pmod_dir_state[1]
|
|
.sym 30676 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 30677 io_ctrl_ins.debug_mode[1]
|
|
.sym 30678 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 30679 io_ctrl_ins.pmod_dir_state[2]
|
|
.sym 30680 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 30681 io_ctrl_ins.o_pmod[2]
|
|
.sym 30682 w_rx_data[1]
|
|
.sym 30710 o_led1$SB_IO_OUT
|
|
.sym 30711 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 30712 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2]
|
|
.sym 30713 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3]
|
|
.sym 30758 lvds_rx_09_inst.r_data[28]
|
|
.sym 30762 lvds_rx_09_inst.r_data[26]
|
|
.sym 30770 lvds_rx_09_inst.r_data[27]
|
|
.sym 30774 lvds_rx_09_inst.r_data[29]
|
|
.sym 30792 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 30793 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30806 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
|
|
.sym 30807 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 30808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 30809 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 30810 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0]
|
|
.sym 30811 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1]
|
|
.sym 30812 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
|
|
.sym 30813 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 30814 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
|
|
.sym 30815 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1]
|
|
.sym 30816 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2]
|
|
.sym 30817 i_smi_a2_SB_LUT4_I1_O[0]
|
|
.sym 30819 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 30824 rx_09_fifo.rd_addr[1]
|
|
.sym 30825 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 30828 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 30829 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
|
|
.sym 30832 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I3[0]
|
|
.sym 30833 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
|
|
.sym 30836 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 30837 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[4]
|
|
.sym 30840 rx_09_fifo.rd_addr[5]
|
|
.sym 30841 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[5]
|
|
.sym 30844 rx_09_fifo.rd_addr[6]
|
|
.sym 30845 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[6]
|
|
.sym 30848 rx_09_fifo.rd_addr[7]
|
|
.sym 30849 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[7]
|
|
.sym 30852 rx_09_fifo.rd_addr[8]
|
|
.sym 30853 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[8]
|
|
.sym 30856 rx_09_fifo.rd_addr[9]
|
|
.sym 30857 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[9]
|
|
.sym 30861 $nextpnr_ICESTORM_LC_4$I3
|
|
.sym 30862 rx_09_fifo.wr_addr[4]
|
|
.sym 30863 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[4]
|
|
.sym 30864 rx_09_fifo.wr_addr[6]
|
|
.sym 30865 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[6]
|
|
.sym 30866 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1]
|
|
.sym 30867 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[1]
|
|
.sym 30868 rx_09_fifo.wr_addr[2]
|
|
.sym 30869 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[2]
|
|
.sym 30870 lvds_rx_24_inst.r_data[28]
|
|
.sym 30874 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[0]
|
|
.sym 30875 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[1]
|
|
.sym 30876 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 30877 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0[3]
|
|
.sym 30878 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
|
|
.sym 30879 rx_09_fifo.wr_addr[2]
|
|
.sym 30880 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[2]
|
|
.sym 30881 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2[3]
|
|
.sym 30883 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 30884 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 30885 w_rx_24_fifo_empty
|
|
.sym 30888 rx_09_fifo.rd_addr[1]
|
|
.sym 30889 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
|
|
.sym 30890 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 30891 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
|
|
.sym 30892 rx_09_fifo.rd_addr[7]
|
|
.sym 30893 rx_09_fifo.wr_addr[7]
|
|
.sym 30898 w_rx_09_fifo_empty
|
|
.sym 30899 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
|
|
.sym 30900 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
|
|
.sym 30901 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
|
|
.sym 30905 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 30906 rx_09_fifo.rd_addr[6]
|
|
.sym 30907 rx_09_fifo.wr_addr[6]
|
|
.sym 30908 rx_09_fifo.rd_addr[8]
|
|
.sym 30909 rx_09_fifo.wr_addr[8]
|
|
.sym 30910 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0]
|
|
.sym 30911 rx_09_fifo.wr_addr[4]
|
|
.sym 30912 rx_09_fifo.rd_addr[9]
|
|
.sym 30913 rx_09_fifo.wr_addr[9]
|
|
.sym 30914 r_tx_data[5]
|
|
.sym 30922 r_tx_data[2]
|
|
.sym 30926 r_tx_data[7]
|
|
.sym 30938 r_tx_data[6]
|
|
.sym 30946 w_cs[0]
|
|
.sym 30947 w_cs[1]
|
|
.sym 30948 w_cs[2]
|
|
.sym 30949 w_cs[3]
|
|
.sym 30950 w_tx_data_sys[0]
|
|
.sym 30951 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
|
|
.sym 30952 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0]
|
|
.sym 30953 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3]
|
|
.sym 30954 w_tx_data_smi[2]
|
|
.sym 30955 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
|
|
.sym 30956 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
|
|
.sym 30957 w_tx_data_io[2]
|
|
.sym 30960 spi_if_ins.w_rx_data[5]
|
|
.sym 30961 spi_if_ins.w_rx_data[6]
|
|
.sym 30965 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 30966 w_cs[0]
|
|
.sym 30967 w_cs[1]
|
|
.sym 30968 w_cs[2]
|
|
.sym 30969 w_cs[3]
|
|
.sym 30977 w_cs[3]
|
|
.sym 30993 r_tx_data_SB_DFFE_Q_E
|
|
.sym 30998 spi_if_ins.spi.r_rx_byte[6]
|
|
.sym 31018 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0]
|
|
.sym 31025 spi_if_ins.o_data_in_SB_DFFE_Q_E
|
|
.sym 31040 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 31041 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
|
|
.sym 31043 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31044 spi_if_ins.state_if[0]
|
|
.sym 31045 spi_if_ins.state_if[1]
|
|
.sym 31047 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31048 spi_if_ins.state_if[0]
|
|
.sym 31049 spi_if_ins.state_if[1]
|
|
.sym 31050 spi_if_ins.state_if[0]
|
|
.sym 31051 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 31052 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31053 spi_if_ins.state_if[1]
|
|
.sym 31058 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
.sym 31059 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 31060 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 31061 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 31066 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31067 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 31068 spi_if_ins.state_if[0]
|
|
.sym 31069 spi_if_ins.state_if[1]
|
|
.sym 31075 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
|
|
.sym 31076 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 31077 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 31080 spi_if_ins.state_if[0]
|
|
.sym 31081 spi_if_ins.state_if[1]
|
|
.sym 31083 w_ioc[2]
|
|
.sym 31084 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 31085 w_ioc[0]
|
|
.sym 31087 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 31088 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31089 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2]
|
|
.sym 31090 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
|
|
.sym 31096 w_ioc[2]
|
|
.sym 31097 w_ioc[3]
|
|
.sym 31099 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 31100 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[1]
|
|
.sym 31101 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[2]
|
|
.sym 31105 w_ioc[0]
|
|
.sym 31108 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
|
|
.sym 31109 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
|
|
.sym 31110 w_ioc[4]
|
|
.sym 31111 w_ioc[3]
|
|
.sym 31112 w_ioc[2]
|
|
.sym 31113 w_ioc[1]
|
|
.sym 31114 w_ioc[4]
|
|
.sym 31115 w_ioc[1]
|
|
.sym 31116 w_ioc[0]
|
|
.sym 31117 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 31119 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 31120 w_ioc[2]
|
|
.sym 31121 w_ioc[0]
|
|
.sym 31124 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I0[2]
|
|
.sym 31125 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 31126 w_ioc[0]
|
|
.sym 31127 w_ioc[4]
|
|
.sym 31128 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
|
|
.sym 31129 w_ioc[1]
|
|
.sym 31131 w_ioc[1]
|
|
.sym 31132 w_ioc[4]
|
|
.sym 31133 w_ioc[3]
|
|
.sym 31135 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 31136 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 31137 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 31138 w_rx_data[1]
|
|
.sym 31144 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 31145 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 31146 w_rx_data[3]
|
|
.sym 31152 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 31153 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
|
|
.sym 31154 w_rx_data[0]
|
|
.sym 31158 w_rx_data[4]
|
|
.sym 31162 w_rx_data[2]
|
|
.sym 31168 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 31169 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 31170 w_rx_data[2]
|
|
.sym 31174 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 31175 o_shdn_tx_lna$SB_IO_OUT
|
|
.sym 31176 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 31177 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
|
|
.sym 31180 io_ctrl_ins.debug_mode[0]
|
|
.sym 31181 io_ctrl_ins.debug_mode[1]
|
|
.sym 31189 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 31191 w_ioc[0]
|
|
.sym 31192 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[1]
|
|
.sym 31193 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2_SB_LUT4_I2_O[2]
|
|
.sym 31194 io_ctrl_ins.debug_mode[0]
|
|
.sym 31195 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 31196 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 31197 io_ctrl_ins.debug_mode[1]
|
|
.sym 31198 w_rx_data[1]
|
|
.sym 31206 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 31207 io_ctrl_ins.o_pmod[7]
|
|
.sym 31208 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 31209 i_button$SB_IO_IN
|
|
.sym 31210 o_shdn_rx_lna$SB_IO_OUT
|
|
.sym 31211 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 31212 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 31213 io_ctrl_ins.o_pmod[1]
|
|
.sym 31228 i_button_SB_LUT4_I3_O[0]
|
|
.sym 31229 i_button_SB_LUT4_I3_O[1]
|
|
.sym 31239 io_ctrl_ins.rf_pin_state[1]
|
|
.sym 31240 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 31241 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 31250 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 31251 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 31252 io_ctrl_ins.rf_pin_state[2]
|
|
.sym 31253 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
|
|
.sym 31269 w_rx_09_fifo_data[31]
|
|
.sym 31273 w_smi_data_output[5]
|
|
.sym 31302 w_rx_09_fifo_pulled_data[6]
|
|
.sym 31303 w_rx_09_fifo_pulled_data[22]
|
|
.sym 31304 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31305 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31306 w_rx_09_fifo_pulled_data[5]
|
|
.sym 31307 w_rx_09_fifo_pulled_data[21]
|
|
.sym 31308 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31309 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31312 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 31313 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
|
|
.sym 31316 i_smi_a2_SB_LUT4_I1_O[1]
|
|
.sym 31317 i_smi_soe_se$SB_IO_IN
|
|
.sym 31318 w_rx_09_fifo_pulled_data[7]
|
|
.sym 31319 w_rx_09_fifo_pulled_data[23]
|
|
.sym 31320 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31321 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31323 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31324 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31325 w_rx_09_fifo_empty
|
|
.sym 31326 w_rx_09_fifo_pulled_data[4]
|
|
.sym 31327 w_rx_09_fifo_pulled_data[20]
|
|
.sym 31328 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31329 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31332 w_rx_24_fifo_empty
|
|
.sym 31333 w_rx_09_fifo_empty
|
|
.sym 31334 rx_09_fifo.wr_addr[5]
|
|
.sym 31335 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[5]
|
|
.sym 31336 rx_09_fifo.wr_addr[8]
|
|
.sym 31337 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[8]
|
|
.sym 31338 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[10]
|
|
.sym 31339 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
|
|
.sym 31340 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
|
|
.sym 31341 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O[3]
|
|
.sym 31342 rx_09_fifo.wr_addr[7]
|
|
.sym 31343 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_I0_SB_LUT4_O_I1[7]
|
|
.sym 31344 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0]
|
|
.sym 31345 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
|
|
.sym 31346 smi_ctrl_ins.r_fifo_09_pull
|
|
.sym 31350 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[0]
|
|
.sym 31351 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[1]
|
|
.sym 31352 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 31353 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I1_O[3]
|
|
.sym 31355 smi_ctrl_ins.r_fifo_09_pull_1
|
|
.sym 31356 w_rx_09_fifo_empty
|
|
.sym 31357 smi_ctrl_ins.r_fifo_09_pull
|
|
.sym 31358 smi_ctrl_ins.w_fifo_09_pull_trigger
|
|
.sym 31363 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 31368 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 31372 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 31373 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 31375 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 31376 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 31377 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 31380 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 31381 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 31385 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 31386 i_ss$SB_IO_IN
|
|
.sym 31387 spi_if_ins.spi.r_rx_bit_count[0]
|
|
.sym 31388 spi_if_ins.spi.r_rx_bit_count[2]
|
|
.sym 31389 spi_if_ins.spi.r_rx_bit_count[1]
|
|
.sym 31390 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0]
|
|
.sym 31391 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[1]
|
|
.sym 31392 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 31393 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3]
|
|
.sym 31395 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 31399 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 31400 $PACKER_VCC_NET
|
|
.sym 31403 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 31404 $PACKER_VCC_NET
|
|
.sym 31405 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
|
|
.sym 31406 w_rx_09_fifo_pulled_data[12]
|
|
.sym 31407 w_rx_09_fifo_pulled_data[28]
|
|
.sym 31408 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31409 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31413 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 31415 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 31416 $PACKER_VCC_NET
|
|
.sym 31417 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 31418 spi_if_ins.spi.SCKr[2]
|
|
.sym 31419 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 31420 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 31421 spi_if_ins.spi.SCKr[1]
|
|
.sym 31425 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 31426 w_rx_09_fifo_pulled_data[15]
|
|
.sym 31427 w_rx_09_fifo_pulled_data[31]
|
|
.sym 31428 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31429 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31430 w_rx_09_fifo_pulled_data[13]
|
|
.sym 31431 w_rx_09_fifo_pulled_data[29]
|
|
.sym 31432 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31433 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31436 spi_if_ins.w_rx_data[5]
|
|
.sym 31437 spi_if_ins.w_rx_data[6]
|
|
.sym 31439 spi_if_ins.spi.r_tx_byte[3]
|
|
.sym 31440 spi_if_ins.spi.r_tx_byte[7]
|
|
.sym 31441 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 31443 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 31444 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
|
|
.sym 31445 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 31446 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
|
|
.sym 31447 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1]
|
|
.sym 31448 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 31449 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 31450 w_rx_09_fifo_pulled_data[14]
|
|
.sym 31451 w_rx_09_fifo_pulled_data[30]
|
|
.sym 31452 smi_ctrl_ins.int_cnt_09[4]
|
|
.sym 31453 smi_ctrl_ins.int_cnt_09[3]
|
|
.sym 31454 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[0]
|
|
.sym 31455 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[1]
|
|
.sym 31456 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[2]
|
|
.sym 31457 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1[3]
|
|
.sym 31458 spi_if_ins.spi.r_tx_byte[1]
|
|
.sym 31459 spi_if_ins.spi.r_tx_byte[5]
|
|
.sym 31460 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 31461 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 31463 spi_if_ins.spi.r_tx_byte[2]
|
|
.sym 31464 spi_if_ins.spi.r_tx_byte[6]
|
|
.sym 31465 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 31466 spi_if_ins.r_tx_byte[3]
|
|
.sym 31470 spi_if_ins.r_tx_byte[2]
|
|
.sym 31474 spi_if_ins.r_tx_byte[7]
|
|
.sym 31478 spi_if_ins.spi.r_tx_byte[0]
|
|
.sym 31479 spi_if_ins.spi.r_tx_byte[4]
|
|
.sym 31480 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
|
|
.sym 31481 spi_if_ins.spi.r_tx_bit_count[2]
|
|
.sym 31482 spi_if_ins.r_tx_byte[5]
|
|
.sym 31486 spi_if_ins.r_tx_byte[6]
|
|
.sym 31494 spi_if_ins.r_tx_byte[4]
|
|
.sym 31500 i_ss$SB_IO_IN
|
|
.sym 31501 spi_if_ins.r_tx_data_valid
|
|
.sym 31510 spi_if_ins.r_tx_byte[1]
|
|
.sym 31514 spi_if_ins.r_tx_byte[0]
|
|
.sym 31529 rx_24_fifo.rd_addr[0]
|
|
.sym 31530 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
|
|
.sym 31534 w_rx_24_fifo_pulled_data[5]
|
|
.sym 31535 w_rx_24_fifo_pulled_data[21]
|
|
.sym 31536 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31537 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 31538 w_rx_24_fifo_pulled_data[4]
|
|
.sym 31539 w_rx_24_fifo_pulled_data[20]
|
|
.sym 31540 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31541 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 31554 spi_if_ins.w_rx_data[0]
|
|
.sym 31558 spi_if_ins.w_rx_data[5]
|
|
.sym 31562 w_rx_24_fifo_pulled_data[7]
|
|
.sym 31563 w_rx_24_fifo_pulled_data[23]
|
|
.sym 31564 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 31566 w_rx_24_fifo_pulled_data[12]
|
|
.sym 31567 w_rx_24_fifo_pulled_data[28]
|
|
.sym 31568 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31569 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 31570 w_rx_24_fifo_pulled_data[13]
|
|
.sym 31571 w_rx_24_fifo_pulled_data[29]
|
|
.sym 31572 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31573 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 31574 spi_if_ins.w_rx_data[4]
|
|
.sym 31578 spi_if_ins.w_rx_data[6]
|
|
.sym 31582 spi_if_ins.w_rx_data[2]
|
|
.sym 31586 spi_if_ins.w_rx_data[3]
|
|
.sym 31594 w_rx_24_fifo_pulled_data[6]
|
|
.sym 31595 w_rx_24_fifo_pulled_data[22]
|
|
.sym 31596 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31597 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
|
|
.sym 31598 spi_if_ins.w_rx_data[2]
|
|
.sym 31602 spi_if_ins.w_rx_data[0]
|
|
.sym 31606 spi_if_ins.w_rx_data[4]
|
|
.sym 31610 w_rx_24_fifo_pulled_data[15]
|
|
.sym 31611 w_rx_24_fifo_pulled_data[31]
|
|
.sym 31612 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31613 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 31614 spi_if_ins.w_rx_data[1]
|
|
.sym 31618 w_rx_data[6]
|
|
.sym 31622 w_rx_data[0]
|
|
.sym 31626 w_rx_data[3]
|
|
.sym 31630 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 31631 io_ctrl_ins.pmod_dir_state[0]
|
|
.sym 31632 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 31633 io_ctrl_ins.debug_mode[0]
|
|
.sym 31634 w_rx_24_fifo_pulled_data[14]
|
|
.sym 31635 w_rx_24_fifo_pulled_data[30]
|
|
.sym 31636 smi_ctrl_ins.int_cnt_24[3]
|
|
.sym 31637 smi_ctrl_ins.int_cnt_24[4]
|
|
.sym 31638 w_rx_data[4]
|
|
.sym 31642 w_rx_data[5]
|
|
.sym 31646 w_rx_data[7]
|
|
.sym 31652 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 31653 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 31656 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 31657 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
|
|
.sym 31658 w_rx_data[5]
|
|
.sym 31662 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 31663 io_ctrl_ins.pmod_dir_state[7]
|
|
.sym 31664 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 31665 o_rx_h_tx_l$SB_IO_OUT
|
|
.sym 31666 w_rx_data[4]
|
|
.sym 31670 w_rx_data[0]
|
|
.sym 31674 w_rx_data[3]
|
|
.sym 31678 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 31679 io_ctrl_ins.pmod_dir_state[5]
|
|
.sym 31680 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 31681 io_ctrl_ins.o_pmod[5]
|
|
.sym 31682 w_rx_data[7]
|
|
.sym 31686 w_rx_data[2]
|
|
.sym 31698 w_rx_data[6]
|
|
.sym 31706 w_rx_data[1]
|
|
.sym 31710 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 31711 io_ctrl_ins.pmod_dir_state[6]
|
|
.sym 31712 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 31713 o_rx_h_tx_l_b$SB_IO_OUT
|
|
.sym 31720 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
|
|
.sym 31721 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
|
|
.sym 31734 io_ctrl_ins.o_pmod[6]
|
|
.sym 31735 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
|
|
.sym 31736 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 31737 i_config[3]$SB_IO_IN
|
|
.sym 31738 o_tr_vc1$SB_IO_OUT
|
|
.sym 31739 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
|
|
.sym 31740 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 31741 i_config[2]$SB_IO_IN
|
|
.sym 31744 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0]
|
|
.sym 31745 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
|
|
.sym 31874 spi_if_ins.spi.SCKr[1]
|
|
.sym 31882 i_sck$SB_IO_IN
|
|
.sym 31894 spi_if_ins.spi.SCKr[0]
|
|
.sym 31905 i_ss$SB_IO_IN
|
|
.sym 31914 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 31935 spi_if_ins.spi.SCKr[2]
|
|
.sym 31936 spi_if_ins.spi.SCKr[1]
|
|
.sym 31937 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 31939 spi_if_ins.r_tx_byte[7]
|
|
.sym 31940 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
|
|
.sym 31941 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
|
|
.sym 31953 w_rx_09_fifo_data[20]
|
|
.sym 31970 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 31974 i_mosi$SB_IO_IN
|
|
.sym 31978 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 31982 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 31986 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 31990 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 31996 i_ss$SB_IO_IN
|
|
.sym 31997 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
|
|
.sym 31998 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 32002 i_mosi$SB_IO_IN
|
|
.sym 32006 spi_if_ins.spi.r_temp_rx_byte[4]
|
|
.sym 32010 spi_if_ins.spi.r_temp_rx_byte[3]
|
|
.sym 32014 spi_if_ins.spi.r_temp_rx_byte[5]
|
|
.sym 32018 spi_if_ins.spi.r_temp_rx_byte[0]
|
|
.sym 32022 spi_if_ins.spi.r_temp_rx_byte[1]
|
|
.sym 32026 spi_if_ins.spi.r_temp_rx_byte[2]
|
|
.sym 32030 spi_if_ins.spi.r_temp_rx_byte[6]
|
|
.sym 32038 spi_if_ins.spi.r_rx_byte[7]
|
|
.sym 32042 spi_if_ins.spi.r_rx_byte[1]
|
|
.sym 32046 spi_if_ins.spi.r_rx_byte[2]
|
|
.sym 32050 spi_if_ins.spi.r_rx_byte[0]
|
|
.sym 32054 spi_if_ins.spi.r_rx_byte[3]
|
|
.sym 32058 spi_if_ins.spi.r_rx_byte[5]
|
|
.sym 32062 spi_if_ins.spi.r_rx_byte[4]
|
|
.sym 32066 spi_if_ins.w_rx_data[3]
|
|
.sym 32074 spi_if_ins.w_rx_data[1]
|
|
.sym 32086 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_I1_O[0]
|
|
.sym 32102 w_rx_data[0]
|
|
.sym 32114 w_rx_data[1]
|
|
.sym 32130 o_led0$SB_IO_OUT
|
|
.sym 32131 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 32132 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[2]
|
|
.sym 32133 io_ctrl_ins.mixer_en_state_SB_LUT4_I0_O[3]
|
|
.sym 32134 i_config[0]$SB_IO_IN
|
|
.sym 32135 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 32136 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
|
|
.sym 32137 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
|
|
.sym 32138 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 32139 io_ctrl_ins.pmod_dir_state[4]
|
|
.sym 32140 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 32141 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
|
|
.sym 32142 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
|
|
.sym 32143 io_ctrl_ins.pmod_dir_state[3]
|
|
.sym 32144 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[0]
|
|
.sym 32145 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
|
|
.sym 32146 i_config[1]$SB_IO_IN
|
|
.sym 32147 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
|
|
.sym 32148 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
|
|
.sym 32149 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
|
|
.sym 32162 w_rx_data[3]
|
|
.sym 32166 io_ctrl_ins.mixer_en_state
|
|
.sym 32167 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
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.sym 32168 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
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.sym 32169 io_ctrl_ins.o_pmod[0]
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.sym 32170 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
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.sym 32171 o_tr_vc1_b$SB_IO_OUT
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.sym 32172 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
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.sym 32173 io_ctrl_ins.o_pmod[4]
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.sym 32174 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
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.sym 32175 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1]
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.sym 32176 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
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.sym 32177 lvds_rx_24_inst.o_debug_state[0]
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.sym 32178 w_rx_data[5]
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.sym 32182 w_rx_data[4]
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.sym 32186 w_rx_data[0]
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.sym 32190 o_tr_vc2$SB_IO_OUT
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.sym 32191 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[0]
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.sym 32192 io_ctrl_ins.rx_h_state_SB_LUT4_I3_I2[2]
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.sym 32193 io_ctrl_ins.o_pmod[3]
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.sym 32198 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32199 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
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.sym 32200 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
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.sym 32201 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
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.sym 32206 w_rx_data[7]
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.sym 32214 w_rx_data[6]
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.sym 32222 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
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.sym 32223 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
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.sym 32224 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
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.sym 32225 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32226 io_ctrl_ins.rf_pin_state[3]
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.sym 32227 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
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.sym 32228 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
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.sym 32229 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32230 io_ctrl_ins.rf_pin_state[0]
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.sym 32231 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
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.sym 32232 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
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.sym 32233 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32430 spi_if_ins.spi.r_rx_done
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.sym 32452 spi_if_ins.spi.r3_rx_done
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.sym 32453 spi_if_ins.spi.r2_rx_done
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.sym 32466 spi_if_ins.spi.r2_rx_done
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.sym 32553 r_counter
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.sym 32675 lvds_rx_24_inst.r_phase_count[0]
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.sym 32679 lvds_rx_24_inst.r_phase_count[1]
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.sym 32680 $PACKER_VCC_NET
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.sym 32681 lvds_rx_24_inst.r_phase_count[0]
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.sym 32682 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
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.sym 32684 $PACKER_VCC_NET
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.sym 32685 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2]
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.sym 32689 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1]
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.sym 32690 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
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.sym 32691 lvds_rx_24_inst.o_debug_state[0]
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.sym 32692 lvds_rx_24_inst.o_debug_state[1]
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.sym 32693 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
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.sym 32697 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
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.sym 32698 lvds_rx_24_inst.o_debug_state[1]
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.sym 32699 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
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.sym 32700 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2]
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.sym 32701 lvds_rx_24_inst.o_debug_state[0]
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.sym 32702 lvds_rx_24_inst.o_debug_state[1]
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.sym 32703 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3]
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.sym 32704 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1]
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.sym 32705 lvds_rx_24_inst.o_debug_state[0]
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.sym 32707 io_ctrl_ins.rf_pin_state[7]
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.sym 32708 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32709 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
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.sym 32715 io_ctrl_ins.rf_pin_state[5]
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.sym 32716 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32717 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
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.sym 32723 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32724 io_ctrl_ins.rf_pin_state[4]
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.sym 32725 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
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.sym 32731 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
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.sym 32732 io_ctrl_ins.rf_pin_state[6]
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.sym 32733 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
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