kopia lustrzana https://github.com/cariboulabs/cariboulite
53 wiersze
1.3 KiB
Verilog
53 wiersze
1.3 KiB
Verilog
module lvds_tx (
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input i_rst_b,
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input i_ddr_clk,
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output [1:0] o_ddr_data,
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input i_fifo_empty,
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output o_fifo_read_clk,
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output reg o_fifo_pull,
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input [31:0] i_fifo_data,
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input i_tx_state,
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input i_sync_input,
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output [ 1:0] o_debug_state
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);
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// Internal Registers
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reg [ 4:0] r_phase_count;
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reg [31:0] r_fifo_data;
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// Initial conditions
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initial begin
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r_phase_count = 5'd31;
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end
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assign o_fifo_read_clk = i_ddr_clk;
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// Main Process / shift register
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always @(posedge i_ddr_clk) begin
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if (i_rst_b == 1'b0) begin
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o_fifo_pull <= 1'b0;
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r_phase_count <= 5'd31;
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r_fifo_data <= 32'b00000000000000000000000000000000;
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end else begin
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if (r_phase_count == 5'd3) begin
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o_fifo_pull <= ~i_fifo_empty;
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end else if (r_phase_count == 5'd1) begin
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if (i_tx_state) begin
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r_fifo_data <= i_fifo_data;
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end else begin
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r_fifo_data <= 32'b00000000000000000000000000000000;
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end
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o_fifo_pull <= 1'b0;
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end else begin
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o_fifo_pull <= 1'b0;
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end
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o_ddr_data <= r_fifo_data[r_phase_count:r_phase_count-1];
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r_phase_count <= r_phase_count - 2;
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end
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end
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endmodule
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