From f97f960be65541ec447be9b0aaf4ae7d0e1255c7 Mon Sep 17 00:00:00 2001 From: David Michaeli Date: Tue, 30 May 2023 14:47:23 +0000 Subject: [PATCH] added TX channel to the FPGA firmware. LVDS RX -> FIFO Slacks are borderline - need perform timing analysis on the RX FIFO IO (add pipeline?) Fixed reference to cariboulite_radio_get_native_mtu_size_samples --- firmware/h-files/cariboulite_fpga_firmware.h | 2806 +- firmware/io.pcf | 10 +- firmware/lvds_rx.v | 2 +- firmware/output.txt | 3286 ++ firmware/smi_ctrl.v | 1 + firmware/top.asc | 22983 ++++++----- firmware/top.bin | Bin 32220 -> 32220 bytes firmware/top.blif | 6145 +-- firmware/top.json | 31791 ++++++++++------ firmware/top.v | 54 +- software/libcariboulite/src/cariboulite.c | 2 +- .../src/cariboulite_fpga_firmware.h | 2806 +- .../libcariboulite/src/cariboulite_radio.h | 2 +- .../soapy_api/CaribouliteStreamFunctions.cpp | 2 +- 14 files changed, 43403 insertions(+), 26487 deletions(-) create mode 100644 firmware/output.txt diff --git a/firmware/h-files/cariboulite_fpga_firmware.h b/firmware/h-files/cariboulite_fpga_firmware.h index 854f650..ecd5628 100644 --- a/firmware/h-files/cariboulite_fpga_firmware.h +++ b/firmware/h-files/cariboulite_fpga_firmware.h @@ -17,15 +17,15 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2023-02-16 - * Time: 07:39:43 + * Date: 2023-05-30 + * Time: 14:43:52 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 43, - .tm_min = 39, - .tm_hour = 7, - .tm_mday = 16, - .tm_mon = 1, /* +1 */ + .tm_sec = 52, + .tm_min = 43, + .tm_hour = 14, + .tm_mday = 30, + .tm_mon = 4, /* +1 */ .tm_year = 123, /* +1900 */ }; @@ -38,379 +38,379 @@ uint8_t cariboulite_firmware[] = { 0xFF, 0x00, 0x00, 0xFF, 0x7E, 0xAA, 0x99, 0x7E, 0x51, 0x00, 0x01, 0x05, 0x92, 0x00, 0x20, 0x62, 0x01, 0x4B, 0x72, 0x00, 0x90, 0x82, 0x00, 0x00, 0x11, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x05, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0xE2, 0x00, 0x00, 0x20, 0x00, 0x00, 0x35, 0x90, 0x18, + 0xC1, 0x00, 0x04, 0x00, 0x00, 0xAA, 0x5D, 0x35, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x30, 0x03, 0x40, 0x20, 0x00, 0x00, 0x14, 0x05, 0x18, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x1C, 0x00, 0x01, 0x00, 0x04, 0xCC, 0xD0, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x30, 0x02, 0x80, + 0xF6, 0xA0, 0x70, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x24, 0x54, + 0x00, 0x09, 0x02, 0x00, 0x01, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x00, 0xB3, + 0x16, 0xE0, 0x18, 0xC0, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x08, + 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x2E, 0xE3, 0x80, 0x53, 0x00, 0x07, 0xE5, 0x80, 0x90, 0xBC, + 0x28, 0x10, 0x81, 0x90, 0x00, 0x00, 0x02, 0x30, 0x04, 0xCC, 0x1E, 0x10, 0xB0, 0x80, 0xC6, 0x43, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x1E, 0x00, 0xE0, 0x01, 0x80, 0x00, + 0x6E, 0x00, 0x00, 0x20, 0x02, 0x3C, 0x7B, 0x71, 0xE0, 0x02, 0xC0, 0x28, 0x10, 0x60, 0x00, 0x00, + 0x53, 0x00, 0xB3, 0x04, 0xA9, 0x00, 0x00, 0x28, 0x80, 0x00, 0x00, 0x21, 0xAD, 0x60, 0x00, 0x00, + 0x01, 0x00, 0x06, 0xCC, 0xE0, 0x00, 0x18, 0x04, 0x05, 0x25, 0xC3, 0x94, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x1A, 0xA1, 0x54, 0x08, 0x00, 0x06, 0x3C, 0x00, 0x00, 0x1A, 0x72, 0x80, 0xD0, 0x58, 0xB0, + 0x00, 0x40, 0x00, 0x00, 0x02, 0x00, 0xF3, 0x40, 0x70, 0x00, 0x52, 0x08, 0x9D, 0x40, 0x00, 0x08, + 0x01, 0xD0, 0x86, 0x00, 0x00, 0x84, 0x70, 0x00, 0x00, 0x00, 0x01, 0xE0, 0x09, 0x01, 0x2A, 0x50, + 0x64, 0x07, 0x00, 0x05, 0x25, 0x54, 0x00, 0xED, 0x00, 0x0C, 0x1C, 0x00, 0x00, 0x00, 0xA4, 0x25, + 0xB9, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0C, 0x00, 0x00, 0x05, 0x33, 0xE3, 0x57, 0x00, + 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x04, 0x0A, 0x03, 0xAC, 0x00, 0x00, 0x01, 0x00, 0x01, + 0x40, 0x08, 0x00, 0x00, 0x04, 0x00, 0x00, 0x02, 0x40, 0xDB, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x36, 0x06, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x00, 0x60, 0x51, 0x82, 0x00, 0x00, 0x00, 0x00, 0x40, 0x20, 0x05, 0x00, 0x01, 0x00, 0x00, 0x00, 0x62, 0x00, 0x3F, 0x72, 0x00, 0x80, 0x11, 0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x58, 0x40, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xB6, 0x33, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/firmware/io.pcf b/firmware/io.pcf index cf36525..9f6cf82 100644 --- a/firmware/io.pcf +++ b/firmware/io.pcf @@ -26,11 +26,11 @@ #set_frequency i_glob_clock 125 -#set_frequency w_clock_sys 64 -#set_frequency smi_ctrl_ins.soe_and_reset 16 -#set_frequency i_smi_swe_srw 16 -set_frequency lvds_clock_buf 64 -#set_frequency i_sck 5 +set_frequency w_clock_sys 64 +set_frequency smi_ctrl_ins.soe_and_reset 16 +set_frequency i_smi_swe_srw 16 +#set_frequency lvds_clock_buf 64 +set_frequency i_sck 5 # CLOCK set_io i_glob_clock A29 diff --git a/firmware/lvds_rx.v b/firmware/lvds_rx.v index 7b40d7b..a66429b 100644 --- a/firmware/lvds_rx.v +++ b/firmware/lvds_rx.v @@ -72,7 +72,7 @@ module lvds_rx ( if (r_phase_count == 3'b000) begin o_fifo_push <= ~i_fifo_full; r_state_if <= state_idle; - o_fifo_data <= {o_fifo_data[29:0], i_ddr_data[1], r_sync_input}; + o_fifo_data <= {o_fifo_data[29:0], i_ddr_data[1], 1'b0}; end else begin o_fifo_push <= 1'b0; r_phase_count <= r_phase_count - 1; diff --git a/firmware/output.txt b/firmware/output.txt new file mode 100644 index 0000000..dbf0706 --- /dev/null +++ b/firmware/output.txt @@ -0,0 +1,3286 @@ +yosys -p 'synth_ice40 -top top -json top.json -blif top.blif' -p 'ice40_opt' -p 'fsm_opt' top.v + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.26+1 (git sha1 b1a011138, gcc 10.2.1-6 -fPIC -Os) + + +-- Parsing `top.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: top.v +Parsing Verilog input from `top.v' to AST representation. +Warning: Yosys has only limited support for tri-state logic at the moment. (top.v:129) +Warning: Yosys has only limited support for tri-state logic at the moment. (top.v:540) +Storing AST representation for module `$abstract\spi_slave'. +Storing AST representation for module `$abstract\spi_if'. +Storing AST representation for module `$abstract\sys_ctrl'. +Storing AST representation for module `$abstract\io_ctrl'. +Storing AST representation for module `$abstract\smi_ctrl'. +Storing AST representation for module `$abstract\lvds_rx'. +Storing AST representation for module `$abstract\lvds_tx'. +Storing AST representation for module `$abstract\complex_fifo'. +Storing AST representation for module `$abstract\top'. +Successfully finished Verilog frontend. + +-- Running command `synth_ice40 -top top -json top.json -blif top.blif' -- + +2. Executing SYNTH_ICE40 pass. + +2.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_sim.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\SB_IO'. +Generating RTLIL representation for module `\SB_GB_IO'. +Generating RTLIL representation for module `\SB_GB'. +Generating RTLIL representation for module `\SB_LUT4'. +Generating RTLIL representation for module `\SB_CARRY'. +Generating RTLIL representation for module `\SB_DFF'. +Generating RTLIL representation for module `\SB_DFFE'. +Generating RTLIL representation for module `\SB_DFFSR'. +Generating RTLIL representation for module `\SB_DFFR'. +Generating RTLIL representation for module `\SB_DFFSS'. +Generating RTLIL representation for module `\SB_DFFS'. +Generating RTLIL representation for module `\SB_DFFESR'. +Generating RTLIL representation for module `\SB_DFFER'. +Generating RTLIL representation for module `\SB_DFFESS'. +Generating RTLIL representation for module `\SB_DFFES'. +Generating RTLIL representation for module `\SB_DFFN'. +Generating RTLIL representation for module `\SB_DFFNE'. +Generating RTLIL representation for module `\SB_DFFNSR'. +Generating RTLIL representation for module `\SB_DFFNR'. +Generating RTLIL representation for module `\SB_DFFNSS'. +Generating RTLIL representation for module `\SB_DFFNS'. +Generating RTLIL representation for module `\SB_DFFNESR'. +Generating RTLIL representation for module `\SB_DFFNER'. +Generating RTLIL representation for module `\SB_DFFNESS'. +Generating RTLIL representation for module `\SB_DFFNES'. +Generating RTLIL representation for module `\SB_RAM40_4K'. +Generating RTLIL representation for module `\SB_RAM40_4KNR'. +Generating RTLIL representation for module `\SB_RAM40_4KNW'. +Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. +Generating RTLIL representation for module `\ICESTORM_LC'. +Generating RTLIL representation for module `\SB_PLL40_CORE'. +Generating RTLIL representation for module `\SB_PLL40_PAD'. +Generating RTLIL representation for module `\SB_PLL40_2_PAD'. +Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. +Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. +Generating RTLIL representation for module `\SB_WARMBOOT'. +Generating RTLIL representation for module `\SB_SPRAM256KA'. +Generating RTLIL representation for module `\SB_HFOSC'. +Generating RTLIL representation for module `\SB_LFOSC'. +Generating RTLIL representation for module `\SB_RGBA_DRV'. +Generating RTLIL representation for module `\SB_LED_DRV_CUR'. +Generating RTLIL representation for module `\SB_RGB_DRV'. +Generating RTLIL representation for module `\SB_I2C'. +Generating RTLIL representation for module `\SB_SPI'. +Generating RTLIL representation for module `\SB_LEDDA_IP'. +Generating RTLIL representation for module `\SB_FILTER_50NS'. +Generating RTLIL representation for module `\SB_IO_I3C'. +Generating RTLIL representation for module `\SB_IO_OD'. +Generating RTLIL representation for module `\SB_MAC16'. +Generating RTLIL representation for module `\ICESTORM_RAM'. +Successfully finished Verilog frontend. + +2.2. Executing HIERARCHY pass (managing design hierarchy). + +2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. +Generating RTLIL representation for module `\top'. + +2.3.1. Analyzing design hierarchy.. +Top module: \top + +2.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\smi_ctrl'. +Generating RTLIL representation for module `\smi_ctrl'. +Warning: wire '\w_fifo_pull_trigger' is assigned in a block at smi_ctrl.v:122.13-122.71. +Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:181.13-181.40. +Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:197.25-197.52. +Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:205.25-205.52. +Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:217.21-217.48. +Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:231.21-231.48. +Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:241.25-241.52. +Warning: wire '\w_fifo_push_trigger' is assigned in a block at smi_ctrl.v:245.25-245.52. +smi_ctrl.v:174: Warning: Identifier `\swe_and_reset' is implicitly declared. +Parameter \ADDR_WIDTH = 10 +Parameter \DATA_WIDTH = 16 + +2.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\complex_fifo'. +Parameter \ADDR_WIDTH = 10 +Parameter \DATA_WIDTH = 16 +Generating RTLIL representation for module `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo'. + +2.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\lvds_tx'. +Generating RTLIL representation for module `\lvds_tx'. +Warning: wire '\o_ddr_data' is assigned in a block at lvds_tx.v:47.7-47.63. +Parameter \ADDR_WIDTH = 10 +Parameter \DATA_WIDTH = 16 +Found cached RTLIL representation for module `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo'. + +2.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\lvds_rx'. +Generating RTLIL representation for module `\lvds_rx'. +Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:40.7-40.26. +Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:52.11-52.32. +Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:67.11-67.30. +Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:73.13-73.40. +Warning: wire '\o_fifo_push' is assigned in a block at lvds_rx.v:77.13-77.34. + +2.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\io_ctrl'. +Generating RTLIL representation for module `\io_ctrl'. + +2.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\sys_ctrl'. +Generating RTLIL representation for module `\sys_ctrl'. + +2.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_if'. +Generating RTLIL representation for module `\spi_if'. + +2.3.9. Analyzing design hierarchy.. +Top module: \top +Used module: \smi_ctrl +Used module: $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo +Used module: \lvds_tx +Used module: \lvds_rx +Used module: \io_ctrl +Used module: \sys_ctrl +Used module: \spi_if + +2.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\spi_slave'. +Generating RTLIL representation for module `\spi_slave'. + +2.3.11. Analyzing design hierarchy.. +Top module: \top +Used module: \smi_ctrl +Used module: $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo +Used module: \lvds_tx +Used module: \lvds_rx +Used module: \io_ctrl +Used module: \sys_ctrl +Used module: \spi_if +Used module: \spi_slave + +2.3.12. Analyzing design hierarchy.. +Top module: \top +Used module: \smi_ctrl +Used module: $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo +Used module: \lvds_tx +Used module: \lvds_rx +Used module: \io_ctrl +Used module: \sys_ctrl +Used module: \spi_if +Used module: \spi_slave +Removing unused module `$abstract\top'. +Removing unused module `$abstract\complex_fifo'. +Removing unused module `$abstract\lvds_tx'. +Removing unused module `$abstract\lvds_rx'. +Removing unused module `$abstract\smi_ctrl'. +Removing unused module `$abstract\io_ctrl'. +Removing unused module `$abstract\sys_ctrl'. +Removing unused module `$abstract\spi_if'. +Removing unused module `$abstract\spi_slave'. +Removed 9 unused modules. + +2.4. Executing PROC pass (convert processes to netlists). + +2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\io_ctrl.$proc$io_ctrl.v:111$577'. +Cleaned up 1 empty switch. + +2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. +Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. +Marked 1 switch rules as full_case in process $proc$spi_slave.v:68$609 in module spi_slave. +Marked 1 switch rules as full_case in process $proc$spi_slave.v:48$603 in module spi_slave. +Marked 2 switch rules as full_case in process $proc$spi_slave.v:27$599 in module spi_slave. +Marked 7 switch rules as full_case in process $proc$spi_if.v:56$592 in module spi_if. +Marked 2 switch rules as full_case in process $proc$sys_ctrl.v:49$587 in module sys_ctrl. +Marked 2 switch rules as full_case in process $proc$io_ctrl.v:209$583 in module io_ctrl. +Marked 2 switch rules as full_case in process $proc$io_ctrl.v:111$577 in module io_ctrl. +Marked 4 switch rules as full_case in process $proc$lvds_rx.v:37$567 in module lvds_rx. +Marked 4 switch rules as full_case in process $proc$lvds_tx.v:28$558 in module lvds_tx. +Marked 2 switch rules as full_case in process $proc$complex_fifo.v:105$521 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. +Marked 2 switch rules as full_case in process $proc$complex_fifo.v:94$512 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. +Marked 2 switch rules as full_case in process $proc$complex_fifo.v:84$492 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. +Marked 2 switch rules as full_case in process $proc$complex_fifo.v:67$480 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. +Marked 2 switch rules as full_case in process $proc$complex_fifo.v:57$459 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. +Marked 2 switch rules as full_case in process $proc$complex_fifo.v:41$447 in module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. +Marked 1 switch rules as full_case in process $proc$smi_ctrl.v:253$433 in module smi_ctrl. +Marked 6 switch rules as full_case in process $proc$smi_ctrl.v:177$427 in module smi_ctrl. +Marked 1 switch rules as full_case in process $proc$smi_ctrl.v:144$419 in module smi_ctrl. +Marked 3 switch rules as full_case in process $proc$smi_ctrl.v:114$408 in module smi_ctrl. +Marked 2 switch rules as full_case in process $proc$smi_ctrl.v:58$396 in module smi_ctrl. +Marked 1 switch rules as full_case in process $proc$top.v:190$382 in module top. +Removed a total of 0 dead cases. + +2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 20 redundant assignments. +Promoted 60 assignments to connections. + +2.4.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'. + Set init value: \Q = 1'0 +Found init rule in `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'. + Set init value: \Q = 1'0 +Found init rule in `\spi_if.$proc$spi_if.v:0$598'. + Set init value: \state_if = 3'000 +Found init rule in `\lvds_rx.$proc$lvds_rx.v:0$576'. + Set init value: \r_state_if = 2'00 + Set init value: \r_phase_count = 3'111 +Found init rule in `\lvds_tx.$proc$lvds_tx.v:0$566'. + Set init value: \r_phase_count = 5'11111 + +2.4.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \S in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. +Found async reset \R in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. +Found async reset \S in `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. +Found async reset \R in `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. +Found async reset \S in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. +Found async reset \R in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. +Found async reset \S in `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. +Found async reset \R in `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. +Found async reset \i_rst_b in `\sys_ctrl.$proc$sys_ctrl.v:49$587'. +Found async reset \i_rst_b in `\io_ctrl.$proc$io_ctrl.v:209$583'. +Found async reset \i_rst_b in `\io_ctrl.$proc$io_ctrl.v:111$577'. +Found async reset \i_rst_b in `\lvds_rx.$proc$lvds_rx.v:37$567'. +Found async reset \i_rst_b in `\smi_ctrl.$proc$smi_ctrl.v:58$396'. + +2.4.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'. +Creating decoders for process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'. +Creating decoders for process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'. +Creating decoders for process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'. +Creating decoders for process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'. +Creating decoders for process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'. +Creating decoders for process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'. +Creating decoders for process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'. +Creating decoders for process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'. +Creating decoders for process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'. +Creating decoders for process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'. +Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'. +Creating decoders for process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'. +Creating decoders for process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'. +Creating decoders for process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'. +Creating decoders for process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'. +Creating decoders for process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'. +Creating decoders for process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'. +Creating decoders for process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'. +Creating decoders for process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'. +Creating decoders for process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. + 1/1: $0\Q[0:0] +Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'. +Creating decoders for process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'. +Creating decoders for process `\spi_slave.$proc$spi_slave.v:68$609'. + 1/3: $0\r_tx_bit_count[2:0] + 2/3: $0\r_tx_byte[7:0] + 3/3: $0\o_spi_miso[0:0] +Creating decoders for process `\spi_slave.$proc$spi_slave.v:62$607'. +Creating decoders for process `\spi_slave.$proc$spi_slave.v:48$603'. + 1/2: $0\o_rx_data_valid[0:0] + 2/2: $0\o_rx_byte[7:0] +Creating decoders for process `\spi_slave.$proc$spi_slave.v:27$599'. + 1/4: $0\r_rx_bit_count[2:0] + 2/4: $0\r_rx_done[0:0] + 3/4: $0\r_rx_byte[7:0] + 4/4: $0\r_temp_rx_byte[7:0] +Creating decoders for process `\spi_if.$proc$spi_if.v:0$598'. +Creating decoders for process `\spi_if.$proc$spi_if.v:56$592'. + 1/10: $3\o_ioc[4:0] + 2/10: $2\o_ioc[4:0] + 3/10: $1\o_ioc[4:0] + 4/10: $0\r_tx_byte[7:0] + 5/10: $0\r_tx_data_valid[0:0] + 6/10: $0\state_if[2:0] + 7/10: $0\o_load_cmd[0:0] + 8/10: $0\o_fetch_cmd[0:0] + 9/10: $0\o_cs[3:0] + 10/10: $0\o_data_in[7:0] +Creating decoders for process `\sys_ctrl.$proc$sys_ctrl.v:49$587'. + 1/4: $0\debug_smi_test[0:0] + 2/4: $0\debug_fifo_pull[0:0] + 3/4: $0\debug_fifo_push[0:0] + 4/4: $0\o_data_out[7:0] +Creating decoders for process `\io_ctrl.$proc$io_ctrl.v:209$583'. + 1/8: $0\tr_vc_2_state[0:0] + 2/8: $0\tr_vc_1_b_state[0:0] + 3/8: $0\tr_vc_1_state[0:0] + 4/8: $0\rx_h_b_state[0:0] + 5/8: $0\rx_h_state[0:0] + 6/8: $0\lna_tx_shutdown_state[0:0] + 7/8: $0\lna_rx_shutdown_state[0:0] + 8/8: $0\mixer_en_state[0:0] +Creating decoders for process `\io_ctrl.$proc$io_ctrl.v:111$577'. + 1/15: $0\o_data_out[7:0] [6] + 2/15: $0\o_data_out[7:0] [5] + 3/15: $0\o_data_out[7:0] [3] + 4/15: $0\o_data_out[7:0] [2] + 5/15: $0\o_data_out[7:0] [0] + 6/15: $0\o_data_out[7:0] [7] + 7/15: $0\o_data_out[7:0] [4] + 8/15: $0\o_data_out[7:0] [1] + 9/15: $0\pmod_state[7:0] + 10/15: $0\pmod_dir_state[7:0] + 11/15: $0\led1_state[0:0] + 12/15: $0\led0_state[0:0] + 13/15: $0\rf_mode[2:0] + 14/15: $0\debug_mode[1:0] + 15/15: $0\rf_pin_state[7:0] +Creating decoders for process `\lvds_rx.$proc$lvds_rx.v:0$576'. +Creating decoders for process `\lvds_rx.$proc$lvds_rx.v:37$567'. + 1/5: $0\r_sync_input[0:0] + 2/5: $0\r_phase_count[2:0] + 3/5: $0\r_state_if[1:0] + 4/5: $0\o_fifo_data[31:0] + 5/5: $0\o_fifo_push[0:0] +Creating decoders for process `\lvds_tx.$proc$lvds_tx.v:0$566'. +Creating decoders for process `\lvds_tx.$proc$lvds_tx.v:28$558'. + 1/4: $0\r_phase_count[4:0] + 2/4: $0\o_fifo_pull[0:0] + 3/4: $0\r_fifo_data[31:0] + 4/4: $0\o_ddr_data[1:0] +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + 1/24: $2$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$551 + 2/24: $2$memwr$\mem_i$complex_fifo.v:109$444_DATA[15:0]$550 + 3/24: $2$memwr$\mem_i$complex_fifo.v:109$444_ADDR[9:0]$549 + 4/24: $2$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$548 + 5/24: $2$memwr$\mem_q$complex_fifo.v:108$443_DATA[15:0]$547 + 6/24: $2$memwr$\mem_q$complex_fifo.v:108$443_ADDR[9:0]$546 + 7/24: $2$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$557 + 8/24: $2$memwr$\mem_i$complex_fifo.v:112$446_DATA[15:0]$556 + 9/24: $2$memwr$\mem_i$complex_fifo.v:112$446_ADDR[9:0]$555 + 10/24: $2$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$554 + 11/24: $2$memwr$\mem_q$complex_fifo.v:111$445_DATA[15:0]$553 + 12/24: $2$memwr$\mem_q$complex_fifo.v:111$445_ADDR[9:0]$552 + 13/24: $1$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$545 + 14/24: $1$memwr$\mem_i$complex_fifo.v:112$446_DATA[15:0]$544 + 15/24: $1$memwr$\mem_i$complex_fifo.v:112$446_ADDR[9:0]$543 + 16/24: $1$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$542 + 17/24: $1$memwr$\mem_q$complex_fifo.v:111$445_DATA[15:0]$541 + 18/24: $1$memwr$\mem_q$complex_fifo.v:111$445_ADDR[9:0]$540 + 19/24: $1$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$539 + 20/24: $1$memwr$\mem_i$complex_fifo.v:109$444_DATA[15:0]$538 + 21/24: $1$memwr$\mem_i$complex_fifo.v:109$444_ADDR[9:0]$537 + 22/24: $1$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$536 + 23/24: $1$memwr$\mem_q$complex_fifo.v:108$443_DATA[15:0]$535 + 24/24: $1$memwr$\mem_q$complex_fifo.v:108$443_ADDR[9:0]$534 +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'. + 1/6: $0\rd_data_o[31:0] [31:16] + 2/6: $0\rd_data_o[31:0] [15:0] + 3/6: $2$mem2bits$\mem_q$complex_fifo.v:99$441[15:0]$517 + 4/6: $1$mem2bits$\mem_i$complex_fifo.v:100$442[15:0]$516 + 5/6: $1$mem2bits$\mem_q$complex_fifo.v:99$441[15:0]$515 + 6/6: $2$mem2bits$\mem_i$complex_fifo.v:100$442[15:0]$518 +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. + 1/9: $2\gray_conv$func$complex_fifo.v:88$439.$result[9:0]$502 + 2/9: $2\gray_conv$func$complex_fifo.v:88$439.in[9:0]$503 + 3/9: $2\gray_conv$func$complex_fifo.v:90$440.in[9:0]$505 + 4/9: $2\gray_conv$func$complex_fifo.v:90$440.$result[9:0]$504 + 5/9: $0\empty_o[0:0] + 6/9: $1\gray_conv$func$complex_fifo.v:90$440.in[9:0]$501 + 7/9: $1\gray_conv$func$complex_fifo.v:90$440.$result[9:0]$500 + 8/9: $1\gray_conv$func$complex_fifo.v:88$439.in[9:0]$499 + 9/9: $1\gray_conv$func$complex_fifo.v:88$439.$result[9:0]$498 +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'. +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. + 1/7: $2\gray_conv$func$complex_fifo.v:74$438.$result[9:0]$486 + 2/7: $2\gray_conv$func$complex_fifo.v:74$438.in[9:0]$487 + 3/7: $1\gray_conv$func$complex_fifo.v:74$438.in[9:0]$485 + 4/7: $1\gray_conv$func$complex_fifo.v:74$438.$result[9:0]$484 + 5/7: $0\debug_buffer[31:0] + 6/7: $0\rd_addr_gray[9:0] + 7/7: $0\rd_addr[9:0] +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. + 1/9: $2\gray_conv$func$complex_fifo.v:61$436.$result[9:0]$469 + 2/9: $2\gray_conv$func$complex_fifo.v:61$436.in[9:0]$470 + 3/9: $2\gray_conv$func$complex_fifo.v:63$437.in[9:0]$472 + 4/9: $2\gray_conv$func$complex_fifo.v:63$437.$result[9:0]$471 + 5/9: $0\full_o[0:0] + 6/9: $1\gray_conv$func$complex_fifo.v:63$437.in[9:0]$468 + 7/9: $1\gray_conv$func$complex_fifo.v:63$437.$result[9:0]$467 + 8/9: $1\gray_conv$func$complex_fifo.v:61$436.in[9:0]$466 + 9/9: $1\gray_conv$func$complex_fifo.v:61$436.$result[9:0]$465 +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'. +Creating decoders for process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'. + 1/6: $2\gray_conv$func$complex_fifo.v:47$435.$result[9:0]$453 + 2/6: $2\gray_conv$func$complex_fifo.v:47$435.in[9:0]$454 + 3/6: $1\gray_conv$func$complex_fifo.v:47$435.in[9:0]$452 + 4/6: $1\gray_conv$func$complex_fifo.v:47$435.$result[9:0]$451 + 5/6: $0\wr_addr_gray[9:0] + 6/6: $0\wr_addr[9:0] +Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:253$433'. + 1/2: $0\r_fifo_push_1[0:0] + 2/2: $0\r_fifo_push[0:0] +Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + 1/14: $0\r_fifo_pushed_data[31:0] [13:8] + 2/14: $0\r_fifo_pushed_data[31:0] [7:0] + 3/14: $0\r_fifo_pushed_data[31:0] [15:14] + 4/14: $0\r_fifo_pushed_data[31:0] [16] + 5/14: $0\r_fifo_pushed_data[31:0] [17] + 6/14: $0\r_fifo_pushed_data[31:0] [24:18] + 7/14: $0\r_fifo_pushed_data[31:0] [29:25] + 8/14: $0\r_fifo_pushed_data[31:0] [31:30] + 9/14: $0\cond_tx_ctrl[0:0] + 10/14: $0\modem_tx_ctrl[0:0] + 11/14: $0\tx_reg_state[1:0] + 12/14: $0\w_fifo_push_trigger[0:0] + 13/14: $0\o_cond_tx[0:0] + 14/14: $0\o_tx_fifo_pushed_data[31:0] +Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:144$419'. + 1/2: $0\r_fifo_pull_1[0:0] + 2/2: $0\r_fifo_pull[0:0] +Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:114$408'. + 1/5: $0\r_fifo_pulled_data[31:0] + 2/5: $0\w_fifo_pull_trigger[0:0] + 3/5: $0\r_smi_test_count[7:0] + 4/5: $0\int_cnt_rx[4:0] + 5/5: $0\o_smi_data_out[7:0] +Creating decoders for process `\smi_ctrl.$proc$smi_ctrl.v:58$396'. + 1/7: $0\o_data_out[7:0] [7:4] + 2/7: $0\o_data_out[7:0] [3] + 3/7: $0\o_data_out[7:0] [2] + 4/7: $0\o_data_out[7:0] [1] + 5/7: $0\o_data_out[7:0] [0] + 6/7: $0\o_address_error[0:0] + 7/7: $0\r_channel[0:0] +Creating decoders for process `\top.$proc$top.v:190$382'. + 1/2: $0\r_counter[0:0] + 2/2: $0\r_tx_data[7:0] + +2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. + created $adff cell `$procdff$1747' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. + created $dff cell `$procdff$1748' with negative edge clock. +Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. + created $adff cell `$procdff$1749' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. + created $dff cell `$procdff$1750' with negative edge clock. +Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. + created $adff cell `$procdff$1751' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. + created $dff cell `$procdff$1752' with negative edge clock. +Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. + created $adff cell `$procdff$1753' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. + created $dff cell `$procdff$1754' with negative edge clock. +Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. + created $dff cell `$procdff$1755' with negative edge clock. +Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'. + created $dff cell `$procdff$1756' with negative edge clock. +Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. + created $adff cell `$procdff$1757' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. + created $dff cell `$procdff$1758' with positive edge clock. +Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. + created $adff cell `$procdff$1759' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. + created $dff cell `$procdff$1760' with positive edge clock. +Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. + created $adff cell `$procdff$1761' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. + created $dff cell `$procdff$1762' with positive edge clock. +Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. + created $adff cell `$procdff$1763' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. + created $dff cell `$procdff$1764' with positive edge clock. +Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. + created $dff cell `$procdff$1765' with positive edge clock. +Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'. + created $dff cell `$procdff$1766' with positive edge clock. +Creating register for signal `\spi_slave.\o_spi_miso' using process `\spi_slave.$proc$spi_slave.v:68$609'. + created $dff cell `$procdff$1767' with positive edge clock. +Creating register for signal `\spi_slave.\r_tx_byte' using process `\spi_slave.$proc$spi_slave.v:68$609'. + created $dff cell `$procdff$1768' with positive edge clock. +Creating register for signal `\spi_slave.\r_tx_bit_count' using process `\spi_slave.$proc$spi_slave.v:68$609'. + created $dff cell `$procdff$1769' with positive edge clock. +Creating register for signal `\spi_slave.\SCKr' using process `\spi_slave.$proc$spi_slave.v:62$607'. + created $dff cell `$procdff$1770' with positive edge clock. +Creating register for signal `\spi_slave.\o_rx_data_valid' using process `\spi_slave.$proc$spi_slave.v:48$603'. + created $dff cell `$procdff$1771' with positive edge clock. +Creating register for signal `\spi_slave.\o_rx_byte' using process `\spi_slave.$proc$spi_slave.v:48$603'. + created $dff cell `$procdff$1772' with positive edge clock. +Creating register for signal `\spi_slave.\r2_rx_done' using process `\spi_slave.$proc$spi_slave.v:48$603'. + created $dff cell `$procdff$1773' with positive edge clock. +Creating register for signal `\spi_slave.\r3_rx_done' using process `\spi_slave.$proc$spi_slave.v:48$603'. + created $dff cell `$procdff$1774' with positive edge clock. +Creating register for signal `\spi_slave.\r_rx_bit_count' using process `\spi_slave.$proc$spi_slave.v:27$599'. + created $dff cell `$procdff$1775' with positive edge clock. +Creating register for signal `\spi_slave.\r_temp_rx_byte' using process `\spi_slave.$proc$spi_slave.v:27$599'. + created $dff cell `$procdff$1776' with positive edge clock. +Creating register for signal `\spi_slave.\r_rx_byte' using process `\spi_slave.$proc$spi_slave.v:27$599'. + created $dff cell `$procdff$1777' with positive edge clock. +Creating register for signal `\spi_slave.\r_rx_done' using process `\spi_slave.$proc$spi_slave.v:27$599'. + created $dff cell `$procdff$1778' with positive edge clock. +Creating register for signal `\spi_if.\o_ioc' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1779' with positive edge clock. +Creating register for signal `\spi_if.\o_data_in' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1780' with positive edge clock. +Creating register for signal `\spi_if.\o_cs' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1781' with positive edge clock. +Creating register for signal `\spi_if.\o_fetch_cmd' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1782' with positive edge clock. +Creating register for signal `\spi_if.\o_load_cmd' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1783' with positive edge clock. +Creating register for signal `\spi_if.\state_if' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1784' with positive edge clock. +Creating register for signal `\spi_if.\r_tx_data_valid' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1785' with positive edge clock. +Creating register for signal `\spi_if.\r_tx_byte' using process `\spi_if.$proc$spi_if.v:56$592'. + created $dff cell `$procdff$1786' with positive edge clock. +Creating register for signal `\sys_ctrl.\o_data_out' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'. + created $adff cell `$procdff$1787' with positive edge clock and negative level reset. +Creating register for signal `\sys_ctrl.\debug_fifo_push' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'. + created $adff cell `$procdff$1788' with positive edge clock and negative level reset. +Creating register for signal `\sys_ctrl.\debug_fifo_pull' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'. + created $adff cell `$procdff$1789' with positive edge clock and negative level reset. +Creating register for signal `\sys_ctrl.\debug_smi_test' using process `\sys_ctrl.$proc$sys_ctrl.v:49$587'. + created $adff cell `$procdff$1790' with positive edge clock and negative level reset. +Creating register for signal `\io_ctrl.\mixer_en_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1793' with positive edge clock. +Creating register for signal `\io_ctrl.\lna_rx_shutdown_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1796' with positive edge clock. +Creating register for signal `\io_ctrl.\lna_tx_shutdown_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1799' with positive edge clock. +Creating register for signal `\io_ctrl.\rx_h_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1802' with positive edge clock. +Creating register for signal `\io_ctrl.\rx_h_b_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1805' with positive edge clock. +Creating register for signal `\io_ctrl.\tr_vc_1_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1808' with positive edge clock. +Creating register for signal `\io_ctrl.\tr_vc_1_b_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1811' with positive edge clock. +Creating register for signal `\io_ctrl.\tr_vc_2_state' using process `\io_ctrl.$proc$io_ctrl.v:209$583'. + created $dff cell `$procdff$1814' with positive edge clock. +Creating register for signal `\io_ctrl.\o_data_out' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $dff cell `$procdff$1817' with positive edge clock. +Creating register for signal `\io_ctrl.\debug_mode' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $adff cell `$procdff$1818' with positive edge clock and negative level reset. +Creating register for signal `\io_ctrl.\rf_mode' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $adff cell `$procdff$1819' with positive edge clock and negative level reset. +Creating register for signal `\io_ctrl.\led0_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $adff cell `$procdff$1820' with positive edge clock and negative level reset. +Creating register for signal `\io_ctrl.\led1_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $adff cell `$procdff$1821' with positive edge clock and negative level reset. +Creating register for signal `\io_ctrl.\pmod_dir_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $dff cell `$procdff$1824' with positive edge clock. +Creating register for signal `\io_ctrl.\pmod_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $dff cell `$procdff$1827' with positive edge clock. +Creating register for signal `\io_ctrl.\rf_pin_state' using process `\io_ctrl.$proc$io_ctrl.v:111$577'. + created $dff cell `$procdff$1830' with positive edge clock. +Creating register for signal `\lvds_rx.\o_fifo_push' using process `\lvds_rx.$proc$lvds_rx.v:37$567'. + created $adff cell `$procdff$1831' with positive edge clock and negative level reset. +Creating register for signal `\lvds_rx.\o_fifo_data' using process `\lvds_rx.$proc$lvds_rx.v:37$567'. + created $dff cell `$procdff$1834' with positive edge clock. +Creating register for signal `\lvds_rx.\r_state_if' using process `\lvds_rx.$proc$lvds_rx.v:37$567'. + created $adff cell `$procdff$1835' with positive edge clock and negative level reset. +Creating register for signal `\lvds_rx.\r_phase_count' using process `\lvds_rx.$proc$lvds_rx.v:37$567'. + created $adff cell `$procdff$1836' with positive edge clock and negative level reset. +Creating register for signal `\lvds_rx.\r_sync_input' using process `\lvds_rx.$proc$lvds_rx.v:37$567'. + created $adff cell `$procdff$1837' with positive edge clock and negative level reset. +Creating register for signal `\lvds_tx.\o_ddr_data' using process `\lvds_tx.$proc$lvds_tx.v:28$558'. + created $dff cell `$procdff$1838' with positive edge clock. +Creating register for signal `\lvds_tx.\o_fifo_pull' using process `\lvds_tx.$proc$lvds_tx.v:28$558'. + created $dff cell `$procdff$1839' with positive edge clock. +Creating register for signal `\lvds_tx.\r_phase_count' using process `\lvds_tx.$proc$lvds_tx.v:28$558'. + created $dff cell `$procdff$1840' with positive edge clock. +Creating register for signal `\lvds_tx.\r_fifo_data' using process `\lvds_tx.$proc$lvds_tx.v:28$558'. + created $dff cell `$procdff$1841' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:108$443_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1842' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:108$443_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1843' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:108$443_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1844' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:109$444_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1845' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:109$444_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1846' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:109$444_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1847' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:111$445_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1848' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:111$445_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1849' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_q$complex_fifo.v:111$445_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1850' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:112$446_ADDR' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1851' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:112$446_DATA' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1852' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$memwr$\mem_i$complex_fifo.v:112$446_EN' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. + created $dff cell `$procdff$1853' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_data_o' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'. + created $dff cell `$procdff$1854' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$mem2bits$\mem_q$complex_fifo.v:99$441' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'. + created $dff cell `$procdff$1855' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$mem2bits$\mem_i$complex_fifo.v:100$442' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'. + created $dff cell `$procdff$1856' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\empty_o' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. + created $dff cell `$procdff$1857' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:88$439.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. + created $dff cell `$procdff$1858' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:88$439.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. + created $dff cell `$procdff$1859' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:90$440.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. + created $dff cell `$procdff$1860' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:90$440.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. + created $dff cell `$procdff$1861' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr_gray_rd' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'. + created $dff cell `$procdff$1862' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr_gray_rd_r' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'. + created $dff cell `$procdff$1863' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. + created $dff cell `$procdff$1864' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr_gray' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. + created $dff cell `$procdff$1865' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\debug_buffer' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. + created $dff cell `$procdff$1866' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:74$438.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. + created $dff cell `$procdff$1867' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:74$438.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. + created $dff cell `$procdff$1868' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\full_o' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. + created $dff cell `$procdff$1869' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:61$436.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. + created $dff cell `$procdff$1870' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:61$436.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. + created $dff cell `$procdff$1871' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:63$437.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. + created $dff cell `$procdff$1872' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:63$437.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. + created $dff cell `$procdff$1873' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr_gray_wr' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'. + created $dff cell `$procdff$1874' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\rd_addr_gray_wr_r' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'. + created $dff cell `$procdff$1875' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'. + created $dff cell `$procdff$1876' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\wr_addr_gray' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'. + created $dff cell `$procdff$1877' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:47$435.$result' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'. + created $dff cell `$procdff$1878' with positive edge clock. +Creating register for signal `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.\gray_conv$func$complex_fifo.v:47$435.in' using process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'. + created $dff cell `$procdff$1879' with positive edge clock. +Creating register for signal `\smi_ctrl.\r_fifo_push' using process `\smi_ctrl.$proc$smi_ctrl.v:253$433'. + created $dff cell `$procdff$1880' with positive edge clock. +Creating register for signal `\smi_ctrl.\r_fifo_push_1' using process `\smi_ctrl.$proc$smi_ctrl.v:253$433'. + created $dff cell `$procdff$1881' with positive edge clock. +Creating register for signal `\smi_ctrl.\o_tx_fifo_pushed_data' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + created $dff cell `$procdff$1882' with negative edge clock. +Creating register for signal `\smi_ctrl.\o_cond_tx' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + created $dff cell `$procdff$1883' with negative edge clock. +Creating register for signal `\smi_ctrl.\r_fifo_pushed_data' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + created $dff cell `$procdff$1884' with negative edge clock. +Creating register for signal `\smi_ctrl.\tx_reg_state' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + created $dff cell `$procdff$1885' with negative edge clock. +Creating register for signal `\smi_ctrl.\modem_tx_ctrl' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + created $dff cell `$procdff$1886' with negative edge clock. +Creating register for signal `\smi_ctrl.\cond_tx_ctrl' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + created $dff cell `$procdff$1887' with negative edge clock. +Creating register for signal `\smi_ctrl.\w_fifo_push_trigger' using process `\smi_ctrl.$proc$smi_ctrl.v:177$427'. + created $dff cell `$procdff$1888' with negative edge clock. +Creating register for signal `\smi_ctrl.\r_fifo_pull' using process `\smi_ctrl.$proc$smi_ctrl.v:144$419'. + created $dff cell `$procdff$1889' with positive edge clock. +Creating register for signal `\smi_ctrl.\r_fifo_pull_1' using process `\smi_ctrl.$proc$smi_ctrl.v:144$419'. + created $dff cell `$procdff$1890' with positive edge clock. +Creating register for signal `\smi_ctrl.\o_smi_data_out' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'. + created $dff cell `$procdff$1891' with negative edge clock. +Creating register for signal `\smi_ctrl.\int_cnt_rx' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'. + created $dff cell `$procdff$1892' with negative edge clock. +Creating register for signal `\smi_ctrl.\r_smi_test_count' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'. + created $dff cell `$procdff$1893' with negative edge clock. +Creating register for signal `\smi_ctrl.\w_fifo_pull_trigger' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'. + created $dff cell `$procdff$1894' with negative edge clock. +Creating register for signal `\smi_ctrl.\r_fifo_pulled_data' using process `\smi_ctrl.$proc$smi_ctrl.v:114$408'. + created $dff cell `$procdff$1895' with negative edge clock. +Creating register for signal `\smi_ctrl.\o_data_out' using process `\smi_ctrl.$proc$smi_ctrl.v:58$396'. + created $dff cell `$procdff$1898' with positive edge clock. +Creating register for signal `\smi_ctrl.\o_address_error' using process `\smi_ctrl.$proc$smi_ctrl.v:58$396'. + created $adff cell `$procdff$1899' with positive edge clock and negative level reset. +Creating register for signal `\smi_ctrl.\r_channel' using process `\smi_ctrl.$proc$smi_ctrl.v:58$396'. + created $dff cell `$procdff$1902' with positive edge clock. +Creating register for signal `\top.\r_counter' using process `\top.$proc$top.v:190$382'. + created $dff cell `$procdff$1903' with positive edge clock. +Creating register for signal `\top.\r_tx_data' using process `\top.$proc$top.v:190$382'. + created $dff cell `$procdff$1904' with positive edge clock. + +2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$244'. +Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. +Removing empty process `SB_DFFNES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1414$241'. +Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$240'. +Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. +Removing empty process `SB_DFFNESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1353$234'. +Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$233'. +Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. +Removing empty process `SB_DFFNER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1273$230'. +Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$229'. +Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. +Removing empty process `SB_DFFNESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1212$223'. +Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$222'. +Removing empty process `SB_DFFNS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1138$220'. +Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$219'. +Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. +Removing empty process `SB_DFFNSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1088$217'. +Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$216'. +Removing empty process `SB_DFFNR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1017$214'. +Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$213'. +Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. +Removing empty process `SB_DFFNSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:967$211'. +Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$210'. +Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. +Removing empty process `SB_DFFNE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:922$209'. +Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$208'. +Removing empty process `SB_DFFN.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:882$207'. +Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$206'. +Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. +Removing empty process `SB_DFFES.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:803$203'. +Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$202'. +Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. +Removing empty process `SB_DFFESS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:742$196'. +Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$195'. +Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. +Removing empty process `SB_DFFER.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:662$192'. +Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$191'. +Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. +Removing empty process `SB_DFFESR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:601$185'. +Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$184'. +Removing empty process `SB_DFFS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:527$182'. +Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$181'. +Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. +Removing empty process `SB_DFFSS.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:477$179'. +Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$178'. +Removing empty process `SB_DFFR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:406$176'. +Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$175'. +Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. +Removing empty process `SB_DFFSR.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:356$173'. +Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$172'. +Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. +Removing empty process `SB_DFFE.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:311$171'. +Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:0$170'. +Removing empty process `SB_DFF.$proc$/usr/local/bin/../share/yosys/ice40/cells_sim.v:271$169'. +Found and cleaned up 3 empty switches in `\spi_slave.$proc$spi_slave.v:68$609'. +Removing empty process `spi_slave.$proc$spi_slave.v:68$609'. +Removing empty process `spi_slave.$proc$spi_slave.v:62$607'. +Found and cleaned up 1 empty switch in `\spi_slave.$proc$spi_slave.v:48$603'. +Removing empty process `spi_slave.$proc$spi_slave.v:48$603'. +Found and cleaned up 3 empty switches in `\spi_slave.$proc$spi_slave.v:27$599'. +Removing empty process `spi_slave.$proc$spi_slave.v:27$599'. +Removing empty process `spi_if.$proc$spi_if.v:0$598'. +Found and cleaned up 7 empty switches in `\spi_if.$proc$spi_if.v:56$592'. +Removing empty process `spi_if.$proc$spi_if.v:56$592'. +Found and cleaned up 5 empty switches in `\sys_ctrl.$proc$sys_ctrl.v:49$587'. +Removing empty process `sys_ctrl.$proc$sys_ctrl.v:49$587'. +Found and cleaned up 3 empty switches in `\io_ctrl.$proc$io_ctrl.v:209$583'. +Removing empty process `io_ctrl.$proc$io_ctrl.v:209$583'. +Found and cleaned up 5 empty switches in `\io_ctrl.$proc$io_ctrl.v:111$577'. +Removing empty process `io_ctrl.$proc$io_ctrl.v:111$577'. +Removing empty process `lvds_rx.$proc$lvds_rx.v:0$576'. +Found and cleaned up 5 empty switches in `\lvds_rx.$proc$lvds_rx.v:37$567'. +Removing empty process `lvds_rx.$proc$lvds_rx.v:37$567'. +Removing empty process `lvds_tx.$proc$lvds_tx.v:0$566'. +Found and cleaned up 4 empty switches in `\lvds_tx.$proc$lvds_tx.v:28$558'. +Removing empty process `lvds_tx.$proc$lvds_tx.v:28$558'. +Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:105$521'. +Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:94$512'. +Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:84$492'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:79$491'. +Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:67$480'. +Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:57$459'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:52$458'. +Found and cleaned up 2 empty switches in `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'. +Removing empty process `$paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo.$proc$complex_fifo.v:41$447'. +Found and cleaned up 1 empty switch in `\smi_ctrl.$proc$smi_ctrl.v:253$433'. +Removing empty process `smi_ctrl.$proc$smi_ctrl.v:253$433'. +Found and cleaned up 6 empty switches in `\smi_ctrl.$proc$smi_ctrl.v:177$427'. +Removing empty process `smi_ctrl.$proc$smi_ctrl.v:177$427'. +Found and cleaned up 1 empty switch in `\smi_ctrl.$proc$smi_ctrl.v:144$419'. +Removing empty process `smi_ctrl.$proc$smi_ctrl.v:144$419'. +Found and cleaned up 4 empty switches in `\smi_ctrl.$proc$smi_ctrl.v:114$408'. +Removing empty process `smi_ctrl.$proc$smi_ctrl.v:114$408'. +Found and cleaned up 5 empty switches in `\smi_ctrl.$proc$smi_ctrl.v:58$396'. +Removing empty process `smi_ctrl.$proc$smi_ctrl.v:58$396'. +Found and cleaned up 2 empty switches in `\top.$proc$top.v:190$382'. +Removing empty process `top.$proc$top.v:190$382'. +Cleaned up 85 empty switches. + +2.4.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module spi_slave. + +Optimizing module spi_if. + +Optimizing module sys_ctrl. + +Optimizing module io_ctrl. + +Optimizing module lvds_rx. + +Optimizing module lvds_tx. + +Optimizing module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. + +Optimizing module smi_ctrl. + +Optimizing module top. + + +2.5. Executing FLATTEN pass (flatten design). +Deleting now unused module spi_slave. +Deleting now unused module spi_if. +Deleting now unused module sys_ctrl. +Deleting now unused module io_ctrl. +Deleting now unused module lvds_rx. +Deleting now unused module lvds_tx. +Deleting now unused module $paramod$88900497bc51eac526f23d116d59d880b810f9af\complex_fifo. +Deleting now unused module smi_ctrl. + + +2.6. Executing TRIBUF pass. + +2.7. Executing DEMINOUT pass (demote inout ports to input or output). +Demoting inout port top.io_pmod to input. + +2.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 208 unused cells and 969 unused wires. + + +2.10. Executing CHECK pass (checking for obvious problems). +Checking module top... +Found and reported 0 problems. + +2.11. Executing OPT pass (performing simple optimizations). + +2.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. + +Removed a total of 158 cells. + +2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1214. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1232. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1250. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1256. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1262. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1268. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1274. + dead port 2/2 on $mux $flatten\rx_fifo.$procmux$1280. + dead port 2/2 on $mux $flatten\spi_if_ins.$procmux$707. + dead port 2/2 on $mux $flatten\spi_if_ins.$procmux$710. + dead port 2/2 on $mux $flatten\spi_if_ins.$procmux$716. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1214. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1232. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1250. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1256. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1262. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1268. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1274. + dead port 2/2 on $mux $flatten\tx_fifo.$procmux$1280. +Removed 19 multiplexer ports. + + +2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. + New ctrl vector for $pmux cell $flatten\lvds_rx_09_inst.$procmux$1180: { $auto$opt_reduce.cc:134:opt_pmux$1912 $flatten\lvds_rx_09_inst.$procmux$1144_CMP } + New ctrl vector for $pmux cell $flatten\lvds_rx_24_inst.$procmux$1180: { $auto$opt_reduce.cc:134:opt_pmux$1914 $flatten\lvds_rx_24_inst.$procmux$1144_CMP } + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$869: { $auto$opt_reduce.cc:134:opt_pmux$1918 $auto$opt_reduce.cc:134:opt_pmux$1916 } + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$941: { $auto$opt_reduce.cc:134:opt_pmux$1922 $auto$opt_reduce.cc:134:opt_pmux$1920 } + Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1283: + Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$557, Y=$flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 + New ports: A=1'0, B=1'1, Y=$flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] + New connections: $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [15:1] = { $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] } + Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1292: + Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$554, Y=$flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 + New ports: A=1'0, B=1'1, Y=$flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] + New connections: $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [15:1] = { $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] } + Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1301: + Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$551, Y=$flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527 + New connections: $flatten\rx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527 = 16'0000000000000000 + Consolidated identical input bits for $mux cell $flatten\rx_fifo.$procmux$1310: + Old ports: A=16'0000000000000000, B=$flatten\rx_fifo.$2$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$548, Y=$flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524 + New connections: $flatten\rx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524 = 16'0000000000000000 + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$881: { $auto$opt_reduce.cc:134:opt_pmux$1926 $auto$opt_reduce.cc:134:opt_pmux$1924 } + New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1614: { $flatten\smi_ctrl_ins.$procmux$1557_CMP $auto$opt_reduce.cc:134:opt_pmux$1928 $flatten\smi_ctrl_ins.$procmux$1595_CMP } + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$893: { $auto$opt_reduce.cc:134:opt_pmux$1932 $auto$opt_reduce.cc:134:opt_pmux$1930 } + New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1687: $auto$opt_reduce.cc:134:opt_pmux$1934 + New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1695: $auto$opt_reduce.cc:134:opt_pmux$1936 + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$905: { $auto$opt_reduce.cc:134:opt_pmux$1940 $auto$opt_reduce.cc:134:opt_pmux$1938 } + New ctrl vector for $pmux cell $flatten\spi_if_ins.$procmux$758: { $flatten\spi_if_ins.$procmux$706_CMP $auto$opt_reduce.cc:134:opt_pmux$1942 } + New ctrl vector for $pmux cell $flatten\spi_if_ins.$procmux$778: { $flatten\spi_if_ins.$procmux$760_CMP $auto$opt_reduce.cc:134:opt_pmux$1944 } + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$917: { $auto$opt_reduce.cc:134:opt_pmux$1948 $auto$opt_reduce.cc:134:opt_pmux$1946 } + New ctrl vector for $pmux cell $flatten\sys_ctrl_ins.$procmux$857: { $auto$opt_reduce.cc:134:opt_pmux$1950 $flatten\io_ctrl_ins.$procmux$1000_CMP } + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$929: { $auto$opt_reduce.cc:134:opt_pmux$1954 $auto$opt_reduce.cc:134:opt_pmux$1952 } + New ctrl vector for $pmux cell $flatten\io_ctrl_ins.$procmux$953: { $auto$opt_reduce.cc:134:opt_pmux$1958 $auto$opt_reduce.cc:134:opt_pmux$1956 } + Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1283: + Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$557, Y=$flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 + New ports: A=1'0, B=1'1, Y=$flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] + New connections: $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [15:1] = { $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:112$446_EN[15:0]$533 [0] } + Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1292: + Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$554, Y=$flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 + New ports: A=1'0, B=1'1, Y=$flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] + New connections: $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [15:1] = { $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:111$445_EN[15:0]$530 [0] } + Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1301: + Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$551, Y=$flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527 + New connections: $flatten\tx_fifo.$0$memwr$\mem_i$complex_fifo.v:109$444_EN[15:0]$527 = 16'0000000000000000 + Consolidated identical input bits for $mux cell $flatten\tx_fifo.$procmux$1310: + Old ports: A=16'0000000000000000, B=$flatten\tx_fifo.$2$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$548, Y=$flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524 + New connections: $flatten\tx_fifo.$0$memwr$\mem_q$complex_fifo.v:108$443_EN[15:0]$524 = 16'0000000000000000 + Optimizing cells in module \top. +Performed a total of 24 changes. + +2.11.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. + +Removed a total of 12 cells. + +2.11.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 202 unused wires. + + +2.11.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.11.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. + New ctrl vector for $pmux cell $flatten\smi_ctrl_ins.$procmux$1614: { $auto$opt_reduce.cc:134:opt_pmux$1928 $auto$opt_reduce.cc:134:opt_pmux$1960 } + Optimizing cells in module \top. +Performed a total of 1 changes. + +2.11.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.11.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.11.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.11.16. Rerunning OPT passes. (Maybe there is more to do..) + +2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.11.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.11.20. Executing OPT_DFF pass (perform DFF optimizations). + +2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.11.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.11.23. Finished OPT passes. (There is nothing left to do.) + +2.12. Executing FSM pass (extract and optimize FSM). + +2.12.1. Executing FSM_DETECT pass (finding FSMs in design). +Not marking top.lvds_rx_09_inst.r_state_if as FSM state register: + Register has an initialization value. +Not marking top.lvds_rx_24_inst.r_state_if as FSM state register: + Register has an initialization value. +Found FSM state register top.smi_ctrl_ins.tx_reg_state. +Not marking top.spi_if_ins.o_cs as FSM state register: + Users of register don't seem to benefit from recoding. +Not marking top.spi_if_ins.state_if as FSM state register: + Register has an initialization value. +Not marking top.sys_ctrl_ins.o_data_out as FSM state register: + Users of register don't seem to benefit from recoding. + +2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\smi_ctrl_ins.tx_reg_state' from module `\top'. + found $dff cell for state register: $flatten\smi_ctrl_ins.$procdff$1885 + root of input selection tree: $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0] + found reset state: 2'00 (guessed from mux tree) + found ctrl input: \i_rst_b + found state code: 2'00 + found ctrl input: $flatten\smi_ctrl_ins.$procmux$1595_CMP + found ctrl input: $flatten\smi_ctrl_ins.$procmux$1506_CMP + found ctrl input: $flatten\smi_ctrl_ins.$procmux$1546_CMP + found ctrl input: $flatten\smi_ctrl_ins.$procmux$1557_CMP + found ctrl input: \smi_ctrl_ins.i_smi_data_in [7] + found state code: 2'11 + found state code: 2'10 + found state code: 2'01 + found ctrl output: $flatten\smi_ctrl_ins.$procmux$1595_CMP + found ctrl output: $flatten\smi_ctrl_ins.$procmux$1557_CMP + found ctrl output: $flatten\smi_ctrl_ins.$procmux$1546_CMP + found ctrl output: $flatten\smi_ctrl_ins.$procmux$1506_CMP + ctrl inputs: { \smi_ctrl_ins.i_smi_data_in [7] \i_rst_b } + ctrl outputs: { $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0] $flatten\smi_ctrl_ins.$procmux$1506_CMP $flatten\smi_ctrl_ins.$procmux$1546_CMP $flatten\smi_ctrl_ins.$procmux$1557_CMP $flatten\smi_ctrl_ins.$procmux$1595_CMP } + transition: 2'00 2'-0 -> 2'00 6'000010 + transition: 2'00 2'01 -> 2'00 6'000010 + transition: 2'00 2'11 -> 2'01 6'010010 + transition: 2'10 2'-0 -> 2'00 6'001000 + transition: 2'10 2'01 -> 2'11 6'111000 + transition: 2'10 2'11 -> 2'00 6'001000 + transition: 2'01 2'-0 -> 2'00 6'000100 + transition: 2'01 2'01 -> 2'10 6'100100 + transition: 2'01 2'11 -> 2'00 6'000100 + transition: 2'11 2'-0 -> 2'00 6'000001 + transition: 2'11 2'-1 -> 2'00 6'000001 + +2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top'. + Merging pattern 2'-0 and 2'-1 from group (3 0 6'000001). + Merging pattern 2'-1 and 2'-0 from group (3 0 6'000001). + +2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 10 unused cells and 10 unused wires. + + +2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top'. + Removing unused output signal $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0] [0]. + Removing unused output signal $flatten\smi_ctrl_ins.$0\tx_reg_state[1:0] [1]. + +2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 00 -> ---1 + 10 -> --1- + 01 -> -1-- + 11 -> 1--- + +2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `top': +------------------------------------- + + Information on FSM $fsm$\smi_ctrl_ins.tx_reg_state$1961 (\smi_ctrl_ins.tx_reg_state): + + Number of input signals: 2 + Number of output signals: 4 + Number of state bits: 4 + + Input signals: + 0: \i_rst_b + 1: \smi_ctrl_ins.i_smi_data_in [7] + + Output signals: + 0: $flatten\smi_ctrl_ins.$procmux$1595_CMP + 1: $flatten\smi_ctrl_ins.$procmux$1557_CMP + 2: $flatten\smi_ctrl_ins.$procmux$1546_CMP + 3: $flatten\smi_ctrl_ins.$procmux$1506_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 2'-0 -> 0 4'0010 + 1: 0 2'01 -> 0 4'0010 + 2: 0 2'11 -> 2 4'0010 + 3: 1 2'-0 -> 0 4'1000 + 4: 1 2'11 -> 0 4'1000 + 5: 1 2'01 -> 3 4'1000 + 6: 2 2'-0 -> 0 4'0100 + 7: 2 2'11 -> 0 4'0100 + 8: 2 2'01 -> 1 4'0100 + 9: 3 2'-- -> 0 4'0001 + +------------------------------------- + +2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\smi_ctrl_ins.tx_reg_state$1961' from module `\top'. + +2.13. Executing OPT pass (performing simple optimizations). + +2.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. + +Removed a total of 4 cells. + +2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.13.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $procdff$1904 ($dff) from module top (D = $procmux$1738_Y, Q = \r_tx_data). +Adding SRST signal on $procdff$1903 ($dff) from module top (D = $logic_not$top.v:194$384_Y, Q = \r_counter, rval = 1'0). +Adding SRST signal on $flatten\tx_fifo.$procdff$1877 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1484_Y, Q = \tx_fifo.wr_addr_gray, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2002 ($sdff) from module top (D = { $flatten\tx_fifo.$add$complex_fifo.v:46$455_Y [9] $flatten\tx_fifo.$xor$complex_fifo.v:37$457_Y }, Q = \tx_fifo.wr_addr_gray). +Adding SRST signal on $flatten\tx_fifo.$procdff$1876 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1490_Y, Q = \tx_fifo.wr_addr, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2004 ($sdff) from module top (D = $flatten\tx_fifo.$add$complex_fifo.v:46$455_Y, Q = \tx_fifo.wr_addr). +Adding SRST signal on $flatten\tx_fifo.$procdff$1869 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1448_Y, Q = \tx_fifo.full_o, rval = 1'0). +Adding SRST signal on $flatten\tx_fifo.$procdff$1865 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1412_Y, Q = \tx_fifo.rd_addr_gray, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2007 ($sdff) from module top (D = { $flatten\tx_fifo.$add$complex_fifo.v:73$488_Y [9] $flatten\tx_fifo.$xor$complex_fifo.v:37$490_Y }, Q = \tx_fifo.rd_addr_gray). +Adding SRST signal on $flatten\tx_fifo.$procdff$1864 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1418_Y, Q = \tx_fifo.rd_addr, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2009 ($sdff) from module top (D = $flatten\tx_fifo.$add$complex_fifo.v:73$488_Y, Q = \tx_fifo.rd_addr). +Adding SRST signal on $flatten\tx_fifo.$procdff$1857 ($dff) from module top (D = $flatten\tx_fifo.$procmux$1373_Y, Q = \tx_fifo.empty_o, rval = 1'1). +Adding EN signal on $flatten\tx_fifo.$procdff$1854 ($dff) from module top (D = { $flatten\tx_fifo.$memrd$\mem_i$complex_fifo.v:100$520_DATA $flatten\tx_fifo.$memrd$\mem_q$complex_fifo.v:99$519_DATA }, Q = \tx_fifo.rd_data_o). +Adding EN signal on $flatten\sys_ctrl_ins.$procdff$1787 ($adff) from module top (D = $flatten\sys_ctrl_ins.$procmux$857_Y, Q = \sys_ctrl_ins.o_data_out). +Adding SRST signal on $flatten\spi_if_ins.\spi.$procdff$1778 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$procmux$687_Y, Q = \spi_if_ins.spi.r_rx_done, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$2018 ($sdff) from module top (D = $flatten\spi_if_ins.\spi.$procmux$687_Y, Q = \spi_if_ins.spi.r_rx_done). +Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1777 ($dff) from module top (D = { \spi_if_ins.spi.r_temp_rx_byte [6:0] \i_mosi }, Q = \spi_if_ins.spi.r_rx_byte). +Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1776 ($dff) from module top (D = { \spi_if_ins.spi.r_temp_rx_byte [6:0] \i_mosi }, Q = \spi_if_ins.spi.r_temp_rx_byte). +Adding SRST signal on $flatten\spi_if_ins.\spi.$procdff$1775 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600_Y [2:0], Q = \spi_if_ins.spi.r_rx_bit_count, rval = 3'000). +Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1772 ($dff) from module top (D = \spi_if_ins.spi.r_rx_byte, Q = \spi_if_ins.spi.o_rx_byte). +Adding SRST signal on $flatten\spi_if_ins.\spi.$procdff$1769 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$procmux$658_Y, Q = \spi_if_ins.spi.r_tx_bit_count, rval = 3'110). +Adding EN signal on $auto$ff.cc:266:slice$2030 ($sdff) from module top (D = $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611_Y [2:0], Q = \spi_if_ins.spi.r_tx_bit_count). +Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1768 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$0\r_tx_byte[7:0], Q = \spi_if_ins.spi.r_tx_byte). +Adding EN signal on $flatten\spi_if_ins.\spi.$procdff$1767 ($dff) from module top (D = $flatten\spi_if_ins.\spi.$0\o_spi_miso[0:0], Q = \spi_if_ins.spi.o_spi_miso). +Adding EN signal on $flatten\spi_if_ins.$procdff$1786 ($dff) from module top (D = \r_tx_data, Q = \spi_if_ins.r_tx_byte). +Adding EN signal on $flatten\spi_if_ins.$procdff$1785 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$745_Y, Q = \spi_if_ins.r_tx_data_valid). +Adding SRST signal on $flatten\spi_if_ins.$procdff$1784 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$765_Y, Q = \spi_if_ins.state_if, rval = 3'000). +Adding EN signal on $auto$ff.cc:266:slice$2056 ($sdff) from module top (D = $flatten\spi_if_ins.$procmux$765_Y, Q = \spi_if_ins.state_if). +Adding EN signal on $flatten\spi_if_ins.$procdff$1783 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$782_Y, Q = \spi_if_ins.o_load_cmd). +Adding EN signal on $flatten\spi_if_ins.$procdff$1782 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$798_Y, Q = \spi_if_ins.o_fetch_cmd). +Adding EN signal on $flatten\spi_if_ins.$procdff$1781 ($dff) from module top (D = $flatten\spi_if_ins.$procmux$807_Y, Q = \spi_if_ins.o_cs). +Adding EN signal on $flatten\spi_if_ins.$procdff$1780 ($dff) from module top (D = \spi_if_ins.spi.o_rx_byte, Q = \spi_if_ins.o_data_in). +Adding EN signal on $flatten\spi_if_ins.$procdff$1779 ($dff) from module top (D = \spi_if_ins.spi.o_rx_byte [4:0], Q = \spi_if_ins.o_ioc). +Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1902 ($dff) from module top (D = \spi_if_ins.o_data_in [0], Q = \smi_ctrl_ins.r_channel). +Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1898 ($dff) from module top (D = 5'00000, Q = \smi_ctrl_ins.o_data_out [7:3]). +Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1898 ($dff) from module top (D = { $flatten\smi_ctrl_ins.$procmux$1703_Y $flatten\smi_ctrl_ins.$procmux$1711_Y $flatten\smi_ctrl_ins.$procmux$1719_Y }, Q = \smi_ctrl_ins.o_data_out [2:0]). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1895 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1651_Y, Q = \smi_ctrl_ins.r_fifo_pulled_data, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$2104 ($sdff) from module top (D = \rx_fifo.rd_data_o, Q = \smi_ctrl_ins.r_fifo_pulled_data). +Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1894 ($dff) from module top (D = $flatten\smi_ctrl_ins.$eq$smi_ctrl.v:122$410_Y, Q = \smi_ctrl_ins.w_fifo_pull_trigger). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1892 ($dff) from module top (D = $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416_Y [4:0], Q = \smi_ctrl_ins.int_cnt_rx, rval = 5'00000). +Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1891 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1681_Y, Q = \smi_ctrl_ins.o_smi_data_out). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1890 ($dff) from module top (D = \smi_ctrl_ins.r_fifo_pull, Q = \smi_ctrl_ins.r_fifo_pull_1, rval = 1'0). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1889 ($dff) from module top (D = \smi_ctrl_ins.w_fifo_pull_trigger, Q = \smi_ctrl_ins.r_fifo_pull, rval = 1'0). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1888 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1614_Y, Q = \smi_ctrl_ins.w_fifo_push_trigger, rval = 1'0). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1886 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1589_Y, Q = \smi_ctrl_ins.modem_tx_ctrl, rval = 1'0). +Adding EN signal on $auto$ff.cc:266:slice$2112 ($sdff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1587_Y, Q = \smi_ctrl_ins.modem_tx_ctrl). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1884 ($dff) from module top (D = { $flatten\smi_ctrl_ins.$procmux$1567_Y $flatten\smi_ctrl_ins.$procmux$1556_Y $flatten\smi_ctrl_ins.$procmux$1545_Y $flatten\smi_ctrl_ins.$procmux$1535_Y $flatten\smi_ctrl_ins.$procmux$1526_Y $flatten\smi_ctrl_ins.$procmux$1517_Y $flatten\smi_ctrl_ins.$procmux$1505_Y }, Q = \smi_ctrl_ins.r_fifo_pushed_data [31:8], rval = 24'000000000000000000000000). +Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1884 ($dff) from module top (D = 8'00000000, Q = \smi_ctrl_ins.r_fifo_pushed_data [7:0]). +Adding EN signal on $auto$ff.cc:266:slice$2114 ($sdff) from module top (D = { 2'10 \smi_ctrl_ins.i_smi_data_in [4:0] }, Q = \smi_ctrl_ins.r_fifo_pushed_data [31:25]). +Adding EN signal on $auto$ff.cc:266:slice$2114 ($sdff) from module top (D = \smi_ctrl_ins.i_smi_data_in [6:0], Q = \smi_ctrl_ins.r_fifo_pushed_data [24:18]). +Adding EN signal on $auto$ff.cc:266:slice$2114 ($sdff) from module top (D = { \smi_ctrl_ins.i_smi_data_in [6] \smi_ctrl_ins.modem_tx_ctrl 2'01 \smi_ctrl_ins.i_smi_data_in [5:0] }, Q = \smi_ctrl_ins.r_fifo_pushed_data [17:8]). +Adding EN signal on $flatten\smi_ctrl_ins.$procdff$1882 ($dff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1636_Y, Q = \smi_ctrl_ins.o_tx_fifo_pushed_data). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1881 ($dff) from module top (D = \smi_ctrl_ins.r_fifo_push, Q = \smi_ctrl_ins.r_fifo_push_1, rval = 1'0). +Adding SRST signal on $flatten\smi_ctrl_ins.$procdff$1880 ($dff) from module top (D = \smi_ctrl_ins.w_fifo_push_trigger, Q = \smi_ctrl_ins.r_fifo_push, rval = 1'0). +Adding SRST signal on $flatten\rx_fifo.$procdff$1877 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1484_Y, Q = \rx_fifo.wr_addr_gray, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2139 ($sdff) from module top (D = { $flatten\rx_fifo.$add$complex_fifo.v:46$455_Y [9] $flatten\rx_fifo.$xor$complex_fifo.v:37$457_Y }, Q = \rx_fifo.wr_addr_gray). +Adding SRST signal on $flatten\rx_fifo.$procdff$1876 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1490_Y, Q = \rx_fifo.wr_addr, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2141 ($sdff) from module top (D = $flatten\rx_fifo.$add$complex_fifo.v:46$455_Y, Q = \rx_fifo.wr_addr). +Adding SRST signal on $flatten\rx_fifo.$procdff$1869 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1448_Y, Q = \rx_fifo.full_o, rval = 1'0). +Adding SRST signal on $flatten\rx_fifo.$procdff$1865 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1412_Y, Q = \rx_fifo.rd_addr_gray, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2144 ($sdff) from module top (D = { $flatten\rx_fifo.$add$complex_fifo.v:73$488_Y [9] $flatten\rx_fifo.$xor$complex_fifo.v:37$490_Y }, Q = \rx_fifo.rd_addr_gray). +Adding SRST signal on $flatten\rx_fifo.$procdff$1864 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1418_Y, Q = \rx_fifo.rd_addr, rval = 10'0000000000). +Adding EN signal on $auto$ff.cc:266:slice$2146 ($sdff) from module top (D = $flatten\rx_fifo.$add$complex_fifo.v:73$488_Y, Q = \rx_fifo.rd_addr). +Adding SRST signal on $flatten\rx_fifo.$procdff$1857 ($dff) from module top (D = $flatten\rx_fifo.$procmux$1373_Y, Q = \rx_fifo.empty_o, rval = 1'1). +Adding EN signal on $flatten\rx_fifo.$procdff$1854 ($dff) from module top (D = { $flatten\rx_fifo.$memrd$\mem_i$complex_fifo.v:100$520_DATA $flatten\rx_fifo.$memrd$\mem_q$complex_fifo.v:99$519_DATA }, Q = \rx_fifo.rd_data_o). +Adding SRST signal on $flatten\lvds_tx_inst.$procdff$1841 ($dff) from module top (D = $flatten\lvds_tx_inst.$procmux$1202_Y, Q = \lvds_tx_inst.r_fifo_data, rval = 0). +Adding EN signal on $auto$ff.cc:266:slice$2150 ($sdff) from module top (D = $flatten\lvds_tx_inst.$procmux$1197_Y, Q = \lvds_tx_inst.r_fifo_data). +Adding SRST signal on $flatten\lvds_tx_inst.$procdff$1840 ($dff) from module top (D = $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565_Y [4:0], Q = \lvds_tx_inst.r_phase_count, rval = 5'11111). +Adding SRST signal on $flatten\lvds_tx_inst.$procdff$1839 ($dff) from module top (D = $flatten\lvds_tx_inst.$not$lvds_tx.v:35$561_Y, Q = \lvds_tx_inst.o_fifo_pull, rval = 1'0). +Adding EN signal on $flatten\lvds_tx_inst.$procdff$1838 ($dff) from module top (D = $flatten\lvds_tx_inst.$shiftx$lvds_tx.v:0$564_Y, Q = \lvds_tx_inst.o_ddr_data). +Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1836 ($adff) from module top (D = $flatten\lvds_rx_24_inst.$0\r_phase_count[2:0], Q = \lvds_rx_24_inst.r_phase_count). +Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1835 ($adff) from module top (D = $flatten\lvds_rx_24_inst.$0\r_state_if[1:0], Q = \lvds_rx_24_inst.r_state_if). +Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1834 ($dff) from module top (D = $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0], Q = \lvds_rx_24_inst.o_fifo_data). +Adding EN signal on $flatten\lvds_rx_24_inst.$procdff$1831 ($adff) from module top (D = $flatten\lvds_rx_24_inst.$0\o_fifo_push[0:0], Q = \lvds_rx_24_inst.o_fifo_push). +Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1836 ($adff) from module top (D = $flatten\lvds_rx_09_inst.$0\r_phase_count[2:0], Q = \lvds_rx_09_inst.r_phase_count). +Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1835 ($adff) from module top (D = $flatten\lvds_rx_09_inst.$0\r_state_if[1:0], Q = \lvds_rx_09_inst.r_state_if). +Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1834 ($dff) from module top (D = $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0], Q = \lvds_rx_09_inst.o_fifo_data). +Adding EN signal on $flatten\lvds_rx_09_inst.$procdff$1831 ($adff) from module top (D = $flatten\lvds_rx_09_inst.$0\o_fifo_push[0:0], Q = \lvds_rx_09_inst.o_fifo_push). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1830 ($dff) from module top (D = \spi_if_ins.o_data_in, Q = \io_ctrl_ins.rf_pin_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1827 ($dff) from module top (D = \spi_if_ins.o_data_in, Q = \io_ctrl_ins.pmod_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1824 ($dff) from module top (D = \spi_if_ins.o_data_in, Q = \io_ctrl_ins.pmod_dir_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1821 ($adff) from module top (D = \spi_if_ins.o_data_in [1], Q = \io_ctrl_ins.led1_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1820 ($adff) from module top (D = \spi_if_ins.o_data_in [0], Q = \io_ctrl_ins.led0_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1819 ($adff) from module top (D = \spi_if_ins.o_data_in [4:2], Q = \io_ctrl_ins.rf_mode). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1818 ($adff) from module top (D = \spi_if_ins.o_data_in [1:0], Q = \io_ctrl_ins.debug_mode). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1817 ($dff) from module top (D = { $flatten\io_ctrl_ins.$procmux$1031_Y $flatten\io_ctrl_ins.$procmux$985_Y $flatten\io_ctrl_ins.$procmux$1043_Y $flatten\io_ctrl_ins.$procmux$1008_Y }, Q = { \io_ctrl_ins.o_data_out [4:3] \io_ctrl_ins.o_data_out [1:0] }). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1817 ($dff) from module top (D = { $flatten\io_ctrl_ins.$procmux$1020_Y $flatten\io_ctrl_ins.$procmux$963_Y $flatten\io_ctrl_ins.$procmux$974_Y }, Q = \io_ctrl_ins.o_data_out [7:5]). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1817 ($dff) from module top (D = $flatten\io_ctrl_ins.$procmux$997_Y, Q = \io_ctrl_ins.o_data_out [2]). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1814 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\tr_vc_2_state[0:0], Q = \io_ctrl_ins.tr_vc_2_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1811 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\tr_vc_1_b_state[0:0], Q = \io_ctrl_ins.tr_vc_1_b_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1808 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\tr_vc_1_state[0:0], Q = \io_ctrl_ins.tr_vc_1_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1805 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\rx_h_b_state[0:0], Q = \io_ctrl_ins.rx_h_b_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1802 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\rx_h_state[0:0], Q = \io_ctrl_ins.rx_h_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1799 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\lna_tx_shutdown_state[0:0], Q = \io_ctrl_ins.lna_tx_shutdown_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1796 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\lna_rx_shutdown_state[0:0], Q = \io_ctrl_ins.lna_rx_shutdown_state). +Adding EN signal on $flatten\io_ctrl_ins.$procdff$1793 ($dff) from module top (D = $flatten\io_ctrl_ins.$0\mixer_en_state[0:0], Q = \io_ctrl_ins.mixer_en_state). +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2117 ($sdffe) from module top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2125 ($sdffe) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2096 ($dffe) from module top. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2096 ($dffe) from module top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2096 ($dffe) from module top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2096 ($dffe) from module top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2096 ($dffe) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2116 ($dffe) from module top. + +2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 173 unused cells and 164 unused wires. + + +2.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. + +Removed a total of 34 cells. + +2.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 34 unused wires. + + +2.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.13.16. Rerunning OPT passes. (Maybe there is more to do..) + +2.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.13.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.13.20. Executing OPT_DFF pass (perform DFF optimizations). + +2.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.13.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.13.23. Finished OPT passes. (There is nothing left to do.) + +2.14. Executing WREDUCE pass (reducing word size of cells). +Removed top 1 bits (of 4) from port B of cell top.$procmux$1741_CMP0 ($eq). +Removed top 2 bits (of 4) from port B of cell top.$procmux$1742_CMP0 ($eq). +Removed top 3 bits (of 4) from port B of cell top.$procmux$1743_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_if_ins.\spi.$eq$spi_slave.v:38$602 ($eq). +Removed top 1 bits (of 2) from port B of cell top.$flatten\spi_if_ins.\spi.$eq$spi_slave.v:63$608 ($eq). +Removed top 31 bits (of 32) from port B of cell top.$flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611 ($sub). +Removed top 29 bits (of 32) from port Y of cell top.$flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611 ($sub). +Removed top 1 bits (of 8) from FF cell top.$auto$ff.cc:266:slice$2027 ($dffe). +Removed top 1 bits (of 2) from port B of cell top.$flatten\spi_if_ins.$procmux$810_CMP0 ($eq). +Removed top 1 bits (of 3) from mux cell top.$flatten\spi_if_ins.$procmux$762 ($mux). +Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_if_ins.$procmux$760_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell top.$flatten\spi_if_ins.$eq$spi_if.v:99$597 ($eq). +Removed top 2 bits (of 3) from port B of cell top.$flatten\spi_if_ins.$eq$spi_if.v:96$596 ($eq). +Removed top 31 bits (of 32) from port B of cell top.$flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600 ($add). +Removed top 29 bits (of 32) from port Y of cell top.$flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600 ($add). +Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2036 ($ne). +Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$1993 ($eq). +Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2079 ($ne). +Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2070 ($ne). +Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2066 ($ne). +Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2061 ($ne). +Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2053 ($ne). +Removed top 3 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1012_CMP0 ($eq). +Removed top 2 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1010_CMP0 ($eq). +Removed top 2 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1009_CMP0 ($eq). +Removed top 4 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1001_CMP0 ($eq). +Removed top 3 bits (of 5) from port B of cell top.$flatten\io_ctrl_ins.$procmux$1000_CMP0 ($eq). +Removed top 2 bits (of 3) from port B of cell top.$flatten\io_ctrl_ins.$procmux$874_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell top.$flatten\io_ctrl_ins.$procmux$873_CMP0 ($eq). +Removed top 1 bits (of 3) from port B of cell top.$flatten\io_ctrl_ins.$procmux$872_CMP0 ($eq). +Removed top 1 bits (of 2) from port B of cell top.$flatten\io_ctrl_ins.$eq$io_ctrl.v:297$586 ($eq). +Removed top 31 bits (of 32) from mux cell top.$flatten\lvds_rx_09_inst.$procmux$1169 ($mux). +Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_09_inst.$procmux$1151_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell top.$flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572 ($sub). +Removed top 29 bits (of 32) from port Y of cell top.$flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572 ($sub). +Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_09_inst.$eq$lvds_rx.v:57$571 ($eq). +Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2310 ($ne). +Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2315 ($ne). +Removed top 31 bits (of 32) from mux cell top.$flatten\lvds_rx_24_inst.$procmux$1169 ($mux). +Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_24_inst.$procmux$1151_CMP0 ($eq). +Removed top 31 bits (of 32) from port B of cell top.$flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572 ($sub). +Removed top 29 bits (of 32) from port Y of cell top.$flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572 ($sub). +Removed top 1 bits (of 2) from port B of cell top.$flatten\lvds_rx_24_inst.$eq$lvds_rx.v:57$571 ($eq). +Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2178 ($ne). +Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2176 ($ne). +Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2174 ($ne). +Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2275 ($ne). +Removed top 31 bits (of 32) from port B of cell top.$flatten\rx_fifo.$add$complex_fifo.v:88$506 ($add). +Removed top 22 bits (of 32) from port Y of cell top.$flatten\rx_fifo.$add$complex_fifo.v:88$506 ($add). +Removed top 30 bits (of 32) from port B of cell top.$flatten\rx_fifo.$add$complex_fifo.v:61$473 ($add). +Removed top 22 bits (of 32) from port Y of cell top.$flatten\rx_fifo.$add$complex_fifo.v:61$473 ($add). +Removed top 30 bits (of 32) from port B of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565 ($sub). +Removed top 27 bits (of 32) from port Y of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565 ($sub). +Removed top 31 bits (of 32) from port B of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563 ($sub). +Removed top 26 bits (of 32) from port Y of cell top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563 ($sub). +Removed top 4 bits (of 5) from port B of cell top.$flatten\lvds_tx_inst.$eq$lvds_tx.v:36$562 ($eq). +Removed top 3 bits (of 5) from port B of cell top.$flatten\lvds_tx_inst.$eq$lvds_tx.v:34$560 ($eq). +Removed top 2 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2282 ($ne). +Removed top 31 bits (of 32) from port B of cell top.$flatten\tx_fifo.$add$complex_fifo.v:88$506 ($add). +Removed top 22 bits (of 32) from port Y of cell top.$flatten\tx_fifo.$add$complex_fifo.v:88$506 ($add). +Removed top 30 bits (of 32) from port B of cell top.$flatten\tx_fifo.$add$complex_fifo.v:61$473 ($add). +Removed top 22 bits (of 32) from port Y of cell top.$flatten\tx_fifo.$add$complex_fifo.v:61$473 ($add). +Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2208 ($ne). +Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2206 ($ne). +Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2204 ($ne). +Removed top 28 bits (of 32) from port B of cell top.$flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416 ($add). +Removed top 27 bits (of 32) from port Y of cell top.$flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416 ($add). +Removed top 1 bits (of 5) from port B of cell top.$flatten\smi_ctrl_ins.$eq$smi_ctrl.v:122$410 ($eq). +Removed top 29 bits (of 32) from wire top.$flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572_Y. +Removed top 29 bits (of 32) from wire top.$flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572_Y. +Removed top 27 bits (of 32) from wire top.$flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565_Y. +Removed top 22 bits (of 32) from wire top.$flatten\rx_fifo.$add$complex_fifo.v:61$473_Y. +Removed top 22 bits (of 32) from wire top.$flatten\rx_fifo.$add$complex_fifo.v:88$506_Y. +Removed top 10 bits (of 16) from wire top.$flatten\rx_fifo.$memrd$\mem_q$complex_fifo.v:99$519_DATA. +Removed top 27 bits (of 32) from wire top.$flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416_Y. +Removed top 22 bits (of 32) from wire top.$flatten\smi_ctrl_ins.$procmux$1636_Y. +Removed top 2 bits (of 32) from wire top.$flatten\smi_ctrl_ins.$procmux$1639_Y. +Removed top 6 bits (of 8) from wire top.$flatten\smi_ctrl_ins.$procmux$1681_Y. +Removed top 1 bits (of 3) from wire top.$flatten\spi_if_ins.$procmux$762_Y. +Removed top 29 bits (of 32) from wire top.$flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600_Y. +Removed top 22 bits (of 32) from wire top.$flatten\tx_fifo.$add$complex_fifo.v:61$473_Y. +Removed top 22 bits (of 32) from wire top.$flatten\tx_fifo.$add$complex_fifo.v:88$506_Y. +Removed top 1 bits (of 32) from wire top.w_rx_09_fifo_data. +Removed top 7 bits (of 32) from wire top.w_rx_fifo_pulled_data. +Removed top 5 bits (of 8) from wire top.w_tx_data_smi. + +2.15. Executing PEEPOPT pass (run peephole optimizers). + +2.16. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 17 unused wires. + + +2.17. Executing SHARE pass (SAT-based resource sharing). + +2.18. Executing TECHMAP pass (map to technology primitives). + +2.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +2.18.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.19. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.20. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.21. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module top: + creating $macc model for $flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572 ($sub). + creating $macc model for $flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572 ($sub). + creating $macc model for $flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563 ($sub). + creating $macc model for $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565 ($sub). + creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:46$455 ($add). + creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:61$473 ($add). + creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:73$488 ($add). + creating $macc model for $flatten\rx_fifo.$add$complex_fifo.v:88$506 ($add). + creating $macc model for $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416 ($add). + creating $macc model for $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600 ($add). + creating $macc model for $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611 ($sub). + creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:46$455 ($add). + creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:61$473 ($add). + creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:73$488 ($add). + creating $macc model for $flatten\tx_fifo.$add$complex_fifo.v:88$506 ($add). + creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:88$506. + creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:73$488. + creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:61$473. + creating $alu model for $macc $flatten\tx_fifo.$add$complex_fifo.v:46$455. + creating $alu model for $macc $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611. + creating $alu model for $macc $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600. + creating $alu model for $macc $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416. + creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:88$506. + creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:73$488. + creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:61$473. + creating $alu model for $macc $flatten\rx_fifo.$add$complex_fifo.v:46$455. + creating $alu model for $macc $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565. + creating $alu model for $macc $flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563. + creating $alu model for $macc $flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572. + creating $alu model for $macc $flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572. + creating $alu cell for $flatten\lvds_rx_09_inst.$sub$lvds_rx.v:64$572: $auto$alumacc.cc:485:replace_alu$2347 + creating $alu cell for $flatten\lvds_rx_24_inst.$sub$lvds_rx.v:64$572: $auto$alumacc.cc:485:replace_alu$2350 + creating $alu cell for $flatten\lvds_tx_inst.$sub$lvds_tx.v:47$563: $auto$alumacc.cc:485:replace_alu$2353 + creating $alu cell for $flatten\lvds_tx_inst.$sub$lvds_tx.v:48$565: $auto$alumacc.cc:485:replace_alu$2356 + creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:46$455: $auto$alumacc.cc:485:replace_alu$2359 + creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:61$473: $auto$alumacc.cc:485:replace_alu$2362 + creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:73$488: $auto$alumacc.cc:485:replace_alu$2365 + creating $alu cell for $flatten\rx_fifo.$add$complex_fifo.v:88$506: $auto$alumacc.cc:485:replace_alu$2368 + creating $alu cell for $flatten\smi_ctrl_ins.$add$smi_ctrl.v:132$416: $auto$alumacc.cc:485:replace_alu$2371 + creating $alu cell for $flatten\spi_if_ins.\spi.$add$spi_slave.v:32$600: $auto$alumacc.cc:485:replace_alu$2374 + creating $alu cell for $flatten\spi_if_ins.\spi.$sub$spi_slave.v:75$611: $auto$alumacc.cc:485:replace_alu$2377 + creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:46$455: $auto$alumacc.cc:485:replace_alu$2380 + creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:61$473: $auto$alumacc.cc:485:replace_alu$2383 + creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:73$488: $auto$alumacc.cc:485:replace_alu$2386 + creating $alu cell for $flatten\tx_fifo.$add$complex_fifo.v:88$506: $auto$alumacc.cc:485:replace_alu$2389 + created 15 $alu and 0 $macc cells. + +2.22. Executing OPT pass (performing simple optimizations). + +2.22.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.22.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. + +Removed a total of 4 cells. + +2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.22.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.22.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 8 unused wires. + + +2.22.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.22.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.22.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.22.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.22.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.22.16. Finished OPT passes. (There is nothing left to do.) + +2.23. Executing MEMORY pass. + +2.23.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 4 transformations. + +2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing top.rx_fifo.mem_i write port 0. + Analyzing top.rx_fifo.mem_q write port 0. + Analyzing top.tx_fifo.mem_i write port 0. + Analyzing top.tx_fifo.mem_q write port 0. + +2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\rx_fifo.mem_i'[0] in module `\top': merging output FF to cell. +Checking read port `\rx_fifo.mem_q'[0] in module `\top': merging output FF to cell. +Checking read port `\tx_fifo.mem_i'[0] in module `\top': merging output FF to cell. +Checking read port `\tx_fifo.mem_q'[0] in module `\top': merging output FF to cell. + +2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 2 unused cells and 68 unused wires. + + +2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +2.24. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). +mapping memory top.rx_fifo.mem_i via $__ICE40_RAM4K_ +mapping memory top.rx_fifo.mem_q via $__ICE40_RAM4K_ +mapping memory top.tx_fifo.mem_i via $__ICE40_RAM4K_ +mapping memory top.tx_fifo.mem_q via $__ICE40_RAM4K_ + + +2.26. Executing TECHMAP pass (map to technology primitives). + +2.26.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/brams_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__ICE40_RAM4K_'. +Successfully finished Verilog frontend. + +2.26.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/spram_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/spram_map.v' to AST representation. +Generating RTLIL representation for module `\$__ICE40_SPRAM_'. +Successfully finished Verilog frontend. + +2.26.3. Continuing TECHMAP pass. +Using template $paramod$152405ab8834e0c4f35bd7e4e60c34790a6f81fa\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. +No more expansions possible. + + +2.27. Executing ICE40_BRAMINIT pass. + +2.28. Executing OPT pass (performing simple optimizations). + +2.28.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.28.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.28.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:266:slice$2049 ($dffe) from module top (D = $flatten\spi_if_ins.$procmux$737_Y, Q = \spi_if_ins.r_tx_data_valid, rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$2032 ($dffe) from module top (D = \spi_if_ins.r_tx_byte, Q = \spi_if_ins.spi.r_tx_byte, rval = 8'00000000). +Adding SRST signal on $auto$ff.cc:266:slice$2130 ($dffe) from module top (D = { \smi_ctrl_ins.r_fifo_pushed_data [31] \smi_ctrl_ins.r_fifo_pushed_data [29:16] \smi_ctrl_ins.r_fifo_pushed_data [14:8] \smi_ctrl_ins.i_smi_data_in [6:0] }, Q = { \smi_ctrl_ins.o_tx_fifo_pushed_data [31] \smi_ctrl_ins.o_tx_fifo_pushed_data [29:16] \smi_ctrl_ins.o_tx_fifo_pushed_data [14:1] }, rval = 29'00000000000000000000000000000). +Adding SRST signal on $auto$ff.cc:266:slice$2130 ($dffe) from module top (D = { $flatten\smi_ctrl_ins.$procmux$1634_Y [30] $flatten\smi_ctrl_ins.$procmux$1634_Y [15] $flatten\smi_ctrl_ins.$procmux$1634_Y [0] }, Q = { \smi_ctrl_ins.o_tx_fifo_pushed_data [30] \smi_ctrl_ins.o_tx_fifo_pushed_data [15] \smi_ctrl_ins.o_tx_fifo_pushed_data [0] }, rval = 3'000). +Adding SRST signal on $auto$ff.cc:266:slice$2111 ($sdff) from module top (D = $flatten\smi_ctrl_ins.$procmux$1612_Y, Q = \smi_ctrl_ins.w_fifo_push_trigger, rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$2099 ($dffe) from module top (D = { \smi_ctrl_ins.r_channel \tx_fifo.full_o \rx_fifo.empty_o }, Q = \smi_ctrl_ins.o_data_out [2:0], rval = 3'001). +Adding SRST signal on $auto$ff.cc:266:slice$2073 ($dffe) from module top (D = $flatten\spi_if_ins.$procmux$792_Y, Q = \spi_if_ins.o_fetch_cmd, rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$2064 ($dffe) from module top (D = $flatten\spi_if_ins.$procmux$778_Y, Q = \spi_if_ins.o_load_cmd, rval = 1'0). + +2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 11 unused cells and 281 unused wires. + + +2.28.5. Rerunning OPT passes. (Removed registers in this run.) + +2.28.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.28.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.28.8. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $auto$ff.cc:266:slice$2156 ($sdff) from module top (D = \lvds_tx_inst.r_phase_count [0], Q = \lvds_tx_inst.r_phase_count [0]). +Handling D = Q on $auto$ff.cc:266:slice$2546 ($sdffe) from module top (conecting SRST instead). +Adding EN signal on $auto$ff.cc:266:slice$2107 ($sdff) from module top (D = \smi_ctrl_ins.int_cnt_rx [2:0], Q = \smi_ctrl_ins.int_cnt_rx [2:0]). +Handling D = Q on $auto$ff.cc:266:slice$2550 ($sdffe) from module top (conecting SRST instead). +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2550 ($dffe) from module top. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2550 ($dffe) from module top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2550 ($dffe) from module top. +Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$2546 ($dffe) from module top. + +2.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 2 unused cells and 3 unused wires. + + +2.28.10. Rerunning OPT passes. (Removed registers in this run.) + +2.28.11. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.28.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.28.13. Executing OPT_DFF pass (perform DFF optimizations). + +2.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 1 unused cells and 9 unused wires. + + +2.28.15. Finished fast OPT passes. + +2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). + +2.30. Executing OPT pass (performing simple optimizations). + +2.30.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.30.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. + Consolidated identical input bits for $mux cell $flatten\lvds_rx_09_inst.$procmux$1160: + Old ports: A=2'00, B=2'11, Y=$flatten\lvds_rx_09_inst.$procmux$1160_Y + New ports: A=1'0, B=1'1, Y=$flatten\lvds_rx_09_inst.$procmux$1160_Y [0] + New connections: $flatten\lvds_rx_09_inst.$procmux$1160_Y [1] = $flatten\lvds_rx_09_inst.$procmux$1160_Y [0] + Consolidated identical input bits for $pmux cell $flatten\lvds_rx_09_inst.$procmux$1171: + Old ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_09_d0 \w_lvds_rx_09_d1 }, B={ \lvds_rx_09_inst.o_fifo_data [29:0] \w_lvds_rx_09_d0 \w_lvds_rx_09_d1 \lvds_rx_09_inst.o_fifo_data [29:0] \w_lvds_rx_09_d0 $flatten\lvds_rx_09_inst.$procmux$1169_Y [0] }, Y=$flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0] + New ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_09_d1 }, B={ \lvds_rx_09_inst.o_fifo_data [29:0] \w_lvds_rx_09_d1 \lvds_rx_09_inst.o_fifo_data [29:0] $flatten\lvds_rx_09_inst.$procmux$1169_Y [0] }, Y={ $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0] [31:2] $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0] [0] } + New connections: $flatten\lvds_rx_09_inst.$0\o_fifo_data[31:0] [1] = \w_lvds_rx_09_d0 + Consolidated identical input bits for $mux cell $flatten\lvds_rx_24_inst.$procmux$1160: + Old ports: A=2'00, B=2'11, Y=$flatten\lvds_rx_24_inst.$procmux$1160_Y + New ports: A=1'0, B=1'1, Y=$flatten\lvds_rx_24_inst.$procmux$1160_Y [0] + New connections: $flatten\lvds_rx_24_inst.$procmux$1160_Y [1] = $flatten\lvds_rx_24_inst.$procmux$1160_Y [0] + Consolidated identical input bits for $pmux cell $flatten\lvds_rx_24_inst.$procmux$1171: + Old ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_24_d0 \w_lvds_rx_24_d1 }, B={ \lvds_rx_24_inst.o_fifo_data [29:0] \w_lvds_rx_24_d0 \w_lvds_rx_24_d1 \lvds_rx_24_inst.o_fifo_data [29:0] \w_lvds_rx_24_d0 $flatten\lvds_rx_24_inst.$procmux$1169_Y [0] }, Y=$flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0] + New ports: A={ 30'000000000000000000000000000000 \w_lvds_rx_24_d1 }, B={ \lvds_rx_24_inst.o_fifo_data [29:0] \w_lvds_rx_24_d1 \lvds_rx_24_inst.o_fifo_data [29:0] $flatten\lvds_rx_24_inst.$procmux$1169_Y [0] }, Y={ $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0] [31:2] $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0] [0] } + New connections: $flatten\lvds_rx_24_inst.$0\o_fifo_data[31:0] [1] = \w_lvds_rx_24_d0 + Consolidated identical input bits for $mux cell $flatten\smi_ctrl_ins.$procmux$1634: + Old ports: A={ \smi_ctrl_ins.r_fifo_pushed_data [31] 1'0 \smi_ctrl_ins.r_fifo_pushed_data [29:16] 1'0 \smi_ctrl_ins.r_fifo_pushed_data [14:8] \smi_ctrl_ins.i_smi_data_in [6:0] 1'0 }, B=0, Y=$flatten\smi_ctrl_ins.$procmux$1634_Y + New ports: A={ \smi_ctrl_ins.r_fifo_pushed_data [31] \smi_ctrl_ins.r_fifo_pushed_data [29:16] \smi_ctrl_ins.r_fifo_pushed_data [14:8] \smi_ctrl_ins.i_smi_data_in [6:0] }, B=29'00000000000000000000000000000, Y={ $flatten\smi_ctrl_ins.$procmux$1634_Y [31] $flatten\smi_ctrl_ins.$procmux$1634_Y [29:16] $flatten\smi_ctrl_ins.$procmux$1634_Y [14:1] } + New connections: { $flatten\smi_ctrl_ins.$procmux$1634_Y [30] $flatten\smi_ctrl_ins.$procmux$1634_Y [15] $flatten\smi_ctrl_ins.$procmux$1634_Y [0] } = 3'000 + Consolidated identical input bits for $mux cell $flatten\spi_if_ins.$procmux$754: + Old ports: A=3'100, B=3'010, Y=$flatten\spi_if_ins.$procmux$754_Y + New ports: A=2'10, B=2'01, Y=$flatten\spi_if_ins.$procmux$754_Y [2:1] + New connections: $flatten\spi_if_ins.$procmux$754_Y [0] = 1'0 + Consolidated identical input bits for $mux cell $flatten\spi_if_ins.$procmux$758: + Old ports: A={ 1'0 $auto$wreduce.cc:455:run$2339 [1:0] }, B=3'000, Y=$flatten\spi_if_ins.$procmux$758_Y + New ports: A=$auto$wreduce.cc:455:run$2339 [1:0], B=2'00, Y=$flatten\spi_if_ins.$procmux$758_Y [1:0] + New connections: $flatten\spi_if_ins.$procmux$758_Y [2] = 1'0 + Consolidated identical input bits for $mux cell $flatten\spi_if_ins.$procmux$762: + Old ports: A=2'01, B=2'11, Y=$auto$wreduce.cc:455:run$2339 [1:0] + New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:455:run$2339 [1] + New connections: $auto$wreduce.cc:455:run$2339 [0] = 1'1 + Consolidated identical input bits for $mux cell $flatten\sys_ctrl_ins.$procmux$857: + Old ports: A=8'00000001, B=8'00000000, Y=$flatten\sys_ctrl_ins.$procmux$857_Y + New ports: A=1'1, B=1'0, Y=$flatten\sys_ctrl_ins.$procmux$857_Y [0] + New connections: $flatten\sys_ctrl_ins.$procmux$857_Y [7:1] = 7'0000000 + Optimizing cells in module \top. +Performed a total of 9 changes. + +2.30.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.30.6. Executing OPT_DFF pass (perform DFF optimizations). + +2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 1 unused cells and 1 unused wires. + + +2.30.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.30.9. Rerunning OPT passes. (Maybe there is more to do..) + +2.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.30.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.30.13. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2013 ($adffe) from module top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2013 ($adffe) from module top. +Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2013 ($adffe) from module top. +Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2013 ($adffe) from module top. +Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2013 ($adffe) from module top. +Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2013 ($adffe) from module top. +Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2013 ($adffe) from module top. +Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2539 ($sdffce) from module top. +Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2539 ($sdffce) from module top. +Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2539 ($sdffce) from module top. + +2.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.30.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.30.16. Rerunning OPT passes. (Maybe there is more to do..) + +2.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \top.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +2.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \top. +Performed a total of 0 changes. + +2.30.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.30.20. Executing OPT_DFF pass (perform DFF optimizations). + +2.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.30.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.30.23. Finished OPT passes. (There is nothing left to do.) + +2.31. Executing ICE40_WRAPCARRY pass (wrap carries). + +2.32. Executing TECHMAP pass (map to technology primitives). + +2.32.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +2.32.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/arith_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_ice40_alu'. +Successfully finished Verilog frontend. + +2.32.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $tribuf. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $mux. +Using template $paramod$ee721315a7b0169d82611b9aea01747035b97792\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $reduce_and. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $logic_and. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod$754650b284649a026620fc6856e5b6886cbfe794\_80_ice40_alu for cells of type $alu. +Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $sdffce. +Using extmapper simplemap for cells of type $reduce_or. +Using template $paramod$c2e415ef15bc3ccd2723772353a6b450d3d76206\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $and. +Using template $paramod$b8c0a997bce700f23568a5ada79cc6781d1f5ca0\_80_ice40_alu for cells of type $alu. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $adffe. +Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_pmux for cells of type $pmux. +Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux. +Using template $paramod$f08cf4b531f7b2bd95251b79857dfb970a6679fc\_90_pmux for cells of type $pmux. +Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. +Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux. +Using extmapper simplemap for cells of type $xor. +Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. +Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu. +Using template $paramod$constmap:c39c2a14b34c884b1bdd5cf6ea238257f5452db9$paramod$dacef1a7b1be4e3e06ba737eb7b1f6b44c4ce930\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_80_ice40_alu for cells of type $alu. +Using template $paramod$constmap:ad62432dc588384ac9e4502cee6ddae521345b24$paramod$8ae51266ce98bc5533551c59a6aa22584269889d\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_80_ice40_alu for cells of type $alu. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using extmapper simplemap for cells of type $or. +No more expansions possible. + + +2.33. Executing OPT pass (performing simple optimizations). + +2.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. + +Removed a total of 137 cells. + +2.33.3. Executing OPT_DFF pass (perform DFF optimizations). + +2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 206 unused cells and 999 unused wires. + + +2.33.5. Finished fast OPT passes. + +2.34. Executing ICE40_OPT pass (performing simple optimizations). + +2.34.1. Running ICE40 specific optimizations. +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2347.slice[0].carry: CO=\lvds_rx_09_inst.r_phase_count [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2350.slice[0].carry: CO=\lvds_rx_24_inst.r_phase_count [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2356.slice[0].carry: CO=\lvds_tx_inst.r_phase_count [1] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2359.slice[0].carry: CO=\rx_fifo.wr_addr [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2362.slice[0].carry: CO=\rx_fifo.wr_addr [1] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2365.slice[0].carry: CO=\rx_fifo.rd_addr [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2374.slice[0].carry: CO=\spi_if_ins.spi.r_rx_bit_count [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2377.slice[0].carry: CO=\spi_if_ins.spi.r_tx_bit_count [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2380.slice[0].carry: CO=\tx_fifo.wr_addr [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2383.slice[0].carry: CO=\tx_fifo.wr_addr [1] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$2386.slice[0].carry: CO=\tx_fifo.rd_addr [0] + +2.34.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.34.3. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.34.4. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:266:slice$4423 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1020.Y_B, Q = \io_ctrl_ins.o_data_out [7], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$4422 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$963.Y_B, Q = \io_ctrl_ins.o_data_out [6], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$4421 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$974.Y_B, Q = \io_ctrl_ins.o_data_out [5], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3986 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [7], Q = \r_tx_data [7], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3985 ($_DFFE_PP_) from module top (D = $procmux$1738.B_AND_S [30], Q = \r_tx_data [6], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3984 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [5], Q = \r_tx_data [5], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3983 ($_DFFE_PP_) from module top (D = $procmux$1738.B_AND_S [28], Q = \r_tx_data [4], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3982 ($_DFFE_PP_) from module top (D = $procmux$1738.B_AND_S [27], Q = \r_tx_data [3], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3981 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [2], Q = \r_tx_data [2], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3980 ($_DFFE_PP_) from module top (D = $procmux$1738.Y_B [1], Q = \r_tx_data [1], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3762 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [30], Q = \lvds_rx_24_inst.o_fifo_data [31], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3761 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [29], Q = \lvds_rx_24_inst.o_fifo_data [30], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3760 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [28], Q = \lvds_rx_24_inst.o_fifo_data [29], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3759 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [27], Q = \lvds_rx_24_inst.o_fifo_data [28], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3758 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [26], Q = \lvds_rx_24_inst.o_fifo_data [27], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3757 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [25], Q = \lvds_rx_24_inst.o_fifo_data [26], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3756 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [24], Q = \lvds_rx_24_inst.o_fifo_data [25], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3755 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [23], Q = \lvds_rx_24_inst.o_fifo_data [24], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3754 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [22], Q = \lvds_rx_24_inst.o_fifo_data [23], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3753 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [21], Q = \lvds_rx_24_inst.o_fifo_data [22], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3752 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [20], Q = \lvds_rx_24_inst.o_fifo_data [21], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3751 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [19], Q = \lvds_rx_24_inst.o_fifo_data [20], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3750 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [18], Q = \lvds_rx_24_inst.o_fifo_data [19], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3749 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [17], Q = \lvds_rx_24_inst.o_fifo_data [18], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3748 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [16], Q = \lvds_rx_24_inst.o_fifo_data [17], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3747 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [15], Q = \lvds_rx_24_inst.o_fifo_data [16], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3746 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [14], Q = \lvds_rx_24_inst.o_fifo_data [15], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3745 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [13], Q = \lvds_rx_24_inst.o_fifo_data [14], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3744 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [12], Q = \lvds_rx_24_inst.o_fifo_data [13], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3743 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [11], Q = \lvds_rx_24_inst.o_fifo_data [12], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3742 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [10], Q = \lvds_rx_24_inst.o_fifo_data [11], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3741 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [9], Q = \lvds_rx_24_inst.o_fifo_data [10], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3740 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [8], Q = \lvds_rx_24_inst.o_fifo_data [9], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3739 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [7], Q = \lvds_rx_24_inst.o_fifo_data [8], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3738 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [6], Q = \lvds_rx_24_inst.o_fifo_data [7], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3737 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [5], Q = \lvds_rx_24_inst.o_fifo_data [6], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3736 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [4], Q = \lvds_rx_24_inst.o_fifo_data [5], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3735 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [3], Q = \lvds_rx_24_inst.o_fifo_data [4], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3734 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [2], Q = \lvds_rx_24_inst.o_fifo_data [3], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3733 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_24_inst.$procmux$1171.Y_B [1], Q = \lvds_rx_24_inst.o_fifo_data [2], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3592 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [30], Q = \lvds_rx_09_inst.o_fifo_data [31], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3591 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [29], Q = \lvds_rx_09_inst.o_fifo_data [30], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3590 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [28], Q = \lvds_rx_09_inst.o_fifo_data [29], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3589 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [27], Q = \lvds_rx_09_inst.o_fifo_data [28], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3588 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [26], Q = \lvds_rx_09_inst.o_fifo_data [27], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3587 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [25], Q = \lvds_rx_09_inst.o_fifo_data [26], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3586 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [24], Q = \lvds_rx_09_inst.o_fifo_data [25], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3585 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [23], Q = \lvds_rx_09_inst.o_fifo_data [24], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3584 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [22], Q = \lvds_rx_09_inst.o_fifo_data [23], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3583 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [21], Q = \lvds_rx_09_inst.o_fifo_data [22], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3582 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [20], Q = \lvds_rx_09_inst.o_fifo_data [21], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3581 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [19], Q = \lvds_rx_09_inst.o_fifo_data [20], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3580 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [18], Q = \lvds_rx_09_inst.o_fifo_data [19], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3579 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [17], Q = \lvds_rx_09_inst.o_fifo_data [18], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3578 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [16], Q = \lvds_rx_09_inst.o_fifo_data [17], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3577 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [15], Q = \lvds_rx_09_inst.o_fifo_data [16], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3576 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [14], Q = \lvds_rx_09_inst.o_fifo_data [15], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3575 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [13], Q = \lvds_rx_09_inst.o_fifo_data [14], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3574 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [12], Q = \lvds_rx_09_inst.o_fifo_data [13], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3573 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [11], Q = \lvds_rx_09_inst.o_fifo_data [12], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3572 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [10], Q = \lvds_rx_09_inst.o_fifo_data [11], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3571 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [9], Q = \lvds_rx_09_inst.o_fifo_data [10], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3570 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [8], Q = \lvds_rx_09_inst.o_fifo_data [9], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3569 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [7], Q = \lvds_rx_09_inst.o_fifo_data [8], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3568 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [6], Q = \lvds_rx_09_inst.o_fifo_data [7], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3567 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [5], Q = \lvds_rx_09_inst.o_fifo_data [6], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3566 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [4], Q = \lvds_rx_09_inst.o_fifo_data [5], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3565 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [3], Q = \lvds_rx_09_inst.o_fifo_data [4], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3564 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [2], Q = \lvds_rx_09_inst.o_fifo_data [3], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3563 ($_DFFE_PP_) from module top (D = $flatten\lvds_rx_09_inst.$procmux$1171.Y_B [1], Q = \lvds_rx_09_inst.o_fifo_data [2], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3310 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1031.Y_B, Q = \io_ctrl_ins.o_data_out [4], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3309 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$985.Y_B, Q = \io_ctrl_ins.o_data_out [3], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3308 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1043.Y_B, Q = \io_ctrl_ins.o_data_out [1], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$3307 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$1008.Y_B, Q = \io_ctrl_ins.o_data_out [0], rval = 1'1). +Adding SRST signal on $auto$ff.cc:266:slice$3095 ($_DFFE_PP_) from module top (D = $flatten\io_ctrl_ins.$procmux$997.Y_B, Q = \io_ctrl_ins.o_data_out [2], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$2944 ($_DFFE_PP_) from module top (D = $flatten\spi_if_ins.$procmux$807.B_AND_S [3], Q = \spi_if_ins.o_cs [3], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$2943 ($_DFFE_PP_) from module top (D = $flatten\spi_if_ins.$procmux$807.B_AND_S [6], Q = \spi_if_ins.o_cs [2], rval = 1'0). +Adding SRST signal on $auto$ff.cc:266:slice$2942 ($_DFFE_PP_) from module top (D = $flatten\spi_if_ins.$procmux$807.B_AND_S [9], Q = \spi_if_ins.o_cs [1], rval = 1'0). + +2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 78 unused cells and 8 unused wires. + + +2.34.6. Rerunning OPT passes. (Removed registers in this run.) + +2.34.7. Running ICE40 specific optimizations. + +2.34.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.34.9. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.34.10. Executing OPT_DFF pass (perform DFF optimizations). + +2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.34.12. Finished OPT passes. (There is nothing left to do.) + +2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +2.36. Executing TECHMAP pass (map to technology primitives). + +2.36.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. +Successfully finished Verilog frontend. + +2.36.2. Continuing TECHMAP pass. +Using template \$_SDFFCE_NP0P_ for cells of type $_SDFFCE_NP0P_. +Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_. +Using template \$_DFF_P_ for cells of type $_DFF_P_. +Using template \$_DFFE_NP_ for cells of type $_DFFE_NP_. +Using template \$_SDFF_NP0_ for cells of type $_SDFF_NP0_. +Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. +Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. +Using template \$_DFF_N_ for cells of type $_DFF_N_. +Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_. +Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. +No more expansions possible. + + +2.37. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). +Mapping top.$auto$alumacc.cc:485:replace_alu$2350.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2356.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2359.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2362.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2365.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2374.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2377.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2380.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2383.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2386.slice[0].carry ($lut). +Mapping top.$auto$alumacc.cc:485:replace_alu$2347.slice[0].carry ($lut). + +2.39. Executing ICE40_OPT pass (performing simple optimizations). + +2.39.1. Running ICE40 specific optimizations. + +2.39.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +2.39.3. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. + +Removed a total of 488 cells. + +2.39.4. Executing OPT_DFF pass (perform DFF optimizations). + +2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. +Removed 0 unused cells and 3329 unused wires. + + +2.39.6. Rerunning OPT passes. (Removed registers in this run.) + +2.39.7. Running ICE40 specific optimizations. + +2.39.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +2.39.9. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +2.39.10. Executing OPT_DFF pass (perform DFF optimizations). + +2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +2.39.12. Finished OPT passes. (There is nothing left to do.) + +2.40. Executing TECHMAP pass (map to technology primitives). + +2.40.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/latches_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +2.40.2. Continuing TECHMAP pass. +No more expansions possible. + + +2.41. Executing ABC pass (technology mapping using ABC). + +2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. +Extracted 1114 gates and 1540 wires to a netlist network with 424 inputs and 328 outputs. + +2.41.1.1. Executing ABC. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ABC command line: "source /abc.script". +ABC: +ABC: + read_blif /input.blif +ABC: + read_lut /lutdefs.txt +ABC: + strash +ABC: + &get -n +ABC: + &fraig -x +ABC: + &put +ABC: + scorr +ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). +ABC: + dc2 +ABC: + dretime +ABC: + strash +ABC: + dch -f +ABC: + if +ABC: + mfs2 +ABC: + lutpack -S 1 +ABC: + dress /input.blif +ABC: Total number of equiv classes = 384. +ABC: Participating nodes from both networks = 829. +ABC: Participating nodes from the first network = 389. ( 77.96 % of nodes) +ABC: Participating nodes from the second network = 440. ( 88.18 % of nodes) +ABC: Node pairs (any polarity) = 389. ( 77.96 % of names can be moved) +ABC: Node pairs (same polarity) = 351. ( 70.34 % of names can be moved) +ABC: Total runtime = 0.11 sec +ABC: + write_blif /output.blif + +2.41.1.2. Re-integrating ABC results. +ABC RESULTS: $lut cells: 498 +ABC RESULTS: internal signals: 788 +ABC RESULTS: input signals: 424 +ABC RESULTS: output signals: 328 +Removing temp directory. + +2.42. Executing ICE40_WRAPCARRY pass (wrap carries). + +2.43. Executing TECHMAP pass (map to technology primitives). + +2.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/ff_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/ff_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DFFE_NP0P_'. +Generating RTLIL representation for module `\$_DFFE_NP1P_'. +Generating RTLIL representation for module `\$_DFFE_PP0P_'. +Generating RTLIL representation for module `\$_DFFE_PP1P_'. +Generating RTLIL representation for module `\$_SDFF_NP0_'. +Generating RTLIL representation for module `\$_SDFF_NP1_'. +Generating RTLIL representation for module `\$_SDFF_PP0_'. +Generating RTLIL representation for module `\$_SDFF_PP1_'. +Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. +Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. +Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. +Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. +Successfully finished Verilog frontend. + +2.43.2. Continuing TECHMAP pass. +No more expansions possible. + +Removed 11 unused cells and 1083 unused wires. + +2.44. Executing OPT_LUT pass (optimize LUTs). +Discovering LUTs. +Number of LUTs: 556 + 1-LUT 32 + 2-LUT 197 + 3-LUT 172 + 4-LUT 155 + with \SB_CARRY (#0) 52 + with \SB_CARRY (#1) 52 + +Eliminating LUTs. +Number of LUTs: 556 + 1-LUT 32 + 2-LUT 197 + 3-LUT 172 + 4-LUT 155 + with \SB_CARRY (#0) 52 + with \SB_CARRY (#1) 52 + +Combining LUTs. +Number of LUTs: 550 + 1-LUT 26 + 2-LUT 197 + 3-LUT 172 + 4-LUT 155 + with \SB_CARRY (#0) 52 + with \SB_CARRY (#1) 52 + +Eliminated 0 LUTs. +Combined 6 LUTs. + + +2.45. Executing TECHMAP pass (map to technology primitives). + +2.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ice40/cells_map.v +Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +2.45.2. Continuing TECHMAP pass. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$a50be0e6fa3a01511bb234559cb74fb8bd3e2061\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101001 for cells of type $lut. +Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9\$lut for cells of type $lut. +Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. +Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2\$lut for cells of type $lut. +Using template $paramod$34c84a38a1bc6aa36f1daa52808ce6e0746a068c\$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. +Using template $paramod$7a9d9396461df152f697894fa3b294ad1b285e08\$lut for cells of type $lut. +Using template $paramod$7ffac03cd0abd3a28c1c30cc28dbcbcc23ba7457\$lut for cells of type $lut. +Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. +Using template $paramod$80cbd08923107235732b36a5d5a7181977144217\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$d6d3aaeac1b9aa2c4b652c48e0deb565040dda72\$lut for cells of type $lut. +Using template $paramod$de3d8c0ac9a85f776878d56395b6e0bf04ae72e7\$lut for cells of type $lut. +Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. +Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. +Using template $paramod$e96de5e9fcce737e52eacf39c70c8f533dc27d63\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. +Using template $paramod$2d8ecce5c907513cebcd38ab5efe0fc26fc03464\$lut for cells of type $lut. +Using template $paramod$a3cdc1eb771a2c6a16f64da161e11100ac409d2b\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$59c595af41d4a5cce2d588c3a5f1342749ce7a77\$lut for cells of type $lut. +Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. +Using template $paramod$977b7e79e3ba9c774a867eb4017ef67f55786548\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. +Using template $paramod$82ac4228e04c92c7b8c133bfa256dd480e0cef1d\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. +Using template $paramod$22295481aee48631dc0088cef4e5f102b07c1986\$lut for cells of type $lut. +Using template $paramod$cde3aa23c1efa60a470cf0f0281347d6ba585afa\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. +Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564\$lut for cells of type $lut. +Using template $paramod$50666a8f9d622ca1f027a4587dfd5f2a7d8810c9\$lut for cells of type $lut. +Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. +Using template $paramod$d6cf0a4b6f6ccd87588da28c41b5b6c258da2509\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. +Using template $paramod$c3d2b1ca136b61a4c0de563fc4d3f82c9bc2587b\$lut for cells of type $lut. +Using template $paramod$8ec29827d94e80e773a6f636dfcf3e1591527264\$lut for cells of type $lut. +Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut. +Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut. +Using template $paramod$298b370b0ed6e6727b735e07db069bd52561f3c3\$lut for cells of type $lut. +Using template $paramod$243c00f5eb9faa1d5ce3478fdc389a56070781f8\$lut for cells of type $lut. +Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut. +Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. +Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. +Using template $paramod$7ad6771b9b40fd01d98988c39e9c94d34bc85f74\$lut for cells of type $lut. +Using template $paramod$5766b753e513aa2393ffc25ef94ebc79dc098484\$lut for cells of type $lut. +Using template $paramod$acf49cb7bd2805dee4b4ebb218aa5924b1be7704\$lut for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. +Using template $paramod$bdb7f9ed72fd4f5c7ad81c376f2d8a5c72a0098d\$lut for cells of type $lut. +Using template $paramod$3d3394a2dba7636f2df80deb551dae557f28c000\$lut for cells of type $lut. +Using template $paramod$84d027b8e91897c1e09c2fa4152cf39e28672ceb\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000001 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. +Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. +Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. +Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. +Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\$lut for cells of type $lut. +Using template $paramod$eb053f45c2a9f7396900cdb1dbe99a65c219c0a6\$lut for cells of type $lut. +Using template $paramod$175104ad114973f30397e1a69eae08cff730fc58\$lut for cells of type $lut. +Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut. +Using template $paramod$26e2df3ec51b730bb541c0780f84ea91c3db55ae\$lut for cells of type $lut. +Using template $paramod$40f3a0e76bf7979db02f9dd35e4ad0450372f384\$lut for cells of type $lut. +No more expansions possible. + +Removed 0 unused cells and 1192 unused wires. + +2.46. Executing AUTONAME pass. +Renamed 15185 objects in module top (45 iterations). + + +2.47. Executing HIERARCHY pass (managing design hierarchy). + +2.47.1. Analyzing design hierarchy.. +Top module: \top + +2.47.2. Analyzing design hierarchy.. +Top module: \top +Removed 0 unused modules. + +2.48. Printing statistics. + +=== top === + + Number of wires: 584 + Number of wire bits: 2425 + Number of public wires: 584 + Number of public wire bits: 2425 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1148 + $_TBUF_ 1 + SB_CARRY 52 + SB_DFF 86 + SB_DFFE 86 + SB_DFFER 20 + SB_DFFESR 203 + SB_DFFESS 4 + SB_DFFN 4 + SB_DFFNE 9 + SB_DFFNESR 84 + SB_DFFNSR 3 + SB_DFFSR 15 + SB_DFFSS 2 + SB_IO 13 + SB_LUT4 550 + SB_RAM40_4K 16 + +2.49. Executing CHECK pass (checking for obvious problems). +Checking module top... +Found and reported 0 problems. + +2.50. Executing BLIF backend. + +2.51. Executing JSON backend. + +-- Running command `ice40_opt' -- + +3. Executing ICE40_OPT pass (performing simple optimizations). + +3.1. Running ICE40 specific optimizations. + +3.2. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + + +3.3. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +3.4. Executing OPT_DFF pass (perform DFF optimizations). + +3.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +3.6. Rerunning OPT passes. (Removed registers in this run.) + +3.7. Running ICE40 specific optimizations. + +3.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module top. + +3.9. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\top'. +Removed a total of 0 cells. + +3.10. Executing OPT_DFF pass (perform DFF optimizations). + +3.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \top.. + +3.12. Finished OPT passes. (There is nothing left to do.) + +-- Running command `fsm_opt' -- + +4. Executing FSM_OPT pass (simple optimizations of FSMs). + +Warnings: 17 unique messages, 17 total +End of script. Logfile hash: d11a7ddf2c, CPU: user 10.77s system 0.10s, MEM: 33.59 MB peak +Yosys 0.26+1 (git sha1 b1a011138, gcc 10.2.1-6 -fPIC -Os) +Time spent: 18% 37x opt_expr (2 sec), 16% 7x techmap (2 sec), ... +nextpnr-ice40 --lp1k --package qn84 --json top.json --pcf ./io.pcf --asc top.asc +Info: constraining clock net 'w_clock_sys' to 64.00 MHz +Info: constraining clock net 'smi_ctrl_ins.soe_and_reset' to 16.00 MHz +Info: constraining clock net 'i_smi_swe_srw' to 16.00 MHz +Info: constraining clock net 'i_sck' to 5.00 MHz +Info: constrained 'i_glob_clock' to bel 'X13/Y8/io1' +Info: constrained 'i_rst_b' to bel 'X7/Y17/io0' +Info: constrained 'io_pmod[0]' to bel 'X13/Y12/io0' +Info: constrained 'io_pmod[1]' to bel 'X13/Y11/io1' +Info: constrained 'io_pmod[2]' to bel 'X13/Y11/io0' +Info: constrained 'io_pmod[3]' to bel 'X13/Y7/io0' +Info: constrained 'io_pmod[4]' to bel 'X13/Y4/io0' +Info: constrained 'io_pmod[5]' to bel 'X13/Y6/io0' +Info: constrained 'io_pmod[6]' to bel 'X13/Y7/io1' +Info: constrained 'io_pmod[7]' to bel 'X13/Y6/io1' +Info: constrained 'o_mixer_fm' to bel 'X13/Y12/io1' +Info: constrained 'o_mixer_en' to bel 'X13/Y9/io0' +Info: constrained 'o_rx_h_tx_l' to bel 'X13/Y13/io1' +Info: constrained 'o_rx_h_tx_l_b' to bel 'X13/Y15/io0' +Info: constrained 'o_tr_vc1' to bel 'X13/Y14/io0' +Info: constrained 'o_tr_vc1_b' to bel 'X13/Y15/io1' +Info: constrained 'o_tr_vc2' to bel 'X13/Y14/io1' +Info: constrained 'o_shdn_rx_lna' to bel 'X4/Y17/io0' +Info: constrained 'o_shdn_tx_lna' to bel 'X2/Y17/io1' +Info: constrained 'o_iq_tx_p' to bel 'X0/Y10/io1' +Info: constrained 'o_iq_tx_n' to bel 'X0/Y10/io0' +Info: constrained 'o_iq_tx_clk_p' to bel 'X0/Y5/io1' +Info: constrained 'o_iq_tx_clk_n' to bel 'X0/Y5/io0' +Info: constrained 'i_iq_rx_09_p' to bel 'X0/Y11/io0' +Info: constrained 'i_iq_rx_24_n' to bel 'X0/Y13/io0' +Info: constrained 'i_iq_rx_clk_p' to bel 'X0/Y12/io0' +Info: constrained 'i_config[0]' to bel 'X10/Y17/io1' +Info: constrained 'i_config[1]' to bel 'X9/Y17/io0' +Info: constrained 'i_config[2]' to bel 'X9/Y17/io1' +Info: constrained 'i_config[3]' to bel 'X8/Y17/io0' +Info: constrained 'i_button' to bel 'X8/Y17/io1' +Info: constrained 'o_led0' to bel 'X11/Y17/io0' +Info: constrained 'o_led1' to bel 'X10/Y17/io0' +Info: constrained 'o_smi_write_req' to bel 'X9/Y0/io1' +Info: constrained 'o_smi_read_req' to bel 'X13/Y3/io1' +Info: constrained 'i_smi_a2' to bel 'X1/Y17/io1' +Info: constrained 'i_smi_a3' to bel 'X3/Y17/io0' +Info: constrained 'i_smi_soe_se' to bel 'X10/Y0/io0' +Info: constrained 'i_smi_swe_srw' to bel 'X8/Y0/io0' +Info: constrained 'io_smi_data[0]' to bel 'X6/Y0/io0' +Info: constrained 'io_smi_data[1]' to bel 'X5/Y0/io1' +Info: constrained 'io_smi_data[2]' to bel 'X5/Y0/io0' +Info: constrained 'io_smi_data[3]' to bel 'X7/Y0/io0' +Info: constrained 'io_smi_data[4]' to bel 'X9/Y0/io0' +Info: constrained 'io_smi_data[5]' to bel 'X10/Y0/io1' +Info: constrained 'io_smi_data[6]' to bel 'X4/Y0/io0' +Info: constrained 'io_smi_data[7]' to bel 'X6/Y0/io1' +Info: constrained 'i_mosi' to bel 'X11/Y0/io1' +Info: constrained 'i_sck' to bel 'X12/Y0/io0' +Info: constrained 'i_ss' to bel 'X12/Y0/io1' +Info: constrained 'o_miso' to bel 'X11/Y0/io0' + +Info: Packing constants.. +Info: Packing IOs.. +Info: io_smi_data[7] feeds SB_IO smi_io7, removing $nextpnr_iobuf io_smi_data[7]. +Info: io_smi_data[6] feeds SB_IO smi_io6, removing $nextpnr_iobuf io_smi_data[6]. +Info: o_iq_tx_p feeds SB_IO iq_tx_p, removing $nextpnr_obuf o_iq_tx_p. +Info: o_iq_tx_n feeds SB_IO iq_tx_n, removing $nextpnr_obuf o_iq_tx_n. +Info: i_iq_rx_clk_p feeds SB_IO iq_rx_clk, removing $nextpnr_ibuf i_iq_rx_clk_p. +Info: i_iq_rx_24_n feeds SB_IO iq_rx_24, removing $nextpnr_ibuf i_iq_rx_24_n. +Info: i_iq_rx_09_p feeds SB_IO iq_rx_09, removing $nextpnr_ibuf i_iq_rx_09_p. +Info: io_smi_data[5] feeds SB_IO smi_io5, removing $nextpnr_iobuf io_smi_data[5]. +Info: io_smi_data[4] feeds SB_IO smi_io4, removing $nextpnr_iobuf io_smi_data[4]. +Info: io_smi_data[3] feeds SB_IO smi_io3, removing $nextpnr_iobuf io_smi_data[3]. +Info: io_smi_data[2] feeds SB_IO smi_io2, removing $nextpnr_iobuf io_smi_data[2]. +Info: io_smi_data[1] feeds SB_IO smi_io1, removing $nextpnr_iobuf io_smi_data[1]. +Info: io_smi_data[0] feeds SB_IO smi_io0, removing $nextpnr_iobuf io_smi_data[0]. +Info: Packing LUT-FFs.. +Info: 367 LCs used as LUT4 only +Info: 183 LCs used as LUT4 and DFF +Info: Packing non-LUT FFs.. +Info: 333 LCs used as DFF only +Info: Packing carries.. +Info: 3 LCs used as CARRY only +Info: Packing indirect carry+LUT pairs... +Info: 1 LUTs merged into carry LCs +Info: Packing RAMs.. +Info: Placing PLLs.. +Info: Packing special functions.. +Info: Packing PLLs.. +Info: Promoting globals.. +Info: promoting o_iq_tx_clk_p$SB_IO_OUT (fanout 215) +Info: promoting r_counter (fanout 209) +Info: promoting i_rst_b_SB_LUT4_I3_O [reset] (fanout 201) +Info: promoting smi_ctrl_ins.swe_and_reset (fanout 57) +Info: promoting smi_ctrl_ins.soe_and_reset (fanout 43) +Info: promoting lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R [reset] (fanout 30) +Info: promoting lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R [reset] (fanout 30) +Info: promoting smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O [reset] (fanout 29) +Info: Constraining chains... +Info: 11 LCs used to legalise carry chains. +Info: Checksum: 0x0610fd56 + +Info: Annotating ports with timing budgets for target frequency 12.00 MHz +Info: Checksum: 0xa3c42850 + +Info: Device utilisation: +Info: ICESTORM_LC: 898/ 1280 70% +Info: ICESTORM_RAM: 16/ 16 100% +Info: SB_IO: 51/ 112 45% +Info: SB_GB: 8/ 8 100% +Info: ICESTORM_PLL: 0/ 1 0% +Info: SB_WARMBOOT: 0/ 1 0% + +Info: Placed 51 cells based on constraints. +Info: Creating initial analytic placement for 859 cells, random placement wirelen = 12699. +Info: at initial placer iter 0, wirelen = 558 +Info: at initial placer iter 1, wirelen = 762 +Info: at initial placer iter 2, wirelen = 789 +Info: at initial placer iter 3, wirelen = 706 +Info: Running main analytical placer. +Info: at iteration #1, type ICESTORM_LC: wirelen solved = 815, spread = 3956, legal = 5325; time = 0.18s +Info: at iteration #1, type SB_GB: wirelen solved = 5294, spread = 5338, legal = 5369; time = 0.02s +Info: at iteration #1, type ICESTORM_RAM: wirelen solved = 4968, spread = 5914, legal = 6193; time = 0.03s +Info: at iteration #1, type ALL: wirelen solved = 657, spread = 4189, legal = 7577; time = 2.03s +Info: at iteration #2, type ICESTORM_LC: wirelen solved = 2271, spread = 4012, legal = 5909; time = 0.61s +Info: at iteration #2, type SB_GB: wirelen solved = 5865, spread = 5898, legal = 5911; time = 0.02s +Info: at iteration #2, type ICESTORM_RAM: wirelen solved = 5601, spread = 5734, legal = 5899; time = 0.03s +Info: at iteration #2, type ALL: wirelen solved = 645, spread = 4234, legal = 7204; time = 0.77s +Info: at iteration #3, type ICESTORM_LC: wirelen solved = 2501, spread = 4092, legal = 5817; time = 0.71s +Info: at iteration #3, type SB_GB: wirelen solved = 5796, spread = 5858, legal = 5863; time = 0.02s +Info: at iteration #3, type ICESTORM_RAM: wirelen solved = 5684, spread = 5806, legal = 6097; time = 0.03s +Info: at iteration #3, type ALL: wirelen solved = 717, spread = 4054, legal = 7225; time = 0.53s +Info: at iteration #4, type ICESTORM_LC: wirelen solved = 2534, spread = 4085, legal = 5514; time = 0.82s +Info: at iteration #4, type SB_GB: wirelen solved = 5487, spread = 5525, legal = 5550; time = 0.02s +Info: at iteration #4, type ICESTORM_RAM: wirelen solved = 5157, spread = 5359, legal = 5837; time = 0.03s +Info: at iteration #4, type ALL: wirelen solved = 845, spread = 3706, legal = 6577; time = 0.97s +Info: at iteration #5, type ICESTORM_LC: wirelen solved = 2461, spread = 4002, legal = 5489; time = 0.37s +Info: at iteration #5, type SB_GB: wirelen solved = 5436, spread = 5487, legal = 5479; time = 0.02s +Info: at iteration #5, type ICESTORM_RAM: wirelen solved = 5216, spread = 5479, legal = 5851; time = 0.03s +Info: at iteration #5, type ALL: wirelen solved = 873, spread = 3768, legal = 6264; time = 0.89s +Info: at iteration #6, type ICESTORM_LC: wirelen solved = 2662, spread = 3924, legal = 5776; time = 0.23s +Info: at iteration #6, type SB_GB: wirelen solved = 5741, spread = 5777, legal = 5798; time = 0.02s +Info: at iteration #6, type ICESTORM_RAM: wirelen solved = 5373, spread = 5615, legal = 5804; time = 0.03s +Info: at iteration #6, type ALL: wirelen solved = 985, spread = 3702, legal = 6646; time = 0.68s +Info: at iteration #7, type ICESTORM_LC: wirelen solved = 2653, spread = 3911, legal = 5688; time = 0.20s +Info: at iteration #7, type SB_GB: wirelen solved = 5663, spread = 5723, legal = 5732; time = 0.02s +Info: at iteration #7, type ICESTORM_RAM: wirelen solved = 5313, spread = 5481, legal = 5709; time = 0.03s +Info: at iteration #7, type ALL: wirelen solved = 1017, spread = 3610, legal = 6825; time = 0.57s +Info: at iteration #8, type ICESTORM_LC: wirelen solved = 2763, spread = 4064, legal = 5700; time = 0.32s +Info: at iteration #8, type SB_GB: wirelen solved = 5643, spread = 5695, legal = 5690; time = 0.02s +Info: at iteration #8, type ICESTORM_RAM: wirelen solved = 5414, spread = 5627, legal = 5945; time = 0.03s +Info: at iteration #8, type ALL: wirelen solved = 1101, spread = 3911, legal = 7705; time = 0.74s +Info: at iteration #9, type ICESTORM_LC: wirelen solved = 2753, spread = 3980, legal = 5663; time = 0.15s +Info: at iteration #9, type SB_GB: wirelen solved = 5634, spread = 5660, legal = 5701; time = 0.02s +Info: at iteration #9, type ICESTORM_RAM: wirelen solved = 5109, spread = 5478, legal = 5802; time = 0.03s +Info: at iteration #9, type ALL: wirelen solved = 1006, spread = 3743, legal = 6631; time = 0.69s +Info: at iteration #10, type ICESTORM_LC: wirelen solved = 2759, spread = 3814, legal = 5567; time = 0.20s +Info: at iteration #10, type SB_GB: wirelen solved = 5523, spread = 5560, legal = 5593; time = 0.02s +Info: at iteration #10, type ICESTORM_RAM: wirelen solved = 5167, spread = 5483, legal = 5782; time = 0.03s +Info: at iteration #10, type ALL: wirelen solved = 1139, spread = 3597, legal = 6489; time = 0.47s +Info: HeAP Placer Time: 13.01s +Info: of which solving equations: 1.35s +Info: of which spreading cells: 0.13s +Info: of which strict legalisation: 11.27s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 528, wirelen = 6264 +Info: at iteration #5: temp = 0.000000, timing cost = 398, wirelen = 5227 +Info: at iteration #10: temp = 0.000000, timing cost = 417, wirelen = 4858 +Info: at iteration #15: temp = 0.000000, timing cost = 415, wirelen = 4546 +Info: at iteration #20: temp = 0.000000, timing cost = 419, wirelen = 4408 +Info: at iteration #25: temp = 0.000000, timing cost = 396, wirelen = 4307 +Info: at iteration #26: temp = 0.000000, timing cost = 365, wirelen = 4299 +Info: SA placement time 2.92s + +Info: Max frequency for clock 'r_counter_$glb_clk': 91.19 MHz (PASS at 64.00 MHz) +Info: Max frequency for clock 'smi_ctrl_ins.swe_and_reset_$glb_clk': 126.92 MHz (PASS at 12.00 MHz) +Info: Max frequency for clock 'i_sck$SB_IO_IN': 219.78 MHz (PASS at 5.00 MHz) +Info: Max frequency for clock 'smi_ctrl_ins.soe_and_reset_$glb_clk': 168.10 MHz (PASS at 16.00 MHz) +Info: Max frequency for clock 'o_iq_tx_clk_p$SB_IO_OUT_$glb_clk': 62.38 MHz (PASS at 12.00 MHz) +Info: Max frequency for clock 'i_glob_clock$SB_IO_IN': 463.61 MHz (PASS at 12.00 MHz) + +Info: Max delay -> : 5.93 ns +Info: Max delay -> posedge i_glob_clock$SB_IO_IN : 7.95 ns +Info: Max delay -> posedge i_sck$SB_IO_IN : 4.91 ns +Info: Max delay -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 9.07 ns +Info: Max delay -> posedge r_counter_$glb_clk : 8.64 ns +Info: Max delay -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 9.15 ns +Info: Max delay -> negedge smi_ctrl_ins.swe_and_reset_$glb_clk: 8.89 ns +Info: Max delay posedge i_glob_clock$SB_IO_IN -> posedge r_counter_$glb_clk : 3.53 ns +Info: Max delay posedge i_sck$SB_IO_IN -> posedge r_counter_$glb_clk : 2.35 ns +Info: Max delay posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -> posedge r_counter_$glb_clk : 3.44 ns +Info: Max delay posedge r_counter_$glb_clk -> : 5.70 ns +Info: Max delay posedge r_counter_$glb_clk -> posedge i_glob_clock$SB_IO_IN : 7.15 ns +Info: Max delay posedge r_counter_$glb_clk -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 9.08 ns +Info: Max delay posedge r_counter_$glb_clk -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 6.41 ns +Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> : 3.36 ns +Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 3.61 ns +Info: Max delay negedge smi_ctrl_ins.swe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 4.14 ns + +Info: Slack histogram: +Info: legend: * represents 20 endpoint(s) +Info: + represents [1,20) endpoint(s) +Info: [ 3667, 13376) |****************************************+ +Info: [ 13376, 23085) |**+ +Info: [ 23085, 32794) |***+ +Info: [ 32794, 42503) |***********+ +Info: [ 42503, 52212) | +Info: [ 52212, 61921) |***+ +Info: [ 61921, 71630) |+ +Info: [ 71630, 81339) |************************************************************ +Info: [ 81339, 91048) |+ +Info: [ 91048, 100757) | +Info: [100757, 110466) | +Info: [110466, 120175) | +Info: [120175, 129884) | +Info: [129884, 139593) | +Info: [139593, 149302) | +Info: [149302, 159011) | +Info: [159011, 168720) | +Info: [168720, 178429) | +Info: [178429, 188138) | +Info: [188138, 197847) |**+ +Info: Checksum: 0x9ea9b6cc + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 2787 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 161 824 | 161 824 | 1969| 0.88 0.88| +Info: 2000 | 435 1522 | 274 698 | 1303| 0.54 1.42| +Info: 3000 | 835 2119 | 400 597 | 834| 0.90 2.32| +Info: 4000 | 1118 2833 | 283 714 | 186| 0.74 3.07| +Info: 4336 | 1225 3063 | 107 230 | 0| 0.41 3.48| +Info: Routing complete. +Info: Router1 time 3.48s +Info: Checksum: 0xd1a3ff27 + +Info: Critical path report for clock 'r_counter_$glb_clk' (posedge -> posedge): +Info: curr total +Info: 0.8 0.8 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_8_LC.O +Info: 0.9 1.7 Net rx_fifo.rd_addr[0] budget 2.072000 ns (4,9) -> (5,9) +Info: Sink $nextpnr_ICESTORM_LC_3.I1 +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.4 2.0 Source $nextpnr_ICESTORM_LC_3.COUT +Info: 0.0 2.0 Net $nextpnr_ICESTORM_LC_3$O budget 0.000000 ns (5,9) -> (5,9) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_7_LC.CIN +Info: 0.2 2.2 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_7_LC.COUT +Info: 0.0 2.2 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] budget 0.000000 ns (5,9) -> (5,9) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_6_LC.CIN +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.2 2.4 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_6_LC.COUT +Info: 0.0 2.4 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] budget 0.000000 ns (5,9) -> (5,9) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_5_LC.CIN +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.2 2.6 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_5_LC.COUT +Info: 0.0 2.6 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] budget 0.000000 ns (5,9) -> (5,9) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_4_LC.CIN +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.2 2.8 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_4_LC.COUT +Info: 0.0 2.8 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] budget 0.000000 ns (5,9) -> (5,9) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_3_LC.CIN +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.2 3.0 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_3_LC.COUT +Info: 0.0 3.0 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] budget 0.000000 ns (5,9) -> (5,9) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_2_LC.CIN +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.2 3.2 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_2_LC.COUT +Info: 0.0 3.2 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] budget 0.000000 ns (5,9) -> (5,9) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_1_LC.CIN +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.2 3.3 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_1_LC.COUT +Info: 0.3 3.6 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] budget 0.290000 ns (5,9) -> (5,10) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_LC.CIN +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.2 3.8 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_O_SB_LUT4_O_LC.COUT +Info: 0.4 4.2 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] budget 0.380000 ns (5,10) -> (5,10) +Info: Sink rx_fifo.rd_addr_gray_SB_LUT4_I2_LC.I3 +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.5 4.7 Source rx_fifo.rd_addr_gray_SB_LUT4_I2_LC.O +Info: 0.9 5.5 Net rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] budget 2.084000 ns (5,10) -> (5,11) +Info: Sink rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_O_LC.I2 +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:73.15-73.29 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27 +Info: 0.6 6.1 Source rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D_SB_LUT4_O_LC.O +Info: 0.9 7.0 Net rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[3] budget 2.084000 ns (5,11) -> (5,11) +Info: Sink rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_O_LC.I3 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.5 7.4 Source rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_O_LC.O +Info: 0.9 8.3 Net rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] budget 2.084000 ns (5,11) -> (4,11) +Info: Sink rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.I3 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.5 8.8 Source rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.O +Info: 2.0 10.7 Net rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] budget 2.083000 ns (4,11) -> (4,6) +Info: Sink rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_LC.I2 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 11.3 Setup rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_LC.I2 +Info: 5.2 ns logic, 6.1 ns routing + +Info: Critical path report for clock 'smi_ctrl_ins.swe_and_reset_$glb_clk' (negedge -> negedge): +Info: curr total +Info: 0.8 0.8 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_D_SB_LUT4_O_LC.O +Info: 1.9 2.7 Net smi_ctrl_ins.tx_reg_state[3] budget 27.108000 ns (11,2) -> (7,2) +Info: Sink smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.I3 +Info: 0.5 3.1 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_1_LC.O +Info: 1.9 5.0 Net smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] budget 27.107000 ns (7,2) -> (5,3) +Info: Sink smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.I2 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 5.6 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.O +Info: 2.9 8.5 Net smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O budget 13.514000 ns (5,3) -> (9,4) +Info: Sink smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN +Info: 0.1 8.6 Setup smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN +Info: 1.9 ns logic, 6.7 ns routing + +Info: Critical path report for clock 'i_sck$SB_IO_IN' (posedge -> posedge): +Info: curr total +Info: 0.8 0.8 Source spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D_SB_LUT4_O_LC.O +Info: 0.9 1.7 Net spi_if_ins.spi.r_rx_bit_count[0] budget 41.667000 ns (9,8) -> (9,9) +Info: Sink spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_O_LC.I1 +Info: Defined in: +Info: top.v:111.10-126.4 +Info: spi_slave.v:32.25-32.43 +Info: spi_if.v:43.13-54.4 +Info: /usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 +Info: 0.6 2.3 Source spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_O_LC.O +Info: 0.9 3.1 Net spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] budget 41.666000 ns (9,9) -> (9,10) +Info: Sink spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.I3 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.5 3.6 Source spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.O +Info: 1.9 5.5 Net spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O budget 66.016998 ns (9,10) -> (9,11) +Info: Sink spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN +Info: 0.1 5.6 Setup spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN +Info: 1.9 ns logic, 3.7 ns routing + +Info: Critical path report for clock 'smi_ctrl_ins.soe_and_reset_$glb_clk' (negedge -> negedge): +Info: curr total +Info: 0.8 0.8 Source smi_ctrl_ins.int_cnt_rx_SB_DFFNSR_Q_1_D_SB_LUT4_O_LC.O +Info: 0.9 1.7 Net smi_ctrl_ins.int_cnt_rx[3] budget 30.507999 ns (2,6) -> (1,7) +Info: Sink smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.I1 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 2.3 Source smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.O +Info: 2.9 5.2 Net smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E budget 15.342000 ns (1,7) -> (4,8) +Info: Sink smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN +Info: 0.1 5.3 Setup smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN +Info: 1.5 ns logic, 3.8 ns routing + +Info: Critical path report for clock 'o_iq_tx_clk_p$SB_IO_OUT_$glb_clk' (negedge -> posedge): +Info: curr total +Info: 0.2 0.2 Source iq_rx_24.D_IN_1 +Info: 1.9 2.1 Net w_lvds_rx_24_d1 budget 13.403000 ns (0,13) -> (2,11) +Info: Sink w_lvds_rx_24_d1_SB_LUT4_I1_LC.I1 +Info: Defined in: +Info: top.v:300.8-300.23 +Info: 0.6 2.7 Source w_lvds_rx_24_d1_SB_LUT4_I1_LC.O +Info: 1.9 4.6 Net w_lvds_rx_24_d1_SB_LUT4_I1_O[2] budget 13.403000 ns (2,11) -> (6,8) +Info: Sink w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_LC.I2 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 5.1 Source w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_LC.O +Info: 3.6 8.7 Net w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O budget 13.403000 ns (6,8) -> (12,6) +Info: Sink lvds_rx_24_inst.r_state_if_SB_LUT4_I2_11_LC.CEN +Info: 0.1 8.8 Setup lvds_rx_24_inst.r_state_if_SB_LUT4_I2_11_LC.CEN +Info: 1.5 ns logic, 7.4 ns routing + +Info: Critical path report for clock 'i_glob_clock$SB_IO_IN' (posedge -> posedge): +Info: curr total +Info: 0.8 0.8 Source r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.O +Info: 0.9 1.7 Net r_counter budget 82.042999 ns (12,5) -> (12,5) +Info: Sink r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.I3 +Info: Defined in: +Info: top.v:393.8-393.23 +Info: 0.5 2.2 Setup r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.I3 +Info: 1.3 ns logic, 0.9 ns routing + +Info: Critical path report for cross-domain path '' -> '': +Info: curr total +Info: 0.0 0.0 Source i_smi_a2$sb_io.D_IN_0 +Info: 3.4 3.4 Net i_smi_a2$SB_IO_IN budget 41.433998 ns (1,17) -> (5,3) +Info: Sink o_smi_read_req_SB_LUT4_O_LC.I3 +Info: Defined in: +Info: top.v:74.11-74.19 +Info: 0.5 3.9 Source o_smi_read_req_SB_LUT4_O_LC.O +Info: 2.3 6.2 Net o_smi_read_req$SB_IO_OUT budget 40.973999 ns (5,3) -> (13,3) +Info: Sink o_smi_read_req$sb_io.D_OUT_0 +Info: Defined in: +Info: top.v:81.12-81.26 +Info: 0.5 ns logic, 5.7 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge i_glob_clock$SB_IO_IN': +Info: curr total +Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0 +Info: 2.5 2.5 Net i_rst_b$SB_IO_IN budget 4.717000 ns (7,17) -> (11,9) +Info: Sink i_rst_b_SB_LUT4_I3_LC.I3 +Info: Defined in: +Info: top.v:401.5-417.4 +Info: complex_fifo.v:6.28-6.38 +Info: 0.5 2.9 Source i_rst_b_SB_LUT4_I3_LC.O +Info: 0.9 3.9 Net i_rst_b_SB_LUT4_I3_O budget 4.717000 ns (11,9) -> (13,9) +Info: Sink $gbuf_i_rst_b_SB_LUT4_I3_O_$glb_sr.USER_SIGNAL_TO_GLOBAL_BUFFER +Info: 0.9 4.8 Source $gbuf_i_rst_b_SB_LUT4_I3_O_$glb_sr.GLOBAL_BUFFER_OUTPUT +Info: 0.7 5.5 Net i_rst_b_SB_LUT4_I3_O_$glb_sr budget 27.285999 ns (13,9) -> (12,5) +Info: Sink r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR +Info: 0.1 5.6 Setup r_counter_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR +Info: 1.5 ns logic, 4.1 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge i_sck$SB_IO_IN': +Info: curr total +Info: 0.0 0.0 Source i_ss$sb_io.D_IN_0 +Info: 2.9 2.9 Net i_ss$SB_IO_IN budget 83.333000 ns (12,0) -> (9,10) +Info: Sink spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.I2 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 3.5 Source spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_LC.O +Info: 1.9 5.4 Net spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O budget 66.016998 ns (9,10) -> (9,11) +Info: Sink spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN +Info: 0.1 5.5 Setup spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_DFFLC.CEN +Info: 0.7 ns logic, 4.8 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk': +Info: curr total +Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0 +Info: 2.9 2.9 Net i_rst_b$SB_IO_IN budget 27.362000 ns (7,17) -> (5,7) +Info: Sink lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2_SB_LUT4_O_LC.I1 +Info: Defined in: +Info: top.v:401.5-417.4 +Info: complex_fifo.v:6.28-6.38 +Info: 0.6 3.5 Source lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2_SB_LUT4_O_LC.O +Info: 0.9 4.4 Net lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[1] budget 27.107000 ns (5,7) -> (6,8) +Info: Sink lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_LC.I2 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 4.9 Source lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_LC.O +Info: 2.3 7.2 Net lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R budget 27.107000 ns (6,8) -> (7,13) +Info: Sink lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR +Info: 0.1 7.3 Setup lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_D_SB_LUT4_O_LC.SR +Info: 1.2 ns logic, 6.0 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge r_counter_$glb_clk': +Info: curr total +Info: 0.0 0.0 Source i_ss$sb_io.D_IN_0 +Info: 3.3 3.3 Net i_ss$SB_IO_IN budget 4.834000 ns (12,0) -> (6,9) +Info: Sink spi_if_ins.r_tx_data_valid_SB_LUT4_I3_LC.I2 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 3.9 Source spi_if_ins.r_tx_data_valid_SB_LUT4_I3_LC.O +Info: 0.9 4.7 Net spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O budget 4.600000 ns (6,9) -> (7,9) +Info: Sink spi_if_ins.spi.SCKr_SB_LUT4_I1_LC.I3 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.5 5.2 Source spi_if_ins.spi.SCKr_SB_LUT4_I1_LC.O +Info: 2.8 8.0 Net spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E budget 4.600000 ns (7,9) -> (11,9) +Info: Sink spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_LC.CEN +Info: 0.1 8.1 Setup spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_LC.CEN +Info: 1.1 ns logic, 7.0 ns routing + +Info: Critical path report for cross-domain path '' -> 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk': +Info: curr total +Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0 +Info: 3.4 3.4 Net i_rst_b$SB_IO_IN budget 15.343000 ns (7,17) -> (1,7) +Info: Sink smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.I3 +Info: Defined in: +Info: top.v:401.5-417.4 +Info: complex_fifo.v:6.28-6.38 +Info: 0.5 3.9 Source smi_ctrl_ins.int_cnt_rx_SB_LUT4_I1_LC.O +Info: 2.9 6.8 Net smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E budget 15.342000 ns (1,7) -> (4,8) +Info: Sink smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN +Info: 0.1 6.9 Setup smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_10_DFFLC.CEN +Info: 0.6 ns logic, 6.4 ns routing + +Info: Critical path report for cross-domain path '' -> 'negedge smi_ctrl_ins.swe_and_reset_$glb_clk': +Info: curr total +Info: 0.0 0.0 Source i_rst_b$sb_io.D_IN_0 +Info: 2.9 2.9 Net i_rst_b$SB_IO_IN budget 13.515000 ns (7,17) -> (6,2) +Info: Sink smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E_SB_LUT4_O_LC.I3 +Info: Defined in: +Info: top.v:401.5-417.4 +Info: complex_fifo.v:6.28-6.38 +Info: 0.5 3.3 Source smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E_SB_LUT4_O_LC.O +Info: 0.9 4.2 Net smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] budget 13.514000 ns (6,2) -> (5,3) +Info: Sink smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.I3 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.5 4.7 Source smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_LC.O +Info: 2.9 7.6 Net smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O budget 13.514000 ns (5,3) -> (9,4) +Info: Sink smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN +Info: 0.1 7.7 Setup smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_11_DFFLC.CEN +Info: 1.0 ns logic, 6.7 ns routing + +Info: Critical path report for cross-domain path 'posedge i_glob_clock$SB_IO_IN' -> 'posedge r_counter_$glb_clk': +Info: curr total +Info: 0.8 0.8 Source r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_2_LC.O +Info: 1.7 2.5 Net r_tx_data[3] budget 14.139000 ns (12,12) -> (7,12) +Info: Sink spi_if_ins.r_tx_byte_SB_DFFE_Q_4_DFFLC.I0 +Info: Defined in: +Info: top.v:111.10-126.4 +Info: spi_if.v:9.22-9.32 +Info: 0.7 3.1 Setup spi_if_ins.r_tx_byte_SB_DFFE_Q_4_DFFLC.I0 +Info: 1.5 ns logic, 1.7 ns routing + +Info: Critical path report for cross-domain path 'posedge i_sck$SB_IO_IN' -> 'posedge r_counter_$glb_clk': +Info: curr total +Info: 0.8 0.8 Source spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_4_DFFLC.O +Info: 0.9 1.7 Net spi_if_ins.spi.r_rx_byte[3] budget 14.139000 ns (9,11) -> (8,11) +Info: Sink spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_4_DFFLC.I0 +Info: Defined in: +Info: top.v:111.10-126.4 +Info: spi_slave.v:19.13-19.22 +Info: spi_if.v:43.13-54.4 +Info: 0.7 2.4 Setup spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_4_DFFLC.I0 +Info: 1.5 ns logic, 0.9 ns routing + +Info: Critical path report for cross-domain path 'posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk' -> 'posedge r_counter_$glb_clk': +Info: curr total +Info: 0.8 0.8 Source rx_fifo.wr_addr_gray_SB_DFFESR_Q_DFFLC.O +Info: 1.9 2.7 Net rx_fifo.wr_addr[9] budget 14.139000 ns (2,14) -> (4,15) +Info: Sink rx_fifo.wr_addr_gray_rd_SB_DFF_Q_DFFLC.I0 +Info: Defined in: +Info: top.v:354.5-367.4 +Info: complex_fifo.v:24.23-24.35 +Info: 0.7 3.4 Setup rx_fifo.wr_addr_gray_rd_SB_DFF_Q_DFFLC.I0 +Info: 1.5 ns logic, 1.9 ns routing + +Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> '': +Info: curr total +Info: 0.8 0.8 Source rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_LC.O +Info: 2.0 2.8 Net w_rx_fifo_empty budget 40.974998 ns (4,6) -> (5,3) +Info: Sink o_smi_read_req_SB_LUT4_O_LC.I1 +Info: Defined in: +Info: top.v:347.8-347.23 +Info: 0.6 3.3 Source o_smi_read_req_SB_LUT4_O_LC.O +Info: 2.3 5.6 Net o_smi_read_req$SB_IO_OUT budget 40.973999 ns (5,3) -> (13,3) +Info: Sink o_smi_read_req$sb_io.D_OUT_0 +Info: Defined in: +Info: top.v:81.12-81.26 +Info: 1.4 ns logic, 4.2 ns routing + +Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> 'posedge i_glob_clock$SB_IO_IN': +Info: curr total +Info: 0.8 0.8 Source spi_if_ins.o_cs_SB_DFFESR_Q_D_SB_LUT4_O_2_LC.O +Info: 1.9 2.7 Net w_cs[3] budget 27.073000 ns (2,10) -> (6,12) +Info: Sink spi_if_ins.o_cs_SB_LUT4_I0_2_LC.I0 +Info: Defined in: +Info: top.v:100.14-100.18 +Info: 0.7 3.3 Source spi_if_ins.o_cs_SB_LUT4_I0_2_LC.O +Info: 0.9 4.2 Net spi_if_ins.o_cs_SB_LUT4_I0_2_O[0] budget 27.073000 ns (6,12) -> (7,12) +Info: Sink r_tx_data_SB_DFFE_Q_E_SB_LUT4_O_LC.I2 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 4.8 Source r_tx_data_SB_DFFE_Q_E_SB_LUT4_O_LC.O +Info: 2.3 7.1 Net r_tx_data_SB_DFFE_Q_E budget 27.073000 ns (7,12) -> (12,12) +Info: Sink r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_2_LC.CEN +Info: 0.1 7.2 Setup r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_2_LC.CEN +Info: 2.1 ns logic, 5.0 ns routing + +Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> 'posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk': +Info: curr total +Info: 0.8 0.8 Source smi_ctrl_ins.r_channel_SB_DFFE_Q_DFFLC.O +Info: 1.4 2.2 Net channel budget 20.082001 ns (4,11) -> (4,14) +Info: Sink rx_fifo.wr_en_i_SB_LUT4_O_LC.I3 +Info: Defined in: +Info: top.v:419.12-451.4 +Info: smi_ctrl.v:106.9-106.18 +Info: 0.5 2.7 Source rx_fifo.wr_en_i_SB_LUT4_O_LC.O +Info: 0.9 3.5 Net w_rx_fifo_push budget 20.082001 ns (4,14) -> (4,15) +Info: Sink rx_fifo.full_o_SB_LUT4_I3_LC.I0 +Info: Defined in: +Info: top.v:342.8-342.22 +Info: 0.7 4.2 Source rx_fifo.full_o_SB_LUT4_I3_LC.O +Info: 0.9 5.1 Net rx_fifo.full_o_SB_LUT4_I3_O[3] budget 20.082001 ns (4,15) -> (4,15) +Info: Sink rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_LC.I3 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.5 5.5 Source rx_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_LC.O +Info: 2.5 8.0 Net rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] budget 15.561000 ns (4,15) -> (4,5) +Info: Sink rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_LC.I1 +Info: Defined in: +Info: /usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 +Info: 0.6 8.6 Setup rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_LC.I1 +Info: 3.0 ns logic, 5.6 ns routing + +Info: Critical path report for cross-domain path 'posedge r_counter_$glb_clk' -> 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk': +Info: curr total +Info: 3.2 3.2 Source rx_fifo.mem_q.0.2_RAM.RDATA_13 +Info: 3.0 6.1 Net w_rx_fifo_pulled_data[11] budget 27.396000 ns (3,15) -> (1,7) +Info: Sink smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_20_DFFLC.I0 +Info: Defined in: +Info: top.v:419.12-451.4 +Info: smi_ctrl.v:16.25-16.46 +Info: 0.7 6.8 Setup smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_20_DFFLC.I0 +Info: 3.9 ns logic, 3.0 ns routing + +Info: Critical path report for cross-domain path 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk' -> '': +Info: curr total +Info: 0.8 0.8 Source smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_LC.O +Info: 2.5 3.3 Net w_smi_data_output[3] budget 40.870998 ns (8,4) -> (7,0) +Info: Sink smi_io3.D_OUT_0 +Info: Defined in: +Info: top.v:453.14-453.31 +Info: 0.8 ns logic, 2.5 ns routing + +Info: Critical path report for cross-domain path 'negedge smi_ctrl_ins.soe_and_reset_$glb_clk' -> 'posedge r_counter_$glb_clk': +Info: curr total +Info: 0.8 0.8 Source smi_ctrl_ins.w_fifo_pull_trigger_SB_DFFNE_Q_D_SB_LUT4_O_LC.O +Info: 1.9 2.7 Net smi_ctrl_ins.w_fifo_pull_trigger budget 6.326000 ns (8,4) -> (4,6) +Info: Sink smi_ctrl_ins.r_fifo_pull_SB_DFFSR_Q_DFFLC.I0 +Info: Defined in: +Info: top.v:419.12-451.4 +Info: smi_ctrl.v:105.10-105.29 +Info: 0.7 3.4 Setup smi_ctrl_ins.r_fifo_pull_SB_DFFSR_Q_DFFLC.I0 +Info: 1.5 ns logic, 1.9 ns routing + +Info: Critical path report for cross-domain path 'negedge smi_ctrl_ins.swe_and_reset_$glb_clk' -> 'posedge r_counter_$glb_clk': +Info: curr total +Info: 0.8 0.8 Source smi_ctrl_ins.o_tx_fifo_pushed_data_SB_DFFNESR_Q_17_DFFLC.O +Info: 3.5 4.3 Net w_tx_fifo_data[12] budget 6.917000 ns (6,2) -> (10,15) +Info: Sink tx_fifo.mem_q.0.3_RAM.WDATA_1 +Info: Defined in: +Info: top.v:394.15-394.29 +Info: 0.1 4.4 Setup tx_fifo.mem_q.0.3_RAM.WDATA_1 +Info: 0.9 ns logic, 3.5 ns routing + +Info: Max frequency for clock 'r_counter_$glb_clk': 88.45 MHz (PASS at 64.00 MHz) +Info: Max frequency for clock 'smi_ctrl_ins.swe_and_reset_$glb_clk': 116.17 MHz (PASS at 12.00 MHz) +Info: Max frequency for clock 'i_sck$SB_IO_IN': 178.48 MHz (PASS at 5.00 MHz) +Info: Max frequency for clock 'smi_ctrl_ins.soe_and_reset_$glb_clk': 189.29 MHz (PASS at 16.00 MHz) +Info: Max frequency for clock 'o_iq_tx_clk_p$SB_IO_OUT_$glb_clk': 56.50 MHz (PASS at 12.00 MHz) +Info: Max frequency for clock 'i_glob_clock$SB_IO_IN': 463.61 MHz (PASS at 12.00 MHz) + +Info: Max delay -> : 6.18 ns +Info: Max delay -> posedge i_glob_clock$SB_IO_IN : 5.56 ns +Info: Max delay -> posedge i_sck$SB_IO_IN : 5.49 ns +Info: Max delay -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 7.28 ns +Info: Max delay -> posedge r_counter_$glb_clk : 8.12 ns +Info: Max delay -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 6.95 ns +Info: Max delay -> negedge smi_ctrl_ins.swe_and_reset_$glb_clk: 7.70 ns +Info: Max delay posedge i_glob_clock$SB_IO_IN -> posedge r_counter_$glb_clk : 3.15 ns +Info: Max delay posedge i_sck$SB_IO_IN -> posedge r_counter_$glb_clk : 2.35 ns +Info: Max delay posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk -> posedge r_counter_$glb_clk : 3.37 ns +Info: Max delay posedge r_counter_$glb_clk -> : 5.61 ns +Info: Max delay posedge r_counter_$glb_clk -> posedge i_glob_clock$SB_IO_IN : 7.16 ns +Info: Max delay posedge r_counter_$glb_clk -> posedge o_iq_tx_clk_p$SB_IO_OUT_$glb_clk : 8.61 ns +Info: Max delay posedge r_counter_$glb_clk -> negedge smi_ctrl_ins.soe_and_reset_$glb_clk: 6.83 ns +Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> : 3.25 ns +Info: Max delay negedge smi_ctrl_ins.soe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 3.37 ns +Info: Max delay negedge smi_ctrl_ins.swe_and_reset_$glb_clk -> posedge r_counter_$glb_clk : 4.41 ns + +Info: Slack histogram: +Info: legend: * represents 20 endpoint(s) +Info: + represents [1,20) endpoint(s) +Info: [ 3397, 13120) |************************************+ +Info: [ 13120, 22843) |****+ +Info: [ 22843, 32566) |*****+ +Info: [ 32566, 42289) |***********+ +Info: [ 42289, 52012) | +Info: [ 52012, 61735) |***+ +Info: [ 61735, 71458) |+ +Info: [ 71458, 81181) |************************************************************ +Info: [ 81181, 90904) |+ +Info: [ 90904, 100627) | +Info: [100627, 110350) | +Info: [110350, 120073) | +Info: [120073, 129796) | +Info: [129796, 139519) | +Info: [139519, 149242) | +Info: [149242, 158965) | +Info: [158965, 168688) | +Info: [168688, 178411) | +Info: [178411, 188134) | +Info: [188134, 197857) |**+ + +Info: Program finished normally. +icepack top.asc top.bin diff --git a/firmware/smi_ctrl.v b/firmware/smi_ctrl.v index 65624d8..127c031 100644 --- a/firmware/smi_ctrl.v +++ b/firmware/smi_ctrl.v @@ -15,6 +15,7 @@ module smi_ctrl output o_rx_fifo_pull, input [31:0] i_rx_fifo_pulled_data, input i_rx_fifo_empty, + output o_tx_fifo_push, output reg [31:0] o_tx_fifo_pushed_data, input i_tx_fifo_full, diff --git a/firmware/top.asc b/firmware/top.asc index dd84247..b33886f 100644 --- a/firmware/top.asc +++ b/firmware/top.asc @@ -56,87 +56,87 @@ .io_tile 4 0 000000000000000010 -000000000000000000 -000000110000000000 -000000000000000001 -000000000000010001 -000000000011110000 -001110000000000000 -000000110000010000 -000000000000000000 -000100000000000000 +001000000000000000 +000010000000000000 +010000110000000001 +000000111010000001 +000000001001110000 +001100000000001000 +000000000000001000 000000000000000000 000000000000000000 +000000000000000100 +000011110000001100 000000000000000000 000000000000000000 000000000000000000 000000000000000000 .io_tile 5 0 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+0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000 + .ram_data 3 7 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 @@ -4608,1262 +4752,1693 @@ 0000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000000000000000000000000000000 -.sym 1 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 2 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 3 lvds_clock_$glb_clk -.sym 4 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 5 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 6 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 7 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 1 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O_$glb_sr +.sym 2 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 3 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 4 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 6 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 7 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr .sym 8 r_counter_$glb_clk -.sym 54 rx_fifo.wr_addr_gray_rd[1] -.sym 79 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 178 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 179 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 180 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 181 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 182 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 183 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 184 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 291 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 292 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 293 rx_fifo.wr_addr[1] -.sym 294 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 295 rx_fifo.wr_addr_gray[4] -.sym 296 rx_fifo.wr_addr_gray[7] -.sym 297 rx_fifo.wr_addr[4] -.sym 298 rx_fifo.wr_addr[2] -.sym 329 rx_fifo.wr_addr[3] -.sym 406 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 409 $io_pmod[3]$iobuf_i -.sym 412 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 430 rx_fifo.wr_addr[4] -.sym 432 rx_fifo.wr_addr[2] -.sym 448 rx_fifo.wr_addr[2] -.sym 460 rx_fifo.wr_addr[2] -.sym 519 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 520 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 521 rx_fifo.rd_addr_gray_wr_r[7] -.sym 522 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 523 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 524 rx_fifo.rd_addr_gray_wr[7] -.sym 525 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 526 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 530 i_rst_b$SB_IO_IN -.sym 634 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 635 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 636 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 637 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] -.sym 638 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 639 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 640 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] -.sym 650 rx_fifo.rd_addr_gray_wr_r[5] -.sym 653 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 699 rx_fifo.rd_addr_gray[7] -.sym 746 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[8] -.sym 747 rx_fifo.wr_addr[6] -.sym 748 rx_fifo.wr_addr[5] -.sym 750 rx_fifo.wr_addr_gray[8] -.sym 751 rx_fifo.wr_addr[9] -.sym 752 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 753 rx_fifo.wr_addr[8] -.sym 766 w_debug_fifo_pull -.sym 830 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 858 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 862 w_rx_09_fifo_data[3] -.sym 869 rx_fifo.wr_addr[9] -.sym 887 rx_fifo.wr_addr[8] -.sym 899 rx_fifo.wr_addr[9] -.sym 908 rx_fifo.wr_addr[6] -.sym 915 rx_fifo.wr_addr[8] -.sym 944 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O -.sym 968 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O -.sym 976 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O -.sym 980 w_rx_24_fifo_data[1] -.sym 1007 lvds_clock -.sym 1037 $PACKER_VCC_NET -.sym 1054 lvds_clock -.sym 1056 $PACKER_VCC_NET -.sym 1088 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 1089 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 1090 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 1093 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 1130 i_rst_b$SB_IO_IN -.sym 1168 w_lvds_rx_09_d1 -.sym 1169 w_lvds_rx_09_d0 -.sym 1173 w_lvds_rx_09_d1 -.sym 1174 w_lvds_rx_09_d0 +.sym 49 w_rx_09_fifo_data[10] +.sym 51 w_rx_09_fifo_data[13] +.sym 135 i_smi_a2$SB_IO_IN +.sym 145 i_smi_a2$SB_IO_IN +.sym 177 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 180 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 181 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 184 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 194 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 203 w_tx_fifo_data[14] +.sym 221 w_rx_09_fifo_data[5] +.sym 291 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 294 o_iq_tx_clk_n$SB_IO_OUT +.sym 295 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 296 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] +.sym 297 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 298 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 328 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 334 i_rst_b$SB_IO_IN +.sym 335 w_rx_09_fifo_data[21] +.sym 405 w_rx_09_fifo_data[27] +.sym 406 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] +.sym 407 w_rx_09_fifo_data[23] +.sym 408 lvds_rx_09_inst.o_fifo_data[31] +.sym 409 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] +.sym 410 w_rx_09_fifo_data[25] +.sym 411 w_rx_09_fifo_data[29] +.sym 412 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] +.sym 414 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] +.sym 432 w_tx_fifo_pulled_data[12] +.sym 438 o_iq_tx_clk_p$SB_IO_OUT +.sym 443 w_rx_fifo_pulled_data[13] +.sym 485 o_iq_tx_clk_p$SB_IO_OUT +.sym 492 o_iq_tx_clk_n$SB_IO_OUT +.sym 497 o_iq_tx_clk_p$SB_IO_OUT +.sym 514 o_iq_tx_clk_n$SB_IO_OUT +.sym 515 o_iq_tx_clk_p$SB_IO_OUT +.sym 520 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] +.sym 521 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] +.sym 525 lvds_rx_09_inst.r_phase_count[1] +.sym 526 w_smi_data_output[7] +.sym 556 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 597 w_rx_09_fifo_data[24] +.sym 601 i_smi_a2$SB_IO_IN +.sym 633 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] +.sym 634 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] +.sym 636 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] +.sym 637 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 639 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 640 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 672 i_rst_b$SB_IO_IN +.sym 675 $PACKER_VCC_NET +.sym 747 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 748 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 749 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 751 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 752 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 753 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 755 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[1] +.sym 761 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 774 w_rx_24_fifo_data[21] +.sym 778 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] +.sym 783 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 786 i_rst_b$SB_IO_IN +.sym 787 w_rx_fifo_pulled_data[10] +.sym 790 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] +.sym 812 channel +.sym 830 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 849 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 863 w_rx_09_fifo_data[1] +.sym 865 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 866 w_rx_09_fifo_data[0] +.sym 868 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 899 rx_fifo.rd_data_o[25] +.sym 901 rx_fifo.rd_data_o[27] +.sym 903 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 940 o_iq_tx_clk_p$SB_IO_OUT +.sym 944 o_iq_tx_clk_p$SB_IO_OUT +.sym 970 o_iq_tx_clk_p$SB_IO_OUT +.sym 974 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 975 iq_tx_p_D_OUT_1 +.sym 980 w_lvds_tx_d0 +.sym 981 iq_tx_p_D_OUT_0 +.sym 1012 w_rx_fifo_data[10] +.sym 1024 w_lvds_rx_09_d0 +.sym 1031 w_lvds_rx_09_d1 +.sym 1052 rx_fifo.rd_addr_gray_wr_r[2] +.sym 1054 w_lvds_rx_09_d0 +.sym 1055 w_lvds_rx_09_d1 +.sym 1056 i_smi_a2$SB_IO_IN +.sym 1061 w_lvds_tx_d1 +.sym 1062 w_lvds_tx_d0 +.sym 1066 iq_tx_p_D_OUT_0 +.sym 1067 iq_tx_p_D_OUT_1 +.sym 1069 $PACKER_VCC_NET +.sym 1071 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 1074 $PACKER_VCC_NET +.sym 1079 iq_tx_p_D_OUT_0 +.sym 1081 iq_tx_p_D_OUT_1 +.sym 1085 w_lvds_tx_d1 +.sym 1086 w_lvds_tx_d0 +.sym 1088 w_rx_24_fifo_data[1] +.sym 1092 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 1094 w_rx_24_fifo_data[0] +.sym 1116 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] +.sym 1125 $PACKER_VCC_NET +.sym 1130 $PACKER_VCC_NET +.sym 1132 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 1135 i_rst_b$SB_IO_IN +.sym 1136 rx_fifo.rd_addr[8] +.sym 1163 w_lvds_tx_d1 +.sym 1167 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 1170 $PACKER_VCC_NET +.sym 1173 w_lvds_rx_09_d0 +.sym 1174 w_lvds_rx_09_d1 .sym 1183 $PACKER_VCC_NET -.sym 1184 lvds_clock_$glb_clk +.sym 1184 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 1188 $PACKER_VCC_NET -.sym 1203 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 1204 w_rx_24_fifo_data[0] -.sym 1246 w_rx_24_fifo_data[10] -.sym 1262 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 1287 lvds_clock +.sym 1204 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 1205 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 1206 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 1207 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 1208 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 1209 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 1222 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 1227 i_mosi$SB_IO_IN +.sym 1235 w_lvds_rx_24_d0 +.sym 1240 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 1246 $PACKER_VCC_NET +.sym 1277 w_rx_24_fifo_data[1] +.sym 1279 w_lvds_rx_24_d1 +.sym 1282 w_lvds_rx_24_d0 +.sym 1283 w_lvds_rx_24_d1 +.sym 1287 o_iq_tx_clk_p$SB_IO_OUT .sym 1297 $PACKER_VCC_NET -.sym 1305 $PACKER_VCC_NET -.sym 1317 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 1318 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 1319 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 1320 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 1321 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 1323 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 1331 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 1353 $PACKER_VCC_NET -.sym 1401 w_lvds_rx_24_d1 -.sym 1402 w_lvds_rx_24_d0 +.sym 1310 $PACKER_VCC_NET +.sym 1316 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1] +.sym 1317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 1318 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 1319 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 1320 rx_fifo.rd_addr_gray_wr[5] +.sym 1321 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 1322 rx_fifo.rd_addr_gray_wr_r[5] +.sym 1323 rx_fifo.rd_addr_gray_wr[4] +.sym 1351 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 1401 w_lvds_rx_24_d0 +.sym 1402 w_lvds_rx_24_d1 .sym 1411 $PACKER_VCC_NET -.sym 1412 lvds_clock_$glb_clk -.sym 1424 $PACKER_VCC_NET -.sym 1432 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 1433 w_rx_09_fifo_data[0] -.sym 1435 w_rx_09_fifo_data[1] -.sym 1467 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 1478 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 1485 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 1412 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 1416 $PACKER_VCC_NET +.sym 1431 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 1432 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 1433 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 1434 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 1435 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 1436 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 1437 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 1455 w_tx_fifo_pull +.sym 1462 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 1464 w_lvds_rx_24_d1 +.sym 1467 i_smi_a2$SB_IO_IN .sym 1490 $PACKER_VCC_NET -.sym 1497 w_lvds_rx_24_d1 -.sym 1547 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 1577 w_lvds_rx_09_d1 -.sym 1589 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 1621 w_lvds_rx_09_d0 -.sym 1879 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 1881 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 1882 rx_fifo.wr_addr_gray_rd[0] -.sym 1883 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 1884 rx_fifo.wr_addr_gray_rd[3] -.sym 1886 rx_fifo.wr_addr_gray_rd[2] -.sym 1893 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 1895 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 1948 rx_fifo.wr_addr[6] -.sym 1951 rx_fifo.wr_addr[5] -.sym 2063 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -.sym 2064 rx_fifo.wr_addr_gray[0] -.sym 2065 rx_fifo.wr_addr_gray[3] -.sym 2066 rx_fifo.wr_addr_gray[1] -.sym 2067 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 2068 rx_fifo.wr_addr[0] -.sym 2070 rx_fifo.wr_addr_gray[2] -.sym 2106 rx_fifo.wr_addr_gray_rd[1] -.sym 2135 rx_fifo.wr_addr[4] -.sym 2137 rx_fifo.wr_addr[8] -.sym 2139 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2141 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 2143 rx_fifo.wr_addr[1] -.sym 2171 rx_fifo.wr_addr_gray[1] -.sym 2227 rx_fifo.wr_addr_gray[1] -.sym 2232 r_counter_$glb_clk -.sym 2234 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 2235 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 2236 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 2237 rx_fifo.wr_addr[3] -.sym 2238 rx_fifo.wr_addr[7] -.sym 2239 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 2240 rx_fifo.wr_addr_gray[5] -.sym 2241 rx_fifo.wr_addr_gray[6] -.sym 2259 rx_fifo.wr_addr[4] -.sym 2260 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2261 rx_fifo.wr_addr[2] -.sym 2262 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 2265 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2267 rx_fifo.wr_addr[1] -.sym 2275 rx_fifo.rd_addr_gray_wr_r[7] -.sym 2288 rx_fifo.wr_addr[5] -.sym 2292 rx_fifo.wr_addr[0] -.sym 2294 rx_fifo.wr_addr[2] -.sym 2297 rx_fifo.wr_addr[1] -.sym 2300 rx_fifo.wr_addr[0] -.sym 2301 rx_fifo.wr_addr[4] -.sym 2302 rx_fifo.wr_addr[6] -.sym 2314 rx_fifo.wr_addr[3] -.sym 2315 rx_fifo.wr_addr[7] -.sym 2319 $nextpnr_ICESTORM_LC_3$O -.sym 2321 rx_fifo.wr_addr[0] -.sym 2325 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 2328 rx_fifo.wr_addr[1] -.sym 2329 rx_fifo.wr_addr[0] -.sym 2331 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 2333 rx_fifo.wr_addr[2] -.sym 2335 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 2337 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 2339 rx_fifo.wr_addr[3] -.sym 2341 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 2343 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 2345 rx_fifo.wr_addr[4] -.sym 2347 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 2349 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 2352 rx_fifo.wr_addr[5] -.sym 2353 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 2355 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 2358 rx_fifo.wr_addr[6] -.sym 2359 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 2361 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 2364 rx_fifo.wr_addr[7] -.sym 2365 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 2369 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 2370 rx_fifo.wr_addr_gray_rd[5] -.sym 2371 rx_fifo.wr_addr_gray_rd[6] -.sym 2372 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[3] -.sym 2373 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 2374 rx_fifo.wr_addr_gray_rd[4] -.sym 2375 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 2376 rx_fifo.wr_addr_gray_rd[7] -.sym 2382 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 2384 rx_fifo.wr_addr[3] -.sym 2395 rx_fifo.rd_addr_gray_wr_r[0] -.sym 2399 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 2402 rx_fifo.rd_addr_gray[3] -.sym 2404 rx_fifo.rd_addr_gray_wr_r[8] -.sym 2405 rx_fifo.wr_addr[1] -.sym 2409 rx_fifo.wr_addr[3] -.sym 2411 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 2417 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 2424 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 2426 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 2428 rx_fifo.wr_addr[8] -.sym 2429 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 2431 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 2432 rx_fifo.wr_addr[9] -.sym 2438 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 2442 rx_fifo.rd_addr_gray_wr_r[7] -.sym 2446 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2449 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2454 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] -.sym 2457 rx_fifo.wr_addr[8] -.sym 2458 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 2463 rx_fifo.wr_addr[9] -.sym 2464 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] -.sym 2467 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 2473 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2475 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 2476 rx_fifo.rd_addr_gray_wr_r[7] -.sym 2481 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 2485 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 2487 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2491 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 2498 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 2501 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2502 lvds_clock_$glb_clk +.sym 1512 i_smi_a2$SB_IO_IN +.sym 1544 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 1545 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 1546 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 1547 rx_fifo.wr_addr[0] +.sym 1549 rx_fifo.wr_addr[8] +.sym 1693 rx_fifo.wr_addr[0] +.sym 1884 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 1891 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 1898 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 1900 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 1908 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 2063 w_rx_09_fifo_data[17] +.sym 2064 w_rx_09_fifo_data[15] +.sym 2065 w_rx_09_fifo_data[16] +.sym 2066 w_rx_09_fifo_data[7] +.sym 2067 w_rx_09_fifo_data[12] +.sym 2068 w_rx_09_fifo_data[5] +.sym 2069 w_rx_09_fifo_data[14] +.sym 2070 w_rx_09_fifo_data[8] +.sym 2078 rx_fifo.wr_addr[0] +.sym 2093 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2125 w_rx_09_fifo_data[8] +.sym 2135 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2136 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2141 w_rx_fifo_pulled_data[2] +.sym 2142 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2145 rx_fifo.wr_addr[0] +.sym 2146 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 2163 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2179 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2182 w_rx_09_fifo_data[11] +.sym 2183 w_rx_09_fifo_data[8] +.sym 2197 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2199 w_rx_09_fifo_data[8] +.sym 2209 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2210 w_rx_09_fifo_data[11] +.sym 2231 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2232 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2233 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 2234 w_rx_09_fifo_data[6] +.sym 2235 w_rx_09_fifo_data[2] +.sym 2236 w_rx_09_fifo_data[3] +.sym 2237 w_rx_09_fifo_data[4] +.sym 2238 w_rx_09_fifo_data[19] +.sym 2239 w_rx_09_fifo_data[21] +.sym 2240 w_rx_09_fifo_data[11] +.sym 2241 w_rx_09_fifo_data[9] +.sym 2247 w_rx_09_fifo_data[14] +.sym 2248 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 2250 w_rx_fifo_pulled_data[15] +.sym 2254 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 2256 w_rx_09_fifo_data[13] +.sym 2257 rx_fifo.rd_addr[7] +.sym 2258 w_rx_09_fifo_data[16] +.sym 2259 w_rx_09_fifo_data[10] +.sym 2260 w_rx_09_fifo_data[7] +.sym 2261 w_rx_09_fifo_data[21] +.sym 2264 rx_fifo.wr_addr[8] +.sym 2266 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2267 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 2268 rx_fifo.wr_addr[2] +.sym 2269 rx_fifo.wr_addr[3] +.sym 2272 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 2273 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] +.sym 2275 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] +.sym 2279 w_rx_fifo_pulled_data[15] +.sym 2280 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 2293 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2298 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 2304 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] +.sym 2308 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2310 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] +.sym 2312 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2314 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 2315 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2317 i_rst_b$SB_IO_IN +.sym 2318 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 2320 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2321 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2322 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2323 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] +.sym 2338 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2339 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2340 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2341 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 2344 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 2345 i_rst_b$SB_IO_IN +.sym 2362 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2363 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2364 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] +.sym 2365 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2366 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O +.sym 2367 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2368 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 2369 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] +.sym 2370 w_rx_fifo_data[7] +.sym 2371 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] +.sym 2372 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 2373 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 2374 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 2375 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 2376 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 2377 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2381 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 2382 w_rx_09_fifo_data[11] +.sym 2391 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2393 w_rx_09_fifo_data[30] +.sym 2394 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2395 w_rx_09_fifo_data[0] +.sym 2396 smi_ctrl_ins.int_cnt_rx[4] +.sym 2398 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2399 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 2400 w_rx_09_fifo_data[1] +.sym 2401 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2402 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] +.sym 2404 smi_ctrl_ins.int_cnt_rx[3] +.sym 2406 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 2408 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2414 w_rx_09_fifo_data[27] +.sym 2422 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2425 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 2429 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 2430 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 2432 w_rx_fifo_pulled_data[2] +.sym 2433 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2434 o_iq_tx_clk_p$SB_IO_OUT +.sym 2437 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 2439 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2444 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2446 w_rx_fifo_pulled_data[15] +.sym 2449 w_rx_fifo_pulled_data[13] +.sym 2455 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2456 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2457 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2458 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 2475 o_iq_tx_clk_p$SB_IO_OUT +.sym 2479 w_rx_fifo_pulled_data[13] +.sym 2487 w_rx_fifo_pulled_data[2] +.sym 2492 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 2493 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 2494 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 2497 w_rx_fifo_pulled_data[15] +.sym 2501 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2502 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 2503 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 2504 rx_fifo.rd_addr_gray_wr_r[3] -.sym 2505 rx_fifo.rd_addr_gray_wr[4] -.sym 2506 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 2507 rx_fifo.rd_addr_gray_wr[1] -.sym 2508 rx_fifo.rd_addr_gray_wr_r[1] -.sym 2509 rx_fifo.rd_addr_gray_wr[3] -.sym 2510 rx_fifo.rd_addr_gray_wr_r[4] -.sym 2511 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 2518 rx_fifo.wr_addr[9] -.sym 2519 rx_fifo.rd_addr_gray_wr_r[5] -.sym 2521 rx_fifo.wr_addr_gray_rd[7] -.sym 2528 $io_pmod[3]$iobuf_i -.sym 2529 rx_fifo.wr_addr[1] -.sym 2530 rx_fifo.mem_i.0.0_RDATA[1] -.sym 2531 rx_fifo.wr_addr[7] -.sym 2537 rx_fifo.wr_addr[4] -.sym 2539 rx_fifo.wr_addr[2] -.sym 2543 rx_fifo.wr_addr[6] -.sym 2545 rx_fifo.wr_addr[5] -.sym 2551 rx_fifo.wr_addr[9] -.sym 2557 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2563 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 2565 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 2566 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 2571 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 2572 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 2580 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 2582 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 2587 rx_fifo.rd_addr_gray_wr_r[4] -.sym 2588 rx_fifo.rd_addr_gray_wr_r[8] -.sym 2596 rx_fifo.rd_addr_gray_wr_r[4] -.sym 2597 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 2598 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 2599 rx_fifo.rd_addr_gray_wr_r[8] -.sym 2614 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 2615 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 2616 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 2617 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 2633 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2635 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 2637 lvds_clock_$glb_clk -.sym 2638 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 2639 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 2640 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 2641 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] -.sym 2642 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 2643 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 2645 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 2646 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 2652 rx_fifo.wr_addr[4] -.sym 2656 rx_fifo.wr_addr[1] -.sym 2662 rx_fifo.rd_addr_gray[1] -.sym 2663 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 2667 io_pmod[0]$SB_IO_IN -.sym 2669 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 2674 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 2675 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2676 rx_fifo.wr_addr[1] -.sym 2677 rx_fifo.wr_addr[8] -.sym 2683 rx_fifo.wr_addr[5] -.sym 2684 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 2686 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 2692 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 2693 rx_fifo.rd_addr_gray[7] -.sym 2694 rx_fifo.rd_addr_gray_wr_r[5] -.sym 2696 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] -.sym 2697 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 2698 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 2699 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] -.sym 2701 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 2702 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 2703 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 2705 rx_fifo.rd_addr_gray_wr[7] -.sym 2706 rx_fifo.rd_addr_gray_wr_r[4] -.sym 2709 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 2710 rx_fifo.rd_addr_gray_wr_r[7] -.sym 2711 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 2712 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 2716 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 2717 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 2722 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 2723 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 2725 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 2726 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 2727 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 2728 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 2732 rx_fifo.rd_addr_gray_wr_r[7] -.sym 2733 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] -.sym 2734 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 2739 rx_fifo.rd_addr_gray_wr[7] -.sym 2743 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 2744 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 2745 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 2746 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 2749 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 2750 rx_fifo.rd_addr_gray_wr_r[4] -.sym 2751 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] -.sym 2757 rx_fifo.rd_addr_gray[7] -.sym 2761 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 2762 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 2763 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 2764 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 2768 rx_fifo.rd_addr_gray_wr_r[5] -.sym 2770 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] -.sym 2772 lvds_clock_$glb_clk -.sym 2774 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] -.sym 2776 channel -.sym 2777 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2778 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2780 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 2781 rx_fifo.rd_addr_gray_wr[9] -.sym 2788 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 2789 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 2794 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 2799 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2800 rx_fifo.wr_addr[4] -.sym 2801 rx_fifo.wr_addr[8] -.sym 2802 rx_fifo.wr_addr[2] -.sym 2803 w_rx_24_fifo_data[0] -.sym 2805 rx_fifo.wr_addr[6] -.sym 2807 rx_fifo.wr_addr[5] -.sym 2808 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[2] -.sym 2809 w_rx_09_fifo_data[2] -.sym 2828 rx_fifo.wr_addr[6] -.sym 2829 rx_fifo.wr_addr[5] -.sym 2834 rx_fifo.wr_addr[8] -.sym 2835 rx_fifo.wr_addr[1] -.sym 2836 rx_fifo.wr_addr[1] -.sym 2837 rx_fifo.wr_addr[7] -.sym 2840 rx_fifo.wr_addr[3] -.sym 2843 rx_fifo.wr_addr[4] -.sym 2845 rx_fifo.wr_addr[2] -.sym 2859 $nextpnr_ICESTORM_LC_4$O -.sym 2861 rx_fifo.wr_addr[1] -.sym 2865 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 2867 rx_fifo.wr_addr[2] -.sym 2869 rx_fifo.wr_addr[1] -.sym 2871 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 2874 rx_fifo.wr_addr[3] -.sym 2875 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 2877 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 2879 rx_fifo.wr_addr[4] -.sym 2881 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 2883 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 2886 rx_fifo.wr_addr[5] -.sym 2887 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 2889 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 2892 rx_fifo.wr_addr[6] -.sym 2893 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 2895 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 2897 rx_fifo.wr_addr[7] -.sym 2899 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 2901 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 2904 rx_fifo.wr_addr[8] -.sym 2905 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 2909 rx_fifo.mem_q.0.0_WDATA_3 -.sym 2910 rx_fifo.wr_addr_gray_rd[9] -.sym 2911 rx_fifo.mem_q.0.0_WDATA -.sym 2912 rx_fifo.mem_q.0.0_WDATA_2 -.sym 2913 rx_fifo.mem_q.0.0_WDATA_1 -.sym 2915 rx_fifo.wr_addr_gray_rd[8] -.sym 2916 rx_fifo.wr_addr[9] -.sym 2917 $io_pmod[5]$iobuf_i -.sym 2920 $io_pmod[5]$iobuf_i -.sym 2922 rx_fifo.wr_addr[5] -.sym 2925 rx_fifo.mem_q.0.0_RDATA_2[1] -.sym 2935 w_rx_09_fifo_data[0] -.sym 2938 w_rx_24_fifo_data[2] -.sym 2939 w_rx_09_fifo_data[1] -.sym 2942 w_rx_24_fifo_data[3] -.sym 2943 rx_fifo.rd_addr_gray_wr_r[8] -.sym 2945 rx_fifo.wr_addr[5] -.sym 2948 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 2957 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 2966 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 2967 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 2969 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 2973 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 2975 rx_fifo.wr_addr[9] -.sym 2980 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 2987 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 2989 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 2997 rx_fifo.wr_addr[9] -.sym 2998 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 3002 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 3007 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 3021 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 3025 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 3034 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3040 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 3041 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 3042 lvds_clock_$glb_clk +.sym 2504 w_rx_09_fifo_data[24] +.sym 2505 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] +.sym 2506 w_rx_09_fifo_data[22] +.sym 2507 w_rx_09_fifo_data[28] +.sym 2508 w_rx_09_fifo_data[18] +.sym 2509 w_rx_09_fifo_data[26] +.sym 2510 w_rx_09_fifo_data[30] +.sym 2511 w_rx_09_fifo_data[20] +.sym 2519 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] +.sym 2522 channel +.sym 2531 w_smi_data_output[7] +.sym 2532 rx_fifo.wr_addr[8] +.sym 2535 w_rx_09_fifo_data[20] +.sym 2536 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2537 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2538 rx_fifo.wr_addr[0] +.sym 2539 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 2544 w_rx_fifo_pulled_data[11] +.sym 2546 w_rx_09_fifo_data[25] +.sym 2550 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] +.sym 2561 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 2562 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 2563 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 2567 w_rx_09_fifo_data[21] +.sym 2571 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 2572 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 2573 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2574 smi_ctrl_ins.int_cnt_rx[4] +.sym 2575 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2578 smi_ctrl_ins.int_cnt_rx[3] +.sym 2581 w_rx_09_fifo_data[27] +.sym 2582 smi_ctrl_ins.int_cnt_rx[4] +.sym 2583 w_rx_09_fifo_data[23] +.sym 2586 w_rx_09_fifo_data[25] +.sym 2587 w_rx_09_fifo_data[29] +.sym 2590 w_rx_09_fifo_data[25] +.sym 2592 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2598 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 2604 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2605 w_rx_09_fifo_data[21] +.sym 2608 w_rx_09_fifo_data[29] +.sym 2609 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2614 smi_ctrl_ins.int_cnt_rx[4] +.sym 2615 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 2616 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 2617 smi_ctrl_ins.int_cnt_rx[3] +.sym 2620 w_rx_09_fifo_data[23] +.sym 2623 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2626 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2627 w_rx_09_fifo_data[27] +.sym 2632 smi_ctrl_ins.int_cnt_rx[3] +.sym 2633 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 2634 smi_ctrl_ins.int_cnt_rx[4] +.sym 2635 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 2636 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2637 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 2638 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 2640 smi_ctrl_ins.int_cnt_rx[4] +.sym 2642 w_rx_fifo_data[29] +.sym 2643 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] +.sym 2644 smi_ctrl_ins.int_cnt_rx[3] +.sym 2645 w_rx_fifo_data[31] +.sym 2646 w_rx_fifo_data[18] +.sym 2651 i_smi_a2$SB_IO_IN +.sym 2654 rx_fifo.wr_addr[0] +.sym 2656 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 2659 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2660 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] +.sym 2661 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] +.sym 2662 w_rx_09_fifo_data[22] +.sym 2663 w_rx_24_fifo_data[19] +.sym 2664 w_rx_09_fifo_data[23] +.sym 2666 w_rx_09_fifo_data[8] +.sym 2668 w_rx_24_fifo_data[31] +.sym 2670 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] +.sym 2672 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 2676 i_smi_a2$SB_IO_IN +.sym 2677 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 2680 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2681 w_rx_fifo_pulled_data[2] +.sym 2685 rx_fifo.wr_addr[0] +.sym 2686 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 2699 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] +.sym 2700 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] +.sym 2701 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] +.sym 2703 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 2705 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 2708 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] +.sym 2710 i_rst_b$SB_IO_IN +.sym 2714 lvds_rx_09_inst.r_phase_count[1] +.sym 2715 $PACKER_VCC_NET +.sym 2721 smi_ctrl_ins.int_cnt_rx[3] +.sym 2723 $PACKER_VCC_NET +.sym 2724 $nextpnr_ICESTORM_LC_5$O +.sym 2727 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] +.sym 2730 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] +.sym 2732 lvds_rx_09_inst.r_phase_count[1] +.sym 2733 $PACKER_VCC_NET +.sym 2734 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] +.sym 2737 $PACKER_VCC_NET +.sym 2739 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 2740 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] +.sym 2761 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 2767 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] +.sym 2768 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] +.sym 2769 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] +.sym 2770 smi_ctrl_ins.int_cnt_rx[3] +.sym 2771 i_rst_b$SB_IO_IN +.sym 2772 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 2774 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.sym 2775 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 2776 w_rx_fifo_data[19] +.sym 2777 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.sym 2778 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] +.sym 2779 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] +.sym 2780 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 2781 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 2784 rx_fifo.wr_addr[0] +.sym 2788 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2790 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 2793 w_rx_fifo_pull +.sym 2794 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 2795 smi_ctrl_ins.int_cnt_rx[4] +.sym 2796 w_rx_24_fifo_data[18] +.sym 2798 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2800 w_rx_09_fifo_data[10] +.sym 2807 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 2808 rx_fifo.wr_addr[8] +.sym 2809 rx_fifo.wr_addr[3] +.sym 2811 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 2813 w_rx_fifo_pulled_data[23] +.sym 2814 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2820 w_rx_fifo_pull +.sym 2828 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 2832 smi_ctrl_ins.int_cnt_rx[3] +.sym 2835 w_rx_fifo_pulled_data[11] +.sym 2836 smi_ctrl_ins.int_cnt_rx[4] +.sym 2837 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 2838 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2840 smi_ctrl_ins.int_cnt_rx[3] +.sym 2841 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 2847 w_rx_fifo_pulled_data[10] +.sym 2848 i_rst_b$SB_IO_IN +.sym 2850 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 2858 w_rx_fifo_pulled_data[23] +.sym 2860 w_rx_fifo_pulled_data[23] +.sym 2866 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 2867 smi_ctrl_ins.int_cnt_rx[3] +.sym 2868 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 2869 smi_ctrl_ins.int_cnt_rx[4] +.sym 2878 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 2879 smi_ctrl_ins.int_cnt_rx[3] +.sym 2880 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 2881 smi_ctrl_ins.int_cnt_rx[4] +.sym 2884 smi_ctrl_ins.int_cnt_rx[4] +.sym 2885 i_rst_b$SB_IO_IN +.sym 2887 smi_ctrl_ins.int_cnt_rx[3] +.sym 2899 w_rx_fifo_pulled_data[11] +.sym 2903 w_rx_fifo_pulled_data[10] +.sym 2906 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2907 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 2908 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 2914 w_rx_fifo_data[23] +.sym 2915 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2916 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2917 i_smi_a2$SB_IO_IN +.sym 2920 i_smi_a2$SB_IO_IN +.sym 2928 w_lvds_tx_d1 +.sym 2934 w_rx_09_fifo_data[0] +.sym 2938 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2940 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 2943 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 2944 w_rx_09_fifo_data[1] +.sym 2948 rx_fifo.rd_data_o[26] +.sym 2949 w_lvds_tx_d1 +.sym 2950 w_rx_09_fifo_data[27] +.sym 2966 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 2971 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 2982 rx_fifo.rd_data_o[27] +.sym 2984 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 2985 rx_fifo.rd_data_o[26] +.sym 2986 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 2988 rx_fifo.rd_data_o[25] +.sym 2989 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 3004 rx_fifo.rd_data_o[27] +.sym 3010 rx_fifo.rd_data_o[26] +.sym 3014 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 3028 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3034 rx_fifo.rd_data_o[25] +.sym 3037 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 3038 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3040 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 3041 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 3042 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 3043 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3044 w_rx_09_fifo_data[6] -.sym 3045 rx_fifo.mem_q.0.1_WDATA_1 -.sym 3046 w_rx_09_fifo_data[4] -.sym 3047 w_rx_09_fifo_data[7] -.sym 3048 rx_fifo.mem_q.0.1_WDATA_2 -.sym 3049 w_rx_09_fifo_data[2] -.sym 3050 w_rx_09_fifo_data[5] -.sym 3051 rx_fifo.mem_q.0.1_WDATA_3 -.sym 3057 rx_fifo.wr_addr_gray_rd[8] -.sym 3063 $PACKER_VCC_NET -.sym 3068 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3069 w_rx_24_fifo_data[1] -.sym 3070 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3075 rx_fifo.wr_addr[9] -.sym 3077 rx_fifo.wr_addr[1] -.sym 3078 rx_fifo.wr_addr[4] -.sym 3079 rx_fifo.wr_addr[8] -.sym 3115 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3123 w_rx_09_fifo_data[1] -.sym 3142 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3143 w_rx_09_fifo_data[1] -.sym 3176 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 3177 lvds_clock_$glb_clk -.sym 3178 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 3179 w_rx_24_fifo_data[6] -.sym 3180 w_rx_24_fifo_data[7] -.sym 3181 w_rx_24_fifo_data[2] -.sym 3183 w_rx_24_fifo_data[3] -.sym 3184 w_rx_24_fifo_data[5] -.sym 3185 w_rx_24_fifo_data[4] -.sym 3190 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3191 $PACKER_VCC_NET -.sym 3194 w_rx_09_fifo_data[7] -.sym 3196 rx_fifo.wr_addr[5] -.sym 3199 rx_fifo.wr_addr[1] -.sym 3207 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 3210 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3212 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3219 w_lvds_rx_24_d1 -.sym 3224 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3237 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 3241 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3242 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3256 w_lvds_rx_24_d1 -.sym 3263 i_rst_b$SB_IO_IN -.sym 3277 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3278 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 3279 i_rst_b$SB_IO_IN -.sym 3280 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3302 w_lvds_rx_24_d1 -.sym 3311 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 3312 lvds_clock_$glb_clk -.sym 3316 io_pmod[1]$SB_IO_IN -.sym 3317 w_rx_24_fifo_data[8] -.sym 3319 w_rx_24_fifo_data[10] -.sym 3335 w_rx_24_fifo_data[7] -.sym 3340 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[2] -.sym 3346 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 3347 w_rx_24_fifo_data[0] -.sym 3348 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3361 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3368 w_lvds_rx_09_d0 -.sym 3369 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 3371 w_lvds_rx_09_d1 -.sym 3376 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3377 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3390 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3392 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3396 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 3400 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3401 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3402 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 3403 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3407 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3408 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3409 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3412 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3414 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3415 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3430 w_lvds_rx_09_d0 -.sym 3431 w_lvds_rx_09_d1 -.sym 3446 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E -.sym 3447 lvds_clock_$glb_clk -.sym 3448 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3450 $io_pmod[0]$iobuf_i -.sym 3451 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E -.sym 3454 w_rx_24_fifo_push -.sym 3456 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[2] -.sym 3464 w_rx_24_fifo_data[8] -.sym 3465 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3470 rx_fifo.wr_addr[5] -.sym 3474 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3476 $PACKER_VCC_NET -.sym 3479 w_rx_09_fifo_data[0] -.sym 3483 w_rx_09_fifo_data[1] -.sym 3494 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3504 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 3506 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3519 w_lvds_rx_24_d0 -.sym 3521 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 3526 w_lvds_rx_09_d1 -.sym 3531 w_lvds_rx_09_d0 -.sym 3543 w_lvds_rx_09_d1 -.sym 3544 w_lvds_rx_09_d0 -.sym 3547 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3548 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 3549 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 3550 w_lvds_rx_24_d0 -.sym 3581 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 3582 lvds_clock_$glb_clk -.sym 3585 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 3586 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 3587 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 3588 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 3589 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 3590 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 3591 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 3605 $io_pmod[0]$iobuf_i -.sym 3608 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3610 w_rx_09_fifo_push -.sym 3612 io_pmod[3]$SB_IO_IN -.sym 3618 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3619 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3639 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 3646 w_lvds_rx_24_d0 -.sym 3649 w_lvds_rx_24_d1 -.sym 3650 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 3655 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 3656 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 3664 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 3665 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3677 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 3678 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3679 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 3683 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 3684 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 3685 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3689 w_lvds_rx_24_d0 -.sym 3690 w_lvds_rx_24_d1 -.sym 3695 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 3696 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 3697 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3700 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3701 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 3702 w_lvds_rx_24_d1 -.sym 3703 w_lvds_rx_24_d0 -.sym 3712 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 3713 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 3714 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3715 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 3716 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E -.sym 3717 lvds_clock_$glb_clk -.sym 3718 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 3723 lvds_rx_24_inst.r_phase_count[1] -.sym 3725 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 3726 w_rx_09_fifo_push -.sym 3741 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 3750 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 3751 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3753 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3774 w_lvds_rx_09_d0 -.sym 3776 w_lvds_rx_09_d1 -.sym 3780 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3782 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3785 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3801 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3817 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3818 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3819 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3820 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 3823 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3824 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3826 w_lvds_rx_09_d0 -.sym 3836 w_lvds_rx_09_d1 -.sym 3851 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 3852 lvds_clock_$glb_clk -.sym 3855 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 3856 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 3857 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 3858 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 3859 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3860 lvds_rx_09_inst.r_phase_count[1] -.sym 3861 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 3889 o_shdn_tx_lna$SB_IO_OUT -.sym 3909 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 3915 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3934 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 3935 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3936 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3958 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 3959 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 3960 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 3961 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 3986 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 3987 lvds_clock_$glb_clk +.sym 3044 rx_fifo.rd_addr_gray_wr_r[2] +.sym 3045 rx_fifo.rd_addr_gray_wr[1] +.sym 3047 w_rx_fifo_data[10] +.sym 3049 rx_fifo.rd_addr_gray_wr[2] +.sym 3050 rx_fifo.rd_addr_gray_wr[6] +.sym 3056 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 3057 w_rx_09_fifo_data[25] +.sym 3060 channel +.sym 3070 rx_fifo.wr_addr[0] +.sym 3071 rx_fifo.wr_addr[8] +.sym 3073 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 3074 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 3076 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3077 spi_if_ins.w_rx_data[5] +.sym 3078 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3083 w_rx_fifo_pulled_data[11] +.sym 3087 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 3103 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3108 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 3109 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 3112 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3117 w_lvds_rx_09_d0 +.sym 3123 w_lvds_rx_09_d1 +.sym 3151 w_lvds_rx_09_d0 +.sym 3160 w_lvds_rx_09_d1 +.sym 3163 w_lvds_rx_09_d0 +.sym 3166 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3167 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 3168 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3169 w_lvds_rx_09_d1 +.sym 3176 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 3177 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3181 w_rx_fifo_data[1] +.sym 3182 w_rx_fifo_data[0] +.sym 3183 w_cs[3] +.sym 3184 w_cs[1] +.sym 3186 w_cs[2] +.sym 3196 rx_fifo.rd_addr_gray[1] +.sym 3202 w_rx_24_fifo_data[0] +.sym 3203 rx_fifo.rd_addr_gray[6] +.sym 3206 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 3208 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 3210 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.sym 3214 w_rx_09_fifo_data[8] +.sym 3216 i_smi_a2$SB_IO_IN +.sym 3220 w_rx_24_fifo_data[0] +.sym 3221 w_rx_fifo_pulled_data[2] +.sym 3223 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 3225 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 3232 w_lvds_tx_d1 +.sym 3236 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 3238 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.sym 3244 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3246 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3248 w_lvds_rx_09_d0 +.sym 3258 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 3259 i_rst_b$SB_IO_IN +.sym 3261 w_lvds_rx_09_d1 +.sym 3262 w_lvds_tx_d0 +.sym 3265 w_lvds_rx_09_d0 +.sym 3266 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3267 w_lvds_rx_09_d1 +.sym 3268 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3273 w_lvds_tx_d0 +.sym 3301 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 3302 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 3303 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.sym 3308 w_lvds_tx_d1 +.sym 3311 i_rst_b$SB_IO_IN +.sym 3312 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3314 w_rx_09_fifo_push +.sym 3315 w_rx_fifo_data[2] +.sym 3316 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 3317 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 3318 w_rx_fifo_data[27] +.sym 3319 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 3320 w_rx_fifo_data[8] +.sym 3321 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 3323 spi_if_ins.state_if[1] +.sym 3329 w_rx_fifo_pull +.sym 3330 w_rx_fifo_pulled_data[23] +.sym 3335 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 3337 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 3339 rx_fifo.rd_addr_gray_wr_r[2] +.sym 3340 rx_fifo.wr_addr[8] +.sym 3342 w_cs[3] +.sym 3345 rx_fifo.wr_addr[8] +.sym 3347 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 3348 w_cs[2] +.sym 3349 rx_fifo.wr_addr[3] +.sym 3371 w_lvds_rx_24_d0 +.sym 3377 w_lvds_rx_24_d1 +.sym 3378 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 3384 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3386 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3390 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 3392 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 3394 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 3400 w_lvds_rx_24_d0 +.sym 3425 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 3427 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 3436 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 3437 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 3438 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 3439 w_lvds_rx_24_d1 +.sym 3446 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 3447 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3449 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 3450 rx_fifo.wr_addr_gray[2] +.sym 3451 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 3452 rx_fifo.wr_addr[7] +.sym 3453 rx_fifo.wr_addr_gray[1] +.sym 3454 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 3457 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 3461 spi_if_ins.w_rx_data[6] +.sym 3462 channel +.sym 3463 rx_fifo.wr_addr[8] +.sym 3464 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 3465 rx_fifo.rd_data_o[26] +.sym 3466 w_rx_fifo_full +.sym 3467 w_rx_09_fifo_data[27] +.sym 3468 w_rx_09_fifo_push +.sym 3471 w_rx_24_fifo_data[2] +.sym 3476 rx_fifo.wr_addr[6] +.sym 3478 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1] +.sym 3479 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 3483 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 3496 rx_fifo.wr_addr[8] +.sym 3504 rx_fifo.wr_addr[6] +.sym 3519 rx_fifo.wr_addr[2] +.sym 3521 rx_fifo.wr_addr[4] +.sym 3525 rx_fifo.wr_addr[8] +.sym 3529 rx_fifo.wr_addr[7] +.sym 3530 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 3531 rx_fifo.wr_addr[3] +.sym 3533 rx_fifo.wr_addr[5] +.sym 3534 $nextpnr_ICESTORM_LC_9$O +.sym 3536 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 3540 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 3543 rx_fifo.wr_addr[2] +.sym 3546 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 3549 rx_fifo.wr_addr[3] +.sym 3550 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 3552 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 3555 rx_fifo.wr_addr[4] +.sym 3556 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 3558 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 3561 rx_fifo.wr_addr[5] +.sym 3562 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 3564 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 3566 rx_fifo.wr_addr[6] +.sym 3568 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 3570 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 3573 rx_fifo.wr_addr[7] +.sym 3574 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 3576 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 3579 rx_fifo.wr_addr[8] +.sym 3580 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 3584 rx_fifo.wr_addr_gray[3] +.sym 3585 rx_fifo.wr_addr[2] +.sym 3586 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 3587 rx_fifo.wr_addr[4] +.sym 3588 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 3589 rx_fifo.wr_addr[3] +.sym 3590 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 3591 rx_fifo.wr_addr[5] +.sym 3598 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 3604 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 3606 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 3610 rx_fifo.wr_addr[7] +.sym 3611 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 3612 rx_fifo.rd_addr_gray_wr_r[5] +.sym 3613 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 3614 rx_fifo.wr_addr[0] +.sym 3615 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 3616 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 3618 rx_fifo.wr_addr[8] +.sym 3619 rx_fifo.wr_addr[2] +.sym 3623 w_rx_fifo_pulled_data[11] +.sym 3632 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 3639 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 3640 rx_fifo.rd_addr_gray[5] +.sym 3641 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 3644 rx_fifo.rd_addr_gray[4] +.sym 3648 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 3650 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 3652 rx_fifo.rd_addr_gray_wr[4] +.sym 3653 rx_fifo.wr_addr[9] +.sym 3665 rx_fifo.rd_addr_gray_wr[5] +.sym 3672 rx_fifo.wr_addr[9] +.sym 3673 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 3677 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 3679 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 3682 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 3684 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 3691 rx_fifo.rd_addr_gray_wr[4] +.sym 3697 rx_fifo.rd_addr_gray[5] +.sym 3701 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 3703 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 3707 rx_fifo.rd_addr_gray_wr[5] +.sym 3714 rx_fifo.rd_addr_gray[4] +.sym 3717 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 3719 rx_fifo.wr_addr[9] +.sym 3720 rx_fifo.wr_addr[6] +.sym 3721 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 3723 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 3724 rx_fifo.wr_addr_gray[4] +.sym 3725 rx_fifo.wr_addr_gray[5] +.sym 3726 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 3733 w_rx_fifo_push +.sym 3734 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 3735 w_rx_fifo_pulled_data[2] +.sym 3736 rx_fifo.rd_addr_gray[5] +.sym 3738 rx_fifo.wr_addr_gray[3] +.sym 3739 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 3740 rx_fifo.rd_addr_gray[4] +.sym 3742 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 3745 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 3760 i_smi_a2$SB_IO_IN +.sym 3773 rx_fifo.wr_addr[2] +.sym 3775 rx_fifo.wr_addr[4] +.sym 3776 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 3779 rx_fifo.wr_addr[5] +.sym 3783 rx_fifo.wr_addr[0] +.sym 3785 rx_fifo.wr_addr[3] +.sym 3789 rx_fifo.wr_addr[6] +.sym 3794 rx_fifo.wr_addr[7] +.sym 3804 $nextpnr_ICESTORM_LC_0$O +.sym 3807 rx_fifo.wr_addr[0] +.sym 3810 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 3812 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 3814 rx_fifo.wr_addr[0] +.sym 3816 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 3818 rx_fifo.wr_addr[2] +.sym 3820 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 3822 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 3824 rx_fifo.wr_addr[3] +.sym 3826 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 3828 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 3830 rx_fifo.wr_addr[4] +.sym 3832 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 3834 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 3837 rx_fifo.wr_addr[5] +.sym 3838 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 3840 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 3842 rx_fifo.wr_addr[6] +.sym 3844 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 3846 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 3848 rx_fifo.wr_addr[7] +.sym 3850 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 3854 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 3855 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 3856 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 3857 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 3858 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 3859 rx_fifo.rd_addr_gray_wr_r[7] +.sym 3861 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 3867 rx_fifo.wr_addr_gray[5] +.sym 3880 rx_fifo.wr_addr[8] +.sym 3882 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 3902 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 3912 rx_fifo.wr_addr[8] +.sym 3915 rx_fifo.wr_addr[9] +.sym 3918 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 3920 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 3921 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 3926 rx_fifo.wr_addr[0] +.sym 3931 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 3939 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 3941 rx_fifo.wr_addr[8] +.sym 3943 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 3946 rx_fifo.wr_addr[9] +.sym 3949 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 3953 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 3954 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 3960 rx_fifo.wr_addr[0] +.sym 3970 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 3986 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 3987 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 3988 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4138 $io_pmod[5]$iobuf_i -.sym 4250 rx_fifo.wr_addr[0] -.sym 4258 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 4280 rx_fifo.wr_addr_gray[0] -.sym 4281 rx_fifo.wr_addr_gray[3] -.sym 4282 rx_fifo.wr_addr_gray_rd[0] -.sym 4286 rx_fifo.wr_addr_gray[2] -.sym 4300 rx_fifo.wr_addr_gray_rd[3] -.sym 4310 rx_fifo.wr_addr_gray_rd[2] -.sym 4312 rx_fifo.wr_addr_gray_rd[2] -.sym 4327 rx_fifo.wr_addr_gray_rd[3] -.sym 4330 rx_fifo.wr_addr_gray[0] -.sym 4339 rx_fifo.wr_addr_gray_rd[0] -.sym 4345 rx_fifo.wr_addr_gray[3] -.sym 4354 rx_fifo.wr_addr_gray[2] -.sym 4359 r_counter_$glb_clk -.sym 4383 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 4387 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 4398 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 4403 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 4416 rx_fifo.wr_addr[7] -.sym 4421 rx_fifo.wr_addr[0] -.sym 4431 rx_fifo.wr_addr[3] -.sym 4447 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 4458 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -.sym 4459 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 4460 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 4461 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 4469 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 4470 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 4471 rx_fifo.wr_addr[0] -.sym 4477 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 4478 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 4483 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 4488 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 4493 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 4494 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 4499 rx_fifo.wr_addr[0] -.sym 4500 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 4506 rx_fifo.wr_addr[0] -.sym 4518 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -.sym 4521 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 4522 lvds_clock_$glb_clk -.sym 4523 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4538 rx_fifo.wr_addr[0] -.sym 4540 rx_fifo.rd_addr_gray[3] -.sym 4555 rx_fifo.wr_addr[0] -.sym 4558 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 4568 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 4569 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 4572 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 4573 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -.sym 4577 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 4578 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 4579 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 4584 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 4590 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 4592 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 4598 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 4601 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 4604 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 4606 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 4611 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 4613 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -.sym 4616 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 4625 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 4628 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 4631 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 4636 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 4637 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 4643 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 4644 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 4645 lvds_clock_$glb_clk -.sym 4646 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 4663 rx_fifo.wr_addr_gray_rd[1] -.sym 4667 rx_fifo.wr_addr[3] -.sym 4669 rx_fifo.wr_addr[7] -.sym 4674 rx_fifo.wr_addr[3] -.sym 4676 rx_fifo.wr_addr[7] -.sym 4677 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 4678 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 4680 rx_fifo.rd_addr[2] -.sym 4682 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 4688 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 4690 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 4691 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 4692 rx_fifo.wr_addr_gray[4] -.sym 4693 rx_fifo.wr_addr_gray[7] -.sym 4694 rx_fifo.rd_addr_gray_wr_r[5] -.sym 4695 rx_fifo.wr_addr_gray[6] -.sym 4698 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 4700 rx_fifo.rd_addr_gray_wr_r[1] -.sym 4702 rx_fifo.wr_addr_gray[5] -.sym 4706 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 4708 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 4709 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 4713 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 4716 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 4718 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 4721 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 4724 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 4727 rx_fifo.wr_addr_gray[5] -.sym 4736 rx_fifo.wr_addr_gray[6] -.sym 4739 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 4740 rx_fifo.rd_addr_gray_wr_r[5] -.sym 4741 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 4745 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 4746 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 4747 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 4748 rx_fifo.rd_addr_gray_wr_r[1] -.sym 4754 rx_fifo.wr_addr_gray[4] -.sym 4757 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 4758 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 4759 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 4760 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 4765 rx_fifo.wr_addr_gray[7] -.sym 4768 r_counter_$glb_clk -.sym 4771 rx_fifo.mem_i.0.0_RDATA_3[0] -.sym 4775 rx_fifo.mem_i.0.0_RDATA_2[0] -.sym 4785 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 4786 rx_fifo.wr_addr_gray_rd[5] -.sym 4788 rx_fifo.wr_addr_gray_rd[6] -.sym 4791 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 4795 rx_fifo.wr_addr[7] -.sym 4796 rx_fifo.wr_addr[3] -.sym 4800 io_pmod[1]$SB_IO_IN -.sym 4801 rx_fifo.wr_addr_gray_rd[4] -.sym 4811 rx_fifo.rd_addr_gray[4] -.sym 4814 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[3] -.sym 4816 rx_fifo.rd_addr_gray[3] -.sym 4820 rx_fifo.rd_addr_gray_wr[4] -.sym 4821 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 4822 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[2] -.sym 4823 rx_fifo.rd_addr_gray[1] -.sym 4824 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 4825 rx_fifo.rd_addr_gray_wr_r[0] -.sym 4827 rx_fifo.rd_addr_gray_wr_r[3] -.sym 4828 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 4831 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 4838 rx_fifo.rd_addr_gray_wr[1] -.sym 4840 rx_fifo.rd_addr_gray_wr[3] -.sym 4846 rx_fifo.rd_addr_gray_wr[3] -.sym 4851 rx_fifo.rd_addr_gray[4] -.sym 4856 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 4857 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 4858 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[2] -.sym 4859 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[3] -.sym 4862 rx_fifo.rd_addr_gray[1] -.sym 4870 rx_fifo.rd_addr_gray_wr[1] -.sym 4876 rx_fifo.rd_addr_gray[3] -.sym 4882 rx_fifo.rd_addr_gray_wr[4] -.sym 4886 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 4887 rx_fifo.rd_addr_gray_wr_r[3] -.sym 4888 rx_fifo.rd_addr_gray_wr_r[0] -.sym 4889 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 4891 lvds_clock_$glb_clk -.sym 4894 rx_fifo.mem_i.0.0_RDATA_1[1] -.sym 4898 rx_fifo.mem_i.0.0_RDATA[0] -.sym 4905 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 4906 rx_fifo.wr_addr[5] -.sym 4908 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[2] -.sym 4909 rx_fifo.wr_addr[1] -.sym 4913 rx_fifo.wr_addr[6] -.sym 4914 rx_fifo.wr_addr[8] -.sym 4915 rx_fifo.rd_addr_gray[4] -.sym 4917 $PACKER_VCC_NET -.sym 4918 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 4920 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 4922 rx_fifo.wr_addr[6] -.sym 4923 io_pmod[0]$SB_IO_IN -.sym 4924 rx_fifo.wr_addr[0] -.sym 4926 rx_fifo.wr_addr[9] -.sym 4927 rx_fifo.wr_addr[2] -.sym 4928 rx_fifo.wr_addr[3] -.sym 4934 rx_fifo.rd_addr_gray_wr_r[3] -.sym 4936 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] -.sym 4937 rx_fifo.rd_addr_gray_wr_r[0] -.sym 4938 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 4939 rx_fifo.mem_i.0.0_RDATA_2[0] -.sym 4941 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 4942 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] -.sym 4945 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 4946 rx_fifo.rd_addr_gray_wr_r[1] -.sym 4947 rx_fifo.wr_addr[1] -.sym 4948 rx_fifo.mem_i.0.0_RDATA[1] -.sym 4952 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 4953 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 4955 rx_fifo.mem_i.0.0_RDATA[0] -.sym 4958 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 4960 rx_fifo.wr_addr[0] -.sym 4963 io_pmod[0]$SB_IO_IN -.sym 4967 rx_fifo.wr_addr[1] -.sym 4968 rx_fifo.rd_addr_gray_wr_r[1] -.sym 4973 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 4974 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 4975 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 4976 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 4980 rx_fifo.wr_addr[0] -.sym 4981 rx_fifo.wr_addr[1] -.sym 4982 rx_fifo.rd_addr_gray_wr_r[0] -.sym 4985 rx_fifo.mem_i.0.0_RDATA[1] -.sym 4987 rx_fifo.mem_i.0.0_RDATA[0] -.sym 4992 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 4993 rx_fifo.rd_addr_gray_wr_r[3] -.sym 5003 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] -.sym 5004 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] -.sym 5005 io_pmod[0]$SB_IO_IN -.sym 5009 rx_fifo.mem_i.0.0_RDATA_2[0] -.sym 5011 rx_fifo.mem_i.0.0_RDATA[1] -.sym 5013 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O +.sym 3991 rx_fifo.wr_addr_gray[6] +.sym 3992 rx_fifo.wr_addr_gray[7] +.sym 3994 rx_fifo.wr_addr_gray[0] +.sym 3996 rx_fifo.wr_addr_gray[8] +.sym 4003 rx_fifo.wr_addr[8] +.sym 4004 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 4005 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 4006 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 4008 rx_fifo.rd_addr_gray_wr_r[8] +.sym 4009 rx_fifo.wr_addr[0] +.sym 4010 i_rst_b$SB_IO_IN +.sym 4014 w_rx_fifo_push +.sym 4138 i_smi_a2$SB_IO_IN +.sym 4148 w_rx_fifo_pulled_data[11] +.sym 4149 rx_fifo.wr_addr_gray[8] +.sym 4163 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 4238 w_rx_fifo_pulled_data[12] +.sym 4242 w_rx_fifo_pulled_data[14] +.sym 4249 w_rx_09_fifo_data[19] +.sym 4260 w_rx_09_fifo_data[2] +.sym 4281 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 4296 w_rx_fifo_pulled_data[12] +.sym 4344 w_rx_fifo_pulled_data[12] +.sym 4358 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 4359 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 4360 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 4366 w_rx_fifo_pulled_data[13] +.sym 4370 w_rx_fifo_pulled_data[15] +.sym 4377 rx_fifo.wr_addr[8] +.sym 4378 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 4379 rx_fifo.wr_addr[3] +.sym 4381 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 4383 rx_fifo.wr_addr[2] +.sym 4391 rx_fifo.wr_addr[4] +.sym 4405 rx_fifo.wr_addr[6] +.sym 4410 w_rx_09_fifo_data[17] +.sym 4411 $PACKER_VCC_NET +.sym 4413 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 4414 rx_fifo.wr_addr[9] +.sym 4415 w_rx_09_fifo_data[16] +.sym 4421 rx_fifo.wr_addr[3] +.sym 4422 w_rx_09_fifo_data[9] +.sym 4424 rx_fifo.wr_addr[5] +.sym 4426 w_rx_fifo_pulled_data[14] +.sym 4427 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 4430 rx_fifo.rd_addr[9] +.sym 4431 w_rx_fifo_pulled_data[13] +.sym 4442 w_rx_09_fifo_data[6] +.sym 4444 w_rx_09_fifo_data[10] +.sym 4446 w_rx_09_fifo_data[12] +.sym 4448 w_rx_09_fifo_data[14] +.sym 4450 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4452 w_rx_09_fifo_data[3] +.sym 4454 w_rx_09_fifo_data[13] +.sym 4467 w_rx_09_fifo_data[15] +.sym 4469 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 4471 w_rx_09_fifo_data[5] +.sym 4475 w_rx_09_fifo_data[15] +.sym 4478 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4481 w_rx_09_fifo_data[13] +.sym 4483 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4487 w_rx_09_fifo_data[14] +.sym 4490 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4493 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4494 w_rx_09_fifo_data[5] +.sym 4500 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4501 w_rx_09_fifo_data[10] +.sym 4505 w_rx_09_fifo_data[3] +.sym 4507 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4511 w_rx_09_fifo_data[12] +.sym 4514 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4517 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4518 w_rx_09_fifo_data[6] +.sym 4521 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 4522 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 4523 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4525 w_rx_fifo_pulled_data[4] +.sym 4529 w_rx_fifo_pulled_data[6] +.sym 4534 rx_fifo.wr_addr[2] +.sym 4536 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4539 rx_fifo.rd_addr[8] +.sym 4540 w_rx_09_fifo_data[15] +.sym 4545 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 4546 w_rx_09_fifo_data[12] +.sym 4548 rx_fifo.wr_addr[7] +.sym 4551 rx_fifo.wr_addr[2] +.sym 4552 w_rx_24_fifo_data[7] +.sym 4554 rx_fifo.wr_addr[4] +.sym 4557 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4558 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 4566 w_rx_09_fifo_data[2] +.sym 4568 w_rx_09_fifo_data[7] +.sym 4573 w_rx_09_fifo_data[17] +.sym 4576 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 4577 w_rx_09_fifo_data[19] +.sym 4584 w_rx_09_fifo_data[4] +.sym 4587 w_rx_09_fifo_data[0] +.sym 4588 w_rx_09_fifo_data[9] +.sym 4590 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4592 w_rx_09_fifo_data[1] +.sym 4594 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4598 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4599 w_rx_09_fifo_data[4] +.sym 4605 w_rx_09_fifo_data[0] +.sym 4607 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4610 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4612 w_rx_09_fifo_data[1] +.sym 4616 w_rx_09_fifo_data[2] +.sym 4617 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4622 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4625 w_rx_09_fifo_data[17] +.sym 4629 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4630 w_rx_09_fifo_data[19] +.sym 4634 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4637 w_rx_09_fifo_data[9] +.sym 4640 w_rx_09_fifo_data[7] +.sym 4641 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4644 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 4645 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 4646 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4648 w_rx_fifo_pulled_data[5] +.sym 4652 w_rx_fifo_pulled_data[7] +.sym 4656 rx_fifo.wr_addr[7] +.sym 4657 rx_fifo.wr_addr[7] +.sym 4658 rx_fifo.rd_addr_gray_wr[6] +.sym 4659 w_rx_09_fifo_data[6] +.sym 4661 rx_fifo.wr_addr[8] +.sym 4663 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 4664 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 4665 rx_fifo.wr_addr[0] +.sym 4667 w_rx_09_fifo_data[4] +.sym 4668 w_smi_data_output[7] +.sym 4672 w_rx_09_fifo_data[3] +.sym 4673 rx_fifo.rd_addr[8] +.sym 4674 rx_fifo.rd_data_o[29] +.sym 4675 rx_fifo.wr_addr[2] +.sym 4677 rx_fifo.wr_addr[6] +.sym 4678 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 4679 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 4681 rx_fifo.wr_addr[6] +.sym 4682 rx_fifo.rd_data_o[31] +.sym 4689 rx_fifo.rd_data_o[31] +.sym 4692 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 4694 w_rx_09_fifo_data[7] +.sym 4697 channel +.sym 4698 rx_fifo.rd_data_o[29] +.sym 4702 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 4703 w_rx_fifo_pulled_data[14] +.sym 4705 rx_fifo.rd_data_o[28] +.sym 4706 smi_ctrl_ins.int_cnt_rx[3] +.sym 4709 rx_fifo.rd_data_o[30] +.sym 4712 w_rx_24_fifo_data[7] +.sym 4714 smi_ctrl_ins.int_cnt_rx[4] +.sym 4715 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 4717 w_rx_fifo_pulled_data[7] +.sym 4723 w_rx_fifo_pulled_data[7] +.sym 4728 channel +.sym 4729 w_rx_24_fifo_data[7] +.sym 4730 w_rx_09_fifo_data[7] +.sym 4733 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 4734 smi_ctrl_ins.int_cnt_rx[4] +.sym 4735 smi_ctrl_ins.int_cnt_rx[3] +.sym 4736 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 4740 w_rx_fifo_pulled_data[14] +.sym 4748 rx_fifo.rd_data_o[28] +.sym 4751 rx_fifo.rd_data_o[29] +.sym 4758 rx_fifo.rd_data_o[31] +.sym 4765 rx_fifo.rd_data_o[30] +.sym 4767 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 4768 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 4769 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 4771 rx_fifo.rd_data_o[28] +.sym 4775 rx_fifo.rd_data_o[30] +.sym 4779 w_rx_24_fifo_data[9] +.sym 4786 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 4788 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] +.sym 4789 w_smi_data_input[0] +.sym 4790 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] +.sym 4793 rx_fifo.rd_addr[7] +.sym 4795 w_rx_09_fifo_data[17] +.sym 4796 w_rx_09_fifo_data[26] +.sym 4797 w_rx_fifo_pulled_data[24] +.sym 4798 channel +.sym 4799 rx_fifo.wr_addr[9] +.sym 4801 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 4802 $PACKER_VCC_NET +.sym 4803 w_rx_09_fifo_data[16] +.sym 4804 w_rx_fifo_pulled_data[8] +.sym 4812 w_rx_09_fifo_data[16] +.sym 4814 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 4816 smi_ctrl_ins.int_cnt_rx[3] +.sym 4819 w_rx_09_fifo_data[24] +.sym 4820 smi_ctrl_ins.int_cnt_rx[4] +.sym 4821 w_rx_09_fifo_data[22] +.sym 4822 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 4824 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4826 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 4827 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4838 w_rx_09_fifo_data[28] +.sym 4839 w_rx_09_fifo_data[18] +.sym 4840 w_rx_09_fifo_data[26] +.sym 4842 w_rx_09_fifo_data[20] +.sym 4844 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4845 w_rx_09_fifo_data[22] +.sym 4850 smi_ctrl_ins.int_cnt_rx[3] +.sym 4851 smi_ctrl_ins.int_cnt_rx[4] +.sym 4852 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 4853 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 4856 w_rx_09_fifo_data[20] +.sym 4858 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4863 w_rx_09_fifo_data[26] +.sym 4865 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4868 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4869 w_rx_09_fifo_data[16] +.sym 4874 w_rx_09_fifo_data[24] +.sym 4875 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4880 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4882 w_rx_09_fifo_data[28] +.sym 4888 w_rx_09_fifo_data[18] +.sym 4889 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 4890 w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 4891 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 4892 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 4894 rx_fifo.rd_data_o[29] +.sym 4898 rx_fifo.rd_data_o[31] +.sym 4904 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 4906 $PACKER_VCC_NET +.sym 4907 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 4908 rx_fifo.wr_addr[8] +.sym 4910 rx_fifo.wr_addr[3] +.sym 4913 w_rx_09_fifo_data[28] +.sym 4915 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 4917 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] +.sym 4918 rx_fifo.wr_addr[3] +.sym 4919 smi_ctrl_ins.int_cnt_rx[3] +.sym 4920 rx_fifo.wr_addr[5] +.sym 4922 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.sym 4923 w_rx_fifo_data[18] +.sym 4926 rx_fifo.rd_addr[9] +.sym 4927 w_rx_fifo_pulled_data[9] +.sym 4928 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.sym 4935 smi_ctrl_ins.int_cnt_rx[4] +.sym 4938 w_rx_09_fifo_data[18] +.sym 4939 smi_ctrl_ins.int_cnt_rx[3] +.sym 4940 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 4943 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 4947 w_rx_24_fifo_data[18] +.sym 4953 lvds_rx_09_inst.o_fifo_data[31] +.sym 4954 w_rx_24_fifo_data[31] +.sym 4956 w_rx_09_fifo_data[29] +.sym 4958 channel +.sym 4961 w_rx_24_fifo_data[29] +.sym 4973 smi_ctrl_ins.int_cnt_rx[4] +.sym 4975 smi_ctrl_ins.int_cnt_rx[3] +.sym 4985 channel +.sym 4986 w_rx_24_fifo_data[29] +.sym 4988 w_rx_09_fifo_data[29] +.sym 4991 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 4992 smi_ctrl_ins.int_cnt_rx[4] +.sym 4993 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 4994 smi_ctrl_ins.int_cnt_rx[3] +.sym 4999 smi_ctrl_ins.int_cnt_rx[3] +.sym 5003 w_rx_24_fifo_data[31] +.sym 5004 lvds_rx_09_inst.o_fifo_data[31] +.sym 5006 channel +.sym 5010 w_rx_24_fifo_data[18] +.sym 5011 channel +.sym 5012 w_rx_09_fifo_data[18] .sym 5014 smi_ctrl_ins.soe_and_reset_$glb_clk .sym 5015 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5017 rx_fifo.mem_q.0.0_RDATA_3[0] -.sym 5021 rx_fifo.mem_q.0.0_RDATA_2[1] -.sym 5028 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 5032 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 5033 rx_fifo.rd_addr_gray_wr_r[0] -.sym 5035 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5036 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 5037 rx_fifo.mem_i.0.0_RDATA_1[1] -.sym 5038 $PACKER_VCC_NET -.sym 5048 rx_fifo.wr_addr[0] -.sym 5051 i_rst_b$SB_IO_IN -.sym 5057 io_pmod[0]$SB_IO_IN -.sym 5063 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 5064 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] -.sym 5065 channel -.sym 5067 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 5072 rx_fifo.rd_addr_gray_wr[9] -.sym 5073 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[8] -.sym 5075 i_rst_b$SB_IO_IN -.sym 5085 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 5087 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5090 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[8] -.sym 5091 rx_fifo.rd_addr_gray_wr_r[8] -.sym 5092 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 5093 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] -.sym 5103 channel -.sym 5110 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 5114 i_rst_b$SB_IO_IN -.sym 5116 io_pmod[0]$SB_IO_IN -.sym 5126 rx_fifo.rd_addr_gray_wr[9] -.sym 5134 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 5137 lvds_clock_$glb_clk -.sym 5140 rx_fifo.mem_q.0.0_RDATA_1[1] -.sym 5144 rx_fifo.mem_q.0.0_RDATA[1] -.sym 5147 channel -.sym 5150 channel -.sym 5152 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5153 rx_fifo.wr_addr[2] -.sym 5154 rx_fifo.wr_addr[9] -.sym 5155 rx_fifo.wr_addr[4] -.sym 5156 rx_fifo.mem_i.0.0_RDATA[1] -.sym 5159 rx_fifo.wr_addr[1] -.sym 5160 $io_pmod[3]$iobuf_i -.sym 5164 rx_fifo.wr_addr[7] -.sym 5166 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 5167 rx_fifo.wr_addr[3] -.sym 5169 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 5172 rx_fifo.rd_addr[2] -.sym 5173 rx_fifo.wr_addr_gray_rd[9] -.sym 5185 rx_fifo.wr_addr[9] -.sym 5187 w_rx_09_fifo_data[2] -.sym 5189 w_rx_24_fifo_data[0] -.sym 5190 channel -.sym 5192 rx_fifo.wr_addr_gray[8] -.sym 5193 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5198 w_rx_09_fifo_data[3] -.sym 5199 w_rx_09_fifo_data[0] -.sym 5200 w_rx_24_fifo_data[2] -.sym 5201 w_rx_24_fifo_data[1] -.sym 5204 w_rx_24_fifo_data[3] -.sym 5211 w_rx_09_fifo_data[1] -.sym 5213 w_rx_24_fifo_data[0] -.sym 5214 w_rx_09_fifo_data[0] -.sym 5215 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5216 channel -.sym 5221 rx_fifo.wr_addr[9] -.sym 5225 w_rx_09_fifo_data[3] -.sym 5226 w_rx_24_fifo_data[3] -.sym 5227 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5228 channel -.sym 5231 channel -.sym 5232 w_rx_24_fifo_data[2] -.sym 5233 w_rx_09_fifo_data[2] -.sym 5234 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5237 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5238 channel -.sym 5239 w_rx_09_fifo_data[1] -.sym 5240 w_rx_24_fifo_data[1] -.sym 5252 rx_fifo.wr_addr_gray[8] -.sym 5257 rx_fifo.wr_addr[9] -.sym 5260 r_counter_$glb_clk -.sym 5263 rx_fifo.mem_q.0.1_RDATA_3[1] -.sym 5267 rx_fifo.mem_q.0.1_RDATA_2[1] -.sym 5274 io_pmod[0]$SB_IO_IN -.sym 5277 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5279 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 5280 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 5281 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5283 rx_fifo.mem_q.0.0_RDATA_1[1] -.sym 5288 rx_fifo.wr_addr[7] -.sym 5293 rx_fifo.wr_addr[3] -.sym 5294 w_rx_09_fifo_data[6] -.sym 5303 w_rx_24_fifo_data[6] -.sym 5305 w_rx_09_fifo_data[3] -.sym 5309 w_rx_24_fifo_data[4] -.sym 5316 w_rx_24_fifo_data[5] -.sym 5317 w_rx_09_fifo_data[0] -.sym 5319 w_rx_09_fifo_data[6] -.sym 5322 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5323 channel -.sym 5327 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5329 w_rx_09_fifo_data[4] -.sym 5331 channel -.sym 5332 w_rx_09_fifo_data[2] -.sym 5333 w_rx_09_fifo_data[5] -.sym 5337 w_rx_09_fifo_data[4] -.sym 5339 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5342 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5343 channel -.sym 5344 w_rx_09_fifo_data[5] -.sym 5345 w_rx_24_fifo_data[5] -.sym 5349 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5350 w_rx_09_fifo_data[2] -.sym 5354 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5356 w_rx_09_fifo_data[5] -.sym 5360 w_rx_24_fifo_data[6] -.sym 5361 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5362 w_rx_09_fifo_data[6] -.sym 5363 channel -.sym 5366 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5368 w_rx_09_fifo_data[0] -.sym 5372 w_rx_09_fifo_data[3] -.sym 5375 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5378 w_rx_09_fifo_data[4] -.sym 5379 channel -.sym 5380 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 5381 w_rx_24_fifo_data[4] -.sym 5382 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 5383 lvds_clock_$glb_clk -.sym 5384 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5386 rx_fifo.mem_q.0.1_RDATA_1[1] -.sym 5390 rx_fifo.mem_q.0.1_RDATA[1] -.sym 5397 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 5400 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 5401 rx_fifo.wr_addr[5] -.sym 5402 rx_fifo.wr_addr[4] -.sym 5404 rx_fifo.wr_addr[2] -.sym 5405 rx_fifo.wr_addr[6] -.sym 5406 rx_fifo.mem_q.0.1_RDATA_3[1] -.sym 5407 rx_fifo.wr_addr[8] -.sym 5409 $PACKER_VCC_NET -.sym 5411 rx_fifo.wr_addr[6] -.sym 5413 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 5414 $PACKER_VCC_NET -.sym 5415 $PACKER_VCC_NET -.sym 5416 io_pmod[0]$SB_IO_IN -.sym 5417 rx_fifo.wr_addr[0] -.sym 5418 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 5419 w_rx_24_fifo_data[7] -.sym 5431 w_rx_24_fifo_data[5] -.sym 5432 w_rx_24_fifo_data[4] -.sym 5436 w_rx_24_fifo_data[2] -.sym 5438 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5440 w_rx_24_fifo_data[1] -.sym 5454 w_rx_24_fifo_data[3] -.sym 5455 w_rx_24_fifo_data[0] -.sym 5459 w_rx_24_fifo_data[4] -.sym 5460 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5465 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5467 w_rx_24_fifo_data[5] -.sym 5473 w_rx_24_fifo_data[0] -.sym 5474 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5484 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5486 w_rx_24_fifo_data[1] -.sym 5489 w_rx_24_fifo_data[3] -.sym 5491 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5496 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5498 w_rx_24_fifo_data[2] -.sym 5505 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 5506 lvds_clock_$glb_clk -.sym 5507 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5509 rx_fifo.mem_q.0.2_RDATA_3[0] -.sym 5513 rx_fifo.mem_q.0.2_RDATA_2[0] -.sym 5523 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 5524 $PACKER_VCC_NET -.sym 5526 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 5529 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 5549 w_rx_24_fifo_data[6] -.sym 5557 io_pmod[1]$SB_IO_IN +.sym 5017 w_rx_fifo_pulled_data[16] +.sym 5021 w_rx_fifo_pulled_data[18] +.sym 5025 tx_fifo.rd_addr[2] +.sym 5026 rx_fifo.rd_addr_gray_wr[1] +.sym 5029 rx_fifo.rd_addr[7] +.sym 5030 smi_ctrl_ins.int_cnt_rx[3] +.sym 5031 tx_fifo.rd_addr[2] +.sym 5035 rx_fifo.rd_addr[8] +.sym 5037 w_rx_09_fifo_data[30] +.sym 5040 rx_fifo.wr_addr[7] +.sym 5041 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 5042 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 5043 w_rx_fifo_pulled_data[20] +.sym 5044 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 5046 rx_fifo.wr_addr[4] +.sym 5047 w_rx_24_fifo_data[29] +.sym 5048 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 5049 $PACKER_VCC_NET +.sym 5050 rx_fifo.wr_addr[2] +.sym 5051 w_rx_fifo_pulled_data[22] +.sym 5059 w_rx_fifo_pulled_data[20] +.sym 5061 w_rx_24_fifo_data[19] +.sym 5062 smi_ctrl_ins.int_cnt_rx[3] +.sym 5064 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 5066 smi_ctrl_ins.int_cnt_rx[4] +.sym 5067 w_rx_fifo_pulled_data[24] +.sym 5068 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 5073 w_rx_09_fifo_data[19] +.sym 5075 w_rx_fifo_pulled_data[22] +.sym 5076 w_rx_fifo_pulled_data[8] +.sym 5078 w_rx_fifo_pulled_data[19] +.sym 5079 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 5085 channel +.sym 5087 w_rx_fifo_pulled_data[9] +.sym 5091 w_rx_fifo_pulled_data[19] +.sym 5098 w_rx_fifo_pulled_data[8] +.sym 5102 w_rx_24_fifo_data[19] +.sym 5104 w_rx_09_fifo_data[19] +.sym 5105 channel +.sym 5111 w_rx_fifo_pulled_data[20] +.sym 5114 smi_ctrl_ins.int_cnt_rx[4] +.sym 5115 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 5116 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 5117 smi_ctrl_ins.int_cnt_rx[3] +.sym 5121 w_rx_fifo_pulled_data[22] +.sym 5127 w_rx_fifo_pulled_data[24] +.sym 5134 w_rx_fifo_pulled_data[9] +.sym 5136 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 5137 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 5138 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5140 w_rx_fifo_pulled_data[17] +.sym 5144 w_rx_fifo_pulled_data[19] +.sym 5147 w_rx_24_fifo_data[22] +.sym 5152 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 5155 rx_fifo.wr_addr[8] +.sym 5156 rx_fifo.wr_addr[0] +.sym 5159 w_rx_09_fifo_data[20] +.sym 5163 w_rx_fifo_data[3] +.sym 5165 w_rx_fifo_data[23] +.sym 5167 w_rx_fifo_data[1] +.sym 5168 rx_fifo.rd_addr[8] +.sym 5169 rx_fifo.rd_addr[8] +.sym 5170 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 5171 rx_fifo.wr_addr[2] +.sym 5173 rx_fifo.wr_addr[6] +.sym 5180 w_rx_09_fifo_data[23] +.sym 5187 channel +.sym 5191 w_rx_24_fifo_data[23] +.sym 5201 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 5202 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 5203 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5207 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 5243 channel +.sym 5244 w_rx_09_fifo_data[23] +.sym 5246 w_rx_24_fifo_data[23] +.sym 5250 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 5251 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 5252 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5255 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5257 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 5258 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 5259 lvds_rx_09_inst.r_state_if_SB_DFFER_Q_E +.sym 5260 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5261 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5263 w_rx_fifo_pulled_data[20] +.sym 5267 w_rx_fifo_pulled_data[22] +.sym 5272 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5275 w_rx_24_fifo_data[19] +.sym 5277 w_rx_24_fifo_data[31] +.sym 5278 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 5279 w_rx_24_fifo_data[23] +.sym 5282 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.sym 5283 rx_fifo.rd_addr[9] +.sym 5285 rx_fifo.rd_addr[7] +.sym 5286 w_rx_fifo_data[20] +.sym 5288 w_rx_fifo_data[24] +.sym 5289 w_rx_fifo_pulled_data[24] +.sym 5290 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 5291 rx_fifo.wr_addr[9] +.sym 5293 spi_if_ins.w_rx_data[6] +.sym 5294 channel +.sym 5295 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 5296 w_rx_09_fifo_data[26] +.sym 5297 w_rx_fifo_pulled_data[10] +.sym 5304 w_rx_24_fifo_data[10] +.sym 5305 channel +.sym 5307 rx_fifo.rd_addr_gray[2] +.sym 5309 rx_fifo.rd_addr_gray[1] +.sym 5314 w_rx_09_fifo_data[10] +.sym 5316 rx_fifo.rd_addr_gray_wr[2] +.sym 5331 rx_fifo.rd_addr_gray[6] +.sym 5336 rx_fifo.rd_addr_gray_wr[2] +.sym 5345 rx_fifo.rd_addr_gray[1] +.sym 5354 w_rx_24_fifo_data[10] +.sym 5355 channel +.sym 5357 w_rx_09_fifo_data[10] +.sym 5369 rx_fifo.rd_addr_gray[2] +.sym 5373 rx_fifo.rd_addr_gray[6] +.sym 5383 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5386 w_rx_fifo_pulled_data[21] +.sym 5390 w_rx_fifo_pulled_data[23] +.sym 5397 rx_fifo.rd_addr_gray_wr_r[2] +.sym 5398 w_rx_24_fifo_data[10] +.sym 5401 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 5402 rx_fifo.wr_addr[3] +.sym 5403 rx_fifo.rd_addr_gray[2] +.sym 5405 rx_fifo.wr_addr[8] +.sym 5409 w_cs[3] +.sym 5410 w_rx_fifo_data[8] +.sym 5411 w_cs[1] +.sym 5412 rx_fifo.rd_data_o[25] +.sym 5413 w_rx_fifo_data[25] +.sym 5415 w_cs[2] +.sym 5416 rx_fifo.wr_addr[5] +.sym 5417 rx_fifo.wr_addr[3] +.sym 5418 rx_fifo.rd_addr[9] +.sym 5420 rx_fifo.rd_data_o[27] +.sym 5430 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 5437 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 5439 spi_if_ins.w_rx_data[5] +.sym 5442 w_rx_24_fifo_data[1] +.sym 5445 w_rx_09_fifo_data[1] +.sym 5448 w_rx_24_fifo_data[0] +.sym 5453 spi_if_ins.w_rx_data[6] +.sym 5454 channel +.sym 5456 w_rx_09_fifo_data[0] +.sym 5471 w_rx_24_fifo_data[1] +.sym 5472 w_rx_09_fifo_data[1] +.sym 5474 channel +.sym 5477 channel +.sym 5478 w_rx_24_fifo_data[0] +.sym 5479 w_rx_09_fifo_data[0] +.sym 5483 spi_if_ins.w_rx_data[5] +.sym 5485 spi_if_ins.w_rx_data[6] +.sym 5490 spi_if_ins.w_rx_data[5] +.sym 5492 spi_if_ins.w_rx_data[6] +.sym 5502 spi_if_ins.w_rx_data[5] +.sym 5504 spi_if_ins.w_rx_data[6] +.sym 5505 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 5506 r_counter_$glb_clk +.sym 5507 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 5509 w_rx_fifo_pulled_data[24] +.sym 5513 rx_fifo.rd_data_o[26] +.sym 5518 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5521 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 5522 w_cs[1] +.sym 5523 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 5525 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 5526 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 5527 rx_fifo.rd_addr[7] +.sym 5530 w_cs[3] +.sym 5532 $PACKER_VCC_NET +.sym 5534 rx_fifo.wr_addr[2] +.sym 5535 w_rx_fifo_data[0] +.sym 5536 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 5537 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 5538 rx_fifo.wr_addr[4] +.sym 5539 w_cs[1] +.sym 5540 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 5541 w_rx_fifo_data[10] +.sym 5542 w_rx_fifo_data[2] +.sym 5543 rx_fifo.wr_addr[7] +.sym 5549 w_rx_24_fifo_data[27] +.sym 5550 w_rx_09_fifo_data[27] +.sym 5551 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 5552 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5553 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 5554 spi_if_ins.w_rx_data[6] +.sym 5555 w_rx_24_fifo_data[8] +.sym 5556 w_rx_09_fifo_data[8] +.sym 5557 spi_if_ins.w_rx_data[5] .sym 5558 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5576 w_rx_24_fifo_data[8] -.sym 5597 io_pmod[1]$SB_IO_IN -.sym 5601 w_rx_24_fifo_data[6] -.sym 5603 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5613 w_rx_24_fifo_data[8] -.sym 5615 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5628 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 5629 lvds_clock_$glb_clk -.sym 5630 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 5632 rx_fifo.mem_q.0.2_RDATA_1[0] -.sym 5636 rx_fifo.mem_q.0.2_RDATA[0] -.sym 5639 io_pmod[1]$SB_IO_IN -.sym 5643 rx_fifo.wr_addr[9] -.sym 5644 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5645 w_rx_24_fifo_data[10] -.sym 5646 io_pmod[3]$SB_IO_IN -.sym 5649 rx_fifo.wr_addr[8] -.sym 5650 rx_fifo.wr_addr[4] -.sym 5651 rx_fifo.wr_addr[9] -.sym 5653 rx_fifo.wr_addr[1] -.sym 5657 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 5675 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 5688 io_pmod[3]$SB_IO_IN -.sym 5690 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E -.sym 5692 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5696 io_pmod[3]$SB_IO_IN -.sym 5698 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 5701 w_rx_24_fifo_push -.sym 5702 w_rx_09_fifo_push -.sym 5703 channel -.sym 5712 channel -.sym 5713 w_rx_09_fifo_push -.sym 5714 w_rx_24_fifo_push -.sym 5719 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5720 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 5735 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 5736 io_pmod[3]$SB_IO_IN -.sym 5737 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 5738 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5747 w_rx_09_fifo_push -.sym 5748 w_rx_24_fifo_push -.sym 5749 io_pmod[3]$SB_IO_IN -.sym 5750 channel -.sym 5751 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E -.sym 5752 lvds_clock_$glb_clk +.sym 5560 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 5561 channel +.sym 5562 w_rx_24_fifo_data[2] +.sym 5563 w_rx_fifo_full +.sym 5564 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 5565 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 5566 w_lvds_rx_24_d0 +.sym 5567 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5570 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 5571 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 5572 w_lvds_rx_24_d1 +.sym 5575 w_rx_09_fifo_data[2] +.sym 5580 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 5582 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 5583 w_rx_fifo_full +.sym 5584 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 5585 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 5588 channel +.sym 5589 w_rx_24_fifo_data[2] +.sym 5590 w_rx_09_fifo_data[2] +.sym 5594 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 5595 w_lvds_rx_24_d0 +.sym 5596 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 5597 w_lvds_rx_24_d1 +.sym 5600 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 5601 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 5603 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 5607 w_rx_09_fifo_data[27] +.sym 5608 w_rx_24_fifo_data[27] +.sym 5609 channel +.sym 5613 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 5615 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5619 w_rx_09_fifo_data[8] +.sym 5620 w_rx_24_fifo_data[8] +.sym 5621 channel +.sym 5624 spi_if_ins.w_rx_data[6] +.sym 5626 spi_if_ins.w_rx_data[5] +.sym 5628 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E +.sym 5629 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 5630 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 5632 rx_fifo.rd_data_o[25] +.sym 5636 rx_fifo.rd_data_o[27] +.sym 5643 w_rx_24_fifo_data[27] +.sym 5648 rx_fifo.wr_addr[2] +.sym 5649 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 5651 w_rx_24_fifo_data[8] +.sym 5652 rx_fifo.wr_addr[0] +.sym 5653 spi_if_ins.w_rx_data[5] +.sym 5655 w_rx_fifo_data[1] +.sym 5656 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 5657 rx_fifo.wr_addr[6] +.sym 5658 rx_fifo.rd_addr[8] +.sym 5659 rx_fifo.rd_addr_gray_wr_r[3] +.sym 5660 w_rx_fifo_data[3] +.sym 5662 rx_fifo.wr_addr[2] +.sym 5664 rx_fifo.rd_addr[8] +.sym 5677 rx_fifo.rd_addr_gray_wr_r[2] +.sym 5683 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5684 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 5685 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 5688 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 5689 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 5690 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 5691 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 5692 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 5694 rx_fifo.rd_addr_gray_wr_r[5] +.sym 5695 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 5697 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 5705 rx_fifo.rd_addr_gray_wr_r[5] +.sym 5706 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 5712 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 5717 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 5718 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 5719 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 5725 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 5729 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 5735 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 5736 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 5737 rx_fifo.rd_addr_gray_wr_r[2] +.sym 5738 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 5751 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5752 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 5753 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5766 w_rx_24_fifo_data[13] -.sym 5770 w_rx_24_fifo_data[12] -.sym 5772 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 5774 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 5797 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 5798 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 5799 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5805 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 5807 lvds_rx_24_inst.r_phase_count[1] -.sym 5808 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 5810 $PACKER_VCC_NET -.sym 5816 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 5817 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 5820 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 5822 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 5823 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 5826 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 5827 $nextpnr_ICESTORM_LC_2$O -.sym 5829 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 5833 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 5835 $PACKER_VCC_NET -.sym 5836 lvds_rx_24_inst.r_phase_count[1] -.sym 5837 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 5840 $PACKER_VCC_NET -.sym 5842 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 5843 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 5846 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 5847 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 5849 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 5852 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5853 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 5854 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 5855 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 5859 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 5864 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5865 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 5866 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 5867 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 5870 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 5871 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 5872 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 5873 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 5874 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 5875 lvds_clock_$glb_clk +.sym 5755 w_rx_fifo_pulled_data[0] +.sym 5759 w_rx_fifo_pulled_data[2] +.sym 5762 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 5767 rx_fifo.rd_addr_gray[6] +.sym 5770 rx_fifo.wr_addr_gray[2] +.sym 5771 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5776 rx_fifo.wr_addr_gray[1] +.sym 5778 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 5780 rx_fifo.wr_addr[3] +.sym 5781 rx_fifo.wr_addr[7] +.sym 5783 rx_fifo.wr_addr[9] +.sym 5788 rx_fifo.wr_addr[2] +.sym 5789 w_rx_fifo_pulled_data[10] +.sym 5800 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 5807 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 5808 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 5809 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 5810 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 5812 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 5813 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5815 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 5819 rx_fifo.rd_addr_gray_wr_r[3] +.sym 5821 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 5822 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 5823 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 5824 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 5830 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 5836 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 5841 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 5842 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 5843 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 5848 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 5855 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 5861 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 5864 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 5865 rx_fifo.rd_addr_gray_wr_r[3] +.sym 5866 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 5867 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 5873 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 5874 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5875 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 5876 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 5891 o_shdn_tx_lna$SB_IO_OUT -.sym 5893 $PACKER_VCC_NET -.sym 5896 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5901 $PACKER_VCC_NET -.sym 5912 $PACKER_VCC_NET -.sym 5918 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5926 io_pmod[3]$SB_IO_IN -.sym 5929 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 5930 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 5931 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 5932 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5978 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 5989 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5990 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 5993 io_pmod[3]$SB_IO_IN -.sym 5994 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 5996 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 5997 lvds_rx_09_inst.o_fifo_push_SB_DFFER_Q_E -.sym 5998 lvds_clock_$glb_clk +.sym 5878 w_rx_fifo_pulled_data[1] +.sym 5882 w_rx_fifo_pulled_data[3] +.sym 5889 $PACKER_VCC_NET +.sym 5892 w_cs[3] +.sym 5894 rx_fifo.wr_addr[8] +.sym 5896 w_cs[2] +.sym 5898 $PACKER_VCC_NET +.sym 5900 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 5903 w_rx_fifo_data[8] +.sym 5904 rx_fifo.wr_addr[4] +.sym 5906 rx_fifo.rd_addr[7] +.sym 5908 rx_fifo.wr_addr[3] +.sym 5910 rx_fifo.rd_addr[9] +.sym 5912 rx_fifo.wr_addr[5] +.sym 5920 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 5921 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 5926 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 5927 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 5928 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 5931 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5932 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 5933 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 5936 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 5943 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 5944 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 5945 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5951 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 5959 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 5963 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 5964 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 5975 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 5978 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 5982 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 5988 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 5993 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 5994 rx_fifo.rd_addr_gray_wr_r[7] +.sym 5995 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 5996 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 5997 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 5998 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 5999 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 6044 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6045 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 6051 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 6052 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6054 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 6055 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 6059 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 6061 $PACKER_VCC_NET -.sym 6062 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 6064 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 6066 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 6068 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6069 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 6071 lvds_rx_09_inst.r_phase_count[1] -.sym 6072 $PACKER_VCC_NET -.sym 6073 $nextpnr_ICESTORM_LC_0$O -.sym 6075 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6079 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 6081 $PACKER_VCC_NET -.sym 6082 lvds_rx_09_inst.r_phase_count[1] -.sym 6083 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 6087 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 6088 $PACKER_VCC_NET -.sym 6089 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 6093 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6098 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 6099 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 6100 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 6101 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 6104 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 6105 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 6106 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 6107 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 6113 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 6116 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 6117 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 6118 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 6119 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 6120 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O -.sym 6121 lvds_clock_$glb_clk -.sym 6122 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 6254 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 6001 w_rx_fifo_pulled_data[8] +.sym 6005 w_rx_fifo_pulled_data[10] +.sym 6012 w_rx_fifo_push +.sym 6014 rx_fifo.wr_addr_gray[4] +.sym 6015 rx_fifo.rd_addr[7] +.sym 6018 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1] +.sym 6021 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 6032 $PACKER_VCC_NET +.sym 6033 w_rx_fifo_data[10] +.sym 6041 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 6042 rx_fifo.rd_addr_gray_wr[7] +.sym 6043 i_rst_b$SB_IO_IN +.sym 6049 rx_fifo.rd_addr_gray_wr_r[8] +.sym 6050 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 6051 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 6054 rx_fifo.rd_addr_gray_wr_r[5] +.sym 6057 rx_fifo.rd_addr_gray_wr[6] +.sym 6062 w_rx_fifo_push +.sym 6066 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 6071 rx_fifo.rd_addr_gray_wr[1] +.sym 6072 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 6074 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 6076 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 6081 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 6083 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 6086 rx_fifo.rd_addr_gray_wr[6] +.sym 6094 rx_fifo.rd_addr_gray_wr[1] +.sym 6098 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 6099 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 6100 rx_fifo.rd_addr_gray_wr_r[5] +.sym 6101 rx_fifo.rd_addr_gray_wr_r[8] +.sym 6106 rx_fifo.rd_addr_gray_wr[7] +.sym 6116 w_rx_fifo_push +.sym 6119 i_rst_b$SB_IO_IN +.sym 6121 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 6124 w_rx_fifo_pulled_data[9] +.sym 6128 w_rx_fifo_pulled_data[11] +.sym 6135 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 6143 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 6145 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 6146 rx_fifo.rd_addr_gray_wr[7] +.sym 6149 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 6152 rx_fifo.rd_addr[8] +.sym 6164 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 6165 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 6172 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 6175 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 6183 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 6211 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 6215 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 6227 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 6241 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 6243 rx_fifo.wr_en_i_SB_LUT4_I2_O +.sym 6244 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 6245 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 6256 rx_fifo.wr_addr_gray[0] +.sym 6260 rx_fifo.wr_addr_gray[6] +.sym 6262 rx_fifo.wr_addr_gray[7] +.sym 6264 o_shdn_tx_lna$SB_IO_OUT +.sym 6281 o_shdn_tx_lna$SB_IO_OUT .sym 6294 o_shdn_tx_lna$SB_IO_OUT -.sym 6310 o_shdn_tx_lna$SB_IO_OUT -.sym 6346 rx_fifo.rd_addr_gray_wr[6] -.sym 6347 rx_fifo.rd_addr_gray_wr[2] -.sym 6349 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 6350 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 6351 rx_fifo.rd_addr_gray_wr_r[5] -.sym 6353 rx_fifo.rd_addr_gray_wr[5] -.sym 6422 rx_fifo.rd_addr_gray[2] -.sym 6423 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 6425 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 6426 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 6427 rx_fifo.rd_addr_gray[3] -.sym 6428 rx_fifo.rd_addr_gray[6] -.sym 6429 rx_fifo.rd_addr_gray[5] -.sym 6467 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 6507 w_smi_data_output[1] -.sym 6512 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 6518 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 6520 w_smi_data_output[6] -.sym 6561 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 6562 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 6563 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 6564 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6565 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 6566 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 6567 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 6604 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 6606 rx_fifo.rd_addr[2] -.sym 6608 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 6610 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 6611 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 6612 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 6618 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 6625 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 6662 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[3] -.sym 6663 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 6664 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[0] -.sym 6665 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 6666 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 6667 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 6668 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 6669 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 6707 rx_fifo.wr_addr_gray_rd[4] -.sym 6716 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 6718 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 6723 io_pmod[0]$SB_IO_IN -.sym 6724 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 6725 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6726 rx_fifo.rd_addr_gray[7] -.sym 6764 rx_fifo.rd_addr_gray[4] -.sym 6765 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 6766 rx_fifo.rd_addr_gray[8] -.sym 6767 rx_fifo.rd_addr_gray[7] -.sym 6768 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 6769 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 6770 rx_fifo.rd_addr_gray[1] -.sym 6771 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[3] -.sym 6806 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 6807 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 6810 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 6811 rx_fifo.wr_addr[0] -.sym 6816 io_pmod[1]$SB_IO_IN -.sym 6817 rx_fifo.wr_addr[0] -.sym 6819 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] +.sym 6307 o_shdn_tx_lna$SB_IO_OUT +.sym 6380 w_smi_data_input[7] +.sym 6386 w_rx_fifo_data[12] +.sym 6388 rx_fifo.wr_addr[4] +.sym 6390 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6393 rx_fifo.wr_addr[3] +.sym 6395 rx_fifo.wr_addr[2] +.sym 6399 rx_fifo.wr_addr[8] +.sym 6400 rx_fifo.wr_addr[7] +.sym 6401 rx_fifo.wr_addr[6] +.sym 6405 rx_fifo.wr_addr[0] +.sym 6406 w_rx_fifo_data[14] +.sym 6409 rx_fifo.wr_addr[9] +.sym 6410 rx_fifo.wr_addr[5] +.sym 6413 w_rx_fifo_push +.sym 6415 $PACKER_VCC_NET +.sym 6418 w_smi_data_input[6] +.sym 6423 w_rx_fifo_data[13] +.sym 6424 w_tx_fifo_data[14] +.sym 6425 w_rx_fifo_data[12] +.sym 6426 w_rx_fifo_data[14] +.sym 6427 w_rx_fifo_data[15] +.sym 6429 w_tx_fifo_data[26] +.sym 6438 rx_fifo.wr_addr[2] +.sym 6439 rx_fifo.wr_addr[3] +.sym 6441 rx_fifo.wr_addr[4] +.sym 6442 rx_fifo.wr_addr[5] +.sym 6443 rx_fifo.wr_addr[6] +.sym 6444 rx_fifo.wr_addr[7] +.sym 6445 rx_fifo.wr_addr[8] +.sym 6446 rx_fifo.wr_addr[9] +.sym 6447 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6448 rx_fifo.wr_addr[0] +.sym 6449 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 6450 w_rx_fifo_push +.sym 6452 w_rx_fifo_data[12] +.sym 6456 w_rx_fifo_data[14] +.sym 6459 $PACKER_VCC_NET +.sym 6468 $PACKER_VCC_NET +.sym 6469 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 6472 rx_fifo.wr_addr[7] +.sym 6481 i_smi_a2$SB_IO_IN +.sym 6488 w_smi_data_output[6] +.sym 6493 rx_fifo.rd_addr[0] +.sym 6495 $PACKER_VCC_NET +.sym 6497 channel +.sym 6500 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6502 w_smi_data_input[6] +.sym 6503 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6505 w_rx_fifo_data[12] +.sym 6507 w_rx_24_fifo_data[12] +.sym 6508 w_rx_fifo_pull +.sym 6514 w_rx_fifo_push +.sym 6530 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 6532 $PACKER_VCC_NET +.sym 6534 rx_fifo.rd_addr[8] +.sym 6539 w_rx_fifo_pull +.sym 6542 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6545 rx_fifo.rd_addr[7] +.sym 6546 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 6547 rx_fifo.rd_addr[9] +.sym 6549 rx_fifo.rd_addr[0] +.sym 6550 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6553 w_rx_fifo_data[13] +.sym 6555 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6556 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6557 w_rx_fifo_data[15] +.sym 6560 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] +.sym 6561 w_rx_fifo_data[6] +.sym 6563 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] +.sym 6564 w_rx_fifo_data[4] +.sym 6565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] +.sym 6567 w_rx_fifo_data[5] +.sym 6576 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6577 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6579 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 6580 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6581 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 6582 rx_fifo.rd_addr[7] +.sym 6583 rx_fifo.rd_addr[8] +.sym 6584 rx_fifo.rd_addr[9] +.sym 6585 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6586 rx_fifo.rd_addr[0] +.sym 6587 r_counter_$glb_clk +.sym 6588 w_rx_fifo_pull +.sym 6589 $PACKER_VCC_NET +.sym 6593 w_rx_fifo_data[15] +.sym 6597 w_rx_fifo_data[13] +.sym 6603 w_rx_24_fifo_data[15] +.sym 6608 $PACKER_VCC_NET +.sym 6618 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6623 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6624 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6625 w_rx_fifo_data[28] +.sym 6631 rx_fifo.wr_addr[0] +.sym 6636 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6638 rx_fifo.wr_addr[5] +.sym 6640 rx_fifo.wr_addr[7] +.sym 6642 rx_fifo.wr_addr[9] +.sym 6643 $PACKER_VCC_NET +.sym 6644 rx_fifo.wr_addr[3] +.sym 6645 rx_fifo.wr_addr[8] +.sym 6648 rx_fifo.wr_addr[2] +.sym 6650 w_rx_fifo_data[4] +.sym 6652 rx_fifo.wr_addr[6] +.sym 6655 w_rx_fifo_data[6] +.sym 6657 w_rx_fifo_push +.sym 6661 rx_fifo.wr_addr[4] +.sym 6662 w_rx_fifo_data[9] +.sym 6665 smi_ctrl_ins.r_fifo_pushed_data[18] +.sym 6678 rx_fifo.wr_addr[2] +.sym 6679 rx_fifo.wr_addr[3] +.sym 6681 rx_fifo.wr_addr[4] +.sym 6682 rx_fifo.wr_addr[5] +.sym 6683 rx_fifo.wr_addr[6] +.sym 6684 rx_fifo.wr_addr[7] +.sym 6685 rx_fifo.wr_addr[8] +.sym 6686 rx_fifo.wr_addr[9] +.sym 6687 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6688 rx_fifo.wr_addr[0] +.sym 6689 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 6690 w_rx_fifo_push +.sym 6692 w_rx_fifo_data[4] +.sym 6696 w_rx_fifo_data[6] +.sym 6699 $PACKER_VCC_NET +.sym 6704 $PACKER_VCC_NET +.sym 6706 i_rst_b$SB_IO_IN +.sym 6710 rx_fifo.wr_addr[9] +.sym 6711 w_rx_24_fifo_data[4] +.sym 6717 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6719 w_rx_09_fifo_data[5] +.sym 6722 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 6723 w_rx_fifo_push +.sym 6724 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 6726 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 6732 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6735 rx_fifo.rd_addr[9] +.sym 6738 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 6741 w_rx_fifo_data[7] +.sym 6743 w_rx_fifo_pull +.sym 6744 rx_fifo.rd_addr[7] +.sym 6747 w_rx_fifo_data[5] +.sym 6752 $PACKER_VCC_NET +.sym 6753 rx_fifo.rd_addr[0] +.sym 6754 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 6756 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6759 rx_fifo.rd_addr[8] +.sym 6761 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6762 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6765 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 6766 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 6767 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 6768 lvds_tx_inst.r_phase_count[2] +.sym 6769 w_rx_fifo_data[28] +.sym 6770 lvds_tx_inst.r_phase_count[3] +.sym 6771 w_rx_fifo_full +.sym 6780 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6781 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6783 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 6784 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6785 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 6786 rx_fifo.rd_addr[7] +.sym 6787 rx_fifo.rd_addr[8] +.sym 6788 rx_fifo.rd_addr[9] +.sym 6789 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6790 rx_fifo.rd_addr[0] +.sym 6791 r_counter_$glb_clk +.sym 6792 w_rx_fifo_pull +.sym 6793 $PACKER_VCC_NET +.sym 6797 w_rx_fifo_data[7] +.sym 6801 w_rx_fifo_data[5] +.sym 6804 w_rx_fifo_pulled_data[8] +.sym 6807 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] +.sym 6808 w_tx_fifo_data[4] +.sym 6810 w_rx_09_fifo_data[9] +.sym 6811 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.sym 6812 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.sym 6813 w_smi_data_input[3] +.sym 6816 smi_ctrl_ins.int_cnt_rx[3] +.sym 6818 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 6819 rx_fifo.rd_addr[0] +.sym 6823 channel +.sym 6824 w_rx_09_fifo_data[21] +.sym 6826 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6827 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6828 $PACKER_VCC_NET +.sym 6834 rx_fifo.wr_addr[2] .sym 6835 rx_fifo.wr_addr[7] -.sym 6836 rx_fifo.wr_addr[8] -.sym 6841 rx_fifo.wr_addr[3] -.sym 6845 rx_fifo.wr_addr[6] -.sym 6846 rx_fifo.wr_addr[5] -.sym 6848 rx_fifo.wr_addr[0] -.sym 6849 rx_fifo.wr_addr[1] -.sym 6850 rx_fifo.mem_i.0.0_WDATA_2 -.sym 6854 $PACKER_VCC_NET -.sym 6855 rx_fifo.wr_addr[9] -.sym 6856 rx_fifo.wr_addr[2] -.sym 6859 rx_fifo.wr_addr[4] -.sym 6861 io_pmod[0]$SB_IO_IN -.sym 6863 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6866 rx_fifo.mem_i.0.0_WDATA_2 -.sym 6867 rx_fifo.wr_addr_gray_rd_r[8] -.sym 6868 rx_fifo.mem_i.0.0_WDATA -.sym 6869 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 6871 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 6836 rx_fifo.wr_addr[6] +.sym 6838 $PACKER_VCC_NET +.sym 6840 rx_fifo.wr_addr[8] +.sym 6847 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6848 rx_fifo.wr_addr[3] +.sym 6849 rx_fifo.wr_addr[4] +.sym 6852 w_rx_fifo_data[28] +.sym 6853 rx_fifo.wr_addr[0] +.sym 6857 rx_fifo.wr_addr[5] +.sym 6861 w_rx_fifo_push +.sym 6862 rx_fifo.wr_addr[9] +.sym 6863 w_rx_fifo_data[30] +.sym 6866 smi_ctrl_ins.r_fifo_pull +.sym 6868 smi_ctrl_ins.r_fifo_pull_1 +.sym 6869 w_rx_fifo_pull +.sym 6870 w_rx_fifo_pull +.sym 6871 w_rx_fifo_data[30] +.sym 6872 w_rx_fifo_data[3] +.sym 6873 w_rx_fifo_empty .sym 6882 rx_fifo.wr_addr[2] .sym 6883 rx_fifo.wr_addr[3] .sym 6885 rx_fifo.wr_addr[4] @@ -5872,81 +6447,100 @@ .sym 6888 rx_fifo.wr_addr[7] .sym 6889 rx_fifo.wr_addr[8] .sym 6890 rx_fifo.wr_addr[9] -.sym 6891 rx_fifo.wr_addr[1] +.sym 6891 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] .sym 6892 rx_fifo.wr_addr[0] -.sym 6893 lvds_clock_$glb_clk -.sym 6894 io_pmod[0]$SB_IO_IN -.sym 6896 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6900 rx_fifo.mem_i.0.0_WDATA_2 +.sym 6893 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 6894 w_rx_fifo_push +.sym 6896 w_rx_fifo_data[28] +.sym 6900 w_rx_fifo_data[30] .sym 6903 $PACKER_VCC_NET -.sym 6912 rx_fifo.mem_i.0.0_RDATA_3[0] -.sym 6922 rx_fifo.wr_addr[8] -.sym 6924 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 6925 w_rx_09_fifo_data[18] -.sym 6926 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 6927 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 6928 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 6929 rx_fifo.wr_addr[2] -.sym 6930 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 6931 w_rx_24_fifo_data[15] -.sym 6936 rx_fifo.rd_addr[2] -.sym 6938 io_pmod[1]$SB_IO_IN -.sym 6940 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 6941 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 6942 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 6943 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 6945 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 6946 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 6947 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 6949 $PACKER_VCC_NET -.sym 6953 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 6954 rx_fifo.mem_i.0.0_WDATA -.sym 6962 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 6963 rx_fifo.mem_i.0.0_WDATA_1 -.sym 6968 w_rx_24_fifo_data[20] -.sym 6969 w_rx_24_fifo_data[17] -.sym 6970 w_rx_24_fifo_data[29] -.sym 6971 rx_fifo.mem_i.0.0_WDATA_1 -.sym 6972 rx_fifo.mem_i.0.0_WDATA_3 -.sym 6973 w_rx_24_fifo_data[18] -.sym 6974 w_rx_24_fifo_data[19] -.sym 6975 w_rx_24_fifo_data[16] -.sym 6984 rx_fifo.rd_addr[2] -.sym 6985 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 6987 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 6988 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 6989 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 6990 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 6991 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 6992 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 6993 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 6994 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 6906 w_rx_fifo_pulled_data[9] +.sym 6908 w_rx_24_fifo_data[7] +.sym 6909 rx_fifo.wr_addr[7] +.sym 6912 $PACKER_VCC_NET +.sym 6915 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 6916 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 6917 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 6918 w_tx_fifo_pull +.sym 6921 w_rx_fifo_pull +.sym 6922 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 6924 w_rx_24_fifo_data[11] +.sym 6929 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.sym 6931 w_rx_fifo_push +.sym 6936 rx_fifo.rd_addr[8] +.sym 6940 $PACKER_VCC_NET +.sym 6942 w_rx_fifo_data[31] +.sym 6945 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 6947 w_rx_fifo_data[29] +.sym 6948 rx_fifo.rd_addr[7] +.sym 6954 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 6957 rx_fifo.rd_addr[0] +.sym 6958 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6959 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6960 rx_fifo.rd_addr[9] +.sym 6963 w_rx_fifo_pull +.sym 6964 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6965 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6968 w_rx_fifo_data[22] +.sym 6969 w_rx_fifo_data[17] +.sym 6970 w_rx_fifo_data[16] +.sym 6971 w_rx_fifo_data[21] +.sym 6972 w_lvds_tx_d1 +.sym 6973 w_rx_fifo_data[11] +.sym 6974 w_rx_fifo_data[20] +.sym 6975 w_rx_fifo_data[24] +.sym 6984 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 6985 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 6987 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 6988 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 6989 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 6990 rx_fifo.rd_addr[7] +.sym 6991 rx_fifo.rd_addr[8] +.sym 6992 rx_fifo.rd_addr[9] +.sym 6993 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 6994 rx_fifo.rd_addr[0] .sym 6995 r_counter_$glb_clk -.sym 6996 io_pmod[1]$SB_IO_IN +.sym 6996 w_rx_fifo_pull .sym 6997 $PACKER_VCC_NET -.sym 7001 rx_fifo.mem_i.0.0_WDATA -.sym 7005 rx_fifo.mem_i.0.0_WDATA_1 -.sym 7016 rx_fifo.wr_addr_gray_rd[9] -.sym 7020 rx_fifo.wr_addr[3] -.sym 7022 w_rx_09_fifo_data[19] -.sym 7032 rx_fifo.mem_q.0.0_RDATA_3[0] -.sym 7040 io_pmod[0]$SB_IO_IN -.sym 7041 rx_fifo.wr_addr[0] +.sym 7001 w_rx_fifo_data[31] +.sym 7005 w_rx_fifo_data[29] +.sym 7006 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] +.sym 7010 w_rx_09_fifo_data[3] +.sym 7011 w_rx_fifo_data[3] +.sym 7012 tx_fifo.rd_addr[5] +.sym 7013 i_rst_b$SB_IO_IN +.sym 7016 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 7019 $PACKER_VCC_NET +.sym 7020 w_rx_24_fifo_data[3] +.sym 7022 w_rx_09_fifo_data[24] +.sym 7023 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7024 w_rx_24_fifo_data[25] +.sym 7025 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7026 w_rx_fifo_pull +.sym 7031 w_rx_fifo_data[22] +.sym 7032 w_rx_fifo_pulled_data[0] +.sym 7039 rx_fifo.wr_addr[9] +.sym 7040 w_rx_fifo_data[18] .sym 7042 $PACKER_VCC_NET -.sym 7043 rx_fifo.wr_addr[9] -.sym 7045 rx_fifo.wr_addr[3] -.sym 7046 rx_fifo.wr_addr[7] -.sym 7047 rx_fifo.wr_addr[6] -.sym 7049 rx_fifo.wr_addr[1] -.sym 7053 rx_fifo.wr_addr[4] -.sym 7054 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7055 rx_fifo.wr_addr[5] -.sym 7060 rx_fifo.wr_addr[8] -.sym 7065 rx_fifo.mem_q.0.0_WDATA_2 -.sym 7067 rx_fifo.wr_addr[2] -.sym 7072 w_rx_09_fifo_data[18] -.sym 7075 w_rx_09_fifo_data[17] -.sym 7076 w_rx_09_fifo_data[19] +.sym 7043 rx_fifo.wr_addr[3] +.sym 7045 rx_fifo.wr_addr[5] +.sym 7052 rx_fifo.wr_addr[0] +.sym 7053 rx_fifo.wr_addr[8] +.sym 7055 rx_fifo.wr_addr[7] +.sym 7056 w_rx_fifo_data[16] +.sym 7058 rx_fifo.wr_addr[2] +.sym 7060 rx_fifo.wr_addr[6] +.sym 7063 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7065 w_rx_fifo_push +.sym 7069 rx_fifo.wr_addr[4] +.sym 7070 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] +.sym 7071 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] +.sym 7072 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.sym 7073 w_rx_fifo_data[25] +.sym 7074 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.sym 7075 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.sym 7076 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.sym 7077 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] .sym 7086 rx_fifo.wr_addr[2] .sym 7087 rx_fifo.wr_addr[3] .sym 7089 rx_fifo.wr_addr[4] @@ -5955,80 +6549,108 @@ .sym 7092 rx_fifo.wr_addr[7] .sym 7093 rx_fifo.wr_addr[8] .sym 7094 rx_fifo.wr_addr[9] -.sym 7095 rx_fifo.wr_addr[1] +.sym 7095 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] .sym 7096 rx_fifo.wr_addr[0] -.sym 7097 lvds_clock_$glb_clk -.sym 7098 io_pmod[0]$SB_IO_IN -.sym 7100 rx_fifo.mem_q.0.0_WDATA_3 -.sym 7104 rx_fifo.mem_q.0.0_WDATA_2 +.sym 7097 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 7098 w_rx_fifo_push +.sym 7100 w_rx_fifo_data[16] +.sym 7104 w_rx_fifo_data[18] .sym 7107 $PACKER_VCC_NET -.sym 7113 w_rx_24_fifo_data[19] -.sym 7116 io_pmod[1]$SB_IO_IN -.sym 7123 w_rx_24_fifo_data[27] -.sym 7126 rx_fifo.mem_q.0.0_RDATA[1] -.sym 7128 rx_fifo.mem_i.0.0_WDATA_3 -.sym 7132 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 7134 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 7140 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 7141 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 7142 rx_fifo.mem_q.0.0_WDATA -.sym 7144 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7146 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 7150 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 7151 io_pmod[1]$SB_IO_IN -.sym 7153 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7154 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 7155 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 7156 rx_fifo.rd_addr[2] -.sym 7157 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 7159 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 7169 $PACKER_VCC_NET -.sym 7172 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 7174 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 7175 rx_fifo.mem_q.0.1_WDATA -.sym 7176 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 7177 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 7178 rx_fifo.mem_q.0.3_WDATA -.sym 7188 rx_fifo.rd_addr[2] -.sym 7189 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 7191 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 7192 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 7193 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 7194 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 7195 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7196 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 7197 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 7198 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 7109 w_rx_fifo_data[11] +.sym 7110 w_rx_fifo_data[11] +.sym 7112 w_rx_09_fifo_data[17] +.sym 7113 w_rx_fifo_data[20] +.sym 7114 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 7116 i_rst_b$SB_IO_IN +.sym 7117 w_rx_fifo_data[24] +.sym 7118 $PACKER_VCC_NET +.sym 7119 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 7120 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 7121 i_rst_b$SB_IO_IN +.sym 7122 w_rx_09_fifo_data[16] +.sym 7123 rx_fifo.wr_addr[9] +.sym 7125 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[0] +.sym 7126 w_rx_fifo_data[21] +.sym 7127 w_rx_fifo_pull +.sym 7128 w_lvds_tx_d1 +.sym 7129 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7130 w_rx_fifo_pulled_data[3] +.sym 7131 w_rx_fifo_push +.sym 7132 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 7133 w_rx_fifo_push +.sym 7134 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 7142 w_rx_fifo_pull +.sym 7144 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7149 w_rx_fifo_data[17] +.sym 7150 rx_fifo.rd_addr[9] +.sym 7152 rx_fifo.rd_addr[7] +.sym 7153 $PACKER_VCC_NET +.sym 7156 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7157 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7158 w_rx_fifo_data[19] +.sym 7160 rx_fifo.rd_addr[8] +.sym 7161 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7162 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7168 rx_fifo.rd_addr[0] +.sym 7171 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7172 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7173 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7174 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[1] +.sym 7175 rx_fifo.rd_addr_gray[1] +.sym 7176 rx_fifo.rd_addr[0] +.sym 7177 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7178 rx_fifo.rd_addr_gray[2] +.sym 7179 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7188 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7189 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7191 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7192 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7193 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7194 rx_fifo.rd_addr[7] +.sym 7195 rx_fifo.rd_addr[8] +.sym 7196 rx_fifo.rd_addr[9] +.sym 7197 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7198 rx_fifo.rd_addr[0] .sym 7199 r_counter_$glb_clk -.sym 7200 io_pmod[1]$SB_IO_IN +.sym 7200 w_rx_fifo_pull .sym 7201 $PACKER_VCC_NET -.sym 7205 rx_fifo.mem_q.0.0_WDATA -.sym 7209 rx_fifo.mem_q.0.0_WDATA_1 -.sym 7215 $PACKER_VCC_NET -.sym 7216 $PACKER_VCC_NET -.sym 7217 io_pmod[1]$SB_IO_IN -.sym 7219 w_rx_data[3] -.sym 7222 rx_fifo.wr_addr[6] -.sym 7223 io_pmod[0]$SB_IO_IN -.sym 7228 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7230 rx_fifo.mem_i.0.0_RDATA[1] -.sym 7242 rx_fifo.wr_addr[2] -.sym 7243 rx_fifo.wr_addr[0] -.sym 7246 rx_fifo.mem_q.0.1_WDATA_2 -.sym 7247 rx_fifo.wr_addr[7] -.sym 7248 rx_fifo.wr_addr[4] -.sym 7249 rx_fifo.wr_addr[5] -.sym 7250 rx_fifo.wr_addr[3] -.sym 7253 rx_fifo.wr_addr[6] -.sym 7255 rx_fifo.wr_addr[8] -.sym 7257 rx_fifo.mem_q.0.1_WDATA_3 -.sym 7262 $PACKER_VCC_NET -.sym 7264 rx_fifo.wr_addr[1] -.sym 7265 rx_fifo.wr_addr[9] -.sym 7269 io_pmod[0]$SB_IO_IN -.sym 7277 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 7278 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 7281 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 7205 w_rx_fifo_data[19] +.sym 7209 w_rx_fifo_data[17] +.sym 7215 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.sym 7217 w_rx_fifo_data[25] +.sym 7219 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] +.sym 7227 rx_fifo.rd_addr[0] +.sym 7229 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 7230 $PACKER_VCC_NET +.sym 7231 channel +.sym 7232 rx_fifo.wr_addr[0] +.sym 7233 w_rx_fifo_pulled_data[21] +.sym 7234 w_rx_fifo_pulled_data[1] +.sym 7235 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7236 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 7237 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 7242 rx_fifo.wr_addr[4] +.sym 7246 rx_fifo.wr_addr[2] +.sym 7248 rx_fifo.wr_addr[6] +.sym 7249 rx_fifo.wr_addr[0] +.sym 7251 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7252 rx_fifo.wr_addr[7] +.sym 7253 rx_fifo.wr_addr[8] +.sym 7255 $PACKER_VCC_NET +.sym 7256 rx_fifo.wr_addr[3] +.sym 7258 w_rx_fifo_data[22] +.sym 7261 rx_fifo.wr_addr[5] +.sym 7267 w_rx_fifo_data[20] +.sym 7269 w_rx_fifo_push +.sym 7270 rx_fifo.wr_addr[9] +.sym 7274 spi_if_ins.state_if[0] +.sym 7275 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 7276 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 7277 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 7278 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 7279 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[2] +.sym 7280 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 7281 spi_if_ins.state_if[1] .sym 7290 rx_fifo.wr_addr[2] .sym 7291 rx_fifo.wr_addr[3] .sym 7293 rx_fifo.wr_addr[4] @@ -6037,78 +6659,105 @@ .sym 7296 rx_fifo.wr_addr[7] .sym 7297 rx_fifo.wr_addr[8] .sym 7298 rx_fifo.wr_addr[9] -.sym 7299 rx_fifo.wr_addr[1] +.sym 7299 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] .sym 7300 rx_fifo.wr_addr[0] -.sym 7301 lvds_clock_$glb_clk -.sym 7302 io_pmod[0]$SB_IO_IN -.sym 7304 rx_fifo.mem_q.0.1_WDATA_3 -.sym 7308 rx_fifo.mem_q.0.1_WDATA_2 +.sym 7301 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 7302 w_rx_fifo_push +.sym 7304 w_rx_fifo_data[20] +.sym 7308 w_rx_fifo_data[22] .sym 7311 $PACKER_VCC_NET -.sym 7318 i_rst_b$SB_IO_IN -.sym 7328 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7329 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 7330 rx_fifo.mem_q.0.2_RDATA_1[0] -.sym 7331 w_rx_24_fifo_data[15] -.sym 7334 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 7336 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 7337 rx_fifo.wr_addr[2] -.sym 7344 rx_fifo.rd_addr[2] -.sym 7346 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 7351 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 7353 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 7354 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 7355 rx_fifo.mem_q.0.1_WDATA -.sym 7358 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 7359 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 7361 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 7362 io_pmod[1]$SB_IO_IN -.sym 7363 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 7364 $PACKER_VCC_NET -.sym 7366 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7369 rx_fifo.mem_q.0.1_WDATA_1 -.sym 7376 w_rx_09_fifo_data[9] -.sym 7377 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7378 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7379 rx_fifo.mem_q.0.2_WDATA_2 -.sym 7380 w_rx_09_fifo_data[8] -.sym 7381 w_rx_09_fifo_data[11] -.sym 7382 rx_fifo.mem_q.0.2_WDATA -.sym 7392 rx_fifo.rd_addr[2] -.sym 7393 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 7395 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 7396 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 7397 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 7398 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 7399 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7400 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 7401 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 7402 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 7313 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7314 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7316 rx_fifo.wr_addr[4] +.sym 7317 w_rx_24_fifo_data[29] +.sym 7318 rx_fifo.wr_addr[7] +.sym 7321 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7323 $PACKER_VCC_NET +.sym 7325 $PACKER_VCC_NET +.sym 7327 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7328 w_rx_fifo_data[26] +.sym 7329 w_rx_fifo_pull +.sym 7330 w_rx_fifo_pull +.sym 7334 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 7335 w_rx_fifo_push +.sym 7338 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7344 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7345 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7346 rx_fifo.rd_addr[8] +.sym 7348 $PACKER_VCC_NET +.sym 7349 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7350 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7352 rx_fifo.rd_addr[7] +.sym 7353 w_rx_fifo_data[23] +.sym 7355 w_rx_fifo_data[21] +.sym 7356 rx_fifo.rd_addr[0] +.sym 7359 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7368 rx_fifo.rd_addr[9] +.sym 7369 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7371 w_rx_fifo_pull +.sym 7376 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 7377 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 7378 channel +.sym 7379 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 7380 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[0] +.sym 7381 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 7382 w_rx_fifo_data[26] +.sym 7383 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 7392 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7393 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7395 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7396 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7397 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7398 rx_fifo.rd_addr[7] +.sym 7399 rx_fifo.rd_addr[8] +.sym 7400 rx_fifo.rd_addr[9] +.sym 7401 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7402 rx_fifo.rd_addr[0] .sym 7403 r_counter_$glb_clk -.sym 7404 io_pmod[1]$SB_IO_IN +.sym 7404 w_rx_fifo_pull .sym 7405 $PACKER_VCC_NET -.sym 7409 rx_fifo.mem_q.0.1_WDATA -.sym 7413 rx_fifo.mem_q.0.1_WDATA_1 -.sym 7421 i_rst_b$SB_IO_IN -.sym 7432 rx_fifo.rd_addr[2] -.sym 7446 rx_fifo.wr_addr[4] -.sym 7449 rx_fifo.wr_addr[7] -.sym 7450 $PACKER_VCC_NET -.sym 7451 rx_fifo.wr_addr[9] -.sym 7452 rx_fifo.wr_addr[6] -.sym 7455 rx_fifo.wr_addr[8] -.sym 7457 io_pmod[0]$SB_IO_IN -.sym 7458 rx_fifo.wr_addr[0] -.sym 7459 rx_fifo.wr_addr[1] -.sym 7460 rx_fifo.wr_addr[3] -.sym 7469 rx_fifo.wr_addr[5] -.sym 7471 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7473 rx_fifo.mem_q.0.2_WDATA_2 -.sym 7475 rx_fifo.wr_addr[2] -.sym 7478 w_rx_24_fifo_data[9] -.sym 7479 w_rx_24_fifo_data[15] -.sym 7480 w_rx_24_fifo_data[11] -.sym 7482 w_rx_24_fifo_data[13] -.sym 7483 w_rx_24_fifo_data[12] +.sym 7409 w_rx_fifo_data[23] +.sym 7413 w_rx_fifo_data[21] +.sym 7418 $PACKER_VCC_NET +.sym 7421 rx_fifo.rd_addr_gray_wr_r[3] +.sym 7422 rx_fifo.rd_addr[8] +.sym 7424 $PACKER_VCC_NET +.sym 7426 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7427 $PACKER_VCC_NET +.sym 7428 i_rst_b$SB_IO_IN +.sym 7429 w_rx_fifo_data[23] +.sym 7430 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 7431 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7432 w_rx_fifo_pulled_data[0] +.sym 7433 rx_fifo.rd_addr[0] +.sym 7434 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7435 w_lvds_rx_24_d1 +.sym 7437 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7438 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 7439 rx_fifo.rd_addr_gray_wr_r[2] +.sym 7441 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 7449 rx_fifo.wr_addr[5] +.sym 7452 rx_fifo.wr_addr[2] +.sym 7454 rx_fifo.wr_addr[3] +.sym 7456 rx_fifo.wr_addr[0] +.sym 7457 w_rx_fifo_data[24] +.sym 7458 rx_fifo.wr_addr[9] +.sym 7459 $PACKER_VCC_NET +.sym 7464 rx_fifo.wr_addr[8] +.sym 7465 rx_fifo.wr_addr[7] +.sym 7466 w_rx_fifo_data[26] +.sym 7468 rx_fifo.wr_addr[6] +.sym 7471 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7473 w_rx_fifo_push +.sym 7477 rx_fifo.wr_addr[4] +.sym 7478 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 7479 rx_fifo.wr_addr_gray_rd_r[9] +.sym 7480 rx_fifo.wr_addr_gray_rd[1] +.sym 7481 rx_fifo.wr_addr_gray_rd[3] +.sym 7482 rx_fifo.wr_addr_gray_rd[2] +.sym 7483 rx_fifo.wr_addr_gray_rd_r[2] +.sym 7484 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 7485 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] .sym 7494 rx_fifo.wr_addr[2] .sym 7495 rx_fifo.wr_addr[3] .sym 7497 rx_fifo.wr_addr[4] @@ -6117,5304 +6766,7978 @@ .sym 7500 rx_fifo.wr_addr[7] .sym 7501 rx_fifo.wr_addr[8] .sym 7502 rx_fifo.wr_addr[9] -.sym 7503 rx_fifo.wr_addr[1] +.sym 7503 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] .sym 7504 rx_fifo.wr_addr[0] -.sym 7505 lvds_clock_$glb_clk -.sym 7506 io_pmod[0]$SB_IO_IN -.sym 7508 rx_fifo.mem_q.0.2_WDATA_3 -.sym 7512 rx_fifo.mem_q.0.2_WDATA_2 +.sym 7505 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 7506 w_rx_fifo_push +.sym 7508 w_rx_fifo_data[24] +.sym 7512 w_rx_fifo_data[26] .sym 7515 $PACKER_VCC_NET -.sym 7531 w_rx_09_fifo_data[6] -.sym 7548 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 7549 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 7550 rx_fifo.mem_q.0.2_WDATA_1 +.sym 7521 spi_if_ins.w_rx_data[6] +.sym 7524 i_rst_b$SB_IO_IN +.sym 7526 rx_fifo.wr_addr[9] +.sym 7527 w_rx_09_fifo_data[26] +.sym 7528 smi_ctrl_ins.r_channel_SB_DFFE_Q_E +.sym 7529 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 7530 rx_fifo.wr_addr[3] +.sym 7531 channel +.sym 7532 channel +.sym 7534 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 7535 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 7536 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7538 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7539 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 7541 w_rx_fifo_push +.sym 7542 w_rx_fifo_pulled_data[3] .sym 7552 $PACKER_VCC_NET -.sym 7553 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 7554 rx_fifo.mem_q.0.2_WDATA -.sym 7556 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 7557 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7559 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 7560 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 7563 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 7565 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 7566 io_pmod[1]$SB_IO_IN -.sym 7570 rx_fifo.rd_addr[2] -.sym 7596 rx_fifo.rd_addr[2] -.sym 7597 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 7599 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 7600 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 7601 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 7602 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 7603 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 7604 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 7605 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 7606 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 7556 rx_fifo.rd_addr[9] +.sym 7558 rx_fifo.rd_addr[7] +.sym 7559 w_rx_fifo_pull +.sym 7561 w_rx_fifo_data[25] +.sym 7563 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7564 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7566 rx_fifo.rd_addr[8] +.sym 7568 w_rx_fifo_data[27] +.sym 7570 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7571 rx_fifo.rd_addr[0] +.sym 7572 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7575 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7578 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7580 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 7581 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[1] +.sym 7582 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[2] +.sym 7583 rx_fifo.rd_addr_gray[5] +.sym 7584 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3[2] +.sym 7585 rx_fifo.rd_addr_gray[4] +.sym 7586 rx_fifo.empty_o_SB_LUT4_I2_O[2] +.sym 7587 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 7596 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7597 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7599 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7600 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7601 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7602 rx_fifo.rd_addr[7] +.sym 7603 rx_fifo.rd_addr[8] +.sym 7604 rx_fifo.rd_addr[9] +.sym 7605 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7606 rx_fifo.rd_addr[0] .sym 7607 r_counter_$glb_clk -.sym 7608 io_pmod[1]$SB_IO_IN +.sym 7608 w_rx_fifo_pull .sym 7609 $PACKER_VCC_NET -.sym 7613 rx_fifo.mem_q.0.2_WDATA -.sym 7617 rx_fifo.mem_q.0.2_WDATA_1 -.sym 7623 io_pmod[0]$SB_IO_IN -.sym 7624 rx_fifo.mem_q.0.2_RDATA[0] -.sym 7629 w_rx_24_fifo_data[7] -.sym 7637 w_rx_24_fifo_data[10] -.sym 7729 o_rx_h_tx_l_b$SB_IO_OUT -.sym 7734 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 7839 o_shdn_rx_lna$SB_IO_OUT +.sym 7613 w_rx_fifo_data[27] +.sym 7617 w_rx_fifo_data[25] +.sym 7623 w_cs[3] +.sym 7624 rx_fifo.rd_addr[7] +.sym 7631 w_cs[2] +.sym 7632 rx_fifo.rd_addr[9] +.sym 7633 w_cs[1] +.sym 7634 $PACKER_VCC_NET +.sym 7635 rx_fifo.rd_addr[0] +.sym 7636 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7638 $PACKER_VCC_NET +.sym 7639 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7641 w_rx_fifo_pulled_data[1] +.sym 7643 rx_fifo.rd_addr[0] +.sym 7644 rx_fifo.wr_addr[0] +.sym 7652 w_rx_fifo_data[0] +.sym 7654 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7655 rx_fifo.wr_addr[3] +.sym 7656 rx_fifo.wr_addr[8] +.sym 7657 rx_fifo.wr_addr[5] +.sym 7659 rx_fifo.wr_addr[2] +.sym 7660 rx_fifo.wr_addr[7] +.sym 7661 w_rx_fifo_data[2] +.sym 7663 $PACKER_VCC_NET +.sym 7665 rx_fifo.wr_addr[4] +.sym 7668 w_rx_fifo_push +.sym 7669 rx_fifo.wr_addr[0] +.sym 7674 rx_fifo.wr_addr[9] +.sym 7675 rx_fifo.wr_addr[6] +.sym 7682 rx_fifo.wr_addr_gray_rd[4] +.sym 7683 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 7684 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[3] +.sym 7685 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 7686 w_rx_fifo_push +.sym 7687 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 7688 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[0] +.sym 7689 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[2] +.sym 7698 rx_fifo.wr_addr[2] +.sym 7699 rx_fifo.wr_addr[3] +.sym 7701 rx_fifo.wr_addr[4] +.sym 7702 rx_fifo.wr_addr[5] +.sym 7703 rx_fifo.wr_addr[6] +.sym 7704 rx_fifo.wr_addr[7] +.sym 7705 rx_fifo.wr_addr[8] +.sym 7706 rx_fifo.wr_addr[9] +.sym 7707 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7708 rx_fifo.wr_addr[0] +.sym 7709 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 7710 w_rx_fifo_push +.sym 7712 w_rx_fifo_data[0] +.sym 7716 w_rx_fifo_data[2] +.sym 7719 $PACKER_VCC_NET +.sym 7724 w_cs[1] +.sym 7726 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 7729 $PACKER_VCC_NET +.sym 7734 i_smi_a2$SB_IO_IN +.sym 7737 w_rx_fifo_push +.sym 7738 w_rx_fifo_pull +.sym 7740 rx_fifo.rd_addr[9] +.sym 7742 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7743 w_rx_fifo_push +.sym 7745 w_rx_fifo_data[9] +.sym 7752 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7754 rx_fifo.rd_addr[8] +.sym 7756 w_rx_fifo_data[3] +.sym 7757 rx_fifo.rd_addr[9] +.sym 7761 w_rx_fifo_data[1] +.sym 7763 w_rx_fifo_pull +.sym 7765 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7766 rx_fifo.rd_addr[7] +.sym 7772 $PACKER_VCC_NET +.sym 7773 rx_fifo.rd_addr[0] +.sym 7774 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7776 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7777 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7782 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7785 rx_fifo.wr_addr_gray_rd[9] +.sym 7786 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 7787 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 7788 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 7789 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 7790 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 7800 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7801 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7803 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7804 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7805 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7806 rx_fifo.rd_addr[7] +.sym 7807 rx_fifo.rd_addr[8] +.sym 7808 rx_fifo.rd_addr[9] +.sym 7809 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7810 rx_fifo.rd_addr[0] +.sym 7811 r_counter_$glb_clk +.sym 7812 w_rx_fifo_pull +.sym 7813 $PACKER_VCC_NET +.sym 7817 w_rx_fifo_data[3] +.sym 7821 w_rx_fifo_data[1] +.sym 7834 rx_fifo.wr_addr[2] +.sym 7839 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7842 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7847 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7857 rx_fifo.wr_addr[3] +.sym 7860 w_rx_fifo_data[8] +.sym 7861 rx_fifo.wr_addr[5] +.sym 7863 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7864 rx_fifo.wr_addr[7] +.sym 7865 rx_fifo.wr_addr[2] +.sym 7867 $PACKER_VCC_NET +.sym 7869 rx_fifo.wr_addr[4] +.sym 7870 w_rx_fifo_data[10] +.sym 7872 rx_fifo.wr_addr[8] +.sym 7878 rx_fifo.wr_addr[9] +.sym 7879 rx_fifo.wr_addr[6] +.sym 7881 w_rx_fifo_push +.sym 7884 rx_fifo.wr_addr[0] +.sym 7888 rx_fifo.wr_addr_gray_rd[7] +.sym 7889 rx_fifo.wr_addr_gray_rd[6] +.sym 7890 rx_fifo.wr_addr_gray_rd[0] +.sym 7891 rx_fifo.wr_addr_gray_rd[8] +.sym 7902 rx_fifo.wr_addr[2] +.sym 7903 rx_fifo.wr_addr[3] +.sym 7905 rx_fifo.wr_addr[4] +.sym 7906 rx_fifo.wr_addr[5] +.sym 7907 rx_fifo.wr_addr[6] +.sym 7908 rx_fifo.wr_addr[7] +.sym 7909 rx_fifo.wr_addr[8] +.sym 7910 rx_fifo.wr_addr[9] +.sym 7911 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7912 rx_fifo.wr_addr[0] +.sym 7913 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 7914 w_rx_fifo_push +.sym 7916 w_rx_fifo_data[8] +.sym 7920 w_rx_fifo_data[10] +.sym 7923 $PACKER_VCC_NET +.sym 7930 rx_fifo.wr_addr[9] +.sym 7940 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7949 o_shdn_rx_lna$SB_IO_OUT +.sym 7960 $PACKER_VCC_NET +.sym 7964 rx_fifo.rd_addr[9] +.sym 7965 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 7967 w_rx_fifo_pull +.sym 7968 rx_fifo.rd_addr[7] +.sym 7971 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 7972 w_rx_fifo_data[9] +.sym 7976 rx_fifo.rd_addr[8] +.sym 7978 w_rx_fifo_data[11] +.sym 7980 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 7982 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 7983 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 7985 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 7986 rx_fifo.rd_addr[0] +.sym 8000 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 8001 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 8003 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 8004 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 8005 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 8006 rx_fifo.rd_addr[7] +.sym 8007 rx_fifo.rd_addr[8] +.sym 8008 rx_fifo.rd_addr[9] +.sym 8009 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 8010 rx_fifo.rd_addr[0] +.sym 8011 r_counter_$glb_clk +.sym 8012 w_rx_fifo_pull +.sym 8013 $PACKER_VCC_NET +.sym 8017 w_rx_fifo_data[11] +.sym 8021 w_rx_fifo_data[9] +.sym 8048 rx_fifo.rd_addr[0] .sym 8093 w_smi_data_output[6] -.sym 8095 i_smi_a2$rename$0 -.sym 8105 i_smi_a2$rename$0 -.sym 8108 w_smi_data_output[6] -.sym 8128 rx_fifo.rd_addr_gray_wr_r[5] -.sym 8129 i_smi_a2$rename$0 -.sym 8142 io_pmod[0]$SB_IO_IN -.sym 8152 w_smi_data_output[1] -.sym 8166 rx_fifo.rd_addr_gray[6] -.sym 8167 rx_fifo.rd_addr_gray[5] -.sym 8168 rx_fifo.rd_addr_gray[2] -.sym 8169 rx_fifo.rd_addr_gray_wr[2] -.sym 8175 rx_fifo.rd_addr_gray_wr[5] -.sym 8176 rx_fifo.rd_addr_gray_wr[6] -.sym 8195 rx_fifo.rd_addr_gray[6] -.sym 8201 rx_fifo.rd_addr_gray[2] -.sym 8212 rx_fifo.rd_addr_gray_wr[2] -.sym 8217 rx_fifo.rd_addr_gray_wr[6] -.sym 8224 rx_fifo.rd_addr_gray_wr[5] -.sym 8235 rx_fifo.rd_addr_gray[5] -.sym 8240 lvds_clock_$glb_clk -.sym 8246 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[2] -.sym 8247 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 8248 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 8249 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 8250 rx_fifo.rd_addr_gray[0] -.sym 8251 rx_fifo.rd_addr[2] -.sym 8252 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 8253 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 8259 w_smi_data_output[6] -.sym 8286 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 8288 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 8294 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8308 rx_fifo.rd_addr_gray_wr_r[5] -.sym 8311 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 8312 w_smi_data_output[2] -.sym 8329 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 8332 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 8333 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 8341 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8342 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 8343 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 8347 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 8350 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8351 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 8352 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8353 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 8358 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 8365 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8374 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 8375 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 8376 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 8377 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 8381 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 8382 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8386 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 8388 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 8392 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 8398 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 8402 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8403 r_counter_$glb_clk -.sym 8404 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8406 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 8407 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8408 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 8409 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 8410 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8411 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 8412 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8414 rx_fifo.rd_addr[2] -.sym 8415 rx_fifo.rd_addr[2] -.sym 8426 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 8428 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 8429 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 8430 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 8436 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8439 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 8440 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 8449 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 8455 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 8457 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 8458 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 8459 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 8460 rx_fifo.wr_addr_gray_rd[4] -.sym 8461 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 8463 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 8468 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 8469 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8472 rx_fifo.wr_addr_gray_rd[1] -.sym 8474 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 8475 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8476 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 8485 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 8488 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8491 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 8493 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 8497 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 8498 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 8499 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 8500 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 8504 rx_fifo.wr_addr_gray_rd[1] -.sym 8509 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 8510 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 8511 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 8512 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 8515 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 8518 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8521 rx_fifo.wr_addr_gray_rd[4] -.sym 8526 r_counter_$glb_clk -.sym 8528 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8529 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 8530 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 8531 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 8532 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 8533 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 8534 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 8535 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 8542 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 8550 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 8552 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8558 smi_ctrl_ins.int_cnt_SB_DFFNESS_Q_E -.sym 8560 smi_ctrl_ins.int_cnt[3] -.sym 8561 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 8563 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 8571 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 8572 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 8574 io_pmod[1]$SB_IO_IN -.sym 8576 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8577 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[3] -.sym 8578 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 8579 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8581 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 8582 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 8583 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 8584 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 8585 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8587 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[0] -.sym 8588 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 8589 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 8591 rx_fifo.wr_addr_gray_rd[7] -.sym 8595 rx_fifo.wr_addr_gray_rd[5] -.sym 8597 rx_fifo.wr_addr_gray_rd[6] -.sym 8599 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 8602 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 8603 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 8605 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 8608 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 8609 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 8610 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8611 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 8615 rx_fifo.wr_addr_gray_rd[5] -.sym 8620 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 8621 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8622 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8626 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[0] -.sym 8627 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 8628 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 8629 io_pmod[1]$SB_IO_IN -.sym 8634 rx_fifo.wr_addr_gray_rd[6] -.sym 8640 rx_fifo.wr_addr_gray_rd[7] -.sym 8644 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[3] -.sym 8645 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 8646 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 8647 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[0] -.sym 8649 r_counter_$glb_clk -.sym 8651 smi_ctrl_ins.int_cnt[4] -.sym 8652 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 8653 smi_ctrl_ins.int_cnt[3] -.sym 8654 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[1] -.sym 8655 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8657 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 8658 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[0] -.sym 8663 w_smi_data_output[1] -.sym 8666 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 8668 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 8678 channel -.sym 8684 smi_ctrl_ins.int_cnt[4] -.sym 8693 rx_fifo.wr_addr_gray_rd_r[8] -.sym 8694 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 8695 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 8696 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 8697 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 8699 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 8700 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8701 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 8703 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8705 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 8706 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8710 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 8712 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8725 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 8731 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 8738 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8739 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 8743 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8745 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 8752 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8755 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 8756 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 8757 rx_fifo.wr_addr_gray_rd_r[8] -.sym 8758 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 8761 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8763 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 8767 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 8768 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 8769 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 8771 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8772 r_counter_$glb_clk +.sym 8095 i_smi_a2$SB_IO_IN +.sym 8099 $PACKER_VCC_NET +.sym 8104 w_smi_data_output[6] +.sym 8107 i_smi_a2$SB_IO_IN +.sym 8112 $PACKER_VCC_NET +.sym 8119 smi_ctrl_ins.r_fifo_pushed_data[11] +.sym 8121 smi_ctrl_ins.r_fifo_pushed_data[8] +.sym 8122 smi_ctrl_ins.r_fifo_pushed_data[9] +.sym 8123 smi_ctrl_ins.r_fifo_pushed_data[14] +.sym 8125 smi_ctrl_ins.r_fifo_pushed_data[10] +.sym 8130 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 8132 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 8134 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 8136 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 8140 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 8142 w_rx_fifo_data[9] +.sym 8150 w_smi_data_input[6] +.sym 8151 $PACKER_VCC_NET +.sym 8152 i_smi_a2$SB_IO_IN +.sym 8242 w_smi_data_input[2] +.sym 8244 w_smi_data_input[1] +.sym 8248 smi_ctrl_ins.r_fifo_pushed_data[25] +.sym 8249 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 8250 smi_ctrl_ins.r_fifo_pushed_data[29] +.sym 8253 smi_ctrl_ins.r_fifo_pushed_data[26] +.sym 8269 w_smi_data_output[6] +.sym 8271 w_smi_data_input[3] +.sym 8286 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 8287 w_smi_data_input[2] +.sym 8288 w_smi_data_input[3] +.sym 8289 w_tx_fifo_data[26] +.sym 8291 w_smi_data_input[1] +.sym 8294 w_rx_24_fifo_data[13] +.sym 8300 w_smi_data_input[1] +.sym 8305 w_smi_data_input[2] +.sym 8306 w_smi_data_output[1] +.sym 8309 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 8312 w_rx_fifo_empty +.sym 8314 i_smi_a2$SB_IO_IN +.sym 8317 w_smi_data_output[2] +.sym 8324 channel +.sym 8326 w_rx_24_fifo_data[14] +.sym 8327 w_rx_24_fifo_data[15] +.sym 8328 smi_ctrl_ins.r_fifo_pushed_data[14] +.sym 8332 channel +.sym 8339 w_rx_09_fifo_data[12] +.sym 8341 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 8343 w_rx_09_fifo_data[14] +.sym 8347 w_rx_24_fifo_data[12] +.sym 8349 w_rx_09_fifo_data[15] +.sym 8350 w_rx_24_fifo_data[13] +.sym 8352 w_rx_09_fifo_data[13] +.sym 8354 smi_ctrl_ins.r_fifo_pushed_data[26] +.sym 8362 channel +.sym 8363 w_rx_24_fifo_data[13] +.sym 8365 w_rx_09_fifo_data[13] +.sym 8371 smi_ctrl_ins.r_fifo_pushed_data[14] +.sym 8374 w_rx_24_fifo_data[12] +.sym 8375 w_rx_09_fifo_data[12] +.sym 8377 channel +.sym 8380 w_rx_09_fifo_data[14] +.sym 8381 w_rx_24_fifo_data[14] +.sym 8382 channel +.sym 8386 w_rx_09_fifo_data[15] +.sym 8388 channel +.sym 8389 w_rx_24_fifo_data[15] +.sym 8401 smi_ctrl_ins.r_fifo_pushed_data[26] +.sym 8402 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 8403 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 8404 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O_$glb_sr +.sym 8405 smi_ctrl_ins.r_fifo_pushed_data[28] +.sym 8407 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 8408 smi_ctrl_ins.r_fifo_pushed_data[27] +.sym 8410 smi_ctrl_ins.r_fifo_pushed_data[31] +.sym 8411 o_smi_read_req$SB_IO_OUT +.sym 8415 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 8422 w_rx_24_fifo_data[14] +.sym 8428 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 8431 w_tx_fifo_full +.sym 8434 w_rx_24_fifo_data[28] +.sym 8436 i_smi_a2$SB_IO_IN +.sym 8438 w_rx_24_fifo_data[6] +.sym 8446 w_rx_24_fifo_data[4] +.sym 8447 w_rx_fifo_pulled_data[4] +.sym 8458 channel +.sym 8459 w_rx_fifo_pulled_data[6] +.sym 8462 w_rx_24_fifo_data[6] +.sym 8463 w_rx_fifo_pulled_data[5] +.sym 8464 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 8468 w_rx_24_fifo_data[5] +.sym 8470 w_rx_09_fifo_data[6] +.sym 8476 w_rx_09_fifo_data[4] +.sym 8477 w_rx_09_fifo_data[5] +.sym 8481 w_rx_fifo_pulled_data[6] +.sym 8485 w_rx_09_fifo_data[6] +.sym 8487 channel +.sym 8488 w_rx_24_fifo_data[6] +.sym 8499 w_rx_fifo_pulled_data[4] +.sym 8503 w_rx_24_fifo_data[4] +.sym 8504 channel +.sym 8506 w_rx_09_fifo_data[4] +.sym 8509 w_rx_fifo_pulled_data[5] +.sym 8522 w_rx_24_fifo_data[5] +.sym 8523 channel +.sym 8524 w_rx_09_fifo_data[5] +.sym 8525 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 8526 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8527 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8528 w_tx_fifo_data[31] +.sym 8529 w_tx_fifo_data[4] +.sym 8530 w_tx_fifo_data[22] +.sym 8531 w_tx_fifo_data[1] +.sym 8532 w_tx_fifo_data[2] +.sym 8533 w_tx_fifo_data[20] +.sym 8535 w_tx_fifo_data[18] +.sym 8540 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] +.sym 8541 o_smi_read_req$SB_IO_OUT +.sym 8542 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] +.sym 8543 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 8544 w_smi_data_input[6] +.sym 8546 channel +.sym 8548 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] +.sym 8554 w_rx_24_fifo_data[5] +.sym 8555 w_rx_fifo_full +.sym 8559 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 8560 rx_fifo.rd_addr[7] +.sym 8561 tx_fifo.rd_addr[1] +.sym 8563 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 8571 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 8574 w_rx_24_fifo_data[9] +.sym 8584 w_rx_09_fifo_data[9] +.sym 8586 channel +.sym 8590 w_smi_data_input[0] +.sym 8603 w_rx_24_fifo_data[9] +.sym 8604 w_rx_09_fifo_data[9] +.sym 8605 channel +.sym 8620 w_smi_data_input[0] +.sym 8648 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 8649 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 8650 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8651 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 8652 lvds_tx_inst.r_phase_count[1] +.sym 8654 w_tx_fifo_empty +.sym 8655 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 8656 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 8658 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 8661 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 8664 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.sym 8666 w_rx_24_fifo_data[11] +.sym 8667 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 8672 w_rx_24_fifo_data[12] +.sym 8675 w_rx_09_fifo_data[11] +.sym 8677 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 8678 w_rx_24_fifo_data[30] +.sym 8681 w_rx_fifo_full +.sym 8682 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 8684 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 8685 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 8694 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 8695 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 8698 lvds_tx_inst.r_phase_count[3] +.sym 8699 $PACKER_VCC_NET +.sym 8700 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 8701 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 8704 w_rx_24_fifo_data[28] +.sym 8707 $PACKER_VCC_NET +.sym 8708 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 8709 lvds_tx_inst.r_phase_count[1] +.sym 8710 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 8712 channel +.sym 8714 w_rx_09_fifo_data[28] +.sym 8717 lvds_tx_inst.r_phase_count[1] +.sym 8720 lvds_tx_inst.r_phase_count[2] +.sym 8722 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 8724 $nextpnr_ICESTORM_LC_6$O +.sym 8726 lvds_tx_inst.r_phase_count[1] +.sym 8730 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 8732 $PACKER_VCC_NET +.sym 8733 lvds_tx_inst.r_phase_count[2] +.sym 8734 lvds_tx_inst.r_phase_count[1] +.sym 8736 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO[3] +.sym 8738 $PACKER_VCC_NET +.sym 8739 lvds_tx_inst.r_phase_count[3] +.sym 8740 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 8744 $PACKER_VCC_NET +.sym 8745 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 8746 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO[3] +.sym 8751 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 8756 channel +.sym 8757 w_rx_24_fifo_data[28] +.sym 8758 w_rx_09_fifo_data[28] +.sym 8763 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 8767 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 8768 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 8769 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 8770 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 8772 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 8773 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 8774 rx_fifo.rd_addr_gray_wr[8] -.sym 8775 smi_ctrl_ins.int_cnt_SB_DFFNESS_Q_E -.sym 8777 rx_fifo.rd_addr_gray_wr_r[0] -.sym 8778 rx_fifo.rd_addr_gray_wr_r[8] -.sym 8780 rx_fifo.rd_addr_gray_wr[0] -.sym 8794 w_rx_09_fifo_data[19] -.sym 8798 smi_ctrl_ins.int_cnt[3] -.sym 8801 $PACKER_VCC_NET -.sym 8802 io_pmod[1]$SB_IO_IN -.sym 8803 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 8804 rx_fifo.wr_addr_gray_rd[8] -.sym 8807 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 8808 rx_fifo.mem_i.0.0_RDATA[1] -.sym 8816 rx_fifo.wr_addr_gray_rd[9] -.sym 8819 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8822 rx_fifo.wr_addr_gray_rd[8] -.sym 8828 w_rx_24_fifo_data[18] -.sym 8829 w_rx_24_fifo_data[19] -.sym 8831 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 8835 w_rx_09_fifo_data[19] -.sym 8838 channel -.sym 8843 w_rx_09_fifo_data[18] -.sym 8848 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 8849 channel -.sym 8850 w_rx_24_fifo_data[18] -.sym 8851 w_rx_09_fifo_data[18] -.sym 8854 rx_fifo.wr_addr_gray_rd[8] -.sym 8860 w_rx_09_fifo_data[19] -.sym 8861 channel -.sym 8862 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 8863 w_rx_24_fifo_data[19] -.sym 8869 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 8878 rx_fifo.wr_addr_gray_rd[9] +.sym 8774 tx_fifo.rd_addr[0] +.sym 8775 tx_fifo.rd_addr[5] +.sym 8776 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 8777 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 8778 tx_fifo.rd_addr[1] +.sym 8779 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] +.sym 8780 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 8781 tx_fifo.rd_addr[2] +.sym 8785 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 8788 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 8789 w_tx_fifo_empty +.sym 8790 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 8791 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 8792 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 8798 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] +.sym 8799 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 8800 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] +.sym 8801 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 8803 channel +.sym 8804 w_rx_fifo_empty +.sym 8806 smi_ctrl_ins.w_fifo_pull_trigger +.sym 8807 tx_fifo.rd_addr[0] +.sym 8808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.sym 8816 channel +.sym 8817 smi_ctrl_ins.w_fifo_pull_trigger +.sym 8819 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 8820 w_rx_24_fifo_data[3] +.sym 8828 w_rx_09_fifo_data[3] +.sym 8830 w_rx_fifo_empty +.sym 8833 smi_ctrl_ins.r_fifo_pull_1 +.sym 8835 w_rx_fifo_pull +.sym 8837 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 8838 w_rx_24_fifo_data[30] +.sym 8839 smi_ctrl_ins.r_fifo_pull +.sym 8841 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 8845 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 8846 w_rx_09_fifo_data[30] +.sym 8850 smi_ctrl_ins.w_fifo_pull_trigger +.sym 8863 smi_ctrl_ins.r_fifo_pull +.sym 8869 w_rx_fifo_pull +.sym 8872 w_rx_fifo_empty +.sym 8873 smi_ctrl_ins.r_fifo_pull +.sym 8874 smi_ctrl_ins.r_fifo_pull_1 +.sym 8878 w_rx_24_fifo_data[30] +.sym 8879 w_rx_09_fifo_data[30] +.sym 8880 channel +.sym 8885 channel +.sym 8886 w_rx_09_fifo_data[3] +.sym 8887 w_rx_24_fifo_data[3] +.sym 8890 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 8891 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 8892 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 8893 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] .sym 8895 r_counter_$glb_clk -.sym 8900 rx_fifo.mem_i.0.0_RDATA[1] -.sym 8905 i_smi_a2$rename$0 -.sym 8919 rx_fifo.mem_q.0.0_RDATA[1] -.sym 8925 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 8926 i_rst_b$SB_IO_IN -.sym 8927 w_rx_09_fifo_data[27] -.sym 8928 smi_ctrl_ins.int_cnt[4] -.sym 8929 w_rx_24_fifo_data[20] -.sym 8930 w_rx_09_fifo_data[18] -.sym 8939 w_rx_24_fifo_data[17] -.sym 8942 w_rx_24_fifo_data[27] -.sym 8945 w_rx_24_fifo_data[15] -.sym 8950 channel +.sym 8896 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 8898 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 8899 w_fetch +.sym 8900 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 8902 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 8903 lvds_tx_inst.r_phase_count_SB_LUT4_I1_1_O_SB_DFFSR_D_Q_SB_LUT4_I3_O[1] +.sym 8904 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[1] +.sym 8907 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 8908 w_rx_fifo_push +.sym 8909 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[0] +.sym 8910 w_rx_fifo_push +.sym 8912 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 8916 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 8917 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 8919 w_rx_fifo_pull +.sym 8921 w_rx_24_fifo_data[28] +.sym 8923 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 8924 w_rx_09_fifo_data[22] +.sym 8925 w_rx_24_fifo_data[6] +.sym 8929 w_tx_fifo_full +.sym 8931 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 8932 w_rx_fifo_empty +.sym 8938 w_rx_24_fifo_data[16] +.sym 8939 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[1] +.sym 8940 i_rst_b$SB_IO_IN +.sym 8941 w_rx_24_fifo_data[24] +.sym 8942 channel +.sym 8943 w_rx_09_fifo_data[16] +.sym 8944 w_rx_24_fifo_data[20] +.sym 8946 w_rx_24_fifo_data[11] +.sym 8947 w_rx_09_fifo_data[11] +.sym 8948 w_rx_09_fifo_data[22] +.sym 8950 w_rx_24_fifo_data[22] .sym 8951 w_rx_09_fifo_data[17] -.sym 8953 w_rx_24_fifo_data[16] -.sym 8955 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 8958 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 8962 w_rx_24_fifo_data[14] -.sym 8967 w_rx_24_fifo_data[18] -.sym 8968 w_rx_09_fifo_data[16] -.sym 8972 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 8973 w_rx_24_fifo_data[18] -.sym 8977 w_rx_24_fifo_data[15] -.sym 8979 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 8983 w_rx_24_fifo_data[27] -.sym 8986 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 8989 w_rx_24_fifo_data[17] -.sym 8990 w_rx_09_fifo_data[17] -.sym 8991 channel -.sym 8992 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 8995 w_rx_24_fifo_data[16] -.sym 8996 channel -.sym 8997 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 8998 w_rx_09_fifo_data[16] -.sym 9001 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9004 w_rx_24_fifo_data[16] -.sym 9008 w_rx_24_fifo_data[17] -.sym 9010 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9013 w_rx_24_fifo_data[14] -.sym 9015 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9017 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 9018 lvds_clock_$glb_clk -.sym 9019 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 9020 w_rx_09_fifo_data[30] -.sym 9021 w_rx_09_fifo_data[28] -.sym 9022 w_rx_09_fifo_data[26] -.sym 9023 w_rx_09_fifo_data[29] -.sym 9024 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9025 w_rx_24_fifo_data[29] -.sym 9026 w_rx_09_fifo_data[16] -.sym 9027 lvds_rx_09_inst.o_fifo_data[31] -.sym 9032 w_rx_24_fifo_data[20] -.sym 9035 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9036 w_debug_smi_test -.sym 9041 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 9045 w_rx_24_fifo_data[29] -.sym 9046 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 9048 w_rx_24_fifo_data[14] -.sym 9050 w_rx_24_fifo_data[7] -.sym 9052 smi_ctrl_ins.int_cnt[3] -.sym 9074 w_rx_09_fifo_data[17] -.sym 9080 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9088 w_rx_09_fifo_data[15] -.sym 9091 w_rx_09_fifo_data[16] -.sym 9107 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9109 w_rx_09_fifo_data[16] -.sym 9124 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9127 w_rx_09_fifo_data[15] -.sym 9130 w_rx_09_fifo_data[17] -.sym 9133 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9140 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 9141 lvds_clock_$glb_clk -.sym 9142 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 9143 w_rx_24_fifo_data[14] -.sym 9144 rx_fifo.mem_i.0.3_WDATA_3 -.sym 9145 rx_fifo.mem_i.0.3_WDATA_2 -.sym 9146 w_rx_24_fifo_data[28] -.sym 9147 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] -.sym 9148 w_rx_24_fifo_data[30] -.sym 9149 w_rx_24_fifo_data[31] -.sym 9150 rx_fifo.mem_i.0.3_WDATA -.sym 9152 $PACKER_VCC_NET -.sym 9169 channel -.sym 9171 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9173 rx_fifo.mem_q.0.0_RDATA_2[1] -.sym 9174 w_rx_09_fifo_data[15] -.sym 9175 channel -.sym 9176 smi_ctrl_ins.int_cnt[4] -.sym 9186 channel -.sym 9187 channel -.sym 9188 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9195 rx_fifo.mem_q.0.0_RDATA_3[0] -.sym 9197 rx_fifo.mem_q.0.1_RDATA_2[1] -.sym 9198 w_rx_09_fifo_data[15] -.sym 9201 rx_fifo.mem_q.0.1_RDATA_1[1] -.sym 9205 rx_fifo.mem_q.0.1_RDATA[1] -.sym 9206 w_rx_09_fifo_data[7] -.sym 9207 w_rx_24_fifo_data[15] -.sym 9210 w_rx_24_fifo_data[7] -.sym 9211 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 9213 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9217 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9219 rx_fifo.mem_q.0.0_RDATA_3[0] -.sym 9229 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9230 rx_fifo.mem_q.0.1_RDATA[1] -.sym 9235 w_rx_24_fifo_data[7] -.sym 9236 w_rx_09_fifo_data[7] -.sym 9237 channel -.sym 9238 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9241 rx_fifo.mem_q.0.1_RDATA_2[1] -.sym 9243 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9248 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9249 rx_fifo.mem_q.0.1_RDATA_1[1] -.sym 9253 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9254 w_rx_09_fifo_data[15] -.sym 9255 channel -.sym 9256 w_rx_24_fifo_data[15] -.sym 9263 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 9264 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 8952 w_rx_24_fifo_data[21] +.sym 8953 w_rx_09_fifo_data[21] +.sym 8954 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 8955 w_rx_09_fifo_data[24] +.sym 8959 w_rx_24_fifo_data[17] +.sym 8967 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[0] +.sym 8968 w_rx_09_fifo_data[20] +.sym 8971 channel +.sym 8972 w_rx_24_fifo_data[22] +.sym 8974 w_rx_09_fifo_data[22] +.sym 8977 w_rx_24_fifo_data[17] +.sym 8978 w_rx_09_fifo_data[17] +.sym 8980 channel +.sym 8983 channel +.sym 8984 w_rx_09_fifo_data[16] +.sym 8985 w_rx_24_fifo_data[16] +.sym 8989 w_rx_24_fifo_data[21] +.sym 8990 channel +.sym 8992 w_rx_09_fifo_data[21] +.sym 8995 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 8996 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[1] +.sym 8997 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[0] +.sym 9002 channel +.sym 9003 w_rx_24_fifo_data[11] +.sym 9004 w_rx_09_fifo_data[11] +.sym 9007 channel +.sym 9008 w_rx_09_fifo_data[20] +.sym 9009 w_rx_24_fifo_data[20] +.sym 9013 w_rx_09_fifo_data[24] +.sym 9015 w_rx_24_fifo_data[24] +.sym 9016 channel +.sym 9017 i_rst_b$SB_IO_IN +.sym 9018 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 9020 w_rx_24_fifo_data[6] +.sym 9022 w_rx_24_fifo_data[19] +.sym 9023 w_rx_24_fifo_data[23] +.sym 9025 w_rx_24_fifo_data[17] +.sym 9027 w_rx_24_fifo_data[31] +.sym 9032 w_rx_24_fifo_data[16] +.sym 9035 $PACKER_VCC_NET +.sym 9037 w_rx_24_fifo_data[24] +.sym 9038 channel +.sym 9039 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] +.sym 9040 w_rx_24_fifo_data[20] +.sym 9041 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 9042 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] +.sym 9043 w_fetch +.sym 9044 w_fetch +.sym 9046 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 9047 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 9051 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9055 w_rx_fifo_full +.sym 9062 w_rx_fifo_pulled_data[17] +.sym 9067 w_rx_24_fifo_data[25] +.sym 9072 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 9075 w_rx_fifo_pulled_data[0] +.sym 9078 channel +.sym 9080 w_rx_fifo_pulled_data[21] +.sym 9081 w_rx_09_fifo_data[25] +.sym 9086 w_rx_fifo_pulled_data[16] +.sym 9089 w_rx_fifo_pulled_data[1] +.sym 9090 w_rx_fifo_pulled_data[18] +.sym 9092 w_rx_fifo_pulled_data[3] +.sym 9094 w_rx_fifo_pulled_data[16] +.sym 9100 w_rx_fifo_pulled_data[1] +.sym 9108 w_rx_fifo_pulled_data[3] +.sym 9113 w_rx_24_fifo_data[25] +.sym 9114 channel +.sym 9115 w_rx_09_fifo_data[25] +.sym 9121 w_rx_fifo_pulled_data[0] +.sym 9126 w_rx_fifo_pulled_data[21] +.sym 9130 w_rx_fifo_pulled_data[18] +.sym 9136 w_rx_fifo_pulled_data[17] +.sym 9140 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 9141 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 9142 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 9144 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9145 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9146 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 9147 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 9148 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 9149 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 9150 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 9153 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 9158 w_rx_24_fifo_data[23] +.sym 9159 tx_fifo.rd_addr_gray_wr_r[7] +.sym 9161 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.sym 9165 w_rx_24_fifo_data[21] +.sym 9166 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 9169 w_rx_fifo_full +.sym 9170 spi_if_ins.state_if[1] +.sym 9171 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 9172 spi_if_ins.state_if[0] +.sym 9173 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 9176 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 9177 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 9178 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 9188 rx_fifo.rd_addr[0] +.sym 9197 w_rx_fifo_pull +.sym 9201 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9202 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9204 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9205 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 9210 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9211 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 9212 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 9218 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9226 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 9229 w_rx_fifo_pull +.sym 9230 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9231 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9232 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9235 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9237 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9243 rx_fifo.rd_addr[0] +.sym 9247 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 9255 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 9256 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9261 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 9263 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9264 r_counter_$glb_clk .sym 9265 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9266 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 9269 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] -.sym 9271 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 9272 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] -.sym 9279 lvds_clock -.sym 9286 w_rx_24_fifo_data[26] -.sym 9288 w_tx_data_sys[0] -.sym 9293 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 9296 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9298 smi_ctrl_ins.int_cnt[3] -.sym 9299 rx_fifo.mem_q.0.3_WDATA -.sym 9300 w_rx_24_fifo_data[12] -.sym 9307 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9318 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 9324 rx_fifo.mem_q.0.2_RDATA_3[0] -.sym 9326 rx_fifo.mem_q.0.2_RDATA_1[0] -.sym 9328 rx_fifo.mem_q.0.2_RDATA_2[0] -.sym 9359 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9360 rx_fifo.mem_q.0.2_RDATA_2[0] -.sym 9366 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9367 rx_fifo.mem_q.0.2_RDATA_3[0] -.sym 9382 rx_fifo.mem_q.0.2_RDATA_1[0] -.sym 9383 rx_fifo.mem_i.0.0_RDATA[1] -.sym 9386 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 9387 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 9266 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 9267 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 9268 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 9269 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9270 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 9271 rx_fifo.rd_addr[8] +.sym 9272 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 9273 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 9278 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 9283 w_rx_24_fifo_data[25] +.sym 9288 rx_fifo.rd_addr[0] +.sym 9289 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 9290 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9291 rx_fifo.rd_addr[9] +.sym 9292 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 9293 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 9294 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 9296 rx_fifo.wr_addr_gray_rd[6] +.sym 9297 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 9299 channel +.sym 9300 rx_fifo.wr_addr_gray_rd_r[2] +.sym 9301 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 9307 rx_fifo.wr_addr_gray_rd_r[2] +.sym 9308 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9309 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9310 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 9311 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[0] +.sym 9312 rx_fifo.rd_addr[0] +.sym 9313 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 9317 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[1] +.sym 9318 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 9319 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 9320 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 9321 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] +.sym 9324 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 9325 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 9327 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9328 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[2] +.sym 9333 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 9336 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 9338 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[3] +.sym 9340 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 9341 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 9343 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 9346 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[1] +.sym 9347 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[3] +.sym 9348 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[2] +.sym 9349 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[0] +.sym 9352 rx_fifo.wr_addr_gray_rd_r[2] +.sym 9354 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 9361 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 9365 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 9367 rx_fifo.rd_addr[0] +.sym 9370 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 9371 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9372 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 9373 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 9378 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 9379 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 9382 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 9383 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 9384 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] +.sym 9386 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 9387 r_counter_$glb_clk .sym 9388 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 9389 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] -.sym 9391 w_rx_09_fifo_data[12] -.sym 9392 w_rx_09_fifo_data[15] -.sym 9393 w_rx_09_fifo_data[14] -.sym 9395 w_rx_09_fifo_data[13] -.sym 9396 w_rx_09_fifo_data[10] -.sym 9404 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] -.sym 9413 i_rst_b$SB_IO_IN -.sym 9416 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9423 w_rx_09_fifo_data[7] -.sym 9430 w_rx_24_fifo_data[9] -.sym 9432 w_rx_24_fifo_data[11] -.sym 9435 w_rx_09_fifo_data[11] -.sym 9438 w_rx_09_fifo_data[9] -.sym 9441 channel -.sym 9442 w_rx_09_fifo_data[6] -.sym 9443 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9447 channel -.sym 9449 w_rx_09_fifo_data[7] -.sym 9453 w_rx_09_fifo_data[10] -.sym 9456 w_rx_24_fifo_data[10] -.sym 9458 w_rx_09_fifo_data[8] -.sym 9460 w_rx_24_fifo_data[8] -.sym 9461 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9463 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9466 w_rx_09_fifo_data[7] -.sym 9469 w_rx_09_fifo_data[8] -.sym 9470 channel -.sym 9471 w_rx_24_fifo_data[8] -.sym 9472 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9475 w_rx_24_fifo_data[9] -.sym 9476 channel -.sym 9477 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9478 w_rx_09_fifo_data[9] -.sym 9481 w_rx_09_fifo_data[10] -.sym 9482 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9483 w_rx_24_fifo_data[10] -.sym 9484 channel -.sym 9489 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9490 w_rx_09_fifo_data[6] -.sym 9493 w_rx_09_fifo_data[9] -.sym 9496 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 9499 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 9500 channel -.sym 9501 w_rx_24_fifo_data[11] -.sym 9502 w_rx_09_fifo_data[11] -.sym 9509 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 9510 lvds_clock_$glb_clk -.sym 9511 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 9513 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 9514 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 9517 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 9519 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 9525 w_rx_09_fifo_data[13] -.sym 9553 w_rx_24_fifo_data[7] -.sym 9557 w_rx_24_fifo_data[13] -.sym 9561 w_rx_24_fifo_data[9] -.sym 9563 w_rx_24_fifo_data[11] -.sym 9576 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9584 w_rx_24_fifo_data[10] -.sym 9586 w_rx_24_fifo_data[7] -.sym 9587 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9592 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9595 w_rx_24_fifo_data[13] -.sym 9599 w_rx_24_fifo_data[9] -.sym 9601 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9611 w_rx_24_fifo_data[11] -.sym 9613 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9618 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 9619 w_rx_24_fifo_data[10] -.sym 9632 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 9633 lvds_clock_$glb_clk -.sym 9634 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 9643 io_pmod[0]$SB_IO_IN -.sym 9651 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 9658 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 9661 rx_fifo.mem_q.0.0_RDATA_2[1] -.sym 9770 o_shdn_rx_lna$SB_IO_OUT -.sym 9905 i_rst_b$SB_IO_IN +.sym 9389 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[3] +.sym 9390 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 9391 spi_if_ins.r_tx_byte[0] +.sym 9392 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9393 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 9394 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 9395 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9396 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[3] +.sym 9401 spi_if_ins.state_if[0] +.sym 9402 w_rx_fifo_push +.sym 9403 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 9404 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9406 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 9409 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 9411 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9413 w_rx_24_fifo_data[28] +.sym 9415 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9416 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 9417 rx_fifo.wr_addr_gray[3] +.sym 9418 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 9419 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 9421 w_tx_fifo_full +.sym 9422 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 9423 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 9424 w_rx_fifo_empty +.sym 9430 w_rx_09_fifo_data[26] +.sym 9431 w_lvds_rx_24_d0 +.sym 9433 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9434 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 9435 rx_fifo.wr_addr_gray_rd_r[2] +.sym 9436 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 9437 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 9438 w_rx_24_fifo_data[26] +.sym 9439 w_rx_data[0] +.sym 9441 smi_ctrl_ins.r_channel_SB_DFFE_Q_E +.sym 9442 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 9443 w_rx_fifo_pull +.sym 9444 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9445 i_rst_b$SB_IO_IN +.sym 9446 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 9448 channel +.sym 9449 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 9452 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 9457 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 9458 w_lvds_rx_24_d1 +.sym 9460 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9461 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 9464 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9466 rx_fifo.wr_addr_gray_rd_r[2] +.sym 9470 w_rx_fifo_pull +.sym 9472 i_rst_b$SB_IO_IN +.sym 9475 w_rx_data[0] +.sym 9481 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 9482 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 9483 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 9484 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 9487 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 9488 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 9489 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 9490 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 9493 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 9494 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 9496 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 9499 channel +.sym 9500 w_rx_24_fifo_data[26] +.sym 9501 w_rx_09_fifo_data[26] +.sym 9505 w_lvds_rx_24_d1 +.sym 9507 w_lvds_rx_24_d0 +.sym 9509 smi_ctrl_ins.r_channel_SB_DFFE_Q_E +.sym 9510 r_counter_$glb_clk +.sym 9512 rx_fifo.rd_addr[9] +.sym 9513 rx_fifo.rd_addr[7] +.sym 9514 rx_fifo.rd_addr_gray[6] +.sym 9515 rx_fifo.rd_addr_gray[7] +.sym 9516 rx_fifo.empty_o_SB_LUT4_I2_I0[0] +.sym 9517 rx_fifo.rd_addr_gray[0] +.sym 9518 rx_fifo.rd_addr_gray[3] +.sym 9519 rx_fifo.rd_addr_gray[8] +.sym 9521 w_rx_data[0] +.sym 9524 w_rx_24_fifo_data[26] +.sym 9525 w_lvds_rx_24_d0 +.sym 9527 $PACKER_VCC_NET +.sym 9531 w_rx_24_fifo_data[1] +.sym 9532 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 9534 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 9537 channel +.sym 9538 rx_fifo.rd_addr_gray_wr_r[3] +.sym 9539 rx_fifo.wr_addr_gray_rd_r[8] +.sym 9540 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 9541 rx_fifo.rd_addr_gray[3] +.sym 9547 w_rx_fifo_full +.sym 9563 rx_fifo.wr_addr_gray_rd[1] +.sym 9564 rx_fifo.wr_addr_gray_rd[3] +.sym 9568 rx_fifo.wr_addr_gray_rd[6] +.sym 9569 rx_fifo.wr_addr_gray[1] +.sym 9571 rx_fifo.wr_addr_gray[2] +.sym 9573 rx_fifo.wr_addr_gray_rd[2] +.sym 9575 rx_fifo.wr_addr_gray_rd[9] +.sym 9577 rx_fifo.wr_addr_gray[3] +.sym 9589 rx_fifo.wr_addr_gray_rd[1] +.sym 9595 rx_fifo.wr_addr_gray_rd[9] +.sym 9598 rx_fifo.wr_addr_gray[1] +.sym 9604 rx_fifo.wr_addr_gray[3] +.sym 9610 rx_fifo.wr_addr_gray[2] +.sym 9617 rx_fifo.wr_addr_gray_rd[2] +.sym 9624 rx_fifo.wr_addr_gray_rd[3] +.sym 9629 rx_fifo.wr_addr_gray_rd[6] +.sym 9633 r_counter_$glb_clk +.sym 9635 w_tx_data_smi[2] +.sym 9636 rx_fifo.empty_o_SB_LUT4_I2_O[0] +.sym 9637 rx_fifo.empty_o_SB_LUT4_I2_I0[1] +.sym 9638 rx_fifo.empty_o_SB_LUT4_I2_O[1] +.sym 9639 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 9640 rx_fifo.empty_o_SB_LUT4_I2_I0[3] +.sym 9641 w_tx_data_smi[0] +.sym 9642 w_tx_data_smi[1] +.sym 9644 w_cs[0] +.sym 9646 w_rx_fifo_data[9] +.sym 9654 rx_fifo.rd_addr[9] +.sym 9656 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9659 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 9661 rx_fifo.wr_addr_gray_rd[9] +.sym 9663 w_rx_09_fifo_push +.sym 9665 rx_fifo.rd_addr_gray[0] +.sym 9666 w_rx_fifo_full +.sym 9669 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 9676 rx_fifo.rd_addr_gray_wr_r[2] +.sym 9677 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 9678 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9682 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[0] +.sym 9683 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9684 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9685 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9686 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[3] +.sym 9687 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9688 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3[2] +.sym 9689 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 9691 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 9692 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 9693 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[1] +.sym 9694 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[2] +.sym 9695 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 9698 rx_fifo.rd_addr_gray_wr_r[3] +.sym 9700 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 9704 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 9705 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 9706 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 9707 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 9709 rx_fifo.rd_addr_gray_wr_r[2] +.sym 9710 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 9711 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9716 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 9717 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3[2] +.sym 9718 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 9721 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 9722 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 9723 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 9724 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 9729 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 9734 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 9735 rx_fifo.rd_addr_gray_wr_r[3] +.sym 9736 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 9739 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 9745 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 9746 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 9747 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9748 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9751 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[1] +.sym 9752 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[0] +.sym 9753 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[3] +.sym 9754 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[2] +.sym 9755 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 9756 r_counter_$glb_clk +.sym 9757 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 9758 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 9759 rx_fifo.wr_addr_gray_rd_r[8] +.sym 9760 rx_fifo.wr_addr_gray_rd[5] +.sym 9764 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 9765 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[0] +.sym 9771 w_tx_data_smi[0] +.sym 9772 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 9775 w_tx_data_smi[1] +.sym 9776 w_rx_24_fifo_data[28] +.sym 9778 w_rx_24_fifo_data[8] +.sym 9783 rx_fifo.rd_addr[9] +.sym 9786 rx_fifo.wr_addr_gray_rd[7] +.sym 9788 rx_fifo.wr_addr_gray_rd[6] +.sym 9791 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 9792 rx_fifo.wr_addr_gray_rd[8] +.sym 9793 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 9800 channel +.sym 9802 rx_fifo.wr_addr[2] +.sym 9803 w_rx_24_fifo_push +.sym 9805 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 9810 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 9811 w_rx_fifo_push +.sym 9812 rx_fifo.rd_addr[0] +.sym 9815 rx_fifo.wr_addr_gray_rd[4] +.sym 9816 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9817 rx_fifo.wr_addr_gray[4] +.sym 9818 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0] +.sym 9819 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1] +.sym 9822 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 9823 w_rx_09_fifo_push +.sym 9824 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9828 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9829 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 9830 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[2] +.sym 9832 rx_fifo.wr_addr_gray[4] +.sym 9838 rx_fifo.wr_addr[2] +.sym 9839 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9844 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[2] +.sym 9845 w_rx_fifo_push +.sym 9846 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1] +.sym 9847 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0] +.sym 9853 rx_fifo.wr_addr_gray_rd[4] +.sym 9857 channel +.sym 9858 w_rx_24_fifo_push +.sym 9859 w_rx_09_fifo_push +.sym 9863 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 9865 rx_fifo.rd_addr[0] +.sym 9868 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 9869 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 9870 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 9871 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 9876 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 9877 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9879 r_counter_$glb_clk +.sym 9882 rx_fifo.rd_addr_gray_wr_r[8] +.sym 9883 rx_fifo.rd_addr_gray_wr[8] +.sym 9884 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0] +.sym 9885 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 9886 rx_fifo.rd_addr_gray_wr[0] +.sym 9887 rx_fifo.rd_addr_gray_wr[7] +.sym 9888 rx_fifo.rd_addr_gray_wr[9] +.sym 9899 w_rx_24_fifo_push +.sym 9903 o_shdn_rx_lna$SB_IO_OUT +.sym 9910 w_rx_fifo_push +.sym 9926 w_rx_fifo_push +.sym 9934 rx_fifo.wr_addr_gray_rd[0] +.sym 9936 w_rx_fifo_full +.sym 9937 rx_fifo.wr_addr[9] +.sym 9940 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 9941 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0] +.sym 9942 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9946 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 9949 rx_fifo.wr_addr[0] +.sym 9950 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 9952 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 9953 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 9964 rx_fifo.wr_addr[9] +.sym 9967 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 9968 w_rx_fifo_full +.sym 9969 w_rx_fifo_push +.sym 9970 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0] +.sym 9973 rx_fifo.wr_addr_gray_rd[0] +.sym 9980 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 9981 rx_fifo.wr_addr[0] +.sym 9985 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 9986 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9987 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 9988 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 9992 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 9993 rx_fifo.wr_addr[0] +.sym 10002 r_counter_$glb_clk +.sym 10063 rx_fifo.wr_addr_gray[0] +.sym 10067 rx_fifo.wr_addr_gray[8] +.sym 10073 rx_fifo.wr_addr_gray[6] +.sym 10075 rx_fifo.wr_addr_gray[7] +.sym 10093 rx_fifo.wr_addr_gray[7] +.sym 10098 rx_fifo.wr_addr_gray[6] +.sym 10102 rx_fifo.wr_addr_gray[0] +.sym 10109 rx_fifo.wr_addr_gray[8] +.sym 10125 r_counter_$glb_clk +.sym 10143 w_rx_fifo_push +.sym 10147 i_rst_b$SB_IO_IN .sym 10172 o_shdn_rx_lna$SB_IO_OUT -.sym 10181 o_shdn_rx_lna$SB_IO_OUT +.sym 10194 o_shdn_rx_lna$SB_IO_OUT .sym 10201 w_smi_data_output[2] -.sym 10203 i_smi_a2$rename$0 +.sym 10203 i_smi_a2$SB_IO_IN .sym 10204 w_smi_data_output[1] -.sym 10206 i_smi_a2$rename$0 -.sym 10210 i_smi_a2$rename$0 -.sym 10218 i_smi_a2$rename$0 -.sym 10224 w_smi_data_output[1] -.sym 10225 w_smi_data_output[2] -.sym 10237 rx_fifo.rd_addr_gray[0] -.sym 10242 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 10244 rx_fifo.mem_i.0.0_RDATA[1] -.sym 10245 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[2] -.sym 10250 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10258 i_smi_a2$rename$0 -.sym 10260 smi_ctrl_ins.soe_and_reset -.sym 10355 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 10365 smi_ctrl_ins.int_cnt[4] -.sym 10380 w_smi_data_output[0] -.sym 10402 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 10404 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10410 rx_fifo.rd_addr[2] -.sym 10415 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 10419 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10420 w_smi_data_output[7] -.sym 10433 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 10436 rx_fifo.rd_addr[2] -.sym 10437 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 10440 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 10441 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10442 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10443 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10447 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 10451 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 10456 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10458 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 10464 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 10466 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10467 rx_fifo.rd_addr[2] -.sym 10473 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10479 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10482 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10483 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 10485 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 10490 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 10497 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 10502 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 10503 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10508 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 10510 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 10511 r_counter_$glb_clk +.sym 10206 i_smi_a2$SB_IO_IN +.sym 10207 $PACKER_VCC_NET +.sym 10211 w_smi_data_output[1] +.sym 10215 $PACKER_VCC_NET +.sym 10216 i_smi_a2$SB_IO_IN +.sym 10219 w_smi_data_output[2] +.sym 10224 i_smi_a2$SB_IO_IN +.sym 10226 w_tx_fifo_data[8] +.sym 10227 w_tx_fifo_data[9] +.sym 10228 w_tx_fifo_data[10] +.sym 10231 w_tx_fifo_data[11] +.sym 10258 w_smi_data_input[3] +.sym 10268 w_smi_data_input[2] +.sym 10277 w_smi_data_input[3] +.sym 10280 w_smi_data_input[0] +.sym 10282 w_smi_data_input[1] +.sym 10294 $PACKER_VCC_NET +.sym 10295 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 10310 w_smi_data_input[3] +.sym 10321 w_smi_data_input[0] +.sym 10326 w_smi_data_input[1] +.sym 10331 $PACKER_VCC_NET +.sym 10344 w_smi_data_input[2] +.sym 10347 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 10348 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 10349 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10350 w_smi_data_input[0] +.sym 10352 w_smi_data_input[7] +.sym 10354 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10355 w_tx_fifo_data[17] +.sym 10356 w_tx_fifo_data[16] +.sym 10357 w_tx_fifo_data[13] +.sym 10358 w_tx_fifo_data[5] +.sym 10359 w_tx_fifo_data[12] +.sym 10360 w_tx_fifo_data[25] +.sym 10361 w_tx_fifo_data[29] +.sym 10364 rx_fifo.rd_addr[7] +.sym 10369 i_smi_a2$SB_IO_IN +.sym 10372 w_smi_data_output[2] +.sym 10377 w_tx_fifo_data[10] +.sym 10382 w_smi_data_input[7] +.sym 10386 w_smi_data_input[0] +.sym 10396 w_smi_data_input[4] +.sym 10403 w_smi_data_output[7] +.sym 10411 w_tx_fifo_data[12] +.sym 10412 w_smi_data_input[7] +.sym 10413 w_smi_data_input[0] +.sym 10433 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10440 w_smi_data_input[1] +.sym 10441 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 10444 w_smi_data_input[0] +.sym 10451 w_smi_data_input[4] +.sym 10476 w_smi_data_input[0] +.sym 10484 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 10488 w_smi_data_input[4] +.sym 10507 w_smi_data_input[1] +.sym 10510 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10511 smi_ctrl_ins.swe_and_reset_$glb_clk .sym 10512 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10513 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[3] -.sym 10514 $io_pmod[4]$iobuf_i -.sym 10515 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 10516 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_E -.sym 10517 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 10520 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] -.sym 10527 rx_fifo.rd_addr[2] -.sym 10529 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10531 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10537 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 10538 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10542 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 10543 w_smi_data_output[0] -.sym 10544 rx_fifo.rd_addr[2] -.sym 10545 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 10548 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 10555 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10556 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10557 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 10561 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 10566 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 10567 rx_fifo.rd_addr[2] -.sym 10569 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 10571 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 10586 $nextpnr_ICESTORM_LC_1$O -.sym 10589 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10592 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 10595 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 10596 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 10598 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 10601 rx_fifo.rd_addr[2] -.sym 10602 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 10604 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 10607 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10608 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 10610 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 10612 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 10614 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 10616 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 10619 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 10620 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 10622 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 10624 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 10626 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 10628 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 10630 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 10632 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 10636 w_smi_data_output[2] -.sym 10638 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 10639 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] -.sym 10640 w_smi_data_output[1] -.sym 10641 w_smi_data_output[7] -.sym 10660 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 10662 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 10663 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 10664 w_rx_09_fifo_data[24] -.sym 10665 smi_ctrl_ins.int_cnt[4] -.sym 10666 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 10667 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 10669 smi_ctrl_ins.int_cnt[3] -.sym 10672 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 10678 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 10682 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 10683 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 10684 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 10686 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 10691 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 10692 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 10694 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 10697 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 10698 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 10700 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 10704 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 10705 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 10707 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 10708 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[3] -.sym 10709 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 10711 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 10713 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 10718 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 10719 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 10722 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 10723 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 10724 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 10725 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 10730 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 10737 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 10740 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 10746 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 10747 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 10748 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[3] -.sym 10749 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 10753 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 10756 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 10757 r_counter_$glb_clk -.sym 10758 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10759 w_rx_09_fifo_data[24] -.sym 10760 w_rx_09_fifo_data[27] -.sym 10761 w_rx_09_fifo_data[20] -.sym 10762 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] -.sym 10763 w_rx_09_fifo_data[21] -.sym 10765 w_rx_09_fifo_data[25] -.sym 10773 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 10774 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 10777 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 10778 w_smi_data_output[2] -.sym 10779 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 10781 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 10783 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 10785 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] -.sym 10786 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 10788 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] -.sym 10792 w_rx_09_fifo_data[24] -.sym 10794 w_rx_09_fifo_data[27] -.sym 10802 smi_ctrl_ins.int_cnt_SB_DFFNESS_Q_E -.sym 10803 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 10804 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 10805 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 10808 smi_ctrl_ins.int_cnt[4] -.sym 10809 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10811 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 10812 i_rst_b$SB_IO_IN -.sym 10813 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10814 rx_fifo.rd_addr[2] -.sym 10816 io_pmod[1]$SB_IO_IN -.sym 10817 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 10818 smi_ctrl_ins.int_cnt[3] -.sym 10819 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[1] -.sym 10821 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 10823 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[0] -.sym 10825 rx_fifo.wr_addr_gray_rd_r[8] -.sym 10827 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[2] -.sym 10829 io_pmod[4]$SB_IO_IN -.sym 10835 smi_ctrl_ins.int_cnt[3] -.sym 10836 smi_ctrl_ins.int_cnt[4] -.sym 10839 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 10840 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 10841 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 10842 rx_fifo.wr_addr_gray_rd_r[8] -.sym 10845 smi_ctrl_ins.int_cnt[3] -.sym 10852 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 10853 rx_fifo.rd_addr[2] -.sym 10854 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10857 io_pmod[1]$SB_IO_IN -.sym 10860 i_rst_b$SB_IO_IN -.sym 10869 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[2] -.sym 10870 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[0] -.sym 10871 io_pmod[4]$SB_IO_IN -.sym 10872 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[1] -.sym 10875 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 10876 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10877 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 10879 smi_ctrl_ins.int_cnt_SB_DFFNESS_Q_E -.sym 10880 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 10513 w_tx_fifo_data[27] +.sym 10514 w_tx_fifo_data[7] +.sym 10515 w_tx_fifo_data[6] +.sym 10516 w_tx_fifo_data[3] +.sym 10517 w_tx_fifo_data[24] +.sym 10518 w_tx_fifo_data[23] +.sym 10519 w_tx_fifo_data[28] +.sym 10520 w_tx_fifo_data[21] +.sym 10526 tx_fifo.rd_addr[1] +.sym 10530 w_tx_fifo_data[29] +.sym 10531 smi_ctrl_ins.tx_reg_state[0] +.sym 10532 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10545 w_tx_fifo_data[25] +.sym 10546 w_tx_fifo_data[22] +.sym 10554 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10562 w_smi_data_input[2] +.sym 10563 w_smi_data_input[3] +.sym 10568 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 10569 w_rx_fifo_empty +.sym 10570 $PACKER_VCC_NET +.sym 10573 w_tx_fifo_full +.sym 10581 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10584 i_smi_a2$SB_IO_IN +.sym 10589 w_smi_data_input[3] +.sym 10601 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10602 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 10605 w_smi_data_input[2] +.sym 10618 $PACKER_VCC_NET +.sym 10624 w_tx_fifo_full +.sym 10625 w_rx_fifo_empty +.sym 10626 i_smi_a2$SB_IO_IN +.sym 10633 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10634 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 10635 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 10638 smi_ctrl_ins.r_fifo_pushed_data[22] +.sym 10639 smi_ctrl_ins.r_fifo_pushed_data[21] +.sym 10641 smi_ctrl_ins.r_fifo_pushed_data[20] +.sym 10642 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 10643 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] +.sym 10646 rx_fifo.rd_addr[8] +.sym 10648 w_smi_data_input[2] +.sym 10649 w_rx_24_fifo_data[13] +.sym 10650 w_smi_data_input[1] +.sym 10658 w_tx_fifo_data[26] +.sym 10660 tx_fifo.rd_addr[0] +.sym 10662 w_tx_fifo_data[20] +.sym 10663 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 10666 w_tx_fifo_data[18] +.sym 10667 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 10668 w_tx_fifo_data[31] +.sym 10670 rx_fifo.rd_addr[8] +.sym 10678 w_smi_data_input[1] +.sym 10679 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 10680 smi_ctrl_ins.r_fifo_pushed_data[18] +.sym 10682 smi_ctrl_ins.r_fifo_pushed_data[31] +.sym 10690 w_smi_data_input[0] +.sym 10695 smi_ctrl_ins.r_fifo_pushed_data[22] +.sym 10698 w_smi_data_input[3] +.sym 10706 smi_ctrl_ins.r_fifo_pushed_data[20] +.sym 10711 smi_ctrl_ins.r_fifo_pushed_data[31] +.sym 10716 w_smi_data_input[3] +.sym 10722 smi_ctrl_ins.r_fifo_pushed_data[22] +.sym 10729 w_smi_data_input[0] +.sym 10735 w_smi_data_input[1] +.sym 10743 smi_ctrl_ins.r_fifo_pushed_data[20] +.sym 10752 smi_ctrl_ins.r_fifo_pushed_data[18] +.sym 10756 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 10757 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 10758 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O_$glb_sr +.sym 10760 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 10761 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 10762 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 10763 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 10764 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 10765 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 10766 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 10772 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] +.sym 10773 w_smi_data_input[4] +.sym 10774 w_smi_data_output[1] +.sym 10776 smi_ctrl_ins.w_fifo_pull_trigger +.sym 10777 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.sym 10778 w_smi_data_input[2] +.sym 10779 w_tx_fifo_data[1] +.sym 10780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] +.sym 10781 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] +.sym 10782 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 10786 tx_fifo.rd_addr[2] +.sym 10788 w_tx_fifo_data[2] +.sym 10789 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 10790 tx_fifo.rd_addr[5] +.sym 10793 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] +.sym 10800 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 10801 lvds_tx_inst.r_phase_count[1] +.sym 10806 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 10807 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 10809 tx_fifo.rd_addr[5] +.sym 10812 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 10814 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 10815 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 10816 w_tx_fifo_pull +.sym 10821 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 10828 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 10829 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 10830 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 10831 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 10833 tx_fifo.rd_addr[5] +.sym 10834 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 10836 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 10842 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 10851 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 10852 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 10853 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 10854 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 10857 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 10858 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 10859 w_tx_fifo_pull +.sym 10865 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 10866 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 10875 lvds_tx_inst.r_phase_count[1] +.sym 10880 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 10881 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 10882 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] -.sym 10885 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] -.sym 10886 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] -.sym 10887 io_ctrl_ins.o_pmod[2] -.sym 10888 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] -.sym 10889 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 10894 smi_ctrl_ins.int_cnt[4] -.sym 10896 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 10898 w_rx_24_fifo_data[20] -.sym 10899 w_rx_09_fifo_data[22] -.sym 10900 smi_ctrl_ins.int_cnt[3] -.sym 10902 rx_fifo.wr_addr[1] -.sym 10903 w_rx_09_fifo_data[27] -.sym 10904 w_rx_09_fifo_data[18] -.sym 10905 w_rx_09_fifo_data[20] -.sym 10906 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 10908 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 10909 io_pmod[0]$SB_IO_IN -.sym 10910 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 10913 w_rx_data[3] -.sym 10914 w_rx_09_fifo_data[25] -.sym 10915 io_pmod[4]$SB_IO_IN -.sym 10916 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 10917 rx_fifo.mem_i.0.0_RDATA[1] -.sym 10931 rx_fifo.rd_addr_gray_wr[8] -.sym 10940 i_rst_b$SB_IO_IN -.sym 10941 rx_fifo.rd_addr_gray[8] -.sym 10945 rx_fifo.rd_addr_gray_wr[0] -.sym 10947 rx_fifo.rd_addr_gray[0] -.sym 10952 w_debug_smi_test -.sym 10958 rx_fifo.rd_addr_gray[8] -.sym 10964 i_rst_b$SB_IO_IN -.sym 10965 w_debug_smi_test -.sym 10975 rx_fifo.rd_addr_gray_wr[0] -.sym 10981 rx_fifo.rd_addr_gray_wr[8] -.sym 10995 rx_fifo.rd_addr_gray[0] -.sym 11003 lvds_clock_$glb_clk -.sym 11005 rx_fifo.mem_i.0.2_WDATA_3 -.sym 11006 rx_fifo.mem_i.0.2_WDATA -.sym 11007 rx_fifo.mem_i.0.2_WDATA_2 -.sym 11008 w_debug_fifo_pull -.sym 11010 w_debug_smi_test -.sym 11011 rx_fifo.mem_i.0.2_WDATA_1 -.sym 11012 w_debug_fifo_push -.sym 11021 smi_ctrl_ins.int_cnt_SB_DFFNESS_Q_E -.sym 11022 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 11023 w_rx_24_fifo_data[21] -.sym 11026 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 11027 w_rx_24_fifo_data[23] -.sym 11028 w_rx_data[2] -.sym 11032 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 11033 w_rx_data[4] -.sym 11036 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 11037 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] -.sym 11039 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 11053 $PACKER_VCC_NET -.sym 11057 io_pmod[1]$SB_IO_IN -.sym 11059 w_debug_fifo_pull -.sym 11097 $PACKER_VCC_NET -.sym 11125 io_pmod[1]$SB_IO_IN +.sym 10882 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 10883 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 10884 tx_fifo.wr_addr_gray_rd[4] +.sym 10885 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[1] +.sym 10886 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[0] +.sym 10887 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 10888 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[0] +.sym 10889 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 10894 i_smi_a2$SB_IO_IN +.sym 10896 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 10897 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 10899 w_tx_fifo_full +.sym 10902 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 10903 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] +.sym 10904 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] +.sym 10906 tx_fifo.rd_addr[1] +.sym 10908 rx_fifo.rd_addr[7] +.sym 10909 w_tx_fifo_empty +.sym 10910 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 10911 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 10912 tx_fifo.rd_addr[2] +.sym 10913 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 10914 w_rx_24_fifo_data[15] +.sym 10916 tx_fifo.rd_addr[5] +.sym 10917 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 10926 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 10928 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 10931 tx_fifo.rd_addr[0] +.sym 10932 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 10933 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 10934 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 10935 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 10936 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 10944 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 10954 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 10959 tx_fifo.rd_addr[0] +.sym 10965 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 10968 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 10969 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 10970 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 10971 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 10974 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 10982 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 10986 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 10988 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 10989 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 10995 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 11000 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 11002 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 11003 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 11004 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 11005 tx_fifo.empty_o_SB_LUT4_I3_I1[1] +.sym 11007 tx_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 11008 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 11009 tx_fifo.empty_o_SB_LUT4_I3_I1[2] +.sym 11010 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 11011 tx_fifo.wr_addr_gray_rd[1] +.sym 11012 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 11017 tx_fifo.rd_addr[0] +.sym 11021 tx_fifo.rd_addr[5] +.sym 11022 w_rx_24_fifo_data[5] +.sym 11024 w_rx_24_fifo_data[18] +.sym 11025 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 11026 smi_ctrl_ins.int_cnt_rx[4] +.sym 11027 tx_fifo.rd_addr[1] +.sym 11031 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 11032 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 11034 w_rx_24_fifo_data[29] +.sym 11035 $PACKER_VCC_NET +.sym 11037 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 11039 w_rx_24_fifo_data[4] +.sym 11040 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 11046 tx_fifo.wr_addr_gray_rd_r[0] +.sym 11047 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 11049 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 11050 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 11053 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 11054 tx_fifo.rd_addr[0] +.sym 11058 tx_fifo.rd_addr[1] +.sym 11059 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 11061 tx_fifo.rd_addr[2] +.sym 11064 i_rst_b$SB_IO_IN +.sym 11069 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 11073 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 11075 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 11076 lvds_tx_inst.r_phase_count_SB_LUT4_I1_1_O_SB_DFFSR_D_Q_SB_LUT4_I3_O[1] +.sym 11077 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 11085 lvds_tx_inst.r_phase_count_SB_LUT4_I1_1_O_SB_DFFSR_D_Q_SB_LUT4_I3_O[1] +.sym 11086 i_rst_b$SB_IO_IN +.sym 11087 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 11088 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 11092 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 11097 tx_fifo.rd_addr[1] +.sym 11098 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 11099 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 11100 tx_fifo.rd_addr[2] +.sym 11109 tx_fifo.rd_addr[0] +.sym 11110 tx_fifo.wr_addr_gray_rd_r[0] +.sym 11117 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 11118 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 11122 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 11123 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 11124 i_rst_b$SB_IO_IN +.sym 11125 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E .sym 11126 r_counter_$glb_clk -.sym 11127 w_debug_fifo_pull -.sym 11128 w_rx_data[4] -.sym 11131 w_rx_data[3] -.sym 11134 w_rx_data[1] -.sym 11140 w_rx_data[2] -.sym 11141 rx_fifo.wr_addr[5] -.sym 11144 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 11145 io_pmod[1]$SB_IO_IN -.sym 11148 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11151 channel -.sym 11152 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 11155 rx_fifo.mem_i.0.3_WDATA -.sym 11156 w_rx_09_fifo_data[24] -.sym 11157 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 11158 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 11159 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 11161 w_rx_data[0] -.sym 11163 rx_fifo.mem_q.0.3_RDATA_1[0] -.sym 11171 w_rx_09_fifo_data[27] -.sym 11174 w_rx_09_fifo_data[24] -.sym 11179 io_pmod[0]$SB_IO_IN -.sym 11184 w_debug_fifo_push -.sym 11187 w_rx_24_fifo_data[29] -.sym 11188 w_rx_09_fifo_data[29] -.sym 11191 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11194 w_rx_09_fifo_data[28] -.sym 11195 w_rx_09_fifo_data[26] -.sym 11197 w_rx_09_fifo_data[14] -.sym 11202 w_rx_09_fifo_data[28] -.sym 11204 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11208 w_rx_09_fifo_data[26] -.sym 11211 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11215 w_rx_09_fifo_data[24] -.sym 11216 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11221 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11223 w_rx_09_fifo_data[27] -.sym 11228 w_debug_fifo_push -.sym 11229 io_pmod[0]$SB_IO_IN -.sym 11235 w_rx_24_fifo_data[29] -.sym 11238 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11241 w_rx_09_fifo_data[14] -.sym 11244 w_rx_09_fifo_data[29] -.sym 11247 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11248 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 11249 lvds_clock_$glb_clk -.sym 11250 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 11251 w_tx_data_sys[0] -.sym 11253 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 11254 rx_fifo.mem_q.0.3_WDATA_3 -.sym 11255 rx_fifo.mem_q.0.3_WDATA_2 -.sym 11256 rx_fifo.mem_i.0.3_WDATA_1 -.sym 11263 io_pmod[1]$SB_IO_IN -.sym 11265 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 11267 $PACKER_VCC_NET -.sym 11269 i_glob_clock$SB_IO_IN -.sym 11272 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 11273 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 11275 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] -.sym 11276 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] -.sym 11279 w_rx_09_fifo_data[12] -.sym 11283 w_rx_09_fifo_data[14] -.sym 11286 rx_fifo.mem_q.0.3_RDATA_3[1] -.sym 11292 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 11295 w_rx_24_fifo_data[28] -.sym 11296 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 11298 smi_ctrl_ins.int_cnt[4] -.sym 11299 lvds_rx_09_inst.o_fifo_data[31] -.sym 11300 w_rx_09_fifo_data[30] -.sym 11301 w_rx_09_fifo_data[28] -.sym 11303 w_rx_24_fifo_data[26] -.sym 11304 smi_ctrl_ins.int_cnt[3] -.sym 11305 w_rx_24_fifo_data[29] -.sym 11306 w_rx_24_fifo_data[31] -.sym 11307 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 11309 channel -.sym 11311 channel -.sym 11314 w_rx_24_fifo_data[12] -.sym 11317 channel -.sym 11320 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 11321 w_rx_24_fifo_data[30] -.sym 11325 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 11327 w_rx_24_fifo_data[12] -.sym 11331 channel -.sym 11332 w_rx_09_fifo_data[28] -.sym 11333 w_rx_24_fifo_data[28] -.sym 11334 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 11337 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 11338 w_rx_09_fifo_data[30] -.sym 11339 w_rx_24_fifo_data[30] -.sym 11340 channel -.sym 11344 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 11346 w_rx_24_fifo_data[26] -.sym 11349 smi_ctrl_ins.int_cnt[4] -.sym 11350 smi_ctrl_ins.int_cnt[3] -.sym 11351 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 11352 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 11355 w_rx_24_fifo_data[28] -.sym 11356 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 11361 w_rx_24_fifo_data[29] -.sym 11363 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 11367 lvds_rx_09_inst.o_fifo_data[31] -.sym 11368 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 11369 w_rx_24_fifo_data[31] -.sym 11370 channel -.sym 11371 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 11372 lvds_clock_$glb_clk -.sym 11373 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 11375 io_ctrl_ins.rf_mode[0] -.sym 11376 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 11377 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 11378 io_ctrl_ins.debug_mode[1] -.sym 11380 io_ctrl_ins.debug_mode[0] -.sym 11381 i_button_SB_LUT4_I0_I2[3] -.sym 11386 $PACKER_VCC_NET -.sym 11390 rx_fifo.mem_i.0.3_WDATA_3 -.sym 11392 rx_fifo.mem_i.0.3_WDATA_2 -.sym 11394 rx_fifo.wr_addr[5] -.sym 11395 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 11400 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 11401 w_rx_24_fifo_data[12] -.sym 11402 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 11404 rx_fifo.mem_q.0.0_RDATA_1[1] -.sym 11405 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 11406 w_rx_data[3] -.sym 11407 io_pmod[4]$SB_IO_IN -.sym 11408 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 11409 io_ctrl_ins.rf_mode[0] -.sym 11416 smi_ctrl_ins.int_cnt[3] -.sym 11426 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 11428 smi_ctrl_ins.int_cnt[4] -.sym 11430 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 11433 rx_fifo.mem_q.0.3_RDATA_1[0] -.sym 11436 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 11440 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11441 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 11444 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 11446 rx_fifo.mem_q.0.3_RDATA_3[1] -.sym 11448 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11450 rx_fifo.mem_q.0.3_RDATA_3[1] -.sym 11466 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 11467 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 11468 smi_ctrl_ins.int_cnt[3] -.sym 11469 smi_ctrl_ins.int_cnt[4] -.sym 11479 rx_fifo.mem_q.0.3_RDATA_1[0] -.sym 11481 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11484 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 11485 smi_ctrl_ins.int_cnt[3] -.sym 11486 smi_ctrl_ins.int_cnt[4] -.sym 11487 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 11494 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 11495 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 11127 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 11128 tx_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 11129 tx_fifo.rd_addr_gray_wr[7] +.sym 11130 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 11131 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R +.sym 11132 tx_fifo.rd_addr_gray_wr_r[8] +.sym 11133 tx_fifo.rd_addr_gray_wr_r[7] +.sym 11135 tx_fifo.rd_addr_gray_wr[8] +.sym 11141 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 11143 tx_fifo.wr_addr_gray[1] +.sym 11144 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 11146 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 11147 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 11148 tx_fifo.wr_addr_gray[7] +.sym 11150 tx_fifo.wr_addr_gray_rd_r[0] +.sym 11151 w_rx_24_fifo_data[30] +.sym 11153 w_fetch +.sym 11155 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 11156 w_rx_24_fifo_data[5] +.sym 11158 rx_fifo.rd_addr[7] +.sym 11160 w_rx_24_fifo_data[6] +.sym 11162 rx_fifo.rd_addr[8] +.sym 11174 w_rx_24_fifo_data[21] +.sym 11181 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 11186 w_rx_24_fifo_data[15] +.sym 11187 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 11190 w_rx_24_fifo_data[17] +.sym 11194 w_rx_24_fifo_data[29] +.sym 11199 w_rx_24_fifo_data[4] +.sym 11203 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 11205 w_rx_24_fifo_data[4] +.sym 11215 w_rx_24_fifo_data[17] +.sym 11217 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 11220 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 11222 w_rx_24_fifo_data[21] +.sym 11232 w_rx_24_fifo_data[15] +.sym 11234 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 11246 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 11247 w_rx_24_fifo_data[29] +.sym 11248 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 11249 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 11250 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 11252 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[1] +.sym 11253 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[2] +.sym 11254 spi_if_ins.r_tx_data_valid +.sym 11256 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 11257 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 11258 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 11267 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 11269 w_rx_24_fifo_data[19] +.sym 11272 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 11273 tx_fifo.rd_addr[0] +.sym 11274 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 11277 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 11281 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 11282 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 11285 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 11286 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 11293 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 11296 rx_fifo.rd_addr[0] +.sym 11297 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 11299 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 11300 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 11303 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 11304 rx_fifo.rd_addr[0] +.sym 11307 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 11314 rx_fifo.rd_addr[7] +.sym 11324 $nextpnr_ICESTORM_LC_3$O +.sym 11326 rx_fifo.rd_addr[0] +.sym 11330 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 11333 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 11334 rx_fifo.rd_addr[0] +.sym 11336 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 11339 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 11340 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 11342 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 11345 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 11346 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 11348 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 11350 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 11352 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 11354 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 11357 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 11358 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 11360 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 11363 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 11364 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 11366 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 11368 rx_fifo.rd_addr[7] +.sym 11370 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 11374 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 11375 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 11376 rx_fifo.rd_addr_gray_wr[3] +.sym 11377 spi_if_ins.state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] +.sym 11378 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 11379 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] +.sym 11380 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 11381 rx_fifo.rd_addr_gray_wr_r[3] +.sym 11382 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 11386 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 11387 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 11388 $PACKER_VCC_NET +.sym 11390 lvds_rx_24_inst.r_phase_count[1] +.sym 11391 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 11393 w_rx_24_fifo_data[0] +.sym 11395 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 11396 i_ss$SB_IO_IN +.sym 11397 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[2] +.sym 11398 rx_fifo.rd_addr[9] +.sym 11399 i_glob_clock$SB_IO_IN +.sym 11400 rx_fifo.rd_addr[7] +.sym 11401 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 11404 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11406 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11408 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 11409 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 11410 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 11415 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11417 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 11426 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 11429 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 11430 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 11438 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 11439 rx_fifo.rd_addr[9] +.sym 11444 rx_fifo.rd_addr[8] +.sym 11447 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 11450 rx_fifo.rd_addr[8] +.sym 11451 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 11454 rx_fifo.rd_addr[9] +.sym 11457 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 11460 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 11461 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 11463 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 11467 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 11474 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 11475 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 11479 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11484 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11486 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 11490 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 11494 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 11495 r_counter_$glb_clk .sym 11496 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11497 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 11499 w_tx_data_smi[1] -.sym 11502 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 11503 w_tx_data_smi[0] -.sym 11504 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 11521 w_rx_data[4] -.sym 11522 rx_fifo.mem_q.0.1_RDATA_3[1] -.sym 11523 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 11524 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 11530 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 11531 i_button_SB_LUT4_I0_I2[3] -.sym 11542 w_rx_09_fifo_data[8] -.sym 11543 w_rx_09_fifo_data[11] -.sym 11548 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11550 smi_ctrl_ins.int_cnt[3] -.sym 11551 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 11552 w_rx_09_fifo_data[13] -.sym 11564 w_rx_09_fifo_data[12] -.sym 11565 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 11566 smi_ctrl_ins.int_cnt[4] -.sym 11569 w_rx_09_fifo_data[10] -.sym 11571 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 11572 smi_ctrl_ins.int_cnt[3] -.sym 11573 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 11574 smi_ctrl_ins.int_cnt[4] -.sym 11584 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11585 w_rx_09_fifo_data[10] -.sym 11589 w_rx_09_fifo_data[13] -.sym 11591 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11596 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11598 w_rx_09_fifo_data[12] -.sym 11608 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11610 w_rx_09_fifo_data[11] -.sym 11614 w_rx_09_fifo_data[8] -.sym 11615 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11617 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 11618 lvds_clock_$glb_clk -.sym 11619 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 11620 io_ctrl_ins.rf_pin_state[2] -.sym 11621 io_ctrl_ins.rf_pin_state[0] -.sym 11622 io_ctrl_ins.rf_pin_state[4] -.sym 11623 io_ctrl_ins.rf_pin_state[1] -.sym 11624 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 11625 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 11627 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 11636 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 11641 rx_fifo.wr_addr[5] -.sym 11642 channel -.sym 11648 o_tr_vc2$SB_IO_OUT -.sym 11668 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11672 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 11676 rx_fifo.mem_q.0.0_RDATA_1[1] -.sym 11679 rx_fifo.mem_q.0.2_RDATA[0] -.sym 11682 rx_fifo.mem_q.0.1_RDATA_3[1] -.sym 11691 rx_fifo.mem_q.0.0_RDATA_2[1] -.sym 11700 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11703 rx_fifo.mem_q.0.0_RDATA_1[1] -.sym 11707 rx_fifo.mem_q.0.1_RDATA_3[1] -.sym 11709 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11724 rx_fifo.mem_q.0.0_RDATA_2[1] -.sym 11726 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11738 rx_fifo.mem_i.0.0_RDATA[1] -.sym 11739 rx_fifo.mem_q.0.2_RDATA[0] -.sym 11740 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 11741 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 11497 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 11498 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11500 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 11502 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 11503 spi_if_ins.spi.r_tx_byte[0] +.sym 11504 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 11510 w_fetch +.sym 11514 rx_fifo.rd_addr_gray_wr_r[3] +.sym 11517 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 11518 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 11520 rx_fifo.rd_addr_gray[3] +.sym 11522 w_rx_24_fifo_data[26] +.sym 11523 i_button_SB_LUT4_I0_I1[0] +.sym 11524 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 11525 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 11526 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 11527 $PACKER_VCC_NET +.sym 11530 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 11532 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11538 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11539 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 11544 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 11546 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 11547 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 11548 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 11552 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11553 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 11554 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[3] +.sym 11556 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11557 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 11558 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 11561 rx_fifo.wr_addr_gray_rd_r[8] +.sym 11562 spi_if_ins.state_if[0] +.sym 11563 rx_fifo.wr_addr_gray_rd_r[9] +.sym 11566 r_tx_data[0] +.sym 11567 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 11569 spi_if_ins.state_if[1] +.sym 11571 rx_fifo.wr_addr_gray_rd_r[9] +.sym 11572 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 11573 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11574 rx_fifo.wr_addr_gray_rd_r[8] +.sym 11577 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 11578 spi_if_ins.state_if[1] +.sym 11579 spi_if_ins.state_if[0] +.sym 11586 r_tx_data[0] +.sym 11590 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 11595 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11596 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 11598 rx_fifo.wr_addr_gray_rd_r[8] +.sym 11601 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 11602 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 11603 spi_if_ins.state_if[0] +.sym 11604 spi_if_ins.state_if[1] +.sym 11607 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[3] +.sym 11608 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 11609 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 11610 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11613 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 11614 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 11616 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 11617 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 11618 r_counter_$glb_clk +.sym 11620 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 11622 smi_ctrl_ins.r_channel_SB_DFFE_Q_E +.sym 11624 r_tx_data[0] +.sym 11625 spi_if_ins.o_cs_SB_LUT4_I0_2_O[0] +.sym 11627 smi_ctrl_ins.r_channel_SB_DFFE_Q_E_SB_LUT4_O_I3[1] +.sym 11634 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 11636 spi_if_ins.state_if[1] +.sym 11637 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 11638 spi_if_ins.state_if[0] +.sym 11639 w_rx_24_fifo_data[2] +.sym 11640 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11643 spi_if_ins.w_rx_data[6] +.sym 11644 w_cs[3] +.sym 11645 w_fetch +.sym 11646 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 11647 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 11648 w_rx_24_fifo_data[5] +.sym 11650 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 11652 w_rx_24_fifo_data[6] +.sym 11653 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 11654 rx_fifo.rd_addr[7] +.sym 11655 w_cs[1] +.sym 11662 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 11663 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 11664 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 11667 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 11668 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 11670 rx_fifo.rd_addr[7] +.sym 11674 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 11678 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11679 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 11680 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 11686 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 11690 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 11695 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 11701 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 11706 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 11715 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 11718 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 11720 rx_fifo.rd_addr[7] +.sym 11721 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 11726 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 11731 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 11732 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 11736 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 11738 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 11740 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 11741 r_counter_$glb_clk .sym 11742 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 11743 o_tr_vc2$SB_IO_OUT -.sym 11744 io_ctrl_ins.mixer_en_state -.sym 11745 o_rx_h_tx_l$SB_IO_OUT -.sym 11746 o_rx_h_tx_l_b$SB_IO_OUT -.sym 11747 o_shdn_rx_lna$SB_IO_OUT -.sym 11748 o_shdn_tx_lna$SB_IO_OUT -.sym 11749 o_tr_vc1_b$SB_IO_OUT -.sym 11750 o_tr_vc1$SB_IO_OUT -.sym 11751 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 11757 $io_pmod[0]$iobuf_i -.sym 11759 rx_fifo.mem_q.0.3_WDATA -.sym 11762 w_rx_data[2] -.sym 11763 w_rx_data[0] -.sym 11883 o_tr_vc1$SB_IO_OUT -.sym 12024 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 12115 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 12117 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 11743 w_rx_24_fifo_data[29] +.sym 11744 w_rx_24_fifo_data[7] +.sym 11745 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 11747 w_rx_24_fifo_data[27] +.sym 11748 w_rx_24_fifo_data[4] +.sym 11749 w_rx_24_fifo_data[28] +.sym 11750 w_rx_24_fifo_data[8] +.sym 11755 rx_fifo.rd_addr[9] +.sym 11762 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 11768 w_rx_24_fifo_data[27] +.sym 11770 rx_fifo.rd_addr_gray[7] +.sym 11772 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 11774 w_rx_24_fifo_data[8] +.sym 11778 rx_fifo.rd_addr_gray[8] +.sym 11784 rx_fifo.rd_addr[9] +.sym 11785 rx_fifo.rd_addr[7] +.sym 11786 w_rx_fifo_empty +.sym 11787 w_tx_fifo_full +.sym 11789 channel +.sym 11790 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11792 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 11793 rx_fifo.wr_addr_gray_rd_r[8] +.sym 11794 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 11795 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 11796 rx_fifo.empty_o_SB_LUT4_I2_I0[0] +.sym 11797 rx_fifo.empty_o_SB_LUT4_I2_I0[3] +.sym 11798 rx_fifo.empty_o_SB_LUT4_I2_O[2] +.sym 11799 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[0] +.sym 11801 rx_fifo.wr_addr_gray_rd_r[9] +.sym 11802 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 11803 rx_fifo.empty_o_SB_LUT4_I2_O[1] +.sym 11804 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 11805 rx_fifo.rd_addr[8] +.sym 11809 rx_fifo.empty_o_SB_LUT4_I2_O[0] +.sym 11810 rx_fifo.empty_o_SB_LUT4_I2_I0[1] +.sym 11818 channel +.sym 11823 rx_fifo.empty_o_SB_LUT4_I2_I0[0] +.sym 11824 rx_fifo.empty_o_SB_LUT4_I2_I0[3] +.sym 11825 rx_fifo.empty_o_SB_LUT4_I2_I0[1] +.sym 11826 w_rx_fifo_empty +.sym 11829 rx_fifo.wr_addr_gray_rd_r[8] +.sym 11830 rx_fifo.wr_addr_gray_rd_r[9] +.sym 11831 rx_fifo.rd_addr[9] +.sym 11832 rx_fifo.rd_addr[8] +.sym 11835 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 11836 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 11837 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 11838 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[0] +.sym 11842 rx_fifo.empty_o_SB_LUT4_I2_O[1] +.sym 11843 rx_fifo.empty_o_SB_LUT4_I2_O[0] +.sym 11844 rx_fifo.empty_o_SB_LUT4_I2_O[2] +.sym 11847 rx_fifo.rd_addr[8] +.sym 11848 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 11849 rx_fifo.rd_addr[7] +.sym 11855 w_rx_fifo_empty +.sym 11859 w_tx_fifo_full +.sym 11863 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 11864 r_counter_$glb_clk +.sym 11865 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 11866 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 11872 w_rx_24_fifo_push +.sym 11878 w_tx_data_smi[2] +.sym 11879 w_rx_24_fifo_data[28] +.sym 11882 smi_ctrl_ins.soe_and_reset +.sym 11883 w_tx_fifo_full +.sym 11890 w_tx_data_sys[0] +.sym 11893 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 11911 rx_fifo.wr_addr_gray[5] +.sym 11912 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 11917 rx_fifo.wr_addr_gray_rd[5] +.sym 11918 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 11928 rx_fifo.wr_addr_gray_rd[7] +.sym 11934 rx_fifo.wr_addr_gray_rd[8] +.sym 11941 rx_fifo.wr_addr_gray_rd[5] +.sym 11947 rx_fifo.wr_addr_gray_rd[8] +.sym 11952 rx_fifo.wr_addr_gray[5] +.sym 11977 rx_fifo.wr_addr_gray_rd[7] +.sym 11982 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 11983 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 11987 r_counter_$glb_clk +.sym 11995 w_tx_data_sys[0] +.sym 12003 w_rx_fifo_full +.sym 12007 rx_fifo.wr_addr_gray[5] +.sym 12035 rx_fifo.rd_addr_gray_wr[0] +.sym 12037 rx_fifo.rd_addr_gray[0] +.sym 12040 rx_fifo.rd_addr_gray[7] +.sym 12043 rx_fifo.rd_addr[9] +.sym 12048 rx_fifo.rd_addr_gray[8] +.sym 12053 rx_fifo.rd_addr_gray_wr[9] +.sym 12056 rx_fifo.rd_addr_gray_wr[8] +.sym 12071 rx_fifo.rd_addr_gray_wr[8] +.sym 12077 rx_fifo.rd_addr_gray[8] +.sym 12083 rx_fifo.rd_addr_gray_wr[9] +.sym 12088 rx_fifo.rd_addr_gray_wr[0] +.sym 12093 rx_fifo.rd_addr_gray[0] +.sym 12102 rx_fifo.rd_addr_gray[7] +.sym 12106 rx_fifo.rd_addr[9] +.sym 12110 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 12116 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 12125 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 12128 rx_fifo.rd_addr_gray_wr_r[8] +.sym 12129 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 12133 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E .sym 12305 i_rst_b$SB_IO_IN -.sym 12309 smi_ctrl_ins.soe_and_reset +.sym 12306 smi_ctrl_ins.soe_and_reset +.sym 12309 smi_ctrl_ins.swe_and_reset .sym 12310 w_smi_data_output[0] -.sym 12312 i_smi_a2$rename$0 +.sym 12312 i_smi_a2$SB_IO_IN .sym 12313 w_smi_data_output[7] -.sym 12315 i_smi_a2$rename$0 -.sym 12319 i_smi_a2$rename$0 -.sym 12321 w_smi_data_output[0] +.sym 12315 i_smi_a2$SB_IO_IN +.sym 12316 $PACKER_VCC_NET +.sym 12321 i_smi_a2$SB_IO_IN +.sym 12324 $PACKER_VCC_NET .sym 12326 w_smi_data_output[7] -.sym 12327 i_smi_a2$rename$0 -.sym 12333 smi_ctrl_ins.soe_and_reset -.sym 12339 i_rst_b_SB_LUT4_I3_O -.sym 12367 i_smi_a2$rename$0 -.sym 12463 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 12464 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 12465 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 12466 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 12467 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 12469 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 12470 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 12473 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 12493 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 12506 w_smi_data_output[3] +.sym 12329 i_smi_a2$SB_IO_IN +.sym 12333 smi_ctrl_ins.swe_and_reset +.sym 12334 w_smi_data_output[0] +.sym 12338 smi_ctrl_ins.modem_tx_ctrl +.sym 12339 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O +.sym 12340 $PACKER_VCC_NET +.sym 12341 smi_ctrl_ins.swe_and_reset +.sym 12353 w_tx_fifo_data[21] +.sym 12364 w_smi_data_output[0] +.sym 12367 w_smi_data_input[4] +.sym 12378 smi_ctrl_ins.r_fifo_pushed_data[11] +.sym 12380 smi_ctrl_ins.r_fifo_pushed_data[8] +.sym 12384 smi_ctrl_ins.r_fifo_pushed_data[10] +.sym 12389 smi_ctrl_ins.r_fifo_pushed_data[9] +.sym 12404 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 12413 smi_ctrl_ins.r_fifo_pushed_data[8] +.sym 12416 smi_ctrl_ins.r_fifo_pushed_data[9] +.sym 12423 smi_ctrl_ins.r_fifo_pushed_data[10] +.sym 12440 smi_ctrl_ins.r_fifo_pushed_data[11] +.sym 12456 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 12457 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 12458 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O_$glb_sr +.sym 12459 w_smi_data_input[3] +.sym 12463 smi_ctrl_ins.r_fifo_pushed_data[17] +.sym 12464 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 12465 smi_ctrl_ins.r_fifo_pushed_data[12] +.sym 12466 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0[0] +.sym 12467 smi_ctrl_ins.modem_tx_ctrl_SB_DFFNESR_Q_E +.sym 12468 smi_ctrl_ins.r_fifo_pushed_data[16] +.sym 12469 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 12470 smi_ctrl_ins.r_fifo_pushed_data[13] +.sym 12474 w_rx_24_fifo_data[29] +.sym 12475 w_tx_fifo_data[8] +.sym 12477 w_tx_fifo_data[11] +.sym 12481 w_smi_data_input[7] +.sym 12485 w_tx_fifo_push +.sym 12489 i_smi_a2$SB_IO_IN +.sym 12492 w_smi_data_input[5] +.sym 12498 w_tx_fifo_data[9] +.sym 12505 w_smi_data_input[4] .sym 12511 i_rst_b$SB_IO_IN -.sym 12512 w_debug_smi_test -.sym 12522 spi_if_ins.w_rx_data[0] -.sym 12523 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 12525 $io_pmod[4]$iobuf_i -.sym 12528 spi_if_ins.w_rx_data[2] -.sym 12529 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 12551 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_E -.sym 12567 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 12582 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 12619 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_E -.sym 12620 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 12621 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12622 spi_if_ins.w_rx_data[0] -.sym 12623 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[0] -.sym 12624 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] -.sym 12625 spi_if_ins.w_rx_data[2] -.sym 12627 spi_if_ins.w_rx_data[1] -.sym 12628 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 12629 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 12633 w_rx_data[1] -.sym 12642 rx_fifo.wr_addr[0] -.sym 12646 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 12648 spi_if_ins.w_rx_data[3] -.sym 12649 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] -.sym 12650 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 12651 i_rst_b$SB_IO_IN -.sym 12654 spi_if_ins.w_rx_data[4] -.sym 12656 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 12663 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[3] -.sym 12670 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] -.sym 12671 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 12673 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 12674 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] -.sym 12675 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 12677 i_rst_b$SB_IO_IN -.sym 12678 w_debug_smi_test -.sym 12679 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 12680 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 12681 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 12682 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 12683 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 12684 rx_fifo.rd_addr[2] -.sym 12686 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 12688 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 12689 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 12690 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 12692 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 12694 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 12696 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 12697 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] -.sym 12698 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 12699 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 12702 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 12703 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 12704 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 12705 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 12708 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 12709 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 12710 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] -.sym 12711 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 12716 i_rst_b$SB_IO_IN -.sym 12717 w_debug_smi_test -.sym 12720 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 12721 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 12722 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[3] -.sym 12723 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 12738 rx_fifo.rd_addr[2] -.sym 12740 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 12741 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 12743 r_counter_$glb_clk -.sym 12744 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 12745 spi_if_ins.w_rx_data[5] -.sym 12747 spi_if_ins.w_rx_data[4] -.sym 12748 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 12750 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 12751 spi_if_ins.w_rx_data[6] -.sym 12752 spi_if_ins.w_rx_data[3] -.sym 12760 rx_fifo.wr_addr[7] -.sym 12765 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 12768 rx_fifo.wr_addr[3] -.sym 12769 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 12770 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 12771 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] -.sym 12777 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] -.sym 12779 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 12780 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 12788 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] -.sym 12792 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 12795 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 12797 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] -.sym 12798 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 12801 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 12804 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 12806 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 12807 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 12808 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] -.sym 12809 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] -.sym 12811 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] -.sym 12812 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] -.sym 12814 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 12816 w_debug_smi_test -.sym 12819 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] -.sym 12820 w_debug_smi_test -.sym 12821 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] -.sym 12822 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 12834 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 12837 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 12838 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 12840 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 12843 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] -.sym 12844 w_debug_smi_test -.sym 12845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 12846 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] -.sym 12849 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] -.sym 12850 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] -.sym 12851 w_debug_smi_test -.sym 12852 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 12865 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 12866 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 12868 w_smi_data_output[6] -.sym 12869 w_smi_data_output[0] -.sym 12870 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] -.sym 12871 w_smi_data_output[5] -.sym 12872 w_smi_data_output[4] -.sym 12875 w_smi_data_output[3] -.sym 12882 rx_fifo.mem_i.0.0_RDATA[1] -.sym 12883 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 12885 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 12887 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 12889 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 12890 io_pmod[4]$SB_IO_IN -.sym 12891 rx_fifo.rd_addr[2] -.sym 12892 spi_if_ins.w_rx_data[4] -.sym 12898 w_rx_24_fifo_data[19] -.sym 12899 w_smi_data_output[3] -.sym 12900 w_rx_24_fifo_data[27] -.sym 12902 w_debug_smi_test +.sym 12518 w_smi_data_input[7] +.sym 12519 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 12522 w_smi_data_input[3] +.sym 12523 w_tx_fifo_data[27] +.sym 12529 w_tx_fifo_data[3] +.sym 12541 w_smi_data_input[7] +.sym 12544 smi_ctrl_ins.r_fifo_pushed_data[29] +.sym 12549 smi_ctrl_ins.tx_reg_state[0] +.sym 12550 smi_ctrl_ins.r_fifo_pushed_data[25] +.sym 12552 w_smi_data_input[4] +.sym 12556 smi_ctrl_ins.r_fifo_pushed_data[17] +.sym 12558 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 12561 smi_ctrl_ins.r_fifo_pushed_data[16] +.sym 12566 smi_ctrl_ins.r_fifo_pushed_data[12] +.sym 12567 i_rst_b$SB_IO_IN +.sym 12571 smi_ctrl_ins.r_fifo_pushed_data[13] +.sym 12573 i_rst_b$SB_IO_IN +.sym 12574 w_smi_data_input[7] +.sym 12575 smi_ctrl_ins.tx_reg_state[0] +.sym 12580 smi_ctrl_ins.r_fifo_pushed_data[17] +.sym 12586 smi_ctrl_ins.r_fifo_pushed_data[16] +.sym 12592 smi_ctrl_ins.r_fifo_pushed_data[13] +.sym 12600 w_smi_data_input[4] +.sym 12603 smi_ctrl_ins.r_fifo_pushed_data[12] +.sym 12610 smi_ctrl_ins.r_fifo_pushed_data[25] +.sym 12616 smi_ctrl_ins.r_fifo_pushed_data[29] +.sym 12619 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 12620 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 12621 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O_$glb_sr +.sym 12622 smi_ctrl_ins.r_fifo_pushed_data[24] +.sym 12623 smi_ctrl_ins.r_fifo_pushed_data[23] +.sym 12624 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 12625 smi_ctrl_ins.r_fifo_pushed_data[19] +.sym 12626 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 12627 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[1] +.sym 12629 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 12634 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 12635 tx_fifo.rd_addr[0] +.sym 12636 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 12638 w_tx_fifo_data[17] +.sym 12640 w_tx_fifo_data[16] +.sym 12642 w_tx_fifo_data[13] +.sym 12643 w_smi_data_input[7] +.sym 12646 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 12647 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 12648 i_rst_b$SB_IO_IN +.sym 12649 $PACKER_VCC_NET +.sym 12650 w_tx_fifo_data[28] +.sym 12651 w_tx_fifo_data[5] +.sym 12652 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 12654 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 12655 w_tx_fifo_pulled_data[22] +.sym 12656 w_tx_fifo_data[7] +.sym 12657 i_smi_a2$SB_IO_IN +.sym 12664 w_smi_data_input[5] +.sym 12665 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 12666 smi_ctrl_ins.r_fifo_pushed_data[27] +.sym 12668 w_smi_data_input[2] +.sym 12671 smi_ctrl_ins.r_fifo_pushed_data[28] +.sym 12674 smi_ctrl_ins.r_fifo_pushed_data[21] +.sym 12687 smi_ctrl_ins.r_fifo_pushed_data[24] +.sym 12688 smi_ctrl_ins.r_fifo_pushed_data[23] +.sym 12689 w_smi_data_input[6] +.sym 12697 smi_ctrl_ins.r_fifo_pushed_data[27] +.sym 12702 w_smi_data_input[6] +.sym 12709 w_smi_data_input[5] +.sym 12716 w_smi_data_input[2] +.sym 12723 smi_ctrl_ins.r_fifo_pushed_data[24] +.sym 12729 smi_ctrl_ins.r_fifo_pushed_data[23] +.sym 12735 smi_ctrl_ins.r_fifo_pushed_data[28] +.sym 12741 smi_ctrl_ins.r_fifo_pushed_data[21] +.sym 12742 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 12743 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 12744 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O_$glb_sr +.sym 12745 lvds_tx_inst.r_fifo_data[30] +.sym 12746 lvds_tx_inst.r_fifo_data[13] +.sym 12747 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 12748 lvds_tx_inst.r_fifo_data[12] +.sym 12749 lvds_tx_inst.r_fifo_data[9] +.sym 12750 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 12751 lvds_tx_inst.r_fifo_data[8] +.sym 12752 lvds_tx_inst.r_fifo_data[22] +.sym 12757 tx_fifo.wr_addr[2] +.sym 12758 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 12759 w_tx_fifo_data[23] +.sym 12761 tx_fifo.rd_addr[2] +.sym 12763 w_tx_fifo_data[6] +.sym 12765 tx_fifo.rd_addr[5] +.sym 12767 w_tx_fifo_data[24] +.sym 12768 w_smi_data_input[5] +.sym 12774 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 12776 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 12778 tx_fifo.rd_addr[7] +.sym 12780 $PACKER_VCC_NET +.sym 12786 w_smi_data_input[2] +.sym 12793 w_smi_data_input[4] +.sym 12797 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 12799 w_smi_data_input[3] +.sym 12806 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 12807 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 12808 lvds_tx_inst.r_fifo_data[8] +.sym 12809 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 12812 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 12813 lvds_tx_inst.r_fifo_data[12] +.sym 12816 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 12817 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 12832 w_smi_data_input[4] +.sym 12840 w_smi_data_input[3] +.sym 12850 w_smi_data_input[2] +.sym 12855 lvds_tx_inst.r_fifo_data[8] +.sym 12856 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 12857 lvds_tx_inst.r_fifo_data[12] +.sym 12858 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 12861 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 12862 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 12863 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 12864 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 12865 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 12866 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 12867 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 12868 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 12869 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 12870 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 12871 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 12872 tx_fifo.wr_addr_gray_rd[5] +.sym 12873 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 12874 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] +.sym 12875 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 12876 w_smi_data_output[0] +.sym 12880 tx_fifo.rd_addr[2] +.sym 12881 tx_fifo.rd_addr[1] +.sym 12882 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 12883 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 12885 w_rx_24_fifo_data[15] +.sym 12886 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 12887 w_tx_fifo_pulled_data[13] +.sym 12888 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 12889 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] +.sym 12890 w_tx_fifo_data[12] +.sym 12891 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] +.sym 12892 $PACKER_VCC_NET +.sym 12897 tx_fifo.rd_addr_gray_wr_r[8] +.sym 12899 $PACKER_VCC_NET +.sym 12902 w_rx_24_fifo_data[4] .sym 12903 i_rst_b$SB_IO_IN -.sym 12909 w_rx_09_fifo_data[23] -.sym 12911 smi_ctrl_ins.int_cnt[3] -.sym 12912 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 12915 w_rx_09_fifo_data[22] -.sym 12917 smi_ctrl_ins.int_cnt[4] -.sym 12922 w_rx_09_fifo_data[18] -.sym 12924 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 12931 w_rx_09_fifo_data[19] -.sym 12933 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 12939 w_rx_09_fifo_data[25] -.sym 12944 w_rx_09_fifo_data[22] -.sym 12945 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 12948 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 12950 w_rx_09_fifo_data[25] -.sym 12955 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 12956 w_rx_09_fifo_data[18] -.sym 12960 smi_ctrl_ins.int_cnt[4] -.sym 12961 smi_ctrl_ins.int_cnt[3] -.sym 12962 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 12963 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 12967 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 12968 w_rx_09_fifo_data[19] -.sym 12979 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 12980 w_rx_09_fifo_data[23] -.sym 12988 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 12989 lvds_clock_$glb_clk -.sym 12990 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 12991 w_rx_24_fifo_data[23] -.sym 12992 w_rx_24_fifo_data[24] -.sym 12993 w_rx_24_fifo_data[27] -.sym 12994 w_rx_24_fifo_data[22] -.sym 12995 w_rx_24_fifo_data[25] -.sym 12996 w_rx_24_fifo_data[26] -.sym 12997 w_rx_24_fifo_data[21] -.sym 12998 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] -.sym 12999 w_rx_09_fifo_data[21] -.sym 13003 w_rx_09_fifo_data[23] -.sym 13004 rx_fifo.wr_addr[5] -.sym 13006 w_smi_data_output[5] -.sym 13007 rx_fifo.wr_addr[6] -.sym 13008 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 13009 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 13011 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 13012 w_smi_data_output[0] -.sym 13013 w_rx_09_fifo_data[21] -.sym 13014 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] -.sym 13015 w_rx_data[4] -.sym 13016 rx_fifo.mem_i.0.2_WDATA_1 -.sym 13018 spi_if_ins.w_rx_data[2] -.sym 13021 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 13024 spi_if_ins.w_rx_data[0] -.sym 13025 w_ioc[0] -.sym 13026 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 13035 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 13036 w_rx_data[2] -.sym 13038 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 13041 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 13043 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 13045 w_debug_smi_test -.sym 13046 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 13048 smi_ctrl_ins.int_cnt[4] -.sym 13049 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 13050 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 13051 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 13056 smi_ctrl_ins.int_cnt[4] -.sym 13058 smi_ctrl_ins.int_cnt[3] -.sym 13061 i_rst_b$SB_IO_IN -.sym 13063 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 13065 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 13066 smi_ctrl_ins.int_cnt[3] -.sym 13067 smi_ctrl_ins.int_cnt[4] -.sym 13068 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 13083 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 13084 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 13085 smi_ctrl_ins.int_cnt[3] -.sym 13086 smi_ctrl_ins.int_cnt[4] -.sym 13089 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 13090 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 13091 smi_ctrl_ins.int_cnt[4] -.sym 13092 smi_ctrl_ins.int_cnt[3] -.sym 13096 w_rx_data[2] -.sym 13101 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 13102 smi_ctrl_ins.int_cnt[3] -.sym 13103 smi_ctrl_ins.int_cnt[4] -.sym 13104 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 13107 smi_ctrl_ins.int_cnt[4] -.sym 13108 w_debug_smi_test -.sym 13109 smi_ctrl_ins.int_cnt[3] -.sym 13110 i_rst_b$SB_IO_IN -.sym 13111 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 13112 r_counter_$glb_clk -.sym 13114 w_ioc[2] -.sym 13115 w_ioc[3] -.sym 13117 w_ioc[0] -.sym 13118 w_cs[0] -.sym 13119 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 13120 w_ioc[4] -.sym 13121 i_rst_b$SB_IO_IN -.sym 13127 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 13128 rx_fifo.mem_i.0.0_RDATA_1[1] -.sym 13129 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 13130 w_rx_data[0] -.sym 13131 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 13132 smi_ctrl_ins.int_cnt[4] -.sym 13133 $PACKER_VCC_NET -.sym 13134 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 13135 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 13136 smi_ctrl_ins.int_cnt[3] -.sym 13137 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 13138 spi_if_ins.w_rx_data[1] -.sym 13139 w_rx_data[1] -.sym 13140 w_debug_smi_test -.sym 13143 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 13144 o_shdn_tx_lna$SB_IO_OUT -.sym 13145 io_ctrl_ins.o_pmod[2] -.sym 13146 spi_if_ins.w_rx_data[4] -.sym 13147 i_rst_b$SB_IO_IN -.sym 13148 spi_if_ins.w_rx_data[3] -.sym 13149 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 13155 channel -.sym 13157 w_rx_09_fifo_data[27] -.sym 13159 w_rx_24_fifo_data[25] -.sym 13160 w_rx_24_fifo_data[26] -.sym 13161 w_rx_data[1] -.sym 13163 w_rx_09_fifo_data[24] -.sym 13164 w_rx_24_fifo_data[24] -.sym 13165 w_rx_24_fifo_data[27] -.sym 13167 w_rx_09_fifo_data[25] -.sym 13168 w_rx_data[2] -.sym 13173 w_rx_09_fifo_data[26] -.sym 13176 w_rx_data[0] -.sym 13182 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E -.sym 13183 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13188 w_rx_24_fifo_data[24] -.sym 13189 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13190 channel -.sym 13191 w_rx_09_fifo_data[24] -.sym 13194 w_rx_24_fifo_data[27] -.sym 13195 channel -.sym 13196 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13197 w_rx_09_fifo_data[27] -.sym 13200 channel -.sym 13201 w_rx_24_fifo_data[26] -.sym 13202 w_rx_09_fifo_data[26] -.sym 13203 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13207 w_rx_data[1] -.sym 13219 w_rx_data[2] -.sym 13224 channel -.sym 13225 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13226 w_rx_24_fifo_data[25] -.sym 13227 w_rx_09_fifo_data[25] -.sym 13232 w_rx_data[0] -.sym 13234 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E -.sym 13235 r_counter_$glb_clk -.sym 13236 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13237 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 13238 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E -.sym 13239 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 13240 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E -.sym 13241 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 13242 w_fetch -.sym 13244 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 13245 channel -.sym 13249 rx_fifo.mem_i.0.2_WDATA_3 -.sym 13250 rx_fifo.wr_addr[2] -.sym 13252 rx_fifo.wr_addr[9] -.sym 13253 rx_fifo.mem_i.0.2_WDATA -.sym 13254 $io_pmod[3]$iobuf_i -.sym 13255 rx_fifo.mem_i.0.2_WDATA_2 -.sym 13256 rx_fifo.wr_addr[4] -.sym 13257 rx_fifo.wr_addr[1] -.sym 13259 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 13260 rx_fifo.wr_addr[1] -.sym 13261 w_rx_data[2] -.sym 13263 w_ioc[0] -.sym 13265 w_rx_data[1] -.sym 13267 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 13269 w_rx_data[4] -.sym 13270 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 13280 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 13298 spi_if_ins.w_rx_data[1] -.sym 13306 spi_if_ins.w_rx_data[4] -.sym 13308 spi_if_ins.w_rx_data[3] -.sym 13314 spi_if_ins.w_rx_data[4] -.sym 13329 spi_if_ins.w_rx_data[3] -.sym 13347 spi_if_ins.w_rx_data[1] -.sym 13357 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 12925 tx_fifo.rd_addr[0] +.sym 12926 tx_fifo.rd_addr[5] +.sym 12929 tx_fifo.rd_addr[1] +.sym 12931 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 12932 tx_fifo.rd_addr[2] +.sym 12936 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 12937 tx_fifo.rd_addr[7] +.sym 12938 tx_fifo.rd_addr[6] +.sym 12941 $nextpnr_ICESTORM_LC_4$O +.sym 12944 tx_fifo.rd_addr[0] +.sym 12947 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 12949 tx_fifo.rd_addr[1] +.sym 12951 tx_fifo.rd_addr[0] +.sym 12953 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 12955 tx_fifo.rd_addr[2] +.sym 12957 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 12959 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 12961 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 12963 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 12965 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 12968 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 12969 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 12971 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 12974 tx_fifo.rd_addr[5] +.sym 12975 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 12977 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 12980 tx_fifo.rd_addr[6] +.sym 12981 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 12983 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 12986 tx_fifo.rd_addr[7] +.sym 12987 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 12991 tx_fifo.rd_addr_gray[1] +.sym 12992 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 12993 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 12994 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 12995 tx_fifo.rd_addr[7] +.sym 12996 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 12997 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 12998 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 13005 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 13007 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 13008 w_tx_fifo_data[25] +.sym 13012 lvds_tx_inst.r_fifo_data[28] +.sym 13013 w_tx_fifo_data[22] +.sym 13015 w_tx_fifo_data[3] +.sym 13016 tx_fifo.rd_addr[7] +.sym 13017 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] +.sym 13019 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 13021 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.sym 13023 tx_fifo.rd_addr_gray_wr_r[8] +.sym 13024 tx_fifo.rd_addr[6] +.sym 13025 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 13026 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13027 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 13033 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 13034 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 13035 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 13037 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] +.sym 13038 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] +.sym 13039 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] +.sym 13041 tx_fifo.wr_addr_gray[4] +.sym 13042 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 13043 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[1] +.sym 13045 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 13046 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] +.sym 13047 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 13049 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13050 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 13053 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 13058 tx_fifo.wr_addr_gray_rd[4] +.sym 13059 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 13061 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 13062 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13064 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 13066 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13068 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 13073 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13074 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 13077 tx_fifo.wr_addr_gray[4] +.sym 13083 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 13084 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 13085 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 13086 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 13089 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 13090 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] +.sym 13091 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] +.sym 13092 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] +.sym 13097 tx_fifo.wr_addr_gray_rd[4] +.sym 13101 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 13102 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 13103 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 13107 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 13108 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 13109 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] +.sym 13110 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[1] +.sym 13112 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13114 tx_fifo.wr_addr_gray_rd_r[0] +.sym 13115 tx_fifo.empty_o_SB_LUT4_I3_I1[0] +.sym 13116 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 13117 tx_fifo.wr_addr_gray_rd[8] +.sym 13118 tx_fifo.wr_addr_gray_rd_r[9] +.sym 13119 tx_fifo.wr_addr_gray_rd[7] +.sym 13120 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1] +.sym 13121 tx_fifo.wr_addr_gray_rd[6] +.sym 13124 w_rx_24_fifo_data[4] +.sym 13125 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 13127 tx_fifo.wr_addr_gray[4] +.sym 13128 smi_ctrl_ins.int_cnt_rx[3] +.sym 13130 tx_fifo.rd_addr[2] +.sym 13131 w_tx_fifo_data[31] +.sym 13133 w_rx_24_fifo_data[5] +.sym 13135 w_tx_fifo_data[18] +.sym 13136 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 13137 w_tx_fifo_data[20] +.sym 13139 w_tx_fifo_pulled_data[22] +.sym 13140 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 13141 $PACKER_VCC_NET +.sym 13143 i_rst_b$SB_IO_IN +.sym 13144 i_rst_b$SB_IO_IN +.sym 13145 w_rx_24_fifo_data[7] +.sym 13147 w_tx_fifo_pull +.sym 13148 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13149 i_smi_a2$SB_IO_IN +.sym 13155 tx_fifo.empty_o_SB_LUT4_I3_I1[1] +.sym 13159 tx_fifo.rd_addr[7] +.sym 13161 tx_fifo.wr_addr_gray[1] +.sym 13164 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13166 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 13167 tx_fifo.empty_o_SB_LUT4_I3_I1[2] +.sym 13170 w_tx_fifo_empty +.sym 13172 tx_fifo.empty_o_SB_LUT4_I3_I1[0] +.sym 13174 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13175 tx_fifo.rd_addr[6] +.sym 13177 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1] +.sym 13182 tx_fifo.wr_addr_gray_rd[8] +.sym 13183 tx_fifo.wr_addr_gray_rd_r[9] +.sym 13185 tx_fifo.wr_addr_gray_rd[1] +.sym 13188 tx_fifo.rd_addr[7] +.sym 13190 tx_fifo.rd_addr[6] +.sym 13200 tx_fifo.empty_o_SB_LUT4_I3_I1[1] +.sym 13201 tx_fifo.empty_o_SB_LUT4_I3_I1[0] +.sym 13202 w_tx_fifo_empty +.sym 13203 tx_fifo.empty_o_SB_LUT4_I3_I1[2] +.sym 13207 tx_fifo.wr_addr_gray_rd[8] +.sym 13212 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 13213 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13214 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13215 tx_fifo.wr_addr_gray_rd_r[9] +.sym 13219 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1] +.sym 13221 tx_fifo.rd_addr[7] +.sym 13226 tx_fifo.wr_addr_gray[1] +.sym 13232 tx_fifo.wr_addr_gray_rd[1] +.sym 13235 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13237 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 13238 tx_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 13239 tx_fifo.rd_addr_gray[8] +.sym 13240 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13241 tx_fifo.rd_addr[6] +.sym 13242 tx_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 13243 tx_fifo.rd_addr_gray[7] +.sym 13244 i_rst_b$SB_IO_IN +.sym 13250 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 13255 w_tx_fifo_data[2] +.sym 13258 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 13262 tx_fifo.rd_addr[6] +.sym 13267 $PACKER_VCC_NET +.sym 13271 i_rst_b$SB_IO_IN +.sym 13272 tx_fifo.rd_addr[5] +.sym 13279 tx_fifo.rd_addr_gray_wr[7] +.sym 13281 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 13284 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 13288 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 13291 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 13293 tx_fifo.rd_addr_gray_wr[8] +.sym 13296 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13297 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13301 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[1] +.sym 13303 i_rst_b$SB_IO_IN +.sym 13304 tx_fifo.rd_addr_gray[8] +.sym 13308 tx_fifo.rd_addr_gray[7] +.sym 13309 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 13311 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13312 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 13313 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 13314 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 13319 tx_fifo.rd_addr_gray[7] +.sym 13323 i_rst_b$SB_IO_IN +.sym 13325 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 13329 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[1] +.sym 13330 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 13331 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 13337 tx_fifo.rd_addr_gray_wr[8] +.sym 13341 tx_fifo.rd_addr_gray_wr[7] +.sym 13355 tx_fifo.rd_addr_gray[8] .sym 13358 r_counter_$glb_clk -.sym 13360 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 13362 w_tx_data_io[2] -.sym 13363 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 13364 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13366 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[0] -.sym 13367 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 13374 rx_fifo.mem_i.0.0_RDATA[1] -.sym 13380 rx_fifo.wr_addr[9] -.sym 13383 io_pmod[0]$SB_IO_IN -.sym 13384 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 13385 io_ctrl_ins.debug_mode[0] -.sym 13387 w_rx_data[3] -.sym 13388 channel -.sym 13391 w_cs[1] -.sym 13393 w_rx_data[1] -.sym 13401 w_rx_24_fifo_data[14] -.sym 13403 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E -.sym 13406 channel -.sym 13414 channel -.sym 13418 w_rx_09_fifo_data[14] -.sym 13422 w_rx_09_fifo_data[12] -.sym 13423 i_button_SB_LUT4_I0_I1[2] -.sym 13424 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 13428 w_rx_09_fifo_data[29] -.sym 13429 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13430 w_rx_24_fifo_data[29] -.sym 13432 w_rx_24_fifo_data[12] -.sym 13434 i_button_SB_LUT4_I0_I1[2] -.sym 13449 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 13452 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13453 w_rx_24_fifo_data[12] -.sym 13454 w_rx_09_fifo_data[12] -.sym 13455 channel -.sym 13458 w_rx_24_fifo_data[14] -.sym 13459 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13460 channel -.sym 13461 w_rx_09_fifo_data[14] -.sym 13464 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 13465 w_rx_09_fifo_data[29] -.sym 13466 channel -.sym 13467 w_rx_24_fifo_data[29] -.sym 13480 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 13361 $PACKER_VCC_NET +.sym 13362 spi_if_ins.spi.r_tx_bit_count[2] +.sym 13363 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 13364 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 13365 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 13366 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 13367 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] +.sym 13372 i_glob_clock$SB_IO_IN +.sym 13373 tx_fifo.rd_addr[2] +.sym 13374 tx_fifo.rd_addr_gray_wr_r[7] +.sym 13375 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 13376 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 13377 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.sym 13378 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 13379 tx_fifo.rd_addr[5] +.sym 13380 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 13381 tx_fifo.rd_addr[1] +.sym 13385 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 13387 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R +.sym 13388 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 13389 tx_fifo.rd_addr_gray_wr_r[8] +.sym 13390 i_rst_b$SB_IO_IN +.sym 13393 i_rst_b$SB_IO_IN +.sym 13394 w_rx_24_fifo_data[4] +.sym 13395 $PACKER_VCC_NET +.sym 13403 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 13404 spi_if_ins.r_tx_data_valid +.sym 13405 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 13406 i_ss$SB_IO_IN +.sym 13407 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 13408 lvds_rx_24_inst.r_phase_count[1] +.sym 13412 lvds_rx_24_inst.r_phase_count[0] +.sym 13413 i_rst_b$SB_IO_IN +.sym 13414 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13416 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13418 $PACKER_VCC_NET +.sym 13420 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 13426 $PACKER_VCC_NET +.sym 13428 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 13432 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 13433 $nextpnr_ICESTORM_LC_8$O +.sym 13436 lvds_rx_24_inst.r_phase_count[0] +.sym 13439 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q_SB_LUT4_O_I3[2] +.sym 13441 $PACKER_VCC_NET +.sym 13442 lvds_rx_24_inst.r_phase_count[1] +.sym 13443 lvds_rx_24_inst.r_phase_count[0] +.sym 13446 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 13447 $PACKER_VCC_NET +.sym 13449 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q_SB_LUT4_O_I3[2] +.sym 13455 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 13464 i_rst_b$SB_IO_IN +.sym 13465 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 13466 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 13471 i_ss$SB_IO_IN +.sym 13473 spi_if_ins.r_tx_data_valid +.sym 13476 i_rst_b$SB_IO_IN +.sym 13477 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13478 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 13479 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 13480 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E .sym 13481 r_counter_$glb_clk -.sym 13482 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13483 w_tx_data_io[0] -.sym 13484 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] -.sym 13485 w_tx_data_io[1] -.sym 13486 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 13487 i_button_SB_LUT4_I0_I2[2] -.sym 13488 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 13489 i_button_SB_LUT4_I0_I1[2] -.sym 13490 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] -.sym 13496 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[0] -.sym 13497 rx_fifo.mem_i.0.3_WDATA_1 -.sym 13498 rx_fifo.wr_addr[8] -.sym 13499 rx_fifo.wr_addr[6] -.sym 13503 rx_fifo.mem_q.0.3_WDATA_3 -.sym 13505 rx_fifo.mem_q.0.3_WDATA_2 -.sym 13506 rx_fifo.wr_addr[6] -.sym 13507 w_rx_data[4] -.sym 13510 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 13512 w_rx_data[4] -.sym 13513 w_ioc[0] -.sym 13516 w_rx_data[3] -.sym 13524 w_rx_data[0] -.sym 13533 w_rx_data[2] -.sym 13536 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13541 w_rx_data[4] -.sym 13547 w_rx_data[3] -.sym 13551 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 13553 w_rx_data[1] -.sym 13566 w_rx_data[2] -.sym 13572 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13575 w_rx_data[4] -.sym 13583 w_rx_data[1] -.sym 13595 w_rx_data[0] -.sym 13601 w_rx_data[3] -.sym 13603 io_ctrl_ins.rf_mode_SB_DFFER_Q_E -.sym 13604 r_counter_$glb_clk -.sym 13605 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 13606 i_button_SB_LUT4_I0_I1[3] -.sym 13607 i_button_SB_LUT4_I0_I2[1] -.sym 13608 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 13609 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] -.sym 13610 io_ctrl_ins.pmod_dir_state[4] -.sym 13611 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 13612 io_ctrl_ins.pmod_dir_state[2] -.sym 13613 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] -.sym 13620 rx_fifo.mem_q.0.3_RDATA_1[0] -.sym 13621 $PACKER_VCC_NET -.sym 13624 o_led1$SB_IO_OUT -.sym 13628 rx_fifo.mem_i.0.3_WDATA -.sym 13630 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 13631 w_rx_data[1] -.sym 13633 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13634 w_tx_data_smi[0] +.sym 13482 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13483 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 13484 spi_if_ins.spi.SCKr[0] +.sym 13485 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 13486 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] +.sym 13487 spi_if_ins.spi.SCKr[2] +.sym 13488 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 13489 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 13490 spi_if_ins.spi.SCKr[1] +.sym 13495 w_rx_24_fifo_data[26] +.sym 13497 w_rx_24_fifo_data[10] +.sym 13498 lvds_rx_24_inst.r_phase_count[0] +.sym 13499 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[1] +.sym 13500 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 13501 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 13504 $PACKER_VCC_NET +.sym 13505 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 13507 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13510 w_load +.sym 13511 w_tx_fifo_pull +.sym 13517 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13518 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 13526 spi_if_ins.state_if[1] +.sym 13527 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 13528 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 13529 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13532 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13534 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13535 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 13536 rx_fifo.rd_addr_gray[3] +.sym 13538 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 13539 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13540 spi_if_ins.state_if[0] +.sym 13541 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 13543 spi_if_ins.state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] +.sym 13545 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 13546 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 13549 i_rst_b$SB_IO_IN +.sym 13550 rx_fifo.rd_addr_gray_wr[3] +.sym 13553 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 13554 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13557 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 13560 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 13563 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 13564 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 13565 spi_if_ins.state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] +.sym 13566 i_rst_b$SB_IO_IN +.sym 13572 rx_fifo.rd_addr_gray[3] +.sym 13575 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13576 spi_if_ins.state_if[0] +.sym 13577 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13578 spi_if_ins.state_if[1] +.sym 13582 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 13583 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 13584 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 13587 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13588 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 13590 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 13593 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 13594 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13596 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13601 rx_fifo.rd_addr_gray_wr[3] +.sym 13604 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13606 spi_if_ins.spi.r_tx_byte[3] +.sym 13607 spi_if_ins.spi.r_tx_byte[4] +.sym 13608 spi_if_ins.spi.r_tx_byte[7] +.sym 13609 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 13610 spi_if_ins.spi.r_tx_byte[6] +.sym 13611 spi_if_ins.spi.r_tx_byte[5] +.sym 13612 spi_if_ins.spi.r_tx_byte[2] +.sym 13613 spi_if_ins.spi.r_tx_byte[1] +.sym 13615 w_tx_fifo_data[21] +.sym 13622 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13630 w_rx_24_fifo_data[29] +.sym 13632 w_rx_24_fifo_data[7] +.sym 13633 i_smi_a2$SB_IO_IN +.sym 13634 w_rx_24_fifo_data[25] .sym 13635 i_rst_b$SB_IO_IN -.sym 13638 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13639 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 13640 o_shdn_tx_lna$SB_IO_OUT -.sym 13641 i_button_SB_LUT4_I0_I2[3] -.sym 13649 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 13650 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13651 i_button_SB_LUT4_I0_I2[2] -.sym 13652 channel -.sym 13653 io_ctrl_ins.debug_mode[0] -.sym 13654 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 13659 io_ctrl_ins.debug_mode[1] -.sym 13660 io_pmod[4]$SB_IO_IN -.sym 13661 io_ctrl_ins.debug_mode[0] -.sym 13662 i_button_SB_LUT4_I0_I2[3] -.sym 13671 i_rst_b$SB_IO_IN -.sym 13681 io_ctrl_ins.debug_mode[0] -.sym 13683 io_ctrl_ins.debug_mode[1] -.sym 13695 channel -.sym 13710 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 13712 io_ctrl_ins.debug_mode[1] -.sym 13718 io_pmod[4]$SB_IO_IN -.sym 13722 i_rst_b$SB_IO_IN -.sym 13723 io_ctrl_ins.debug_mode[0] -.sym 13724 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13725 i_button_SB_LUT4_I0_I2[3] -.sym 13726 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13636 w_rx_24_fifo_data[2] +.sym 13639 w_tx_fifo_pull +.sym 13641 $PACKER_VCC_NET +.sym 13648 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 13651 i_rst_b$SB_IO_IN +.sym 13652 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 13654 spi_if_ins.state_if[1] +.sym 13656 spi_if_ins.state_if[0] +.sym 13657 spi_if_ins.r_tx_byte[0] +.sym 13659 i_rst_b$SB_IO_IN +.sym 13660 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 13662 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13663 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13671 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13674 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 13678 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13680 spi_if_ins.state_if[0] +.sym 13681 spi_if_ins.state_if[1] +.sym 13686 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 13687 i_rst_b$SB_IO_IN +.sym 13688 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 13698 i_rst_b$SB_IO_IN +.sym 13699 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 13700 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13701 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13711 spi_if_ins.state_if[0] +.sym 13712 spi_if_ins.state_if[1] +.sym 13713 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13717 spi_if_ins.r_tx_byte[0] +.sym 13723 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13725 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 13726 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .sym 13727 r_counter_$glb_clk -.sym 13728 i_button_SB_LUT4_I0_I2[2] -.sym 13729 io_ctrl_ins.o_pmod[0] -.sym 13730 io_ctrl_ins.o_pmod[1] -.sym 13731 io_ctrl_ins.o_pmod[3] -.sym 13732 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] -.sym 13733 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 13734 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 13735 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 13736 io_ctrl_ins.o_pmod[4] -.sym 13743 rx_fifo.mem_q.0.3_RDATA_3[1] -.sym 13747 rx_fifo.wr_addr[8] -.sym 13749 rx_fifo.wr_addr[9] -.sym 13750 i_config[0]$SB_IO_IN -.sym 13751 io_pmod[3]$SB_IO_IN -.sym 13754 w_tx_data_smi[1] -.sym 13755 w_ioc[0] -.sym 13756 o_tr_vc1$SB_IO_OUT +.sym 13728 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 13729 spi_if_ins.r_tx_byte[3] +.sym 13730 spi_if_ins.r_tx_byte[5] +.sym 13731 spi_if_ins.r_tx_byte[1] +.sym 13732 r_tx_data_SB_DFFE_Q_E +.sym 13733 spi_if_ins.r_tx_byte[6] +.sym 13734 spi_if_ins.r_tx_byte[2] +.sym 13735 spi_if_ins.r_tx_byte[7] +.sym 13736 spi_if_ins.r_tx_byte[4] +.sym 13741 spi_if_ins.w_rx_data[5] +.sym 13749 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] .sym 13757 i_rst_b$SB_IO_IN -.sym 13758 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 13760 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 13762 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 13770 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13771 w_rx_data[3] -.sym 13772 io_ctrl_ins.rf_mode[0] -.sym 13773 w_rx_data[0] -.sym 13774 w_rx_data[4] -.sym 13778 w_rx_data[2] -.sym 13784 i_button_SB_LUT4_I0_I2[3] -.sym 13788 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 13790 w_rx_data[1] -.sym 13793 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13804 w_rx_data[2] -.sym 13811 w_rx_data[0] -.sym 13815 w_rx_data[4] -.sym 13822 w_rx_data[1] -.sym 13827 io_ctrl_ins.rf_mode[0] -.sym 13828 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13829 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13830 i_button_SB_LUT4_I0_I2[3] -.sym 13833 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13834 io_ctrl_ins.rf_mode[0] -.sym 13845 w_rx_data[3] -.sym 13849 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 13850 r_counter_$glb_clk -.sym 13853 io_ctrl_ins.rf_pin_state[5] -.sym 13854 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 13855 io_ctrl_ins.rf_pin_state[7] -.sym 13856 io_ctrl_ins.rf_pin_state[6] -.sym 13857 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] -.sym 13864 io_pmod[0]$SB_IO_IN -.sym 13869 w_rx_24_fifo_data[13] -.sym 13877 i_rst_b$SB_IO_IN -.sym 13880 o_tr_vc1_b$SB_IO_OUT -.sym 13893 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13895 io_ctrl_ins.rf_pin_state[4] -.sym 13896 io_ctrl_ins.rf_pin_state[1] -.sym 13897 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 13898 i_button_SB_LUT4_I0_I2[3] -.sym 13900 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 13901 io_ctrl_ins.rf_pin_state[2] -.sym 13902 io_ctrl_ins.rf_pin_state[0] -.sym 13903 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13904 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13906 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 13910 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13911 i_button_SB_LUT4_I0_I2[3] -.sym 13912 io_ctrl_ins.rf_pin_state[7] -.sym 13918 io_ctrl_ins.rf_pin_state[5] -.sym 13920 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 13921 io_ctrl_ins.rf_pin_state[6] -.sym 13926 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13927 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 13928 i_button_SB_LUT4_I0_I2[3] -.sym 13929 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13932 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13933 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13934 i_button_SB_LUT4_I0_I2[3] -.sym 13935 io_ctrl_ins.rf_pin_state[0] -.sym 13938 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 13939 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13941 io_ctrl_ins.rf_pin_state[7] -.sym 13944 io_ctrl_ins.rf_pin_state[6] -.sym 13945 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 13946 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13950 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13952 i_button_SB_LUT4_I0_I2[3] -.sym 13953 io_ctrl_ins.rf_pin_state[1] -.sym 13956 i_button_SB_LUT4_I0_I2[3] -.sym 13957 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13958 io_ctrl_ins.rf_pin_state[2] -.sym 13959 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 13962 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 13963 i_button_SB_LUT4_I0_I2[3] -.sym 13964 io_ctrl_ins.rf_pin_state[4] -.sym 13965 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13968 i_button_SB_LUT4_I0_I2[3] -.sym 13969 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 13970 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 13971 io_ctrl_ins.rf_pin_state[5] -.sym 13972 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_O -.sym 13973 r_counter_$glb_clk -.sym 13989 o_shdn_tx_lna$SB_IO_OUT -.sym 13991 $PACKER_VCC_NET -.sym 13993 o_rx_h_tx_l$SB_IO_OUT -.sym 13994 i_button_SB_LUT4_I0_I2[3] -.sym 13995 o_rx_h_tx_l_b$SB_IO_OUT -.sym 14008 o_tr_vc1_b$SB_IO_OUT -.sym 14113 o_tr_vc2$SB_IO_OUT +.sym 13760 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 13762 i_rst_b$SB_IO_IN +.sym 13770 i_glob_clock$SB_IO_IN +.sym 13775 w_cs[0] +.sym 13778 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 13779 w_tx_data_sys[0] +.sym 13780 w_load +.sym 13783 w_cs[0] +.sym 13784 i_button_SB_LUT4_I0_I1[0] +.sym 13786 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 13787 w_cs[3] +.sym 13788 w_cs[2] +.sym 13790 w_cs[3] +.sym 13791 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 13794 w_fetch +.sym 13795 i_rst_b$SB_IO_IN +.sym 13796 w_cs[1] +.sym 13797 r_tx_data_SB_DFFE_Q_E +.sym 13801 smi_ctrl_ins.r_channel_SB_DFFE_Q_E_SB_LUT4_O_I3[1] +.sym 13803 w_cs[3] +.sym 13804 w_cs[1] +.sym 13805 w_cs[2] +.sym 13806 w_cs[0] +.sym 13817 smi_ctrl_ins.r_channel_SB_DFFE_Q_E_SB_LUT4_O_I3[1] +.sym 13818 i_button_SB_LUT4_I0_I1[0] +.sym 13827 w_tx_data_sys[0] +.sym 13828 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 13829 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 13830 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 13833 w_cs[1] +.sym 13834 w_cs[0] +.sym 13835 w_cs[3] +.sym 13836 w_cs[2] +.sym 13845 w_load +.sym 13846 i_rst_b$SB_IO_IN +.sym 13847 w_fetch +.sym 13848 w_cs[2] +.sym 13849 r_tx_data_SB_DFFE_Q_E +.sym 13850 i_glob_clock$SB_IO_IN +.sym 13852 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 13853 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 13854 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[0] +.sym 13855 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 13856 w_tx_fifo_pull +.sym 13857 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 13858 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1] +.sym 13859 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 13860 r_tx_data[3] +.sym 13865 w_tx_data_sys[0] +.sym 13873 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 13876 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 13877 smi_ctrl_ins.r_channel_SB_DFFE_Q_E +.sym 13878 w_rx_24_fifo_data[4] +.sym 13880 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R +.sym 13881 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 13883 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 13885 i_rst_b$SB_IO_IN +.sym 13886 i_rst_b$SB_IO_IN +.sym 13887 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 13893 w_rx_24_fifo_data[26] +.sym 13898 w_fetch +.sym 13901 w_rx_24_fifo_data[5] +.sym 13902 w_cs[2] +.sym 13905 w_rx_24_fifo_data[6] +.sym 13906 w_rx_24_fifo_data[25] +.sym 13908 w_rx_24_fifo_data[2] +.sym 13911 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[0] +.sym 13913 w_rx_24_fifo_data[27] +.sym 13917 i_rst_b$SB_IO_IN +.sym 13919 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13920 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 13927 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13928 w_rx_24_fifo_data[27] +.sym 13932 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13934 w_rx_24_fifo_data[5] +.sym 13938 w_cs[2] +.sym 13939 w_fetch +.sym 13940 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[0] +.sym 13941 i_rst_b$SB_IO_IN +.sym 13950 w_rx_24_fifo_data[25] +.sym 13951 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13958 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13959 w_rx_24_fifo_data[2] +.sym 13963 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13964 w_rx_24_fifo_data[26] +.sym 13968 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 13970 w_rx_24_fifo_data[6] +.sym 13972 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 13973 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 13974 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 13976 w_tx_data_io[2] +.sym 13980 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 13981 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 13984 i_button_SB_LUT4_I0_I1[0] +.sym 13988 w_cs[2] +.sym 13989 i_button_SB_LUT4_I0_I1[0] +.sym 13990 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 13994 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 13995 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 13996 w_cs[3] +.sym 14003 w_tx_fifo_pull +.sym 14005 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 14007 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 14018 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 14023 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 14031 w_rx_fifo_full +.sym 14041 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 14042 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 14050 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 14052 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 14085 w_rx_fifo_full +.sym 14086 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 14087 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 14088 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 14095 lvds_rx_24_inst.o_fifo_push_SB_DFFER_Q_E +.sym 14096 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 14097 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14101 io_ctrl_ins.o_pmod[2] +.sym 14105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] +.sym 14110 w_fetch +.sym 14112 w_cs[1] +.sym 14116 w_cs[1] +.sym 14123 i_button_SB_LUT4_I0_I1[1] .sym 14131 i_rst_b$SB_IO_IN +.sym 14151 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 14157 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 14209 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 14218 sys_ctrl_ins.o_data_out_SB_DFFER_Q_E +.sym 14219 r_counter_$glb_clk +.sym 14220 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14221 i_rst_b$SB_IO_IN +.sym 14223 io_ctrl_ins.rf_pin_state[2] .sym 14249 i_rst_b$SB_IO_IN -.sym 14270 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 14277 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 14282 i_rst_b$SB_IO_IN -.sym 14316 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 14325 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 14326 i_rst_b$SB_IO_IN +.sym 14277 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 14321 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] .sym 14344 i_rst_b$SB_IO_IN -.sym 14352 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 14365 i_rst_b$SB_IO_IN -.sym 14388 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14401 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R -.sym 14418 i_rst_b_SB_LUT4_I3_O +.sym 14362 o_shdn_tx_lna$SB_IO_OUT +.sym 14373 i_rst_b$SB_IO_IN +.sym 14388 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14410 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R +.sym 14418 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O .sym 14419 w_smi_data_output[3] -.sym 14421 i_smi_a2$rename$0 -.sym 14430 w_smi_data_output[3] -.sym 14436 i_smi_a2$rename$0 -.sym 14440 i_rst_b_SB_LUT4_I3_O -.sym 14445 spi_if_ins.spi.r2_rx_done -.sym 14446 smi_ctrl_ins.soe_and_reset -.sym 14458 spi_if_ins.w_rx_data[1] -.sym 14466 spi_if_ins.w_rx_data[3] +.sym 14421 i_smi_a2$SB_IO_IN +.sym 14425 $PACKER_VCC_NET +.sym 14430 $PACKER_VCC_NET +.sym 14434 w_smi_data_output[3] +.sym 14438 i_smi_a2$SB_IO_IN +.sym 14440 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O +.sym 14444 w_tx_fifo_push +.sym 14446 smi_ctrl_ins.r_fifo_push_1 +.sym 14448 smi_ctrl_ins.r_fifo_push +.sym 14450 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 14455 smi_ctrl_ins.modem_tx_ctrl_SB_DFFNESR_Q_E +.sym 14462 $PACKER_VCC_NET +.sym 14472 w_smi_data_output[3] .sym 14474 i_rst_b$SB_IO_IN -.sym 14476 i_smi_a2$rename$0 +.sym 14476 w_smi_data_input[4] +.sym 14478 w_smi_data_input[5] +.sym 14490 i_smi_swe_srw$SB_IO_IN +.sym 14495 w_smi_data_input[6] +.sym 14504 $PACKER_VCC_NET +.sym 14506 smi_ctrl_ins.tx_reg_state[3] .sym 14510 i_rst_b$SB_IO_IN -.sym 14546 i_rst_b$SB_IO_IN -.sym 14572 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 14573 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 14575 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 14576 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 14577 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 14578 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 14579 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 14595 i_rst_b$SB_IO_IN -.sym 14597 i_smi_soe_se$SB_IO_IN -.sym 14614 spi_if_ins.w_rx_data[0] -.sym 14626 spi_if_ins.w_rx_data[5] -.sym 14627 w_smi_data_output[4] -.sym 14649 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 14650 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 14658 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 14663 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 14664 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 14667 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 14676 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_E -.sym 14680 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 14682 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 14688 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 14689 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 14695 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 14696 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 14701 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 14703 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 14706 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 14718 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 14720 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 14724 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 14725 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 14728 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_E -.sym 14729 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 14513 smi_ctrl_ins.modem_tx_ctrl_SB_DFFNESR_Q_E +.sym 14516 w_smi_data_input[7] +.sym 14538 w_smi_data_input[6] +.sym 14539 w_smi_data_input[7] +.sym 14543 smi_ctrl_ins.tx_reg_state[3] +.sym 14544 w_smi_data_input[7] +.sym 14552 $PACKER_VCC_NET +.sym 14555 i_smi_swe_srw$SB_IO_IN +.sym 14556 i_rst_b$SB_IO_IN +.sym 14565 smi_ctrl_ins.modem_tx_ctrl_SB_DFFNESR_Q_E +.sym 14566 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 14567 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14568 i_smi_swe_srw$SB_IO_IN +.sym 14573 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 14574 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 14575 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 14576 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 14577 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 14578 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 14579 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 14584 tx_fifo.wr_addr[5] +.sym 14585 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 14590 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 14591 w_tx_fifo_push +.sym 14592 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 14594 i_rst_b$SB_IO_IN +.sym 14597 w_smi_data_input[6] +.sym 14600 smi_ctrl_ins.tx_reg_state[3] +.sym 14602 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 14607 smi_ctrl_ins.tx_reg_state[3] +.sym 14610 smi_ctrl_ins.tx_reg_state[2] +.sym 14611 smi_ctrl_ins.tx_reg_state[1] +.sym 14614 w_smi_data_input[6] +.sym 14620 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 14621 $PACKER_VCC_NET +.sym 14622 w_tx_fifo_push +.sym 14629 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 14633 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.sym 14638 smi_ctrl_ins.r_fifo_pushed_data[19] +.sym 14649 smi_ctrl_ins.tx_reg_state[0] +.sym 14651 w_smi_data_input[7] +.sym 14652 smi_ctrl_ins.modem_tx_ctrl +.sym 14657 w_smi_data_input[5] +.sym 14660 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 14661 w_smi_data_input[4] +.sym 14663 smi_ctrl_ins.tx_reg_state[3] +.sym 14665 smi_ctrl_ins.tx_reg_state[2] +.sym 14668 smi_ctrl_ins.tx_reg_state[1] +.sym 14669 w_smi_data_input[6] +.sym 14680 i_rst_b$SB_IO_IN +.sym 14684 w_smi_data_input[6] +.sym 14689 smi_ctrl_ins.tx_reg_state[0] +.sym 14690 smi_ctrl_ins.tx_reg_state[3] +.sym 14697 w_smi_data_input[4] +.sym 14700 smi_ctrl_ins.tx_reg_state[3] +.sym 14701 smi_ctrl_ins.tx_reg_state[2] +.sym 14702 smi_ctrl_ins.tx_reg_state[1] +.sym 14706 smi_ctrl_ins.tx_reg_state[0] +.sym 14708 i_rst_b$SB_IO_IN +.sym 14712 smi_ctrl_ins.modem_tx_ctrl +.sym 14718 i_rst_b$SB_IO_IN +.sym 14720 w_smi_data_input[7] +.sym 14721 smi_ctrl_ins.tx_reg_state[1] +.sym 14726 w_smi_data_input[5] +.sym 14728 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_9_E +.sym 14729 smi_ctrl_ins.swe_and_reset_$glb_clk .sym 14730 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 14731 spi_if_ins.spi.r_rx_byte[2] -.sym 14732 spi_if_ins.spi.r_rx_byte[4] -.sym 14733 spi_if_ins.spi.r_rx_byte[6] -.sym 14734 spi_if_ins.spi.r_rx_byte[5] -.sym 14735 spi_if_ins.spi.r_rx_byte[7] -.sym 14736 spi_if_ins.spi.r_rx_byte[0] -.sym 14737 spi_if_ins.spi.r_rx_byte[3] -.sym 14738 spi_if_ins.spi.r_rx_byte[1] -.sym 14743 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 14747 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 14752 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 14754 i_mosi$SB_IO_IN -.sym 14755 w_smi_data_output[6] -.sym 14758 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 14764 spi_if_ins.spi.r2_rx_done -.sym 14772 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 14773 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 14774 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 14775 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 14776 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 14779 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 14781 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[0] -.sym 14782 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] -.sym 14786 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 14793 spi_if_ins.spi.r_rx_byte[0] -.sym 14795 spi_if_ins.spi.r_rx_byte[1] -.sym 14796 spi_if_ins.spi.r_rx_byte[2] -.sym 14797 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 14799 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 14806 spi_if_ins.spi.r_rx_byte[0] -.sym 14811 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 14812 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 14813 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 14814 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 14817 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 14818 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 14819 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 14820 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 14823 spi_if_ins.spi.r_rx_byte[2] -.sym 14837 spi_if_ins.spi.r_rx_byte[1] -.sym 14842 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 14847 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] -.sym 14850 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[0] -.sym 14851 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 14852 r_counter_$glb_clk -.sym 14855 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 14856 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 14857 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 14859 spi_if_ins.spi.r3_rx_done -.sym 14861 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 14862 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 14877 i_mosi$SB_IO_IN -.sym 14878 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] -.sym 14879 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 14881 spi_if_ins.w_rx_data[2] -.sym 14886 spi_if_ins.w_rx_data[5] -.sym 14888 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 14889 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 14897 spi_if_ins.spi.r_rx_byte[6] -.sym 14901 spi_if_ins.spi.r_rx_byte[3] -.sym 14902 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 14904 spi_if_ins.spi.r_rx_byte[4] -.sym 14906 spi_if_ins.spi.r_rx_byte[5] -.sym 14907 spi_if_ins.spi.r_rx_byte[7] -.sym 14913 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 14925 w_debug_smi_test -.sym 14926 i_rst_b$SB_IO_IN -.sym 14930 spi_if_ins.spi.r_rx_byte[5] -.sym 14940 spi_if_ins.spi.r_rx_byte[4] -.sym 14948 spi_if_ins.spi.r_rx_byte[7] -.sym 14958 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 14960 w_debug_smi_test -.sym 14961 i_rst_b$SB_IO_IN -.sym 14964 spi_if_ins.spi.r_rx_byte[6] -.sym 14971 spi_if_ins.spi.r_rx_byte[3] -.sym 14974 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 14975 r_counter_$glb_clk -.sym 14978 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] -.sym 14979 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] -.sym 14980 w_rx_09_fifo_data[22] -.sym 14981 w_rx_09_fifo_data[23] -.sym 14982 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] -.sym 14983 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] -.sym 14988 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 14989 spi_if_ins.w_rx_data[5] -.sym 14992 rx_fifo.wr_addr[0] -.sym 14994 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 14995 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 14997 $io_pmod[4]$iobuf_i -.sym 14999 io_pmod[1]$SB_IO_IN -.sym 15000 rx_fifo.wr_addr[0] -.sym 15001 spi_if_ins.w_rx_data[0] -.sym 15002 w_rx_24_fifo_data[20] -.sym 15004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 15007 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 15010 spi_if_ins.w_rx_data[6] -.sym 15011 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 15020 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 15021 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 15022 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] -.sym 15023 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 15024 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] -.sym 15028 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 15029 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 15031 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 15032 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 15033 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] -.sym 15034 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] -.sym 15036 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 15037 w_debug_smi_test -.sym 15038 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] -.sym 15040 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] -.sym 15042 smi_ctrl_ins.int_cnt[4] -.sym 15043 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] -.sym 15045 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] -.sym 15046 smi_ctrl_ins.int_cnt[3] -.sym 15047 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] -.sym 15048 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] -.sym 15051 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] -.sym 15052 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 15053 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] -.sym 15054 w_debug_smi_test -.sym 15057 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 15058 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] -.sym 15059 w_debug_smi_test -.sym 15060 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] -.sym 15063 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 15064 smi_ctrl_ins.int_cnt[4] -.sym 15065 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 15066 smi_ctrl_ins.int_cnt[3] -.sym 15069 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 15070 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] -.sym 15071 w_debug_smi_test -.sym 15072 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] -.sym 15075 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] -.sym 15076 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 15077 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] -.sym 15078 w_debug_smi_test -.sym 15093 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] -.sym 15094 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] -.sym 15095 w_debug_smi_test -.sym 15096 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 15097 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 15098 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 15100 w_rx_data[6] -.sym 15101 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 15102 w_rx_data[5] -.sym 15104 w_rx_data[7] -.sym 15105 w_rx_data[0] -.sym 15106 w_rx_data[2] -.sym 15107 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15108 i_rst_b$SB_IO_IN +.sym 14731 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 14732 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 14733 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 14734 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 14735 tx_fifo.wr_addr[2] +.sym 14736 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 14737 tx_fifo.wr_addr[8] +.sym 14738 tx_fifo.wr_addr_gray[5] +.sym 14739 smi_ctrl_ins.tx_reg_state[0] +.sym 14743 w_tx_fifo_data[9] +.sym 14744 tx_fifo.rd_addr[7] +.sym 14745 w_rx_24_fifo_data[15] +.sym 14747 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 14749 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 14751 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0[0] +.sym 14757 tx_fifo.rd_addr_gray_wr_r[4] +.sym 14758 w_tx_fifo_pulled_data[10] +.sym 14760 w_tx_fifo_pulled_data[8] +.sym 14761 w_tx_fifo_pulled_data[30] +.sym 14762 w_tx_fifo_full +.sym 14763 w_smi_data_output[6] +.sym 14764 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 14765 tx_fifo.rd_addr_gray_wr_r[6] +.sym 14775 tx_fifo.rd_addr_gray_wr_r[4] +.sym 14776 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 14777 w_smi_data_input[7] +.sym 14778 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 14781 w_smi_data_input[6] +.sym 14783 smi_ctrl_ins.tx_reg_state[2] +.sym 14784 w_smi_data_input[5] +.sym 14785 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 14786 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 14787 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 14790 w_smi_data_input[1] +.sym 14791 tx_fifo.rd_addr_gray_wr_r[6] +.sym 14792 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 14799 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 14800 i_rst_b$SB_IO_IN +.sym 14805 w_smi_data_input[6] +.sym 14813 w_smi_data_input[5] +.sym 14817 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 14819 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 14826 w_smi_data_input[1] +.sym 14829 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 14830 tx_fifo.rd_addr_gray_wr_r[4] +.sym 14831 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 14835 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 14836 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 14837 tx_fifo.rd_addr_gray_wr_r[6] +.sym 14838 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 14847 w_smi_data_input[7] +.sym 14849 i_rst_b$SB_IO_IN +.sym 14850 smi_ctrl_ins.tx_reg_state[2] +.sym 14851 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 14852 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 14853 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14854 w_smi_data_output[2] +.sym 14855 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[0] +.sym 14856 w_smi_data_output[6] +.sym 14857 smi_ctrl_ins.w_fifo_pull_trigger +.sym 14858 w_smi_data_output[4] +.sym 14859 w_smi_data_output[3] +.sym 14860 w_smi_data_output[0] +.sym 14861 w_smi_data_output[1] +.sym 14867 tx_fifo.wr_addr[8] +.sym 14869 smi_ctrl_ins.tx_reg_state[2] +.sym 14871 i_rst_b$SB_IO_IN +.sym 14875 w_tx_fifo_pulled_data[26] +.sym 14877 tx_fifo.rd_addr_gray_wr_r[8] +.sym 14878 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 14879 tx_fifo.rd_addr_gray_wr_r[2] +.sym 14880 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 14881 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 14885 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[1] +.sym 14886 w_rx_24_fifo_data[14] +.sym 14888 tx_fifo.wr_addr_gray[5] +.sym 14889 w_tx_fifo_pulled_data[9] +.sym 14896 w_tx_fifo_pulled_data[9] +.sym 14897 w_tx_fifo_pulled_data[12] +.sym 14900 w_tx_fifo_pulled_data[22] +.sym 14903 w_tx_fifo_pulled_data[13] +.sym 14906 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 14908 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 14910 i_smi_a2$SB_IO_IN +.sym 14912 lvds_tx_inst.r_fifo_data[13] +.sym 14918 w_tx_fifo_pulled_data[10] +.sym 14920 w_tx_fifo_pulled_data[8] +.sym 14921 w_tx_fifo_pulled_data[30] +.sym 14923 lvds_tx_inst.r_fifo_data[9] +.sym 14924 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 14930 i_smi_a2$SB_IO_IN +.sym 14931 w_tx_fifo_pulled_data[30] +.sym 14935 i_smi_a2$SB_IO_IN +.sym 14936 w_tx_fifo_pulled_data[13] +.sym 14940 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 14941 lvds_tx_inst.r_fifo_data[9] +.sym 14942 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 14943 lvds_tx_inst.r_fifo_data[13] +.sym 14947 i_smi_a2$SB_IO_IN +.sym 14949 w_tx_fifo_pulled_data[12] +.sym 14953 w_tx_fifo_pulled_data[9] +.sym 14954 i_smi_a2$SB_IO_IN +.sym 14960 w_tx_fifo_pulled_data[10] +.sym 14961 i_smi_a2$SB_IO_IN +.sym 14964 w_tx_fifo_pulled_data[8] +.sym 14966 i_smi_a2$SB_IO_IN +.sym 14972 w_tx_fifo_pulled_data[22] +.sym 14973 i_smi_a2$SB_IO_IN +.sym 14974 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 14975 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 14976 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 14977 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[3] +.sym 14978 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 14979 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 14980 w_tx_fifo_full +.sym 14981 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 14982 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 14983 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 14984 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 14985 i_rst_b$SB_IO_IN +.sym 14986 w_smi_data_output[3] +.sym 14988 i_rst_b$SB_IO_IN +.sym 14989 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.sym 14990 w_tx_fifo_data[4] +.sym 14991 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 14992 smi_ctrl_ins.int_cnt_rx[3] +.sym 14993 tx_fifo.rd_addr_gray_wr_r[8] +.sym 14994 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] +.sym 14995 w_tx_fifo_data[27] +.sym 14997 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.sym 14998 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.sym 14999 tx_fifo.rd_addr[6] +.sym 15000 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] +.sym 15002 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] +.sym 15003 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 15004 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] +.sym 15006 w_tx_fifo_push +.sym 15007 $PACKER_VCC_NET +.sym 15008 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] +.sym 15011 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] +.sym 15012 lvds_tx_inst.r_fifo_data[22] +.sym 15018 lvds_tx_inst.r_fifo_data[30] +.sym 15019 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 15021 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 15024 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 15028 lvds_tx_inst.r_fifo_data[28] +.sym 15029 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 15030 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 15031 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 15032 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 15033 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 15040 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 15041 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 15044 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 15045 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 15046 tx_fifo.wr_addr_gray_rd[5] +.sym 15047 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 15048 tx_fifo.wr_addr_gray[5] +.sym 15051 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 15053 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 15057 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 15060 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 15064 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 15066 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 15069 tx_fifo.wr_addr_gray_rd[5] +.sym 15076 tx_fifo.wr_addr_gray[5] +.sym 15082 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 15084 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 15087 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 15088 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 15089 lvds_tx_inst.r_fifo_data[30] +.sym 15090 lvds_tx_inst.r_fifo_data[28] +.sym 15093 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 15094 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 15095 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 15096 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 15098 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 15100 tx_fifo.rd_addr_gray[2] +.sym 15101 tx_fifo.rd_addr_gray[0] +.sym 15102 tx_fifo.rd_addr_gray[5] +.sym 15103 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 15104 tx_fifo.rd_addr_gray[4] +.sym 15105 tx_fifo.rd_addr_gray[3] +.sym 15106 tx_fifo.rd_addr_gray[6] +.sym 15107 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O .sym 15111 i_rst_b$SB_IO_IN -.sym 15114 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 15116 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 15117 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 15119 rx_fifo.mem_i.0.0_RDATA_3[0] -.sym 15122 w_debug_smi_test -.sym 15123 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] -.sym 15124 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15126 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 15127 w_rx_data[0] -.sym 15129 w_smi_data_output[4] -.sym 15132 spi_if_ins.w_rx_data[5] -.sym 15135 w_ioc[0] -.sym 15146 smi_ctrl_ins.int_cnt[3] -.sym 15149 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 15150 smi_ctrl_ins.int_cnt[4] -.sym 15151 w_rx_24_fifo_data[19] -.sym 15158 w_rx_24_fifo_data[24] -.sym 15162 w_rx_24_fifo_data[20] -.sym 15163 w_rx_24_fifo_data[21] -.sym 15165 w_rx_24_fifo_data[23] -.sym 15166 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15168 w_rx_24_fifo_data[22] -.sym 15169 w_rx_24_fifo_data[25] -.sym 15172 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 15174 w_rx_24_fifo_data[21] -.sym 15176 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15181 w_rx_24_fifo_data[22] -.sym 15183 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15186 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15189 w_rx_24_fifo_data[25] -.sym 15192 w_rx_24_fifo_data[20] -.sym 15193 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15198 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15199 w_rx_24_fifo_data[23] -.sym 15204 w_rx_24_fifo_data[24] -.sym 15207 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15210 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 15211 w_rx_24_fifo_data[19] -.sym 15216 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 15217 smi_ctrl_ins.int_cnt[4] -.sym 15218 smi_ctrl_ins.int_cnt[3] -.sym 15219 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 15220 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce -.sym 15221 lvds_clock_$glb_clk -.sym 15222 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 15224 spi_if_ins.spi.r_tx_byte[1] -.sym 15225 spi_if_ins.spi.r_tx_byte[6] -.sym 15226 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15227 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15229 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15231 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 15236 w_rx_data[2] -.sym 15237 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] -.sym 15240 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 15241 rx_fifo.wr_addr[3] -.sym 15243 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15244 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 15245 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 15247 w_rx_data[5] -.sym 15248 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 15249 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15250 w_rx_24_fifo_data[22] -.sym 15251 w_rx_data[7] -.sym 15252 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15253 i_button_SB_LUT4_I0_I1[0] -.sym 15254 w_rx_24_fifo_data[26] -.sym 15257 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15265 spi_if_ins.w_rx_data[4] -.sym 15269 spi_if_ins.w_rx_data[0] -.sym 15271 spi_if_ins.w_rx_data[2] -.sym 15281 spi_if_ins.w_rx_data[3] -.sym 15282 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 15286 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15290 spi_if_ins.w_rx_data[1] -.sym 15292 i_rst_b$SB_IO_IN -.sym 15298 spi_if_ins.w_rx_data[2] -.sym 15303 spi_if_ins.w_rx_data[3] -.sym 15317 spi_if_ins.w_rx_data[0] -.sym 15323 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15327 spi_if_ins.w_rx_data[1] -.sym 15334 spi_if_ins.w_rx_data[4] -.sym 15341 i_rst_b$SB_IO_IN -.sym 15343 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 15344 r_counter_$glb_clk -.sym 15347 i_button_SB_LUT4_I0_I1[0] -.sym 15348 io_pmod_SB_DFFE_Q_E -.sym 15349 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15351 w_load -.sym 15358 w_cs[1] -.sym 15359 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 15361 spi_if_ins.r_tx_byte[1] -.sym 15365 channel -.sym 15366 io_pmod[1]$SB_IO_IN -.sym 15368 w_cs[0] -.sym 15373 w_ioc[0] -.sym 15374 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] -.sym 15376 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15377 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15378 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15380 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 15381 i_button_SB_LUT4_I0_I1[0] -.sym 15387 w_ioc[2] -.sym 15389 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15391 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15392 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15394 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15395 w_ioc[2] -.sym 15396 w_ioc[3] -.sym 15398 w_ioc[0] -.sym 15399 w_cs[0] -.sym 15400 w_fetch -.sym 15401 w_ioc[4] -.sym 15403 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15412 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E -.sym 15414 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15415 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 15417 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15420 w_ioc[3] -.sym 15421 w_ioc[4] -.sym 15422 w_ioc[2] -.sym 15423 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15426 w_cs[0] -.sym 15428 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 15429 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15433 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15434 w_fetch -.sym 15435 w_cs[0] -.sym 15439 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E -.sym 15444 w_ioc[0] -.sym 15446 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15450 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 15462 w_ioc[2] -.sym 15463 w_ioc[3] -.sym 15464 w_ioc[4] -.sym 15466 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 15467 r_counter_$glb_clk -.sym 15468 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 15469 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 15471 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 15475 r_tx_data[0] -.sym 15476 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 15481 rx_fifo.mem_i.0.2_WDATA_1 -.sym 15483 $PACKER_VCC_NET -.sym 15486 io_pmod[1]$SB_IO_IN -.sym 15487 io_pmod[0]$SB_IO_IN -.sym 15490 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 15491 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 15492 rx_fifo.wr_addr[6] -.sym 15495 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15502 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 15503 w_cs[2] -.sym 15504 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15510 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15512 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 15513 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 15514 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[0] -.sym 15515 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 15516 w_ioc[0] -.sym 15517 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15518 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15519 i_rst_b$SB_IO_IN -.sym 15521 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15523 w_fetch -.sym 15524 io_ctrl_ins.o_pmod[2] -.sym 15525 o_shdn_tx_lna$SB_IO_OUT -.sym 15529 w_cs[2] -.sym 15532 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[0] -.sym 15533 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 15534 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 15543 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15544 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15556 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 15558 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 15561 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15562 w_ioc[0] -.sym 15563 io_ctrl_ins.o_pmod[2] -.sym 15564 o_shdn_tx_lna$SB_IO_OUT -.sym 15567 i_rst_b$SB_IO_IN -.sym 15568 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 15569 w_fetch -.sym 15570 w_cs[2] -.sym 15579 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15580 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15581 w_ioc[0] -.sym 15585 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 15586 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[0] -.sym 15587 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 15589 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 15113 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 15114 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 15115 w_tx_fifo_data[28] +.sym 15118 w_tx_fifo_data[5] +.sym 15119 w_tx_fifo_data[7] +.sym 15120 w_rx_24_fifo_data[7] +.sym 15124 tx_fifo.rd_addr[7] +.sym 15125 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 15126 w_rx_24_fifo_data[21] +.sym 15127 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 15129 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.sym 15130 w_rx_24_fifo_data[12] +.sym 15131 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 15133 tx_fifo.rd_addr_gray_wr_r[7] +.sym 15134 w_rx_24_fifo_data[11] +.sym 15135 w_tx_fifo_pull +.sym 15141 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 15142 tx_fifo.empty_o_SB_LUT4_I3_I1[0] +.sym 15146 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 15147 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[0] +.sym 15149 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 15150 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 15153 tx_fifo.wr_addr_gray_rd_r[9] +.sym 15158 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 15160 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 15167 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 15168 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 15170 w_tx_fifo_pull +.sym 15172 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 15175 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 15177 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 15180 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 15187 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 15188 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 15192 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 15195 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 15198 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 15204 tx_fifo.wr_addr_gray_rd_r[9] +.sym 15205 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 15207 w_tx_fifo_pull +.sym 15210 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[0] +.sym 15211 tx_fifo.empty_o_SB_LUT4_I3_I1[0] +.sym 15212 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 15213 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 15216 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 15218 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 15220 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 15221 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 15222 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15224 w_rx_24_fifo_data[12] +.sym 15225 w_rx_24_fifo_data[22] +.sym 15226 w_rx_24_fifo_data[13] +.sym 15227 tx_fifo.wr_addr_gray[6] +.sym 15228 tx_fifo.wr_addr_gray[8] +.sym 15229 w_rx_24_fifo_data[30] +.sym 15230 w_rx_24_fifo_data[21] +.sym 15235 tx_fifo.rd_addr_gray[1] +.sym 15236 tx_fifo.rd_addr[5] +.sym 15238 i_rst_b$SB_IO_IN +.sym 15239 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 15240 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 15241 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 15242 w_rx_24_fifo_data[3] +.sym 15243 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 15244 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 15245 tx_fifo.rd_addr[7] +.sym 15246 lvds_tx_inst.r_fifo_data[15] +.sym 15248 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15249 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 15250 w_rx_24_fifo_data[10] +.sym 15251 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 15252 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 15253 w_rx_24_fifo_data[28] +.sym 15255 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 15257 w_tx_fifo_empty +.sym 15258 w_rx_24_fifo_data[12] +.sym 15270 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1] +.sym 15271 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 15274 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15277 tx_fifo.wr_addr_gray_rd[7] +.sym 15285 tx_fifo.wr_addr_gray_rd[9] +.sym 15286 tx_fifo.wr_addr_gray[7] +.sym 15287 tx_fifo.wr_addr_gray_rd[6] +.sym 15289 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 15290 tx_fifo.wr_addr_gray_rd[0] +.sym 15292 tx_fifo.wr_addr_gray[6] +.sym 15293 tx_fifo.wr_addr_gray[8] +.sym 15300 tx_fifo.wr_addr_gray_rd[0] +.sym 15305 tx_fifo.wr_addr_gray_rd[6] +.sym 15309 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1] +.sym 15310 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15311 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 15312 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 15318 tx_fifo.wr_addr_gray[8] +.sym 15322 tx_fifo.wr_addr_gray_rd[9] +.sym 15328 tx_fifo.wr_addr_gray[7] +.sym 15335 tx_fifo.wr_addr_gray_rd[7] +.sym 15341 tx_fifo.wr_addr_gray[6] +.sym 15344 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 15346 tx_fifo.wr_addr_gray_rd[3] +.sym 15347 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 15348 tx_fifo.wr_addr_gray_rd[0] +.sym 15349 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 15350 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] +.sym 15351 tx_fifo.wr_addr_gray_rd[9] +.sym 15352 tx_fifo.wr_addr_gray_rd[2] +.sym 15353 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 15358 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[1] +.sym 15359 $PACKER_VCC_NET +.sym 15360 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 15361 w_rx_24_fifo_data[13] +.sym 15366 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 15368 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 15370 tx_fifo.rd_addr[6] +.sym 15372 w_rx_24_fifo_data[16] +.sym 15375 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 15377 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 15378 w_rx_24_fifo_data[14] +.sym 15380 w_rx_24_fifo_data[24] +.sym 15381 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 15387 tx_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 15388 tx_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 15390 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 15391 tx_fifo.rd_addr[6] +.sym 15393 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 15397 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 15398 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 15399 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 15401 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 15405 tx_fifo.rd_addr[5] +.sym 15406 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 15407 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] +.sym 15408 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15413 tx_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 15414 i_rst_b$SB_IO_IN +.sym 15415 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 15416 tx_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 15420 tx_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 15421 tx_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 15422 tx_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 15423 tx_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 15426 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 15427 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 15428 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 15429 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] +.sym 15433 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 15438 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 15445 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 15450 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 15451 tx_fifo.rd_addr[5] +.sym 15453 tx_fifo.rd_addr[6] +.sym 15457 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 15463 i_rst_b$SB_IO_IN +.sym 15466 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 15467 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 15468 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 15469 w_rx_24_fifo_data[25] +.sym 15470 w_rx_24_fifo_data[10] +.sym 15471 w_rx_24_fifo_data[14] +.sym 15473 w_rx_24_fifo_data[26] +.sym 15474 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 15475 w_rx_24_fifo_data[2] +.sym 15476 w_rx_24_fifo_data[16] +.sym 15481 tx_fifo.rd_addr[7] +.sym 15483 w_tx_fifo_pull +.sym 15486 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 15488 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 15489 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 15490 w_tx_fifo_data[3] +.sym 15491 tx_fifo.rd_addr[6] +.sym 15494 w_rx_24_fifo_data[26] +.sym 15496 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 15498 w_tx_fifo_pull +.sym 15500 w_rx_24_fifo_data[16] +.sym 15501 w_fetch +.sym 15502 i_sck$SB_IO_IN +.sym 15503 $PACKER_VCC_NET +.sym 15513 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] +.sym 15514 spi_if_ins.spi.SCKr[2] +.sym 15516 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 15517 spi_if_ins.spi.SCKr[1] +.sym 15518 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 15520 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15521 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 15523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15527 $PACKER_VCC_NET +.sym 15535 $PACKER_VCC_NET +.sym 15537 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 15539 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 15542 $nextpnr_ICESTORM_LC_7$O +.sym 15545 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15548 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 15550 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 15551 $PACKER_VCC_NET +.sym 15555 $PACKER_VCC_NET +.sym 15556 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15558 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 15562 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 15563 $PACKER_VCC_NET +.sym 15564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15567 spi_if_ins.spi.SCKr[2] +.sym 15568 spi_if_ins.spi.SCKr[1] +.sym 15569 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15570 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15574 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15579 spi_if_ins.spi.SCKr[2] +.sym 15581 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 15582 spi_if_ins.spi.SCKr[1] +.sym 15585 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 15586 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15587 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] +.sym 15588 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 15589 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E .sym 15590 r_counter_$glb_clk -.sym 15591 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[0] -.sym 15593 w_tx_data_io[2] -.sym 15594 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 15595 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 15597 o_led0$SB_IO_OUT -.sym 15598 o_led1$SB_IO_OUT -.sym 15599 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 15606 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 15610 i_rst_b$SB_IO_IN -.sym 15611 w_tx_data_smi[0] -.sym 15612 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 15613 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 15614 w_cs[1] -.sym 15615 i_rst_b$SB_IO_IN -.sym 15616 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 15617 w_rx_data[2] -.sym 15618 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 15620 w_rx_data[0] -.sym 15621 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15622 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] -.sym 15623 w_ioc[0] -.sym 15624 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 15625 i_button_SB_LUT4_I0_I1[0] -.sym 15627 w_ioc[0] -.sym 15634 io_ctrl_ins.rf_mode[0] -.sym 15636 w_cs[1] -.sym 15637 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 15639 io_ctrl_ins.pmod_dir_state[2] -.sym 15640 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] -.sym 15641 i_button_SB_LUT4_I0_I1[3] -.sym 15642 o_led1$SB_IO_OUT -.sym 15643 w_ioc[0] -.sym 15644 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] -.sym 15645 io_ctrl_ins.debug_mode[1] -.sym 15646 io_ctrl_ins.debug_mode[0] -.sym 15647 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15648 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15649 i_button_SB_LUT4_I0_I1[2] -.sym 15650 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] -.sym 15651 i_button_SB_LUT4_I0_I1[0] -.sym 15653 i_button_SB_LUT4_I0_I2[2] -.sym 15654 o_led0$SB_IO_OUT -.sym 15655 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15657 i_button_SB_LUT4_I0_I1[2] -.sym 15660 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 15661 i_button_SB_LUT4_I0_I2[2] -.sym 15663 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] -.sym 15664 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] -.sym 15666 i_button_SB_LUT4_I0_I1[2] -.sym 15667 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] -.sym 15668 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] -.sym 15669 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] -.sym 15672 o_led0$SB_IO_OUT -.sym 15673 i_button_SB_LUT4_I0_I1[0] -.sym 15674 i_button_SB_LUT4_I0_I2[2] -.sym 15675 io_ctrl_ins.debug_mode[0] -.sym 15678 i_button_SB_LUT4_I0_I2[2] -.sym 15679 io_ctrl_ins.debug_mode[1] -.sym 15680 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] -.sym 15681 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] -.sym 15685 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15686 w_cs[1] -.sym 15687 i_button_SB_LUT4_I0_I2[2] -.sym 15690 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 15691 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15693 w_ioc[0] -.sym 15696 io_ctrl_ins.rf_mode[0] -.sym 15697 i_button_SB_LUT4_I0_I1[2] -.sym 15698 i_button_SB_LUT4_I0_I2[2] -.sym 15699 io_ctrl_ins.pmod_dir_state[2] -.sym 15704 i_button_SB_LUT4_I0_I1[2] -.sym 15708 i_button_SB_LUT4_I0_I1[3] -.sym 15709 o_led1$SB_IO_OUT -.sym 15710 i_button_SB_LUT4_I0_I1[2] -.sym 15711 i_button_SB_LUT4_I0_I1[0] -.sym 15712 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] +.sym 15591 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 15592 spi_if_ins.spi.r2_rx_done +.sym 15593 tx_fifo.rd_addr_gray_wr_r[9] +.sym 15594 spi_if_ins.spi.r3_rx_done +.sym 15595 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 15597 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 15599 tx_fifo.rd_addr_gray_wr[9] +.sym 15600 i_rst_b$SB_IO_IN +.sym 15603 i_rst_b$SB_IO_IN +.sym 15605 w_rx_24_fifo_data[2] +.sym 15608 $PACKER_VCC_NET +.sym 15611 w_rx_24_fifo_data[25] +.sym 15613 w_tx_fifo_pulled_data[22] +.sym 15614 $PACKER_VCC_NET +.sym 15621 w_rx_24_fifo_data[23] +.sym 15622 w_tx_fifo_pull +.sym 15633 spi_if_ins.spi.r_tx_byte[3] +.sym 15634 spi_if_ins.spi.r_tx_byte[4] +.sym 15635 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15638 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15639 spi_if_ins.spi.r_tx_byte[2] +.sym 15640 spi_if_ins.spi.r_tx_byte[1] +.sym 15642 spi_if_ins.spi.SCKr[0] +.sym 15643 spi_if_ins.spi.r_tx_byte[7] +.sym 15644 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 15645 spi_if_ins.spi.r_tx_byte[6] +.sym 15646 spi_if_ins.spi.r_tx_byte[5] +.sym 15647 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 15648 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] +.sym 15656 spi_if_ins.spi.SCKr[1] +.sym 15659 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 15662 i_sck$SB_IO_IN +.sym 15663 spi_if_ins.spi.r_tx_byte[0] +.sym 15667 spi_if_ins.spi.r_tx_byte[4] +.sym 15668 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15669 spi_if_ins.spi.r_tx_byte[0] +.sym 15675 i_sck$SB_IO_IN +.sym 15678 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15679 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15680 spi_if_ins.spi.r_tx_byte[3] +.sym 15681 spi_if_ins.spi.r_tx_byte[7] +.sym 15685 spi_if_ins.spi.r_tx_byte[5] +.sym 15686 spi_if_ins.spi.r_tx_byte[1] +.sym 15687 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15691 spi_if_ins.spi.SCKr[1] +.sym 15696 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 15697 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 15698 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 15699 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] +.sym 15702 spi_if_ins.spi.r_tx_byte[2] +.sym 15703 spi_if_ins.spi.r_tx_byte[6] +.sym 15704 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15705 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 15709 spi_if_ins.spi.SCKr[0] .sym 15713 r_counter_$glb_clk -.sym 15714 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 15715 i_button_SB_LUT4_I0_I1[2] -.sym 15716 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 15717 w_tx_data_io[3] -.sym 15718 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 15719 w_tx_data_io[4] -.sym 15720 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 15721 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 15728 o_led1$SB_IO_OUT -.sym 15730 w_rx_data[1] -.sym 15733 w_tx_data_io[1] -.sym 15734 w_tx_data_smi[1] -.sym 15740 i_button$SB_IO_IN -.sym 15741 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 15742 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 15744 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15745 o_led0$SB_IO_OUT -.sym 15746 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 15747 w_rx_data[5] -.sym 15748 w_rx_data[7] -.sym 15749 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] -.sym 15750 i_button_SB_LUT4_I0_I1[0] -.sym 15758 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 15760 w_rx_data[4] -.sym 15764 w_rx_data[1] -.sym 15765 i_button_SB_LUT4_I0_I2[1] -.sym 15766 w_rx_data[3] -.sym 15768 i_button_SB_LUT4_I0_I2[2] -.sym 15772 i_button_SB_LUT4_I0_I1[2] -.sym 15777 w_rx_data[2] -.sym 15779 i_button_SB_LUT4_I0_I2[3] -.sym 15780 w_rx_data[0] -.sym 15783 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 15784 io_ctrl_ins.pmod_dir_state[4] -.sym 15785 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 15790 w_rx_data[1] -.sym 15795 w_rx_data[3] -.sym 15803 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 15807 w_rx_data[0] -.sym 15815 w_rx_data[4] -.sym 15819 i_button_SB_LUT4_I0_I2[2] -.sym 15820 i_button_SB_LUT4_I0_I1[2] -.sym 15821 i_button_SB_LUT4_I0_I2[3] -.sym 15822 i_button_SB_LUT4_I0_I2[1] -.sym 15828 w_rx_data[2] -.sym 15831 i_button_SB_LUT4_I0_I2[2] -.sym 15832 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 15833 io_ctrl_ins.pmod_dir_state[4] -.sym 15834 i_button_SB_LUT4_I0_I1[2] -.sym 15835 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O +.sym 15715 spi_if_ins.w_rx_data[3] +.sym 15716 spi_if_ins.w_rx_data[2] +.sym 15717 spi_if_ins.w_rx_data[1] +.sym 15718 spi_if_ins.w_rx_data[4] +.sym 15719 spi_if_ins.w_rx_data[5] +.sym 15720 spi_if_ins.w_rx_data[0] +.sym 15721 spi_if_ins.w_rx_data[6] +.sym 15722 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 15727 tx_fifo.rd_addr[6] +.sym 15728 $PACKER_VCC_NET +.sym 15729 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 15735 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 15737 i_rst_b$SB_IO_IN +.sym 15743 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 15744 w_rx_24_fifo_data[28] +.sym 15746 w_rx_24_fifo_data[8] +.sym 15747 w_tx_data_smi[1] +.sym 15749 w_tx_fifo_empty +.sym 15750 w_tx_data_io[0] +.sym 15757 spi_if_ins.r_tx_byte[5] +.sym 15758 spi_if_ins.r_tx_byte[1] +.sym 15760 spi_if_ins.r_tx_byte[6] +.sym 15761 spi_if_ins.r_tx_byte[2] +.sym 15762 spi_if_ins.r_tx_byte[7] +.sym 15763 spi_if_ins.r_tx_byte[4] +.sym 15764 spi_if_ins.r_tx_byte[3] +.sym 15769 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 15783 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15784 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15790 spi_if_ins.r_tx_byte[3] +.sym 15795 spi_if_ins.r_tx_byte[4] +.sym 15801 spi_if_ins.r_tx_byte[7] +.sym 15807 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15813 spi_if_ins.r_tx_byte[6] +.sym 15819 spi_if_ins.r_tx_byte[5] +.sym 15826 spi_if_ins.r_tx_byte[2] +.sym 15832 spi_if_ins.r_tx_byte[1] +.sym 15835 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .sym 15836 r_counter_$glb_clk -.sym 15838 io_ctrl_ins.pmod_dir_state[7] -.sym 15839 io_ctrl_ins.pmod_dir_state[5] -.sym 15840 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[1] -.sym 15841 i_button_SB_LUT4_I0_O[1] -.sym 15842 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 15843 io_ctrl_ins.pmod_dir_state[6] -.sym 15844 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] -.sym 15845 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[1] -.sym 15851 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 15857 i_rst_b$SB_IO_IN -.sym 15863 w_rx_data[6] -.sym 15865 w_ioc[0] -.sym 15866 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15879 w_rx_data[3] -.sym 15880 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 15883 w_rx_data[4] -.sym 15884 w_rx_data[1] -.sym 15887 io_ctrl_ins.o_pmod[0] -.sym 15888 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 15889 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 15890 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 15892 w_rx_data[0] -.sym 15894 w_ioc[0] -.sym 15895 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15896 io_ctrl_ins.mixer_en_state -.sym 15903 o_tr_vc2$SB_IO_OUT -.sym 15905 io_ctrl_ins.o_pmod[3] -.sym 15912 w_rx_data[0] -.sym 15918 w_rx_data[1] -.sym 15926 w_rx_data[3] -.sym 15930 io_ctrl_ins.mixer_en_state -.sym 15931 w_ioc[0] -.sym 15932 io_ctrl_ins.o_pmod[0] -.sym 15933 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15936 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 15937 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 15942 o_tr_vc2$SB_IO_OUT -.sym 15943 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15944 io_ctrl_ins.o_pmod[3] -.sym 15945 w_ioc[0] -.sym 15948 w_ioc[0] -.sym 15949 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 15950 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 15957 w_rx_data[4] -.sym 15958 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O +.sym 15837 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 15838 r_tx_data[7] +.sym 15839 r_tx_data[6] +.sym 15840 r_tx_data[2] +.sym 15841 r_tx_data[1] +.sym 15842 r_tx_data[4] +.sym 15843 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 15844 r_tx_data[5] +.sym 15845 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 15851 spi_if_ins.w_rx_data[6] +.sym 15855 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 15856 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 15859 spi_if_ins.w_rx_data[2] +.sym 15861 spi_if_ins.w_rx_data[1] +.sym 15862 w_load +.sym 15866 spi_if_ins.r_tx_byte[7] +.sym 15881 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 15888 i_rst_b$SB_IO_IN +.sym 15890 r_tx_data[3] +.sym 15892 spi_if_ins.o_cs_SB_LUT4_I0_2_O[0] +.sym 15895 r_tx_data[7] +.sym 15897 r_tx_data[2] +.sym 15904 r_tx_data[6] +.sym 15906 r_tx_data[1] +.sym 15907 r_tx_data[4] +.sym 15909 r_tx_data[5] +.sym 15912 r_tx_data[3] +.sym 15918 r_tx_data[5] +.sym 15924 r_tx_data[1] +.sym 15931 i_rst_b$SB_IO_IN +.sym 15933 spi_if_ins.o_cs_SB_LUT4_I0_2_O[0] +.sym 15936 r_tx_data[6] +.sym 15945 r_tx_data[2] +.sym 15948 r_tx_data[7] +.sym 15954 r_tx_data[4] +.sym 15958 spi_if_ins.r_tx_byte_SB_DFFE_Q_E .sym 15959 r_counter_$glb_clk -.sym 15961 io_ctrl_ins.o_pmod[6] -.sym 15962 io_ctrl_ins.o_pmod[7] -.sym 15963 io_ctrl_ins.o_pmod[5] -.sym 15965 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[0] -.sym 15966 i_button_SB_LUT4_I0_O[0] -.sym 15968 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[0] -.sym 15974 o_tr_vc1_b$SB_IO_OUT -.sym 15980 io_pmod[0]$SB_IO_IN -.sym 16006 o_shdn_rx_lna$SB_IO_OUT -.sym 16007 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 16011 io_ctrl_ins.o_pmod[1] -.sym 16014 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 16016 w_ioc[0] -.sym 16018 w_rx_data[7] -.sym 16019 w_rx_data[5] -.sym 16020 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 16023 w_rx_data[6] -.sym 16041 w_rx_data[5] -.sym 16050 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 16054 w_rx_data[7] -.sym 16060 w_rx_data[6] -.sym 16065 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 16066 io_ctrl_ins.o_pmod[1] -.sym 16067 w_ioc[0] -.sym 16068 o_shdn_rx_lna$SB_IO_OUT -.sym 16081 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 16082 r_counter_$glb_clk -.sym 16102 w_tx_data_io[6] -.sym 16104 o_rx_h_tx_l_b$SB_IO_OUT -.sym 16105 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 16223 o_tr_vc1$SB_IO_OUT -.sym 16236 i_button$SB_IO_IN -.sym 16237 o_led0$SB_IO_OUT -.sym 16345 o_tr_vc1_b$SB_IO_OUT +.sym 15961 w_tx_data_io[4] +.sym 15963 io_ctrl_ins.led1_state_SB_DFFER_Q_E +.sym 15964 w_tx_data_io[1] +.sym 15965 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 15966 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[3] +.sym 15967 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 15968 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 15973 w_cs[1] +.sym 15974 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 15975 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 15977 w_load +.sym 15979 w_cs[3] +.sym 15980 w_tx_fifo_pull +.sym 15981 r_tx_data_SB_DFFE_Q_E +.sym 15982 w_cs[2] +.sym 15985 w_tx_fifo_pull +.sym 15986 w_fetch +.sym 15987 w_rx_data[0] +.sym 15988 io_ctrl_ins.debug_mode[0] +.sym 15989 w_rx_data[2] +.sym 15991 w_rx_data[4] +.sym 15993 w_fetch +.sym 15994 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 15995 $PACKER_VCC_NET +.sym 15996 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 16002 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 16003 w_tx_data_io[2] +.sym 16004 w_cs[3] +.sym 16005 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 16006 w_cs[0] +.sym 16007 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 16010 w_cs[1] +.sym 16011 w_ioc[1] +.sym 16012 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 16013 w_cs[1] +.sym 16014 w_cs[2] +.sym 16017 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 16018 w_tx_data_smi[2] +.sym 16019 w_fetch +.sym 16020 w_tx_data_io[0] +.sym 16021 w_tx_fifo_empty +.sym 16022 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 16026 i_rst_b$SB_IO_IN +.sym 16028 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[0] +.sym 16030 w_tx_data_smi[0] +.sym 16031 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R +.sym 16035 w_cs[0] +.sym 16036 w_cs[2] +.sym 16037 w_cs[3] +.sym 16038 w_cs[1] +.sym 16041 w_fetch +.sym 16043 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 16044 w_cs[0] +.sym 16047 w_ioc[1] +.sym 16048 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 16053 w_fetch +.sym 16054 w_cs[1] +.sym 16055 i_rst_b$SB_IO_IN +.sym 16062 w_tx_fifo_empty +.sym 16065 w_tx_data_smi[0] +.sym 16066 w_tx_data_io[0] +.sym 16067 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 16068 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 16071 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 16072 w_tx_data_io[2] +.sym 16073 w_tx_data_smi[2] +.sym 16074 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 16077 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[0] +.sym 16078 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 16079 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 16080 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 16082 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 16083 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R +.sym 16084 io_ctrl_ins.pmod_dir_state[4] +.sym 16085 io_ctrl_ins.pmod_dir_state[0] +.sym 16086 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] +.sym 16087 io_ctrl_ins.pmod_dir_state[3] +.sym 16088 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] +.sym 16089 io_ctrl_ins.pmod_dir_state[1] +.sym 16090 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3] +.sym 16091 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 16092 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 16096 o_led0$SB_IO_OUT +.sym 16097 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 16098 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 16100 w_ioc[1] +.sym 16101 w_cs[1] +.sym 16102 w_cs[0] +.sym 16104 i_button_SB_LUT4_I0_I1[1] +.sym 16106 w_cs[1] +.sym 16107 w_ioc[1] +.sym 16113 w_tx_fifo_pull +.sym 16118 w_ioc[0] +.sym 16126 w_cs[1] +.sym 16129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 16130 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 16132 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 16134 w_load +.sym 16136 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 16138 w_fetch +.sym 16140 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] +.sym 16141 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 16145 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] +.sym 16154 i_button_SB_LUT4_I0_I1[1] +.sym 16164 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 16165 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 16167 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] +.sym 16188 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 16189 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] +.sym 16191 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 16194 w_fetch +.sym 16195 w_cs[1] +.sym 16196 w_load +.sym 16197 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 16204 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E +.sym 16205 r_counter_$glb_clk +.sym 16206 i_button_SB_LUT4_I0_I1[1] +.sym 16207 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 16208 io_ctrl_ins.debug_mode[0] +.sym 16210 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 16211 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 16212 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 16213 io_ctrl_ins.debug_mode[1] +.sym 16214 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16221 i_rst_b$SB_IO_IN +.sym 16248 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 16251 io_ctrl_ins.o_pmod[2] +.sym 16261 w_rx_data[2] +.sym 16264 o_shdn_tx_lna$SB_IO_OUT +.sym 16275 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 16278 w_ioc[0] +.sym 16302 w_rx_data[2] +.sym 16323 w_ioc[0] +.sym 16324 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 16325 io_ctrl_ins.o_pmod[2] +.sym 16326 o_shdn_tx_lna$SB_IO_OUT +.sym 16327 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 16328 r_counter_$glb_clk +.sym 16330 o_shdn_tx_lna$SB_IO_OUT +.sym 16332 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 16342 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 16343 i_rst_b$SB_IO_IN +.sym 16347 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16351 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 16352 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 16359 w_rx_data[2] +.sym 16379 i_rst_b$SB_IO_IN +.sym 16383 w_rx_data[2] +.sym 16398 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 16405 i_rst_b$SB_IO_IN +.sym 16419 w_rx_data[2] +.sym 16450 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 16451 r_counter_$glb_clk .sym 16453 i_config[3]$SB_IO_IN .sym 16455 i_button$SB_IO_IN -.sym 16497 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16512 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O -.sym 16556 i_ss_SB_LUT4_I3_O -.sym 16560 spi_if_ins.spi.r_rx_done -.sym 16575 w_rx_data[0] -.sym 16577 w_rx_data[2] -.sym 16585 i_smi_soe_se$SB_IO_IN -.sym 16587 w_smi_data_output[4] -.sym 16604 i_smi_soe_se$SB_IO_IN -.sym 16607 i_rst_b$SB_IO_IN -.sym 16626 spi_if_ins.spi.r_rx_done -.sym 16637 spi_if_ins.spi.r_rx_done -.sym 16642 i_smi_soe_se$SB_IO_IN -.sym 16643 i_rst_b$SB_IO_IN +.sym 16480 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 16497 smi_ctrl_ins.soe_and_reset +.sym 16508 smi_ctrl_ins.soe_and_reset +.sym 16553 tx_fifo.wr_addr[3] +.sym 16554 tx_fifo.wr_addr[7] +.sym 16555 tx_fifo.wr_addr[6] +.sym 16556 tx_fifo.wr_addr[4] +.sym 16557 tx_fifo.wr_addr[5] +.sym 16558 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 16559 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 16560 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 16586 $PACKER_VCC_NET +.sym 16587 i_smi_a2$SB_IO_IN +.sym 16598 w_tx_fifo_full +.sym 16599 smi_ctrl_ins.r_fifo_push +.sym 16608 i_rst_b$SB_IO_IN +.sym 16610 smi_ctrl_ins.w_fifo_push_trigger +.sym 16620 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 16621 smi_ctrl_ins.r_fifo_push_1 +.sym 16629 w_tx_fifo_full +.sym 16630 smi_ctrl_ins.r_fifo_push +.sym 16631 smi_ctrl_ins.r_fifo_push_1 +.sym 16642 smi_ctrl_ins.r_fifo_push +.sym 16654 smi_ctrl_ins.w_fifo_push_trigger +.sym 16664 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 16666 i_rst_b$SB_IO_IN .sym 16675 r_counter_$glb_clk -.sym 16683 spi_if_ins.spi.r_rx_bit_count[2] -.sym 16684 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 16685 spi_if_ins.spi.r_rx_bit_count[0] -.sym 16686 spi_if_ins.spi.r_rx_bit_count[1] -.sym 16687 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 16697 spi_if_ins.spi.r2_rx_done -.sym 16700 i_sck$SB_IO_IN -.sym 16710 i_ss$SB_IO_IN -.sym 16736 smi_ctrl_ins.soe_and_reset -.sym 16758 i_sck$SB_IO_IN -.sym 16764 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 16769 i_ss_SB_LUT4_I3_O -.sym 16770 i_mosi$SB_IO_IN -.sym 16777 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 16782 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 16786 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 16787 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 16789 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 16794 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 16797 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 16810 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 16815 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 16824 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 16828 i_mosi$SB_IO_IN -.sym 16833 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 16837 i_ss_SB_LUT4_I3_O -.sym 16838 i_sck$SB_IO_IN -.sym 16846 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 16851 w_rx_data[6] -.sym 16853 i_ss$SB_IO_IN -.sym 16859 i_sck$SB_IO_IN -.sym 16862 i_sck$SB_IO_IN -.sym 16867 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 16870 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 16872 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 16881 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 16882 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 16884 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 16885 i_mosi$SB_IO_IN -.sym 16887 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 16888 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 16890 i_sck$SB_IO_IN -.sym 16892 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 16893 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 16894 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 16916 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 16920 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 16928 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 16932 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 16939 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 16945 i_mosi$SB_IO_IN -.sym 16951 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 16959 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 16960 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 16961 i_sck$SB_IO_IN -.sym 16964 rx_fifo.wr_addr[4] -.sym 16965 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] -.sym 16967 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 16969 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 16976 i_sck$SB_IO_IN -.sym 16981 i_ss$SB_IO_IN -.sym 16989 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 16990 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 16992 w_rx_24_fifo_data[21] -.sym 16993 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 16995 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 16996 w_rx_24_fifo_data[23] -.sym 16998 rx_fifo.rd_addr[2] -.sym 17009 spi_if_ins.spi.r2_rx_done -.sym 17013 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17032 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 17033 spi_if_ins.spi.r3_rx_done -.sym 17043 spi_if_ins.spi.r2_rx_done -.sym 17046 spi_if_ins.spi.r3_rx_done -.sym 17052 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 17058 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17069 spi_if_ins.spi.r2_rx_done -.sym 17080 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17084 r_counter_$glb_clk -.sym 17086 rx_fifo.mem_i.0.1_WDATA -.sym 17087 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 17088 rx_fifo.mem_i.0.1_WDATA_3 -.sym 17089 rx_fifo.mem_i.0.1_WDATA_2 -.sym 17090 rx_fifo.mem_i.0.1_WDATA_1 -.sym 17091 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 17092 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 17093 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 17103 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17111 w_rx_data[2] -.sym 17113 channel -.sym 17114 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 17117 rx_fifo.mem_i.0.0_RDATA[1] -.sym 17121 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 17137 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 17140 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 17141 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 17142 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 17144 smi_ctrl_ins.int_cnt[3] -.sym 17148 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 17149 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 17151 w_rx_09_fifo_data[21] -.sym 17152 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 17155 w_rx_09_fifo_data[20] -.sym 17156 smi_ctrl_ins.int_cnt[4] -.sym 17157 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 17158 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 17166 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 17167 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 17168 smi_ctrl_ins.int_cnt[3] -.sym 17169 smi_ctrl_ins.int_cnt[4] -.sym 17172 smi_ctrl_ins.int_cnt[4] -.sym 17173 smi_ctrl_ins.int_cnt[3] -.sym 17174 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 17175 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 17178 w_rx_09_fifo_data[20] -.sym 17179 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 17186 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 17187 w_rx_09_fifo_data[21] -.sym 17190 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 17191 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 17192 smi_ctrl_ins.int_cnt[3] -.sym 17193 smi_ctrl_ins.int_cnt[4] -.sym 17196 smi_ctrl_ins.int_cnt[4] -.sym 17197 smi_ctrl_ins.int_cnt[3] -.sym 17198 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 17199 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 17206 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 17207 lvds_clock_$glb_clk -.sym 17208 lvds_rx_09_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr -.sym 17209 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 17210 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] -.sym 17211 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 17212 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 17213 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 17214 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 17215 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 17216 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 17223 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 17228 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 17230 w_rx_24_fifo_data[22] -.sym 17233 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 17235 w_rx_data[0] -.sym 17236 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 17237 w_rx_data[2] -.sym 17238 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 17239 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17240 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 17243 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 17244 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 17251 spi_if_ins.w_rx_data[5] -.sym 17252 spi_if_ins.w_rx_data[2] -.sym 17253 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17254 spi_if_ins.w_rx_data[0] -.sym 17257 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17261 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17263 spi_if_ins.w_rx_data[6] -.sym 17264 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17265 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 17269 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17273 i_rst_b$SB_IO_IN -.sym 17281 i_rst_b$SB_IO_IN -.sym 17283 spi_if_ins.w_rx_data[6] -.sym 17289 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17290 i_rst_b$SB_IO_IN -.sym 17291 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 17292 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 17296 spi_if_ins.w_rx_data[5] -.sym 17310 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 17316 spi_if_ins.w_rx_data[0] -.sym 17321 spi_if_ins.w_rx_data[2] -.sym 17325 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 17326 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 17327 i_rst_b$SB_IO_IN -.sym 17329 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17330 r_counter_$glb_clk -.sym 17333 spi_if_ins.spi.SCKr[0] -.sym 17334 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 17335 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17336 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 17337 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 17338 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 17339 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 17346 w_rx_data[0] -.sym 17347 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 17348 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 17351 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 17353 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 17354 rx_fifo.mem_q.0.0_RDATA[1] -.sym 17361 smi_ctrl_ins.int_cnt[3] -.sym 17362 $PACKER_VCC_NET -.sym 17366 spi_if_ins.r_tx_byte[6] -.sym 17376 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 17377 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17380 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17381 spi_if_ins.w_rx_data[6] -.sym 17385 spi_if_ins.w_rx_data[5] -.sym 17387 spi_if_ins.r_tx_byte[1] -.sym 17392 spi_if_ins.r_tx_byte[6] -.sym 17400 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17414 spi_if_ins.r_tx_byte[1] -.sym 17421 spi_if_ins.r_tx_byte[6] -.sym 17424 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17431 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 17443 spi_if_ins.w_rx_data[5] -.sym 17445 spi_if_ins.w_rx_data[6] -.sym 17452 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17453 r_counter_$glb_clk -.sym 17454 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17456 $PACKER_VCC_NET -.sym 17457 spi_if_ins.spi.r_tx_bit_count[2] -.sym 17458 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 17459 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 17460 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 17461 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 17462 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 17469 w_debug_smi_test -.sym 17471 rx_fifo.mem_i.0.0_RDATA[1] -.sym 17472 i_sck$SB_IO_IN -.sym 17473 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17474 w_cs[2] -.sym 17475 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17477 spi_if_ins.w_rx_data[6] -.sym 17479 rx_fifo.rd_addr[2] -.sym 17480 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 17483 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 17487 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 17490 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 17499 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17500 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17501 w_load -.sym 17503 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 17507 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 17509 w_fetch -.sym 17513 i_button_SB_LUT4_I0_I1[0] -.sym 17515 w_ioc[0] -.sym 17518 w_cs[2] -.sym 17519 i_rst_b$SB_IO_IN -.sym 17523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 17525 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 17535 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 17536 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 17537 w_ioc[0] -.sym 17541 w_cs[2] -.sym 17542 i_rst_b$SB_IO_IN -.sym 17543 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 17544 i_button_SB_LUT4_I0_I1[0] -.sym 17547 w_load -.sym 17550 w_fetch -.sym 17559 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 17575 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 17576 r_counter_$glb_clk -.sym 17577 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R -.sym 17578 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] -.sym 17579 spi_if_ins.spi.r_tx_byte[5] -.sym 17580 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 17581 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 17582 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 17583 spi_if_ins.spi.r_tx_byte[2] -.sym 17584 spi_if_ins.spi.r_tx_byte[7] -.sym 17585 spi_if_ins.spi.r_tx_byte[3] -.sym 17594 i_button_SB_LUT4_I0_I1[0] -.sym 17595 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 17596 io_pmod_SB_DFFE_Q_E -.sym 17599 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 17604 channel -.sym 17605 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 17608 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 17609 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 17610 io_pmod[1]$SB_IO_IN -.sym 17611 w_cs[1] -.sym 17613 i_config[1]$SB_IO_IN -.sym 17619 w_tx_data_sys[0] -.sym 17621 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 17622 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 17623 i_rst_b$SB_IO_IN -.sym 17624 w_cs[1] -.sym 17626 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 17627 w_tx_data_smi[0] -.sym 17630 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 17634 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 17635 w_tx_data_io[0] -.sym 17637 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 17643 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 17644 i_glob_clock$SB_IO_IN -.sym 17647 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 17648 w_fetch -.sym 17650 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 17652 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 17654 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 17655 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 17664 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 17665 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 17666 w_tx_data_io[0] -.sym 17667 w_tx_data_smi[0] -.sym 17688 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 17689 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 17690 w_tx_data_sys[0] -.sym 17691 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 17694 w_cs[1] -.sym 17695 w_fetch -.sym 17697 i_rst_b$SB_IO_IN -.sym 17698 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 17699 i_glob_clock$SB_IO_IN -.sym 17701 spi_if_ins.r_tx_byte[5] -.sym 17702 spi_if_ins.r_tx_byte[2] -.sym 17704 spi_if_ins.r_tx_byte[0] -.sym 17708 spi_if_ins.r_tx_byte[3] -.sym 17712 i_config[3]$SB_IO_IN -.sym 17713 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 17714 lvds_clock -.sym 17716 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 17723 w_tx_data_sys[0] -.sym 17725 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 17728 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 17729 w_rx_data[2] -.sym 17730 i_glob_clock$SB_IO_IN -.sym 17731 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 17732 w_rx_data[0] -.sym 17733 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 17736 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 17742 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 17744 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 17748 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 17752 i_button_SB_LUT4_I0_I1[0] -.sym 17756 w_rx_data[1] -.sym 17757 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 17760 w_tx_data_io[2] -.sym 17768 w_rx_data[0] -.sym 17771 w_cs[1] -.sym 17784 w_tx_data_io[2] -.sym 17789 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 17794 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 17807 w_rx_data[0] -.sym 17814 w_rx_data[1] -.sym 17817 i_button_SB_LUT4_I0_I1[0] -.sym 17818 w_cs[1] -.sym 17820 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 17821 io_ctrl_ins.led1_state_SB_DFFER_Q_E +.sym 16676 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 16677 w_smi_data_input[4] +.sym 16682 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 16683 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 16684 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 16685 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] +.sym 16686 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 16687 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[6] +.sym 16688 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[7] +.sym 16695 w_tx_fifo_pulled_data[8] +.sym 16696 w_tx_fifo_full +.sym 16697 w_tx_fifo_pulled_data[10] +.sym 16702 smi_ctrl_ins.w_fifo_push_trigger +.sym 16706 w_tx_fifo_push +.sym 16708 i_smi_a2$SB_IO_IN +.sym 16709 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 16711 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 16722 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 16723 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 16724 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 16725 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 16731 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 16732 w_tx_fifo_push +.sym 16734 tx_fifo.wr_addr[9] +.sym 16736 i_ss$SB_IO_IN +.sym 16737 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 16740 w_smi_data_input[4] +.sym 16741 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.sym 16742 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 16744 w_smi_data_output[4] +.sym 16758 tx_fifo.wr_addr[3] +.sym 16762 tx_fifo.wr_addr[2] +.sym 16764 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 16765 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 16767 tx_fifo.wr_addr[7] +.sym 16768 tx_fifo.wr_addr[6] +.sym 16769 tx_fifo.wr_addr[4] +.sym 16770 tx_fifo.wr_addr[5] +.sym 16773 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 16790 $nextpnr_ICESTORM_LC_2$O +.sym 16792 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 16796 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 16798 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 16800 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 16802 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 16805 tx_fifo.wr_addr[2] +.sym 16806 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 16808 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 16810 tx_fifo.wr_addr[3] +.sym 16812 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 16814 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 16817 tx_fifo.wr_addr[4] +.sym 16818 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 16820 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 16823 tx_fifo.wr_addr[5] +.sym 16824 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 16826 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 16828 tx_fifo.wr_addr[6] +.sym 16830 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 16832 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 16834 tx_fifo.wr_addr[7] +.sym 16836 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 16840 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[8] +.sym 16841 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 16842 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 16843 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 16844 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 16845 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 16846 w_smi_data_output[5] +.sym 16847 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] +.sym 16853 smi_ctrl_ins.tx_reg_state[3] +.sym 16854 w_tx_fifo_pulled_data[9] +.sym 16855 smi_ctrl_ins.tx_reg_state[1] +.sym 16856 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 16857 smi_ctrl_ins.tx_reg_state[2] +.sym 16862 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 16864 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] +.sym 16865 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 16867 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 16868 tx_fifo.wr_addr[8] +.sym 16869 w_smi_data_output[2] +.sym 16871 tx_fifo.rd_addr_gray_wr_r[6] +.sym 16872 w_tx_fifo_push +.sym 16873 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] +.sym 16876 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 16883 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 16887 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[6] +.sym 16888 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 16891 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 16892 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 16894 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 16895 tx_fifo.rd_addr_gray_wr_r[6] +.sym 16896 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 16900 tx_fifo.wr_addr[9] +.sym 16905 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 16911 tx_fifo.wr_addr[8] +.sym 16913 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 16915 tx_fifo.wr_addr[8] +.sym 16917 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 16920 tx_fifo.wr_addr[9] +.sym 16923 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 16926 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 16928 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[6] +.sym 16929 tx_fifo.rd_addr_gray_wr_r[6] +.sym 16933 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 16939 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 16944 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 16946 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 16953 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 16957 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 16960 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 16961 r_counter_$glb_clk +.sym 16962 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 16963 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 16964 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[2] +.sym 16965 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 16966 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 16967 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 16968 w_tx_fifo_data[19] +.sym 16969 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 16970 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 16975 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 16976 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] +.sym 16977 w_tx_fifo_pulled_data[24] +.sym 16979 w_tx_fifo_push +.sym 16980 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 16985 tx_fifo.wr_addr[2] +.sym 16986 o_smi_read_req$SB_IO_OUT +.sym 16987 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 16988 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 16990 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 16991 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 16992 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 16993 smi_ctrl_ins.int_cnt_rx[4] +.sym 16994 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 16996 w_tx_fifo_data[29] +.sym 16997 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 16998 w_tx_fifo_full +.sym 17005 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] +.sym 17007 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.sym 17008 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] +.sym 17009 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.sym 17010 smi_ctrl_ins.int_cnt_rx[3] +.sym 17011 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.sym 17012 tx_fifo.rd_addr_gray_wr_r[7] +.sym 17013 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.sym 17014 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.sym 17015 i_rst_b$SB_IO_IN +.sym 17017 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 17018 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] +.sym 17019 smi_ctrl_ins.int_cnt_rx[4] +.sym 17020 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 17021 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] +.sym 17022 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] +.sym 17023 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] +.sym 17024 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] +.sym 17025 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] +.sym 17027 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] +.sym 17030 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 17032 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] +.sym 17033 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] +.sym 17034 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] +.sym 17035 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] +.sym 17037 smi_ctrl_ins.int_cnt_rx[3] +.sym 17038 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] +.sym 17039 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] +.sym 17040 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.sym 17043 tx_fifo.rd_addr_gray_wr_r[7] +.sym 17044 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 17045 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 17046 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 17049 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] +.sym 17050 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] +.sym 17051 smi_ctrl_ins.int_cnt_rx[3] +.sym 17052 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] +.sym 17056 smi_ctrl_ins.int_cnt_rx[3] +.sym 17058 smi_ctrl_ins.int_cnt_rx[4] +.sym 17061 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] +.sym 17062 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] +.sym 17063 smi_ctrl_ins.int_cnt_rx[3] +.sym 17064 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.sym 17067 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.sym 17068 smi_ctrl_ins.int_cnt_rx[3] +.sym 17069 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] +.sym 17070 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.sym 17073 smi_ctrl_ins.int_cnt_rx[3] +.sym 17074 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] +.sym 17075 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] +.sym 17076 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.sym 17079 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] +.sym 17080 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] +.sym 17081 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] +.sym 17082 smi_ctrl_ins.int_cnt_rx[3] +.sym 17083 i_rst_b$SB_IO_IN +.sym 17084 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 17086 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 17087 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 17088 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 17089 tx_fifo.rd_addr_gray_wr_r[6] +.sym 17090 tx_fifo.rd_addr_gray_wr[4] +.sym 17091 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 17092 tx_fifo.rd_addr_gray_wr[6] +.sym 17093 tx_fifo.rd_addr_gray_wr_r[4] +.sym 17098 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17100 w_tx_fifo_pull +.sym 17101 w_rx_24_fifo_data[11] +.sym 17103 tx_fifo.rd_addr_gray_wr_r[2] +.sym 17104 smi_ctrl_ins.r_fifo_pushed_data[19] +.sym 17106 tx_fifo.rd_addr[7] +.sym 17108 tx_fifo.rd_addr_gray_wr_r[7] +.sym 17109 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.sym 17110 tx_fifo.wr_addr_gray[7] +.sym 17111 w_tx_fifo_push +.sym 17112 tx_fifo.wr_addr[9] +.sym 17113 tx_fifo.rd_addr_gray_wr_r[9] +.sym 17114 w_tx_fifo_push +.sym 17115 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 17116 w_rx_24_fifo_data[13] +.sym 17117 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 17118 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 17119 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 17120 tx_fifo.wr_addr_gray[1] +.sym 17121 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 17127 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 17128 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[2] +.sym 17129 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 17130 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[1] +.sym 17131 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 17132 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 17134 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 17135 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 17136 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[0] +.sym 17137 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 17138 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 17140 tx_fifo.rd_addr_gray_wr_r[2] +.sym 17141 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 17142 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 17143 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[3] +.sym 17144 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 17145 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 17147 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 17148 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 17149 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 17150 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 17152 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 17153 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 17157 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 17160 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 17161 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 17162 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 17163 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 17166 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 17167 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 17168 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 17169 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 17172 tx_fifo.rd_addr_gray_wr_r[2] +.sym 17173 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 17175 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 17178 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 17179 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 17180 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 17181 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 17187 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 17190 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 17191 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 17192 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 17193 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 17198 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 17199 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 17202 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[2] +.sym 17203 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[0] +.sym 17204 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[1] +.sym 17205 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[3] +.sym 17207 r_counter_$glb_clk +.sym 17208 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 17209 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[2] +.sym 17210 tx_fifo.wr_addr_gray[2] +.sym 17211 tx_fifo.wr_addr_gray[4] +.sym 17212 tx_fifo.wr_addr_gray[1] +.sym 17213 tx_fifo.wr_addr_gray[6] +.sym 17214 tx_fifo.wr_addr_gray[8] +.sym 17215 tx_fifo.wr_addr_gray[7] +.sym 17216 tx_fifo.wr_addr[9] +.sym 17221 tx_fifo.rd_addr_gray_wr[1] +.sym 17223 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 17224 tx_fifo.rd_addr_gray_wr_r[6] +.sym 17225 w_tx_fifo_pulled_data[30] +.sym 17226 tx_fifo.rd_addr_gray_wr_r[4] +.sym 17228 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17229 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 17231 tx_fifo.rd_addr_gray_wr[5] +.sym 17233 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 17235 i_ss$SB_IO_IN +.sym 17236 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 17238 w_rx_24_fifo_data[19] +.sym 17239 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 17240 tx_fifo.wr_addr[9] +.sym 17243 w_tx_fifo_data[1] +.sym 17244 tx_fifo.wr_addr_gray[2] +.sym 17252 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 17253 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 17256 i_rst_b$SB_IO_IN +.sym 17257 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 17259 w_tx_fifo_push +.sym 17261 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 17268 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 17269 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 17271 tx_fifo.rd_addr[0] +.sym 17274 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 17279 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 17281 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 17286 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 17289 tx_fifo.rd_addr[0] +.sym 17291 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 17295 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 17302 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 17303 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 17307 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 17314 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 17320 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 17326 i_rst_b$SB_IO_IN +.sym 17328 w_tx_fifo_push +.sym 17329 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 17330 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 17331 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 17332 tx_fifo.wr_addr_gray[3] +.sym 17333 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] +.sym 17334 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 17335 o_miso_$_TBUF__Y_E +.sym 17336 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] +.sym 17337 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[1] +.sym 17339 tx_fifo.wr_addr_gray[0] +.sym 17344 tx_fifo.rd_addr_gray[2] +.sym 17346 tx_fifo.rd_addr_gray[3] +.sym 17347 lvds_tx_inst.o_fifo_pull_SB_LUT4_I2_O +.sym 17348 tx_fifo.rd_addr_gray[0] +.sym 17349 w_rx_24_fifo_data[16] +.sym 17350 tx_fifo.rd_addr_gray[5] +.sym 17351 w_rx_24_fifo_data[24] +.sym 17352 tx_fifo.rd_addr[6] +.sym 17353 tx_fifo.rd_addr_gray_wr_r[2] +.sym 17356 tx_fifo.wr_addr[8] +.sym 17357 lvds_tx_inst.r_fifo_data[11] +.sym 17361 $PACKER_VCC_NET +.sym 17365 tx_fifo.wr_addr[8] +.sym 17366 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 17367 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 17378 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17379 w_rx_24_fifo_data[20] +.sym 17384 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 17385 tx_fifo.wr_addr_gray[6] +.sym 17386 tx_fifo.wr_addr_gray[8] +.sym 17387 w_rx_24_fifo_data[11] +.sym 17398 w_rx_24_fifo_data[19] +.sym 17399 w_rx_24_fifo_data[10] +.sym 17404 w_rx_24_fifo_data[28] +.sym 17412 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17414 w_rx_24_fifo_data[10] +.sym 17420 w_rx_24_fifo_data[20] +.sym 17421 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17424 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17426 w_rx_24_fifo_data[11] +.sym 17433 tx_fifo.wr_addr_gray[6] +.sym 17439 tx_fifo.wr_addr_gray[8] +.sym 17444 w_rx_24_fifo_data[28] +.sym 17445 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17450 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17451 w_rx_24_fifo_data[19] +.sym 17452 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 17453 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 17454 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 17457 spi_if_ins.spi.r_rx_bit_count[2] +.sym 17458 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.sym 17459 spi_if_ins.spi.r_rx_bit_count[1] +.sym 17460 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 17461 spi_if_ins.spi.r_rx_bit_count[0] +.sym 17462 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 17467 w_rx_24_fifo_data[24] +.sym 17468 lvds_tx_inst.r_fifo_data[20] +.sym 17469 lvds_tx_inst.r_fifo_data[22] +.sym 17473 w_rx_24_fifo_data[22] +.sym 17474 lvds_tx_inst.r_fifo_data[18] +.sym 17475 w_rx_24_fifo_data[20] +.sym 17476 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 17477 i_sck$SB_IO_IN +.sym 17478 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[0] +.sym 17481 o_miso_$_TBUF__Y_E +.sym 17483 tx_fifo.rd_addr[0] +.sym 17485 tx_fifo.rd_addr[5] +.sym 17486 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 17488 tx_fifo.rd_addr[1] +.sym 17497 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 17503 tx_fifo.wr_addr_gray[0] +.sym 17504 tx_fifo.wr_addr_gray[3] +.sym 17510 tx_fifo.wr_addr[9] +.sym 17511 i_rst_b$SB_IO_IN +.sym 17513 w_tx_fifo_pull +.sym 17514 tx_fifo.wr_addr_gray[2] +.sym 17518 tx_fifo.wr_addr_gray_rd[2] +.sym 17520 tx_fifo.wr_addr_gray_rd[3] +.sym 17521 tx_fifo.rd_addr[2] +.sym 17532 tx_fifo.wr_addr_gray[3] +.sym 17538 tx_fifo.wr_addr_gray_rd[2] +.sym 17542 tx_fifo.wr_addr_gray[0] +.sym 17547 tx_fifo.wr_addr_gray_rd[3] +.sym 17553 tx_fifo.rd_addr[2] +.sym 17554 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 17561 tx_fifo.wr_addr[9] +.sym 17565 tx_fifo.wr_addr_gray[2] +.sym 17571 w_tx_fifo_pull +.sym 17572 i_rst_b$SB_IO_IN +.sym 17576 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 17580 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 17581 spi_if_ins.spi.r_rx_done +.sym 17582 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 17584 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17585 lvds_rx_24_inst.r_phase_count[0] +.sym 17590 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 17591 lvds_tx_inst.r_fifo_data[23] +.sym 17594 w_tx_fifo_pulled_data[7] +.sym 17595 lvds_tx_inst.r_fifo_data[21] +.sym 17597 i_sck$SB_IO_IN +.sym 17599 tx_fifo.rd_addr[7] +.sym 17601 i_ss$SB_IO_IN +.sym 17602 w_tx_fifo_push +.sym 17603 i_ss$SB_IO_IN +.sym 17604 w_tx_fifo_push +.sym 17606 w_rx_24_fifo_data[2] +.sym 17607 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 17609 tx_fifo.rd_addr_gray_wr_r[9] +.sym 17621 w_rx_24_fifo_data[12] +.sym 17624 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17625 w_rx_24_fifo_data[8] +.sym 17633 w_rx_24_fifo_data[24] +.sym 17637 w_rx_24_fifo_data[14] +.sym 17643 w_rx_24_fifo_data[0] +.sym 17644 w_rx_24_fifo_data[23] +.sym 17646 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 17647 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 17652 w_rx_24_fifo_data[23] +.sym 17655 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17658 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17659 w_rx_24_fifo_data[8] +.sym 17665 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17666 w_rx_24_fifo_data[12] +.sym 17677 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17679 w_rx_24_fifo_data[24] +.sym 17684 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 17689 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17691 w_rx_24_fifo_data[0] +.sym 17696 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 17697 w_rx_24_fifo_data[14] +.sym 17698 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 17699 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 17700 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 17701 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 17702 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 17703 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 17704 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 17705 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 17706 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 17707 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 17708 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17713 w_rx_24_fifo_data[25] +.sym 17719 i_sck$SB_IO_IN +.sym 17721 w_rx_24_fifo_data[8] +.sym 17723 i_ss$SB_IO_IN +.sym 17725 i_glob_clock$SB_IO_IN +.sym 17730 spi_if_ins.w_rx_data[3] +.sym 17732 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17734 tx_fifo.rd_addr[0] +.sym 17735 w_tx_fifo_data[1] +.sym 17736 spi_if_ins.w_rx_data[4] +.sym 17749 tx_fifo.rd_addr_gray_wr[9] +.sym 17753 spi_if_ins.spi.r_rx_done +.sym 17757 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 17758 spi_if_ins.spi.r2_rx_done +.sym 17768 spi_if_ins.spi.r3_rx_done +.sym 17769 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17775 spi_if_ins.spi.r_rx_done +.sym 17783 tx_fifo.rd_addr_gray_wr[9] +.sym 17787 spi_if_ins.spi.r2_rx_done +.sym 17793 spi_if_ins.spi.r3_rx_done +.sym 17796 spi_if_ins.spi.r2_rx_done +.sym 17808 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17818 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] .sym 17822 r_counter_$glb_clk -.sym 17823 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 17825 r_tx_data[2] -.sym 17826 r_tx_data[3] -.sym 17827 rx_fifo.mem_q.0.3_WDATA_1 -.sym 17848 w_tx_data_io[4] -.sym 17849 r_tx_data[5] -.sym 17853 i_config[2]$SB_IO_IN -.sym 17865 i_button_SB_LUT4_I0_I1[2] -.sym 17866 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 17867 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 17868 w_ioc[0] -.sym 17869 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 17870 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 17872 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] -.sym 17873 i_rst_b$SB_IO_IN -.sym 17874 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 17875 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 17876 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 17878 i_button_SB_LUT4_I0_I1[0] -.sym 17879 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] -.sym 17880 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 17881 w_cs[1] -.sym 17883 i_config[1]$SB_IO_IN -.sym 17884 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 17885 i_button_SB_LUT4_I0_I2[2] -.sym 17888 i_config[0]$SB_IO_IN -.sym 17894 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 17898 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 17899 w_ioc[0] -.sym 17901 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 17905 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 17906 i_rst_b$SB_IO_IN -.sym 17907 w_cs[1] -.sym 17910 i_button_SB_LUT4_I0_I1[0] -.sym 17911 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 17912 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 17913 i_config[0]$SB_IO_IN -.sym 17916 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 17918 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 17919 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 17922 i_button_SB_LUT4_I0_I1[0] -.sym 17923 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] -.sym 17924 i_config[1]$SB_IO_IN -.sym 17925 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] -.sym 17929 i_button_SB_LUT4_I0_I1[2] -.sym 17931 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 17936 i_button_SB_LUT4_I0_I2[2] -.sym 17937 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 17944 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] +.sym 17824 spi_if_ins.spi.r_rx_byte[0] +.sym 17825 spi_if_ins.spi.r_rx_byte[3] +.sym 17826 spi_if_ins.spi.r_rx_byte[5] +.sym 17827 spi_if_ins.spi.r_rx_byte[6] +.sym 17828 spi_if_ins.spi.r_rx_byte[2] +.sym 17829 spi_if_ins.spi.r_rx_byte[1] +.sym 17830 spi_if_ins.spi.r_rx_byte[4] +.sym 17831 spi_if_ins.spi.r_rx_byte[7] +.sym 17838 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 17842 i_sck$SB_IO_IN +.sym 17843 spi_if_ins.r_tx_byte[7] +.sym 17844 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 17845 w_load +.sym 17848 tx_fifo.wr_addr[4] +.sym 17849 i_config[1]$SB_IO_IN +.sym 17853 i_rst_b$SB_IO_IN +.sym 17854 w_tx_data_io[1] +.sym 17855 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 17856 smi_ctrl_ins.soe_and_reset +.sym 17858 tx_fifo.wr_addr[8] +.sym 17859 i_button_SB_LUT4_I0_I1[0] +.sym 17876 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17883 spi_if_ins.spi.r_rx_byte[5] +.sym 17884 spi_if_ins.spi.r_rx_byte[6] +.sym 17888 spi_if_ins.spi.r_rx_byte[7] +.sym 17889 spi_if_ins.spi.r_rx_byte[0] +.sym 17890 spi_if_ins.spi.r_rx_byte[3] +.sym 17893 spi_if_ins.spi.r_rx_byte[2] +.sym 17894 spi_if_ins.spi.r_rx_byte[1] +.sym 17895 spi_if_ins.spi.r_rx_byte[4] +.sym 17900 spi_if_ins.spi.r_rx_byte[3] +.sym 17904 spi_if_ins.spi.r_rx_byte[2] +.sym 17912 spi_if_ins.spi.r_rx_byte[1] +.sym 17918 spi_if_ins.spi.r_rx_byte[4] +.sym 17924 spi_if_ins.spi.r_rx_byte[5] +.sym 17928 spi_if_ins.spi.r_rx_byte[0] +.sym 17935 spi_if_ins.spi.r_rx_byte[6] +.sym 17942 spi_if_ins.spi.r_rx_byte[7] +.sym 17944 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .sym 17945 r_counter_$glb_clk -.sym 17946 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 17949 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 17950 w_tx_data_io[7] -.sym 17951 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 17954 w_tx_data_io[5] -.sym 17962 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 17963 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 17965 w_rx_09_fifo_data[13] -.sym 17968 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 17969 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 17988 i_button_SB_LUT4_I0_I1[2] -.sym 17989 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 17990 w_ioc[0] -.sym 17991 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 17992 o_tr_vc1_b$SB_IO_OUT -.sym 17993 w_rx_data[7] -.sym 17994 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 17995 i_button_SB_LUT4_I0_I1[0] -.sym 17996 io_ctrl_ins.pmod_dir_state[7] -.sym 17998 w_ioc[0] -.sym 18000 w_rx_data[5] -.sym 18001 i_button$SB_IO_IN -.sym 18003 io_ctrl_ins.o_pmod[4] -.sym 18005 io_ctrl_ins.pmod_dir_state[5] -.sym 18006 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 18007 i_config[3]$SB_IO_IN -.sym 18008 w_rx_data[6] -.sym 18013 i_config[2]$SB_IO_IN -.sym 18017 io_ctrl_ins.pmod_dir_state[6] -.sym 18024 w_rx_data[7] -.sym 18029 w_rx_data[5] -.sym 18033 i_config[2]$SB_IO_IN -.sym 18034 io_ctrl_ins.pmod_dir_state[5] -.sym 18035 i_button_SB_LUT4_I0_I1[2] -.sym 18036 i_button_SB_LUT4_I0_I1[0] -.sym 18039 io_ctrl_ins.pmod_dir_state[7] -.sym 18040 i_button_SB_LUT4_I0_I1[2] -.sym 18041 i_button_SB_LUT4_I0_I1[0] -.sym 18042 i_button$SB_IO_IN -.sym 18045 w_ioc[0] -.sym 18046 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 18047 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 18048 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 18052 w_rx_data[6] -.sym 18057 o_tr_vc1_b$SB_IO_OUT -.sym 18058 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 18059 io_ctrl_ins.o_pmod[4] -.sym 18060 w_ioc[0] -.sym 18063 i_config[3]$SB_IO_IN -.sym 18064 i_button_SB_LUT4_I0_I1[2] -.sym 18065 i_button_SB_LUT4_I0_I1[0] -.sym 18066 io_ctrl_ins.pmod_dir_state[6] -.sym 18067 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 18068 r_counter_$glb_clk -.sym 18076 w_tx_data_io[6] -.sym 18078 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 18111 w_rx_data[7] -.sym 18112 w_rx_data[5] -.sym 18113 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O -.sym 18119 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 18126 w_ioc[0] -.sym 18129 io_ctrl_ins.o_pmod[5] -.sym 18130 w_rx_data[6] -.sym 18133 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18135 io_ctrl_ins.o_pmod[6] -.sym 18136 io_ctrl_ins.o_pmod[7] -.sym 18139 o_rx_h_tx_l$SB_IO_OUT -.sym 18141 o_tr_vc1$SB_IO_OUT -.sym 18147 w_rx_data[6] -.sym 18151 w_rx_data[7] -.sym 18157 w_rx_data[5] -.sym 18168 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18169 io_ctrl_ins.o_pmod[6] -.sym 18170 w_ioc[0] -.sym 18171 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 18174 o_rx_h_tx_l$SB_IO_OUT -.sym 18175 io_ctrl_ins.o_pmod[7] -.sym 18176 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 18177 w_ioc[0] -.sym 18186 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 18187 io_ctrl_ins.o_pmod[5] -.sym 18188 o_tr_vc1$SB_IO_OUT -.sym 18189 w_ioc[0] -.sym 18190 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O +.sym 17949 smi_ctrl_ins.soe_and_reset +.sym 17959 spi_if_ins.w_rx_data[3] +.sym 17960 w_rx_24_fifo_data[1] +.sym 17961 spi_if_ins.w_rx_data[0] +.sym 17962 w_rx_data[2] +.sym 17963 w_tx_fifo_pulled_data[2] +.sym 17964 w_rx_data[0] +.sym 17965 i_sck$SB_IO_IN +.sym 17966 $PACKER_VCC_NET +.sym 17967 spi_if_ins.w_rx_data[4] +.sym 17968 w_rx_data[4] +.sym 17969 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17971 tx_fifo.rd_addr[0] +.sym 17973 tx_fifo.rd_addr[5] +.sym 17974 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 17978 w_fetch +.sym 17981 tx_fifo.rd_addr[1] +.sym 17988 w_tx_data_io[7] +.sym 17989 w_cs[3] +.sym 17990 w_cs[2] +.sym 17991 w_cs[0] +.sym 17992 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 17996 w_tx_data_io[4] +.sym 17997 i_glob_clock$SB_IO_IN +.sym 17998 w_tx_data_io[5] +.sym 17999 r_tx_data_SB_DFFE_Q_E +.sym 18000 w_tx_data_smi[1] +.sym 18001 w_cs[1] +.sym 18002 w_tx_data_io[6] +.sym 18004 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 18012 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 18014 w_tx_data_io[1] +.sym 18017 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18018 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1] +.sym 18019 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 18021 w_tx_data_io[7] +.sym 18023 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18024 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 18027 w_tx_data_io[6] +.sym 18028 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18034 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1] +.sym 18035 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 18039 w_tx_data_io[1] +.sym 18040 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 18041 w_tx_data_smi[1] +.sym 18042 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18045 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18048 w_tx_data_io[4] +.sym 18051 w_cs[0] +.sym 18052 w_cs[1] +.sym 18053 w_cs[3] +.sym 18054 w_cs[2] +.sym 18057 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18058 w_tx_data_io[5] +.sym 18060 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 18063 w_cs[0] +.sym 18064 w_cs[1] +.sym 18065 w_cs[3] +.sym 18066 w_cs[2] +.sym 18067 r_tx_data_SB_DFFE_Q_E +.sym 18068 i_glob_clock$SB_IO_IN +.sym 18069 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 18070 o_led1$SB_IO_OUT +.sym 18072 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 18074 o_led0$SB_IO_OUT +.sym 18077 i_button_SB_LUT4_I0_I1[1] +.sym 18082 w_tx_data_io[7] +.sym 18084 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 18086 w_tx_data_io[5] +.sym 18087 w_cs[0] +.sym 18089 w_ioc[0] +.sym 18090 w_tx_data_io[6] +.sym 18094 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18095 w_rx_data[5] +.sym 18097 w_rx_data[6] +.sym 18099 w_rx_data[1] +.sym 18101 w_tx_fifo_push +.sym 18105 w_rx_data[3] +.sym 18114 io_ctrl_ins.pmod_dir_state[3] +.sym 18115 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18117 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3] +.sym 18118 w_ioc[1] +.sym 18119 i_config[1]$SB_IO_IN +.sym 18120 io_ctrl_ins.pmod_dir_state[0] +.sym 18121 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] +.sym 18122 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 18123 w_load +.sym 18125 w_cs[1] +.sym 18126 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 18127 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18129 i_button_SB_LUT4_I0_I1[0] +.sym 18131 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 18134 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 18135 o_led1$SB_IO_OUT +.sym 18137 io_ctrl_ins.debug_mode[0] +.sym 18138 w_fetch +.sym 18139 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2] +.sym 18141 w_ioc[0] +.sym 18142 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] +.sym 18144 i_button_SB_LUT4_I0_I1[0] +.sym 18145 i_config[1]$SB_IO_IN +.sym 18146 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] +.sym 18147 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] +.sym 18156 i_button_SB_LUT4_I0_I1[0] +.sym 18157 w_cs[1] +.sym 18158 w_fetch +.sym 18159 w_load +.sym 18162 o_led1$SB_IO_OUT +.sym 18163 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3] +.sym 18164 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2] +.sym 18165 i_button_SB_LUT4_I0_I1[0] +.sym 18168 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 18169 w_ioc[1] +.sym 18171 w_ioc[0] +.sym 18174 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 18175 io_ctrl_ins.pmod_dir_state[0] +.sym 18176 io_ctrl_ins.debug_mode[0] +.sym 18177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18180 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18181 io_ctrl_ins.pmod_dir_state[3] +.sym 18182 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18183 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 18186 w_ioc[0] +.sym 18188 w_ioc[1] +.sym 18189 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 18190 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E .sym 18191 r_counter_$glb_clk -.sym 18345 i_config[2]$SB_IO_IN +.sym 18192 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 18193 io_ctrl_ins.o_pmod[3] +.sym 18194 io_ctrl_ins.o_pmod[0] +.sym 18196 io_ctrl_ins.o_pmod[1] +.sym 18197 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2] +.sym 18198 io_ctrl_ins.o_pmod[4] +.sym 18200 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] +.sym 18207 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[3] +.sym 18210 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 18211 w_rx_data[1] +.sym 18212 w_tx_data_io[0] +.sym 18214 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 18215 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18217 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 18218 w_ioc[0] +.sym 18219 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 18222 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18224 w_ioc[0] +.sym 18227 tx_fifo.rd_addr[0] +.sym 18235 w_load +.sym 18236 w_rx_data[4] +.sym 18237 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18238 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18239 w_fetch +.sym 18240 w_rx_data[0] +.sym 18241 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 18244 w_rx_data[2] +.sym 18245 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 18248 io_ctrl_ins.debug_mode[1] +.sym 18249 i_rst_b$SB_IO_IN +.sym 18250 io_ctrl_ins.pmod_dir_state[4] +.sym 18252 w_cs[1] +.sym 18259 w_rx_data[1] +.sym 18263 io_ctrl_ins.pmod_dir_state[1] +.sym 18265 w_rx_data[3] +.sym 18267 w_rx_data[4] +.sym 18276 w_rx_data[0] +.sym 18279 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18280 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18281 io_ctrl_ins.pmod_dir_state[4] +.sym 18282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 18286 w_rx_data[3] +.sym 18294 w_rx_data[2] +.sym 18300 w_rx_data[1] +.sym 18303 io_ctrl_ins.pmod_dir_state[1] +.sym 18304 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 18305 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 18306 io_ctrl_ins.debug_mode[1] +.sym 18309 w_load +.sym 18310 w_cs[1] +.sym 18311 w_fetch +.sym 18312 i_rst_b$SB_IO_IN +.sym 18313 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 18314 r_counter_$glb_clk +.sym 18316 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 18317 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 18318 io_ctrl_ins.o_pmod[6] +.sym 18319 io_ctrl_ins.o_pmod[5] +.sym 18320 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 18321 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[2] +.sym 18322 io_ctrl_ins.o_pmod[7] +.sym 18323 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 18329 w_ioc[0] +.sym 18330 w_rx_data[2] +.sym 18332 w_rx_data[0] +.sym 18334 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 18335 o_shdn_rx_lna$SB_IO_OUT +.sym 18336 w_rx_data[4] +.sym 18337 io_ctrl_ins.o_pmod[0] +.sym 18339 o_tr_vc1_b$SB_IO_OUT +.sym 18340 i_rst_b$SB_IO_IN +.sym 18341 i_config[1]$SB_IO_IN +.sym 18346 smi_ctrl_ins.soe_and_reset +.sym 18351 i_button_SB_LUT4_I0_I1[0] +.sym 18359 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 18360 w_rx_data[0] +.sym 18362 w_rx_data[2] +.sym 18363 w_ioc[0] +.sym 18364 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 18369 w_rx_data[1] +.sym 18370 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 18372 w_rx_data[4] +.sym 18374 io_ctrl_ins.debug_mode[0] +.sym 18375 w_rx_data[3] +.sym 18379 io_ctrl_ins.debug_mode[1] +.sym 18393 w_rx_data[2] +.sym 18398 w_rx_data[0] +.sym 18411 w_rx_data[4] +.sym 18414 w_rx_data[3] +.sym 18420 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 18421 w_ioc[0] +.sym 18423 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 18429 w_rx_data[1] +.sym 18432 io_ctrl_ins.debug_mode[0] +.sym 18435 io_ctrl_ins.debug_mode[1] +.sym 18436 io_ctrl_ins.rf_mode_SB_DFFER_Q_E +.sym 18437 r_counter_$glb_clk +.sym 18438 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 18442 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 18443 io_ctrl_ins.pmod_dir_state[7] +.sym 18444 io_ctrl_ins.pmod_dir_state[6] +.sym 18446 io_ctrl_ins.pmod_dir_state[5] +.sym 18451 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 18452 io_ctrl_ins.o_pmod[7] +.sym 18453 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 18454 io_ctrl_ins.o_pmod[5] +.sym 18456 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18458 $PACKER_VCC_NET +.sym 18459 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18461 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18462 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 18482 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 18484 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18487 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 18490 io_ctrl_ins.rf_pin_state[2] +.sym 18491 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18492 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 18513 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18514 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 18515 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18516 io_ctrl_ins.rf_pin_state[2] +.sym 18526 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 18559 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 18560 r_counter_$glb_clk .sym 18562 i_config[1]$SB_IO_IN .sym 18564 i_config[2]$SB_IO_IN -.sym 18632 o_led0$SB_IO_OUT +.sym 18572 w_tx_fifo_pull +.sym 18573 w_rx_data[7] +.sym 18574 i_button$SB_IO_IN +.sym 18575 io_ctrl_ins.pmod_dir_state[5] +.sym 18586 w_rx_data[6] +.sym 18591 w_rx_data[5] +.sym 18602 i_button$SB_IO_IN +.sym 18633 i_config[2]$SB_IO_IN .sym 18636 w_smi_data_output[4] -.sym 18638 i_smi_a2$rename$0 -.sym 18651 w_smi_data_output[4] -.sym 18653 i_smi_a2$rename$0 -.sym 18679 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 18693 i_smi_a2$rename$0 +.sym 18638 i_smi_a2$SB_IO_IN +.sym 18642 $PACKER_VCC_NET +.sym 18648 i_smi_a2$SB_IO_IN +.sym 18649 w_smi_data_output[4] +.sym 18658 $PACKER_VCC_NET +.sym 18662 w_tx_fifo_pulled_data[8] +.sym 18666 w_tx_fifo_pulled_data[10] +.sym 18671 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 18673 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 18674 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 18677 tx_fifo.wr_addr[3] +.sym 18684 tx_fifo.wr_addr[4] .sym 18695 i_ss$SB_IO_IN -.sym 18703 i_sck$SB_IO_IN -.sym 18705 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 18714 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 18716 i_ss$SB_IO_IN -.sym 18755 i_ss$SB_IO_IN -.sym 18779 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 18782 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 18783 i_sck$SB_IO_IN -.sym 18784 i_ss$SB_IO_IN +.sym 18710 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 18720 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 18721 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 18723 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 18730 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 18732 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 18733 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 18734 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 18736 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 18743 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 18749 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 18757 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 18762 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 18767 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 18769 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 18775 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 18778 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 18782 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 18783 r_counter_$glb_clk +.sym 18784 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 18785 i_smi_soe_se$SB_IO_IN -.sym 18805 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 18858 i_ss_SB_LUT4_I3_O +.sym 18787 w_smi_data_input[5] +.sym 18790 w_tx_fifo_pulled_data[9] +.sym 18794 w_tx_fifo_pulled_data[11] +.sym 18803 tx_fifo.wr_addr[8] +.sym 18807 tx_fifo.wr_addr[6] +.sym 18810 w_tx_fifo_push +.sym 18812 w_tx_fifo_data[10] +.sym 18814 tx_fifo.wr_addr[3] +.sym 18818 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 18820 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 18824 tx_fifo.wr_addr[7] +.sym 18827 tx_fifo.wr_addr[6] +.sym 18830 tx_fifo.rd_addr[5] +.sym 18831 tx_fifo.wr_addr[5] +.sym 18832 tx_fifo.rd_addr[2] +.sym 18834 w_smi_data_input[5] +.sym 18835 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 18837 tx_fifo.wr_addr[2] +.sym 18838 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 18840 tx_fifo.wr_addr[3] +.sym 18841 tx_fifo.wr_addr[9] +.sym 18842 tx_fifo.wr_addr[7] +.sym 18844 tx_fifo.wr_addr[6] +.sym 18846 tx_fifo.wr_addr[4] +.sym 18849 tx_fifo.rd_addr_gray_wr_r[7] +.sym 18851 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 18853 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 18854 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 18855 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 18856 $PACKER_VCC_NET +.sym 18858 tx_fifo.wr_addr[4] .sym 18859 w_smi_data_output[5] -.sym 18866 i_sck$SB_IO_IN -.sym 18868 spi_if_ins.spi.r_rx_bit_count[2] -.sym 18870 i_ss$SB_IO_IN -.sym 18874 i_ss$SB_IO_IN -.sym 18878 spi_if_ins.spi.r_rx_bit_count[0] -.sym 18895 spi_if_ins.spi.r_rx_bit_count[1] -.sym 18898 $nextpnr_ICESTORM_LC_5$O -.sym 18900 spi_if_ins.spi.r_rx_bit_count[0] -.sym 18904 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 18906 spi_if_ins.spi.r_rx_bit_count[1] -.sym 18913 spi_if_ins.spi.r_rx_bit_count[2] -.sym 18914 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 18918 spi_if_ins.spi.r_rx_bit_count[1] -.sym 18919 spi_if_ins.spi.r_rx_bit_count[0] -.sym 18920 spi_if_ins.spi.r_rx_bit_count[2] -.sym 18924 spi_if_ins.spi.r_rx_bit_count[0] -.sym 18929 spi_if_ins.spi.r_rx_bit_count[0] -.sym 18932 spi_if_ins.spi.r_rx_bit_count[1] -.sym 18935 spi_if_ins.spi.r_rx_bit_count[2] -.sym 18936 spi_if_ins.spi.r_rx_bit_count[0] -.sym 18937 spi_if_ins.spi.r_rx_bit_count[1] -.sym 18938 i_ss$SB_IO_IN -.sym 18946 i_sck$SB_IO_IN -.sym 18947 i_ss$SB_IO_IN -.sym 18958 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 18972 rx_fifo.wr_addr[2] +.sym 18866 tx_fifo.wr_addr[3] +.sym 18869 tx_fifo.wr_addr[4] +.sym 18870 tx_fifo.wr_addr[5] +.sym 18872 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 18875 tx_fifo.wr_addr[7] +.sym 18876 tx_fifo.wr_addr[6] +.sym 18886 tx_fifo.wr_addr[2] +.sym 18888 tx_fifo.wr_addr[8] +.sym 18898 $nextpnr_ICESTORM_LC_1$O +.sym 18901 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 18904 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 18906 tx_fifo.wr_addr[2] +.sym 18908 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 18910 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 18913 tx_fifo.wr_addr[3] +.sym 18914 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 18916 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 18919 tx_fifo.wr_addr[4] +.sym 18920 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 18922 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 18925 tx_fifo.wr_addr[5] +.sym 18926 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 18928 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 18931 tx_fifo.wr_addr[6] +.sym 18932 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 18934 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 18937 tx_fifo.wr_addr[7] +.sym 18938 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 18940 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 18942 tx_fifo.wr_addr[8] +.sym 18944 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 18949 w_tx_fifo_pulled_data[24] +.sym 18953 w_tx_fifo_pulled_data[26] +.sym 18964 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 18967 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 18970 smi_ctrl_ins.tx_reg_state[0] +.sym 18971 tx_fifo.rd_addr[1] +.sym 18972 tx_fifo.wr_addr[3] +.sym 18973 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 18974 w_tx_fifo_data[25] +.sym 18975 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] .sym 18976 w_smi_data_output[5] -.sym 18981 rx_fifo.wr_addr[6] -.sym 18983 i_rst_b$SB_IO_IN -.sym 18990 i_ss$SB_IO_IN -.sym 19000 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 19058 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 19059 i_ss$SB_IO_IN -.sym 19098 rx_fifo.mem_i.0.3_RDATA_1[0] -.sym 19100 rx_fifo.mem_i.0.0_RDATA_1[1] -.sym 19102 rx_fifo.wr_addr[0] -.sym 19106 rx_fifo.mem_i.0.1_RDATA[0] -.sym 19114 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 19118 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 19119 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 19124 rx_fifo.wr_addr[4] -.sym 19126 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 19130 rx_fifo.mem_i.0.1_RDATA[0] -.sym 19135 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19138 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] -.sym 19139 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 19142 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19143 i_rst_b$SB_IO_IN -.sym 19151 rx_fifo.wr_addr[4] -.sym 19158 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 19159 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 19160 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 19169 rx_fifo.mem_i.0.1_RDATA[0] -.sym 19170 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19181 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 19182 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 19183 i_rst_b$SB_IO_IN -.sym 19184 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] -.sym 19191 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 19192 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 19193 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19195 rx_fifo.mem_i.0.1_RDATA_3[1] -.sym 19199 rx_fifo.mem_i.0.1_RDATA_2[0] -.sym 19214 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 19223 rx_fifo.wr_addr[7] -.sym 19225 rx_fifo.mem_q.0.3_RDATA_2[0] -.sym 19226 rx_fifo.wr_addr[3] -.sym 19227 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 19228 rx_fifo.wr_addr[7] -.sym 19237 w_rx_24_fifo_data[22] -.sym 19238 w_rx_09_fifo_data[22] -.sym 19239 w_rx_09_fifo_data[23] -.sym 19240 w_rx_24_fifo_data[23] -.sym 19242 w_rx_09_fifo_data[21] -.sym 19244 w_rx_24_fifo_data[21] -.sym 19245 w_rx_24_fifo_data[20] -.sym 19248 w_rx_09_fifo_data[20] -.sym 19252 rx_fifo.mem_i.0.1_RDATA_1[1] -.sym 19253 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 19256 rx_fifo.mem_i.0.0_RDATA_3[0] -.sym 19257 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19260 rx_fifo.mem_i.0.0_RDATA_1[1] -.sym 19261 channel -.sym 19264 rx_fifo.mem_i.0.1_RDATA_2[0] -.sym 19266 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 19268 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 19269 w_rx_24_fifo_data[23] -.sym 19270 w_rx_09_fifo_data[23] -.sym 19271 channel -.sym 19275 rx_fifo.mem_i.0.1_RDATA_2[0] -.sym 19277 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19280 w_rx_09_fifo_data[20] -.sym 19281 channel -.sym 19282 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 19283 w_rx_24_fifo_data[20] -.sym 19286 channel -.sym 19287 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 19288 w_rx_09_fifo_data[22] -.sym 19289 w_rx_24_fifo_data[22] -.sym 19292 w_rx_24_fifo_data[21] -.sym 19293 channel -.sym 19294 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 19295 w_rx_09_fifo_data[21] -.sym 19300 rx_fifo.mem_i.0.0_RDATA_3[0] -.sym 19301 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19304 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19305 rx_fifo.mem_i.0.1_RDATA_1[1] -.sym 19311 rx_fifo.mem_i.0.0_RDATA_1[1] -.sym 19313 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19314 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 19315 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 19316 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19318 rx_fifo.mem_i.0.1_RDATA_1[1] -.sym 19322 rx_fifo.mem_i.0.1_RDATA[0] -.sym 19329 $PACKER_VCC_NET -.sym 19331 w_rx_24_fifo_data[20] -.sym 19333 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 19334 smi_ctrl_ins.int_cnt[4] -.sym 19336 w_rx_09_fifo_data[20] -.sym 19338 smi_ctrl_ins.int_cnt[3] -.sym 19339 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 19340 rx_fifo.wr_addr[1] -.sym 19341 rx_fifo.mem_q.0.3_RDATA[0] -.sym 19342 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 19344 rx_fifo.rd_addr[2] -.sym 19345 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 19347 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 19348 rx_fifo.wr_addr[9] -.sym 19349 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 19350 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 19352 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 19359 rx_fifo.mem_q.0.3_RDATA[0] -.sym 19360 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 19361 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19363 rx_fifo.mem_q.0.0_RDATA[1] -.sym 19367 rx_fifo.mem_i.0.1_RDATA_3[1] -.sym 19368 rx_fifo.mem_i.0.3_RDATA_1[0] -.sym 19369 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 19370 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 19375 smi_ctrl_ins.int_cnt[3] -.sym 19379 rx_fifo.mem_i.0.2_RDATA_2[1] -.sym 19383 smi_ctrl_ins.int_cnt[4] -.sym 19384 rx_fifo.mem_i.0.2_RDATA_1[0] -.sym 19385 rx_fifo.mem_q.0.3_RDATA_2[0] -.sym 19391 rx_fifo.mem_q.0.3_RDATA_2[0] -.sym 19392 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19397 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 19398 smi_ctrl_ins.int_cnt[4] -.sym 19399 smi_ctrl_ins.int_cnt[3] -.sym 19400 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 19404 rx_fifo.mem_q.0.3_RDATA[0] -.sym 19406 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19409 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19411 rx_fifo.mem_q.0.0_RDATA[1] -.sym 19415 rx_fifo.mem_i.0.1_RDATA_3[1] -.sym 19416 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19421 rx_fifo.mem_i.0.2_RDATA_1[0] -.sym 19423 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19428 rx_fifo.mem_i.0.3_RDATA_1[0] -.sym 19430 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19433 rx_fifo.mem_i.0.2_RDATA_2[1] -.sym 19435 rx_fifo.mem_i.0.0_RDATA[1] -.sym 19437 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 19438 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 18977 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] +.sym 18978 tx_fifo.wr_addr[4] +.sym 18980 $PACKER_VCC_NET +.sym 18981 w_tx_fifo_push +.sym 18983 w_tx_fifo_data[11] +.sym 18984 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 18990 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.sym 18992 tx_fifo.wr_addr[9] +.sym 18993 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] +.sym 18994 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 18996 tx_fifo.rd_addr_gray_wr_r[9] +.sym 18999 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 19000 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 19002 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 19003 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[6] +.sym 19004 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[7] +.sym 19005 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[8] +.sym 19006 tx_fifo.rd_addr_gray_wr_r[8] +.sym 19007 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 19008 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 19012 tx_fifo.rd_addr_gray_wr_r[4] +.sym 19013 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] +.sym 19014 tx_fifo.rd_addr_gray_wr_r[7] +.sym 19016 i_rst_b$SB_IO_IN +.sym 19017 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 19020 smi_ctrl_ins.int_cnt_rx[3] +.sym 19023 tx_fifo.wr_addr[9] +.sym 19025 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 19028 tx_fifo.rd_addr_gray_wr_r[8] +.sym 19029 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[7] +.sym 19030 tx_fifo.rd_addr_gray_wr_r[9] +.sym 19031 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[8] +.sym 19035 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 19037 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 19040 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 19041 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 19042 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 19043 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 19046 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 19047 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 19052 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[6] +.sym 19053 tx_fifo.rd_addr_gray_wr_r[7] +.sym 19055 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[7] +.sym 19058 smi_ctrl_ins.int_cnt_rx[3] +.sym 19059 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.sym 19060 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] +.sym 19061 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] +.sym 19066 tx_fifo.rd_addr_gray_wr_r[4] +.sym 19067 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 19068 i_rst_b$SB_IO_IN +.sym 19069 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 19072 w_tx_fifo_pulled_data[25] +.sym 19076 w_tx_fifo_pulled_data[27] +.sym 19082 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 19086 w_tx_fifo_data[26] +.sym 19088 tx_fifo.wr_addr[9] +.sym 19092 tx_fifo.rd_addr_gray_wr_r[9] +.sym 19095 tx_fifo.rd_addr[0] +.sym 19096 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19097 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 19098 tx_fifo.rd_addr_gray_wr_r[4] +.sym 19099 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 19100 w_tx_fifo_data[16] +.sym 19101 w_tx_fifo_data[17] +.sym 19102 w_tx_fifo_data[13] +.sym 19103 tx_fifo.wr_addr[7] +.sym 19104 tx_fifo.rd_addr_gray_wr[0] +.sym 19105 tx_fifo.wr_addr[6] +.sym 19106 smi_ctrl_ins.int_cnt_rx[3] +.sym 19113 smi_ctrl_ins.r_fifo_pushed_data[19] +.sym 19114 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 19115 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 19116 w_tx_fifo_push +.sym 19117 tx_fifo.rd_addr_gray_wr_r[7] +.sym 19118 tx_fifo.rd_addr_gray_wr_r[2] +.sym 19119 tx_fifo.rd_addr_gray_wr_r[4] +.sym 19120 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 19121 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 19122 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 19123 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 19124 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 19126 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 19127 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] +.sym 19129 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 19130 tx_fifo.rd_addr_gray_wr_r[8] +.sym 19131 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 19132 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 19133 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 19136 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 19137 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] +.sym 19138 w_tx_fifo_full +.sym 19140 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 19141 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 19142 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 19143 tx_fifo.rd_addr_gray_wr_r[9] +.sym 19145 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 19146 w_tx_fifo_full +.sym 19147 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 19148 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 19151 tx_fifo.rd_addr_gray_wr_r[4] +.sym 19152 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 19153 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 19154 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 19157 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 19158 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 19159 w_tx_fifo_push +.sym 19160 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 19163 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 19164 tx_fifo.rd_addr_gray_wr_r[2] +.sym 19165 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 19169 tx_fifo.rd_addr_gray_wr_r[9] +.sym 19170 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 19171 tx_fifo.rd_addr_gray_wr_r[8] +.sym 19172 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 19177 smi_ctrl_ins.r_fifo_pushed_data[19] +.sym 19181 tx_fifo.rd_addr_gray_wr_r[2] +.sym 19182 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 19183 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 19184 tx_fifo.rd_addr_gray_wr_r[7] +.sym 19187 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 19188 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] +.sym 19189 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 19190 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] +.sym 19191 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 19192 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 19193 smi_ctrl_ins.tx_reg_state_SB_LUT4_I3_O_$glb_sr +.sym 19195 w_tx_fifo_pulled_data[28] +.sym 19199 w_tx_fifo_pulled_data[30] +.sym 19207 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 19218 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 19219 tx_fifo.wr_addr[2] +.sym 19220 w_tx_fifo_data[23] +.sym 19221 tx_fifo.wr_addr[9] +.sym 19222 tx_fifo.wr_addr[3] +.sym 19223 w_tx_fifo_data[6] +.sym 19224 o_miso_$_TBUF__Y_E +.sym 19225 w_tx_fifo_data[19] +.sym 19226 tx_fifo.wr_addr[5] +.sym 19227 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19228 tx_fifo.wr_addr[7] +.sym 19229 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 19238 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 19240 tx_fifo.rd_addr_gray_wr[1] +.sym 19241 tx_fifo.rd_addr_gray_wr[6] +.sym 19247 tx_fifo.rd_addr_gray_wr[4] +.sym 19248 tx_fifo.rd_addr_gray_wr[5] +.sym 19250 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 19252 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 19255 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19263 tx_fifo.rd_addr_gray[4] +.sym 19264 tx_fifo.rd_addr_gray_wr[0] +.sym 19265 tx_fifo.rd_addr_gray[6] +.sym 19268 tx_fifo.rd_addr_gray_wr[5] +.sym 19276 tx_fifo.rd_addr_gray_wr[1] +.sym 19280 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19281 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 19282 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 19283 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 19287 tx_fifo.rd_addr_gray_wr[6] +.sym 19295 tx_fifo.rd_addr_gray[4] +.sym 19301 tx_fifo.rd_addr_gray_wr[0] +.sym 19305 tx_fifo.rd_addr_gray[6] +.sym 19310 tx_fifo.rd_addr_gray_wr[4] +.sym 19315 r_counter_$glb_clk +.sym 19318 w_tx_fifo_pulled_data[29] +.sym 19322 w_tx_fifo_pulled_data[31] +.sym 19329 lvds_tx_inst.r_fifo_data[11] +.sym 19336 tx_fifo.wr_addr[8] +.sym 19339 i_smi_a2$SB_IO_IN +.sym 19340 $PACKER_VCC_NET +.sym 19341 w_tx_fifo_data[12] +.sym 19342 tx_fifo.wr_addr[6] +.sym 19343 tx_fifo.wr_addr[6] +.sym 19344 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 19345 tx_fifo.wr_addr[4] +.sym 19346 tx_fifo.rd_addr_gray_wr_r[7] +.sym 19348 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 19350 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19351 w_tx_fifo_pulled_data[13] +.sym 19352 tx_fifo.wr_addr[4] +.sym 19359 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 19361 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 19363 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 19365 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 19369 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 19370 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 19371 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 19372 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 19375 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 19379 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19383 lvds_tx_inst.r_fifo_data[15] +.sym 19385 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 19386 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 19387 lvds_tx_inst.r_fifo_data[11] +.sym 19391 lvds_tx_inst.r_fifo_data[15] +.sym 19392 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 19393 lvds_tx_inst.r_fifo_data[11] +.sym 19394 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19400 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 19406 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 19409 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 19412 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 19416 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 19418 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 19421 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 19423 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 19430 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 19433 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 19437 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 19438 r_counter_$glb_clk .sym 19439 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 19441 rx_fifo.mem_i.0.2_RDATA_3[0] -.sym 19445 rx_fifo.mem_i.0.2_RDATA_2[1] -.sym 19453 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 19454 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 19455 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 19456 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 19457 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 19458 rx_fifo.rd_addr[2] -.sym 19463 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 19469 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 19470 rx_fifo.mem_i.0.2_RDATA_1[0] -.sym 19471 $PACKER_VCC_NET -.sym 19472 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 19473 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 19474 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 19484 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19485 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19487 i_sck$SB_IO_IN -.sym 19491 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19492 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 19503 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 19506 spi_if_ins.spi.SCKr[0] -.sym 19507 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 19509 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 19521 i_sck$SB_IO_IN -.sym 19526 spi_if_ins.spi.SCKr[0] -.sym 19532 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19534 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 19535 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 19538 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 19539 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 19540 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19541 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19544 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 19545 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 19547 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 19553 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 19557 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19441 w_tx_fifo_pulled_data[4] +.sym 19445 w_tx_fifo_pulled_data[6] +.sym 19452 tx_fifo.rd_addr[0] +.sym 19454 tx_fifo.rd_addr[5] +.sym 19456 w_tx_fifo_data[29] +.sym 19458 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 19459 w_rx_24_fifo_data[18] +.sym 19461 w_rx_24_fifo_data[5] +.sym 19462 tx_fifo.rd_addr[1] +.sym 19463 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 19464 $PACKER_VCC_NET +.sym 19465 i_smi_soe_se$SB_IO_IN +.sym 19466 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19467 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 19469 tx_fifo.wr_addr[3] +.sym 19470 tx_fifo.wr_addr[4] +.sym 19473 w_tx_fifo_data[22] +.sym 19474 w_tx_fifo_push +.sym 19475 tx_fifo.wr_addr[9] +.sym 19481 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[2] +.sym 19482 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19483 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O +.sym 19484 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] +.sym 19485 lvds_tx_inst.r_fifo_data[20] +.sym 19487 i_ss$SB_IO_IN +.sym 19488 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 19489 lvds_tx_inst.r_fifo_data[18] +.sym 19490 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 19491 lvds_tx_inst.r_fifo_data[16] +.sym 19493 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[0] +.sym 19494 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19496 lvds_tx_inst.r_fifo_data[22] +.sym 19497 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[1] +.sym 19498 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] +.sym 19499 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19500 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 19501 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] +.sym 19507 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19508 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 19514 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 19520 lvds_tx_inst.r_fifo_data[16] +.sym 19521 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19522 lvds_tx_inst.r_fifo_data[18] +.sym 19523 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19526 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[2] +.sym 19527 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 19528 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[1] +.sym 19529 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[0] +.sym 19533 i_ss$SB_IO_IN +.sym 19538 lvds_tx_inst.r_fifo_data[20] +.sym 19539 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19540 lvds_tx_inst.r_fifo_data[22] +.sym 19541 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19544 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] +.sym 19545 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] +.sym 19546 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] +.sym 19547 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 19558 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 19560 smi_ctrl_ins.o_tx_fifo_push_SB_LUT4_I2_O .sym 19561 r_counter_$glb_clk -.sym 19564 rx_fifo.mem_i.0.2_RDATA_1[0] -.sym 19568 rx_fifo.mem_i.0.2_RDATA[0] -.sym 19576 rx_fifo.wr_addr[5] -.sym 19577 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 19585 w_cs[1] -.sym 19586 channel -.sym 19590 rx_fifo.mem_i.0.3_RDATA_1[0] -.sym 19593 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 19594 rx_fifo.wr_addr[0] -.sym 19595 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 19597 $PACKER_VCC_NET -.sym 19604 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] -.sym 19605 $PACKER_VCC_NET -.sym 19608 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19613 spi_if_ins.spi.r_tx_byte[5] -.sym 19614 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 19615 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19616 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19617 spi_if_ins.spi.r_tx_byte[2] -.sym 19621 spi_if_ins.spi.r_tx_byte[1] -.sym 19622 spi_if_ins.spi.r_tx_byte[6] -.sym 19625 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 19629 $PACKER_VCC_NET -.sym 19630 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19631 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 19633 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 19636 $nextpnr_ICESTORM_LC_6$O -.sym 19638 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19642 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 19644 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19645 $PACKER_VCC_NET -.sym 19649 $PACKER_VCC_NET -.sym 19650 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19652 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 19655 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19657 $PACKER_VCC_NET -.sym 19658 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19664 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19667 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19668 spi_if_ins.spi.r_tx_byte[6] -.sym 19669 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19670 spi_if_ins.spi.r_tx_byte[2] -.sym 19673 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19674 spi_if_ins.spi.r_tx_byte[1] -.sym 19675 spi_if_ins.spi.r_tx_byte[5] -.sym 19676 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19679 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 19680 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] -.sym 19681 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 19682 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 19683 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 19684 r_counter_$glb_clk -.sym 19685 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 19687 rx_fifo.mem_i.0.3_RDATA_3[1] -.sym 19691 rx_fifo.mem_i.0.3_RDATA_2[1] -.sym 19698 io_pmod[1]$SB_IO_IN +.sym 19562 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 19564 w_tx_fifo_pulled_data[5] +.sym 19568 w_tx_fifo_pulled_data[7] +.sym 19575 i_ss$SB_IO_IN +.sym 19576 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19577 lvds_tx_inst.r_fifo_data[16] +.sym 19579 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 19580 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] +.sym 19582 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19583 w_tx_fifo_push +.sym 19587 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 19588 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 19590 tx_fifo.rd_addr[2] +.sym 19591 tx_fifo.wr_addr[7] +.sym 19592 w_tx_fifo_data[16] +.sym 19593 w_tx_fifo_data[18] +.sym 19594 w_tx_fifo_data[13] +.sym 19595 w_tx_fifo_data[20] +.sym 19597 tx_fifo.wr_addr[6] +.sym 19598 w_tx_fifo_data[17] +.sym 19604 i_sck$SB_IO_IN +.sym 19606 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 19608 i_ss$SB_IO_IN +.sym 19609 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 19610 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19612 lvds_tx_inst.r_fifo_data[19] +.sym 19614 lvds_tx_inst.r_fifo_data[17] +.sym 19616 lvds_tx_inst.r_fifo_data[23] +.sym 19617 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 19618 lvds_tx_inst.r_fifo_data[21] +.sym 19626 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19627 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 19629 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19630 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19632 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19636 $nextpnr_ICESTORM_LC_10$O +.sym 19639 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19642 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 19645 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19650 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19652 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 19655 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 19656 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 19657 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 19658 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 19662 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19663 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19667 lvds_tx_inst.r_fifo_data[23] +.sym 19668 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19669 lvds_tx_inst.r_fifo_data[21] +.sym 19670 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19675 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19679 lvds_tx_inst.r_fifo_data[19] +.sym 19680 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 19681 lvds_tx_inst.r_fifo_data[17] +.sym 19682 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 19684 i_sck$SB_IO_IN +.sym 19685 i_ss$SB_IO_IN +.sym 19687 w_tx_fifo_pulled_data[20] +.sym 19691 w_tx_fifo_pulled_data[22] +.sym 19698 lvds_tx_inst.r_fifo_data[19] .sym 19699 i_glob_clock$SB_IO_IN -.sym 19700 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 19701 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 19702 $PACKER_VCC_NET -.sym 19704 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 19706 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 19710 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 19711 rx_fifo.wr_addr[3] -.sym 19714 rx_fifo.wr_addr[4] -.sym 19716 rx_fifo.mem_i.0.2_WDATA -.sym 19717 rx_fifo.wr_addr[1] -.sym 19718 rx_fifo.wr_addr[1] -.sym 19719 io_pmod[3]$SB_IO_IN -.sym 19720 rx_fifo.wr_addr[7] -.sym 19721 rx_fifo.mem_q.0.3_RDATA_2[0] -.sym 19730 spi_if_ins.r_tx_byte[0] -.sym 19731 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 19732 spi_if_ins.r_tx_byte[4] -.sym 19733 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 19734 spi_if_ins.r_tx_byte[7] -.sym 19735 spi_if_ins.r_tx_byte[5] -.sym 19736 spi_if_ins.r_tx_byte[2] -.sym 19737 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19738 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 19739 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19742 spi_if_ins.r_tx_byte[3] -.sym 19745 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 19749 spi_if_ins.spi.r_tx_byte[7] -.sym 19755 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 19758 spi_if_ins.spi.r_tx_byte[3] -.sym 19760 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 19761 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19762 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 19763 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 19768 spi_if_ins.r_tx_byte[5] -.sym 19772 spi_if_ins.spi.r_tx_byte[3] -.sym 19773 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 19774 spi_if_ins.spi.r_tx_byte[7] -.sym 19775 spi_if_ins.spi.r_tx_bit_count[2] -.sym 19778 spi_if_ins.r_tx_byte[0] -.sym 19785 spi_if_ins.r_tx_byte[4] -.sym 19791 spi_if_ins.r_tx_byte[2] -.sym 19797 spi_if_ins.r_tx_byte[7] -.sym 19803 spi_if_ins.r_tx_byte[3] -.sym 19806 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 19807 r_counter_$glb_clk -.sym 19808 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 19810 rx_fifo.mem_i.0.3_RDATA_1[0] -.sym 19814 rx_fifo.mem_i.0.3_RDATA[0] -.sym 19820 i_config[1]$SB_IO_IN -.sym 19821 r_tx_data[5] -.sym 19822 $PACKER_VCC_NET -.sym 19824 spi_if_ins.r_tx_byte[6] -.sym 19825 rx_fifo.mem_i.0.3_WDATA_3 -.sym 19827 rx_fifo.mem_i.0.3_WDATA_2 -.sym 19828 spi_if_ins.r_tx_byte[4] -.sym 19829 w_tx_data_io[4] -.sym 19830 spi_if_ins.r_tx_byte[7] -.sym 19832 rx_fifo.wr_addr[5] -.sym 19833 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 19835 w_rx_24_fifo_data[13] -.sym 19836 rx_fifo.rd_addr[2] -.sym 19837 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 19839 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 19840 io_pmod[0]$SB_IO_IN -.sym 19842 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 19843 rx_fifo.wr_addr[9] -.sym 19844 rx_fifo.mem_q.0.3_RDATA[0] -.sym 19852 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 19859 r_tx_data[2] -.sym 19860 r_tx_data[3] -.sym 19871 r_tx_data[5] -.sym 19872 r_tx_data[0] -.sym 19886 r_tx_data[5] -.sym 19890 r_tx_data[2] -.sym 19904 r_tx_data[0] -.sym 19927 r_tx_data[3] -.sym 19929 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 19930 r_counter_$glb_clk -.sym 19933 rx_fifo.mem_q.0.3_RDATA_3[1] -.sym 19937 rx_fifo.mem_q.0.3_RDATA_2[0] -.sym 19947 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 19952 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 19953 rx_fifo.rd_addr[2] -.sym 19957 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 19958 rx_fifo.mem_i.0.3_WDATA_1 -.sym 19959 w_tx_data_io[5] -.sym 19961 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 19962 rx_fifo.wr_addr[6] -.sym 19963 rx_fifo.mem_q.0.3_WDATA_3 -.sym 19964 $PACKER_VCC_NET -.sym 19965 rx_fifo.mem_q.0.3_WDATA_2 -.sym 19967 w_tx_data_io[7] -.sym 19973 i_glob_clock$SB_IO_IN -.sym 19974 w_rx_09_fifo_data[13] -.sym 19975 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 19983 w_tx_data_io[3] -.sym 19984 channel -.sym 19985 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 19986 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 19987 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 19993 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 19995 w_rx_24_fifo_data[13] -.sym 19998 w_tx_data_io[2] -.sym 20013 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 20014 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 20015 w_tx_data_io[2] -.sym 20020 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 20021 w_tx_data_io[3] -.sym 20024 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 20025 channel -.sym 20026 w_rx_09_fifo_data[13] -.sym 20027 w_rx_24_fifo_data[13] -.sym 20052 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 20053 i_glob_clock$SB_IO_IN -.sym 20054 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 20056 rx_fifo.mem_q.0.3_RDATA_1[0] -.sym 20060 rx_fifo.mem_q.0.3_RDATA[0] -.sym 20067 i_glob_clock$SB_IO_IN -.sym 20072 rx_fifo.wr_addr[5] -.sym 20078 io_pmod[1]$SB_IO_IN +.sym 19700 lvds_tx_inst.r_fifo_data[17] +.sym 19702 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 19708 tx_fifo.rd_addr[0] +.sym 19710 tx_fifo.wr_addr[3] +.sym 19711 tx_fifo.wr_addr[2] +.sym 19712 w_tx_fifo_data[23] +.sym 19714 w_tx_fifo_pulled_data[18] +.sym 19715 w_tx_fifo_data[2] +.sym 19716 tx_fifo.wr_addr[7] +.sym 19717 w_tx_fifo_data[19] +.sym 19718 tx_fifo.wr_addr[5] +.sym 19719 tx_fifo.wr_addr[3] +.sym 19720 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19721 tx_fifo.wr_addr[9] +.sym 19729 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19731 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19732 i_ss$SB_IO_IN +.sym 19736 i_sck$SB_IO_IN +.sym 19738 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 19739 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19740 i_ss$SB_IO_IN +.sym 19741 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19745 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 19748 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 19772 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19773 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19774 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19775 i_ss$SB_IO_IN +.sym 19780 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19784 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19785 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19786 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19797 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 19803 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 19806 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 19807 i_sck$SB_IO_IN +.sym 19808 i_ss$SB_IO_IN +.sym 19810 w_tx_fifo_pulled_data[21] +.sym 19814 w_tx_fifo_pulled_data[23] +.sym 19817 tx_fifo.wr_addr[3] +.sym 19821 i_ss$SB_IO_IN +.sym 19822 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 19823 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 19826 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 19828 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[2] +.sym 19829 lvds_rx_24_inst.r_phase_count[1] +.sym 19830 tx_fifo.wr_addr[8] +.sym 19833 tx_fifo.rd_addr[2] +.sym 19834 tx_fifo.rd_addr[1] +.sym 19835 tx_fifo.wr_addr[6] +.sym 19836 w_tx_fifo_pulled_data[23] +.sym 19837 tx_fifo.rd_addr[5] +.sym 19838 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 19840 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 19841 w_tx_fifo_data[12] +.sym 19842 tx_fifo.wr_addr[4] +.sym 19843 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 19844 w_tx_fifo_pulled_data[3] +.sym 19850 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19851 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 19855 i_ss$SB_IO_IN +.sym 19856 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 19858 i_mosi$SB_IO_IN +.sym 19859 i_sck$SB_IO_IN +.sym 19860 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 19861 o_miso_$_TBUF__Y_E +.sym 19862 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19869 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 19878 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 19884 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 19889 i_mosi$SB_IO_IN +.sym 19896 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 19902 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 19908 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 19913 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 19921 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19925 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19927 i_ss$SB_IO_IN +.sym 19929 o_miso_$_TBUF__Y_E +.sym 19930 i_sck$SB_IO_IN +.sym 19933 w_tx_fifo_pulled_data[0] +.sym 19937 w_tx_fifo_pulled_data[2] +.sym 19944 i_mosi$SB_IO_IN +.sym 19945 tx_fifo.rd_addr[5] +.sym 19951 tx_fifo.rd_addr[0] +.sym 19952 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 19954 tx_fifo.rd_addr[1] +.sym 19956 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 19957 $PACKER_VCC_NET +.sym 19958 i_smi_soe_se$SB_IO_IN +.sym 19959 w_tx_fifo_push +.sym 19962 tx_fifo.wr_addr[3] +.sym 19963 tx_fifo.wr_addr[9] +.sym 19973 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19974 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 19975 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 19976 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 19977 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 19982 i_sck$SB_IO_IN +.sym 19984 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19985 i_mosi$SB_IO_IN +.sym 19986 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 19987 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 20009 i_mosi$SB_IO_IN +.sym 20015 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 20021 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 20024 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 20032 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 20036 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 20042 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 20049 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 20052 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 20053 i_sck$SB_IO_IN +.sym 20056 w_tx_fifo_pulled_data[1] +.sym 20060 w_tx_fifo_pulled_data[3] +.sym 20067 w_rx_data[5] +.sym 20069 w_rx_data[1] +.sym 20073 w_rx_data[3] +.sym 20076 w_tx_fifo_push +.sym 20077 w_rx_data[6] +.sym 20079 w_tx_fifo_data[17] +.sym 20080 w_tx_fifo_data[16] +.sym 20082 tx_fifo.rd_addr[2] .sym 20084 o_led1$SB_IO_OUT -.sym 20090 rx_fifo.mem_q.0.3_RDATA_1[0] -.sym 20099 i_button_SB_LUT4_I0_O[1] -.sym 20100 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 20106 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[1] -.sym 20107 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 20108 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 20123 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 20125 i_button_SB_LUT4_I0_O[0] -.sym 20127 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[0] -.sym 20144 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 20149 i_button_SB_LUT4_I0_O[1] -.sym 20150 i_button_SB_LUT4_I0_O[0] -.sym 20153 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 20172 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[0] -.sym 20173 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[1] -.sym 20175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 20176 r_counter_$glb_clk -.sym 20177 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 20191 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 20192 $io_pmod[0]$iobuf_i -.sym 20194 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 20195 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 20196 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 20197 rx_fifo.mem_q.0.3_WDATA -.sym 20208 i_config[0]$SB_IO_IN -.sym 20221 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 20223 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 20231 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[0] -.sym 20242 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[1] -.sym 20289 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[1] -.sym 20291 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[0] -.sym 20298 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 20087 w_tx_fifo_data[13] +.sym 20088 tx_fifo.wr_addr[7] +.sym 20089 tx_fifo.wr_addr[6] +.sym 20090 w_tx_fifo_data[18] +.sym 20105 i_rst_b$SB_IO_IN +.sym 20118 i_smi_soe_se$SB_IO_IN +.sym 20141 i_rst_b$SB_IO_IN +.sym 20143 i_smi_soe_se$SB_IO_IN +.sym 20179 w_tx_fifo_pulled_data[16] +.sym 20183 w_tx_fifo_pulled_data[18] +.sym 20190 w_ioc[0] +.sym 20192 spi_if_ins.w_rx_data[3] +.sym 20193 w_tx_fifo_data[1] +.sym 20194 tx_fifo.rd_addr[0] +.sym 20196 spi_if_ins.w_rx_data[4] +.sym 20200 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 20202 tx_fifo.wr_addr[9] +.sym 20203 tx_fifo.wr_addr[2] +.sym 20204 w_rx_data[7] +.sym 20205 w_tx_fifo_pulled_data[18] +.sym 20206 tx_fifo.wr_addr[5] +.sym 20207 tx_fifo.wr_addr[3] +.sym 20208 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 20209 w_tx_fifo_data[19] +.sym 20210 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 20212 w_rx_data[0] +.sym 20213 tx_fifo.wr_addr[7] +.sym 20221 io_ctrl_ins.led1_state_SB_DFFER_Q_E +.sym 20225 i_button_SB_LUT4_I0_I1[0] +.sym 20227 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20228 w_rx_data[1] +.sym 20229 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 20238 w_rx_data[0] +.sym 20242 i_button_SB_LUT4_I0_I1[1] +.sym 20246 w_ioc[0] +.sym 20252 w_rx_data[1] +.sym 20265 i_button_SB_LUT4_I0_I1[1] +.sym 20266 i_button_SB_LUT4_I0_I1[0] +.sym 20277 w_rx_data[0] +.sym 20294 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20296 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 20297 w_ioc[0] +.sym 20298 io_ctrl_ins.led1_state_SB_DFFER_Q_E .sym 20299 r_counter_$glb_clk -.sym 20300 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 20577 o_led1$SB_IO_OUT +.sym 20300 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 20302 w_tx_fifo_pulled_data[17] +.sym 20306 w_tx_fifo_pulled_data[19] +.sym 20314 tx_fifo.wr_addr[4] +.sym 20315 i_button_SB_LUT4_I0_I1[0] +.sym 20319 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 20320 tx_fifo.wr_addr[8] +.sym 20323 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20327 tx_fifo.rd_addr[1] +.sym 20328 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 20329 tx_fifo.rd_addr[5] +.sym 20330 tx_fifo.rd_addr[2] +.sym 20331 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 20333 w_tx_fifo_data[12] +.sym 20334 tx_fifo.wr_addr[4] +.sym 20335 tx_fifo.wr_addr[6] +.sym 20343 w_rx_data[1] +.sym 20345 w_rx_data[4] +.sym 20346 w_ioc[0] +.sym 20349 w_rx_data[3] +.sym 20350 o_shdn_rx_lna$SB_IO_OUT +.sym 20351 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20354 o_tr_vc1_b$SB_IO_OUT +.sym 20357 w_rx_data[0] +.sym 20361 io_ctrl_ins.o_pmod[1] +.sym 20363 io_ctrl_ins.o_pmod[4] +.sym 20369 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 20376 w_rx_data[3] +.sym 20384 w_rx_data[0] +.sym 20393 w_rx_data[1] +.sym 20399 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20400 o_shdn_rx_lna$SB_IO_OUT +.sym 20401 w_ioc[0] +.sym 20402 io_ctrl_ins.o_pmod[1] +.sym 20405 w_rx_data[4] +.sym 20417 io_ctrl_ins.o_pmod[4] +.sym 20418 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20419 o_tr_vc1_b$SB_IO_OUT +.sym 20420 w_ioc[0] +.sym 20421 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 20422 r_counter_$glb_clk +.sym 20425 w_tx_fifo_pulled_data[12] +.sym 20429 w_tx_fifo_pulled_data[14] +.sym 20436 io_ctrl_ins.o_pmod[3] +.sym 20439 tx_fifo.rd_addr[1] +.sym 20440 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 20441 tx_fifo.rd_addr[5] +.sym 20445 tx_fifo.rd_addr[0] +.sym 20449 $PACKER_VCC_NET +.sym 20452 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 20453 i_config[0]$SB_IO_IN +.sym 20456 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 20465 w_rx_data[5] +.sym 20466 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 20467 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 20468 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 20469 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20470 w_ioc[0] +.sym 20471 o_rx_h_tx_l_b$SB_IO_OUT +.sym 20472 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20474 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 20475 w_rx_data[6] +.sym 20476 w_rx_data[7] +.sym 20477 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20479 io_ctrl_ins.debug_mode[1] +.sym 20483 io_ctrl_ins.o_pmod[6] +.sym 20490 i_rst_b$SB_IO_IN +.sym 20496 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 20498 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 20499 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20501 w_ioc[0] +.sym 20504 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20505 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20506 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 20513 w_rx_data[6] +.sym 20517 w_rx_data[5] +.sym 20522 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 20524 i_rst_b$SB_IO_IN +.sym 20525 io_ctrl_ins.debug_mode[1] +.sym 20528 w_ioc[0] +.sym 20529 io_ctrl_ins.o_pmod[6] +.sym 20530 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 20531 o_rx_h_tx_l_b$SB_IO_OUT +.sym 20534 w_rx_data[7] +.sym 20541 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 20542 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 20544 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 20545 r_counter_$glb_clk +.sym 20548 w_tx_fifo_pulled_data[13] +.sym 20552 w_tx_fifo_pulled_data[15] +.sym 20559 io_ctrl_ins.pmod_state_SB_DFFE_Q_E +.sym 20564 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 20567 w_tx_fifo_push +.sym 20572 o_led1$SB_IO_OUT +.sym 20579 w_tx_fifo_data[13] +.sym 20595 i_button_SB_LUT4_I0_I1[0] +.sym 20599 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 20601 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[2] +.sym 20602 w_rx_data[7] +.sym 20609 w_rx_data[5] +.sym 20612 w_rx_data[6] +.sym 20616 i_config[3]$SB_IO_IN +.sym 20639 i_button_SB_LUT4_I0_I1[0] +.sym 20641 i_config[3]$SB_IO_IN +.sym 20642 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[2] +.sym 20646 w_rx_data[7] +.sym 20653 w_rx_data[6] +.sym 20663 w_rx_data[5] +.sym 20667 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E +.sym 20668 r_counter_$glb_clk .sym 20672 i_config[0]$SB_IO_IN -.sym 20695 i_config[0]$SB_IO_IN +.sym 20680 io_ctrl_ins.pmod_dir_state[6] +.sym 20681 tx_fifo.rd_addr[0] +.sym 20686 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 20688 io_ctrl_ins.pmod_dir_state[7] .sym 20748 w_smi_data_output[5] -.sym 20750 i_smi_a2$rename$0 -.sym 20754 i_smi_a2$rename$0 +.sym 20750 i_smi_a2$SB_IO_IN +.sym 20751 $PACKER_VCC_NET +.sym 20756 i_smi_a2$SB_IO_IN .sym 20762 w_smi_data_output[5] -.sym 20784 rx_fifo.wr_addr[8] -.sym 20798 rx_fifo.wr_addr[2] -.sym 20802 i_smi_a2$rename$0 -.sym 20803 i_ss_SB_LUT4_I3_O +.sym 20767 $PACKER_VCC_NET +.sym 20775 smi_ctrl_ins.w_fifo_push_trigger +.sym 20786 i_smi_soe_se$SB_IO_IN +.sym 20803 o_miso_$_TBUF__Y_E +.sym 20804 i_ss$SB_IO_IN +.sym 20810 w_tx_fifo_data[8] +.sym 20811 tx_fifo.wr_addr[7] +.sym 20812 w_tx_fifo_push +.sym 20814 w_tx_fifo_data[10] +.sym 20816 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 20817 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 20818 tx_fifo.wr_addr[3] +.sym 20819 tx_fifo.wr_addr[6] +.sym 20821 tx_fifo.wr_addr[4] +.sym 20822 tx_fifo.wr_addr[5] +.sym 20823 $PACKER_VCC_NET +.sym 20825 tx_fifo.wr_addr[8] +.sym 20832 tx_fifo.wr_addr[2] +.sym 20836 tx_fifo.wr_addr[9] .sym 20844 i_mosi$SB_IO_IN -.sym 20913 i_mosi$SB_IO_IN -.sym 20921 i_mosi$SB_IO_IN -.sym 21088 spi_if_ins.state_if[1] -.sym 21089 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 21091 spi_if_ins.state_if[0] -.sym 21092 spi_if_ins.state_if_SB_DFFESR_Q_D[1] -.sym 21093 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 21141 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21142 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 21146 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21147 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 21188 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[2] -.sym 21190 spi_if_ins.state_if_SB_DFFESR_Q_E[1] -.sym 21191 smi_ctrl_ins.w_fifo_pull_trigger -.sym 21192 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 21193 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 21194 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 21195 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 21228 rx_fifo.wr_addr[2] -.sym 21230 io_pmod[4]$SB_IO_IN -.sym 21239 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 21248 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 21249 io_pmod[1]$SB_IO_IN -.sym 21258 rx_fifo.wr_addr[6] -.sym 21259 rx_fifo.wr_addr[5] -.sym 21260 rx_fifo.mem_i.0.1_WDATA_3 -.sym 21261 rx_fifo.wr_addr[0] -.sym 21262 rx_fifo.wr_addr[1] -.sym 21267 rx_fifo.wr_addr[2] -.sym 21269 rx_fifo.mem_i.0.1_WDATA_2 -.sym 21271 $PACKER_VCC_NET -.sym 21275 rx_fifo.wr_addr[3] -.sym 21277 rx_fifo.wr_addr[9] -.sym 21280 rx_fifo.wr_addr[8] -.sym 21283 rx_fifo.wr_addr[4] -.sym 21285 io_pmod[0]$SB_IO_IN -.sym 21286 rx_fifo.wr_addr[7] -.sym 21290 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 21291 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 21294 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 21295 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 21297 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 21306 rx_fifo.wr_addr[2] -.sym 21307 rx_fifo.wr_addr[3] -.sym 21309 rx_fifo.wr_addr[4] -.sym 21310 rx_fifo.wr_addr[5] -.sym 21311 rx_fifo.wr_addr[6] -.sym 21312 rx_fifo.wr_addr[7] -.sym 21313 rx_fifo.wr_addr[8] -.sym 21314 rx_fifo.wr_addr[9] -.sym 21315 rx_fifo.wr_addr[1] -.sym 21316 rx_fifo.wr_addr[0] -.sym 21317 lvds_clock_$glb_clk -.sym 21318 io_pmod[0]$SB_IO_IN -.sym 21320 rx_fifo.mem_i.0.1_WDATA_3 -.sym 21324 rx_fifo.mem_i.0.1_WDATA_2 +.sym 20846 smi_ctrl_ins.tx_reg_state[0] +.sym 20848 smi_ctrl_ins.tx_reg_state[3] +.sym 20849 smi_ctrl_ins.tx_reg_state[2] +.sym 20853 smi_ctrl_ins.tx_reg_state[1] +.sym 20862 tx_fifo.wr_addr[2] +.sym 20863 tx_fifo.wr_addr[3] +.sym 20865 tx_fifo.wr_addr[4] +.sym 20866 tx_fifo.wr_addr[5] +.sym 20867 tx_fifo.wr_addr[6] +.sym 20868 tx_fifo.wr_addr[7] +.sym 20869 tx_fifo.wr_addr[8] +.sym 20870 tx_fifo.wr_addr[9] +.sym 20871 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 20872 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 20873 r_counter_$glb_clk +.sym 20874 w_tx_fifo_push +.sym 20876 w_tx_fifo_data[8] +.sym 20880 w_tx_fifo_data[10] +.sym 20883 $PACKER_VCC_NET +.sym 20888 w_tx_fifo_data[8] +.sym 20897 w_smi_data_input[7] +.sym 20927 i_rst_b$SB_IO_IN +.sym 20929 smi_ctrl_ins.tx_reg_state[2] +.sym 20931 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 20932 w_tx_fifo_pulled_data[25] +.sym 20933 tx_fifo.rd_addr[6] +.sym 20940 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 20954 tx_fifo.rd_addr[6] +.sym 20955 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 20956 tx_fifo.rd_addr[1] +.sym 20957 tx_fifo.rd_addr[5] +.sym 20960 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 20964 tx_fifo.rd_addr[0] +.sym 20967 tx_fifo.rd_addr[2] +.sym 20968 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 20970 w_tx_fifo_pull +.sym 20972 $PACKER_VCC_NET +.sym 20977 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 20980 tx_fifo.rd_addr[7] +.sym 20981 w_tx_fifo_data[9] +.sym 20983 w_tx_fifo_data[11] +.sym 20986 w_tx_fifo_pull +.sym 21000 tx_fifo.rd_addr[2] +.sym 21001 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21003 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21004 tx_fifo.rd_addr[5] +.sym 21005 tx_fifo.rd_addr[6] +.sym 21006 tx_fifo.rd_addr[7] +.sym 21007 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21008 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21009 tx_fifo.rd_addr[1] +.sym 21010 tx_fifo.rd_addr[0] +.sym 21011 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 21012 w_tx_fifo_pull +.sym 21013 $PACKER_VCC_NET +.sym 21017 w_tx_fifo_data[11] +.sym 21021 w_tx_fifo_data[9] +.sym 21025 w_tx_fifo_data[14] +.sym 21031 w_smi_data_input[7] +.sym 21032 tx_fifo.rd_addr[0] +.sym 21039 w_rx_24_fifo_data[7] +.sym 21042 tx_fifo.wr_addr[5] +.sym 21043 $PACKER_VCC_NET +.sym 21045 w_tx_fifo_pulled_data[11] +.sym 21046 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21048 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21049 w_tx_fifo_push +.sym 21054 w_tx_fifo_data[24] +.sym 21055 tx_fifo.wr_addr[5] +.sym 21057 tx_fifo.wr_addr[7] +.sym 21058 $PACKER_VCC_NET +.sym 21060 w_tx_fifo_data[26] +.sym 21061 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21064 tx_fifo.wr_addr[9] +.sym 21065 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21067 tx_fifo.wr_addr[6] +.sym 21069 tx_fifo.wr_addr[4] +.sym 21070 tx_fifo.wr_addr[2] +.sym 21071 tx_fifo.wr_addr[3] +.sym 21072 w_tx_fifo_push +.sym 21074 tx_fifo.wr_addr[8] +.sym 21087 w_rx_24_fifo_data[15] +.sym 21091 w_rx_24_fifo_data[9] +.sym 21093 w_rx_24_fifo_data[11] +.sym 21102 tx_fifo.wr_addr[2] +.sym 21103 tx_fifo.wr_addr[3] +.sym 21105 tx_fifo.wr_addr[4] +.sym 21106 tx_fifo.wr_addr[5] +.sym 21107 tx_fifo.wr_addr[6] +.sym 21108 tx_fifo.wr_addr[7] +.sym 21109 tx_fifo.wr_addr[8] +.sym 21110 tx_fifo.wr_addr[9] +.sym 21111 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21112 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21113 r_counter_$glb_clk +.sym 21114 w_tx_fifo_push +.sym 21116 w_tx_fifo_data[24] +.sym 21120 w_tx_fifo_data[26] +.sym 21123 $PACKER_VCC_NET +.sym 21131 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21132 tx_fifo.wr_addr[9] +.sym 21137 o_miso_$_TBUF__Y_E +.sym 21138 w_tx_fifo_data[24] +.sym 21140 tx_fifo.rd_addr[5] +.sym 21145 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 21148 lvds_tx_inst.r_fifo_data[15] +.sym 21149 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21151 w_rx_24_fifo_data[15] +.sym 21156 tx_fifo.rd_addr[2] +.sym 21157 tx_fifo.rd_addr[5] +.sym 21158 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21160 $PACKER_VCC_NET +.sym 21162 w_tx_fifo_data[25] +.sym 21163 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21164 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21165 tx_fifo.rd_addr[1] +.sym 21172 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21173 tx_fifo.rd_addr[0] +.sym 21174 w_tx_fifo_pull +.sym 21181 w_tx_fifo_data[27] +.sym 21185 tx_fifo.rd_addr[6] +.sym 21186 tx_fifo.rd_addr[7] +.sym 21188 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[0] +.sym 21189 lvds_tx_inst.r_fifo_data[29] +.sym 21190 lvds_tx_inst.r_fifo_data[15] +.sym 21191 lvds_tx_inst.r_fifo_data[28] +.sym 21192 lvds_tx_inst.r_fifo_data[11] +.sym 21193 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 21194 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 21195 lvds_tx_inst.r_fifo_data[31] +.sym 21204 tx_fifo.rd_addr[2] +.sym 21205 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21207 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21208 tx_fifo.rd_addr[5] +.sym 21209 tx_fifo.rd_addr[6] +.sym 21210 tx_fifo.rd_addr[7] +.sym 21211 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21212 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21213 tx_fifo.rd_addr[1] +.sym 21214 tx_fifo.rd_addr[0] +.sym 21215 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 21216 w_tx_fifo_pull +.sym 21217 $PACKER_VCC_NET +.sym 21221 w_tx_fifo_data[27] +.sym 21225 w_tx_fifo_data[25] +.sym 21228 w_tx_fifo_pulled_data[12] +.sym 21230 tx_fifo.rd_addr[2] +.sym 21231 tx_fifo.rd_addr[1] +.sym 21232 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21234 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 21239 w_rx_24_fifo_data[15] +.sym 21240 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 21242 tx_fifo.wr_addr[8] +.sym 21243 w_tx_fifo_pulled_data[26] +.sym 21246 w_rx_24_fifo_data[13] +.sym 21249 w_tx_fifo_pulled_data[27] +.sym 21251 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 21252 w_tx_fifo_pulled_data[14] +.sym 21253 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 21258 tx_fifo.wr_addr[8] +.sym 21259 tx_fifo.wr_addr[3] +.sym 21262 $PACKER_VCC_NET +.sym 21264 tx_fifo.wr_addr[6] +.sym 21266 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21270 tx_fifo.wr_addr[7] +.sym 21271 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21273 tx_fifo.wr_addr[4] +.sym 21274 tx_fifo.wr_addr[2] +.sym 21275 tx_fifo.wr_addr[5] +.sym 21276 w_tx_fifo_push +.sym 21280 w_tx_fifo_data[28] +.sym 21281 tx_fifo.wr_addr[9] +.sym 21290 tx_fifo.rd_addr_gray_wr[2] +.sym 21291 tx_fifo.rd_addr_gray_wr[3] +.sym 21292 tx_fifo.rd_addr_gray_wr[1] +.sym 21293 tx_fifo.rd_addr_gray_wr[5] +.sym 21294 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] +.sym 21295 tx_fifo.rd_addr_gray_wr_r[2] +.sym 21296 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 21297 tx_fifo.rd_addr_gray_wr[0] +.sym 21306 tx_fifo.wr_addr[2] +.sym 21307 tx_fifo.wr_addr[3] +.sym 21309 tx_fifo.wr_addr[4] +.sym 21310 tx_fifo.wr_addr[5] +.sym 21311 tx_fifo.wr_addr[6] +.sym 21312 tx_fifo.wr_addr[7] +.sym 21313 tx_fifo.wr_addr[8] +.sym 21314 tx_fifo.wr_addr[9] +.sym 21315 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21316 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21317 r_counter_$glb_clk +.sym 21318 w_tx_fifo_push +.sym 21320 w_tx_fifo_data[28] .sym 21327 $PACKER_VCC_NET -.sym 21339 i_rst_b$SB_IO_IN -.sym 21343 rx_fifo.wr_addr[5] -.sym 21344 $PACKER_VCC_NET -.sym 21345 spi_if_ins.w_rx_data[5] -.sym 21346 rx_fifo.wr_addr[6] -.sym 21347 rx_fifo.wr_addr[0] -.sym 21349 rx_fifo.wr_addr[0] -.sym 21351 io_pmod[0]$SB_IO_IN -.sym 21354 rx_fifo.mem_i.0.2_RDATA[0] -.sym 21362 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21364 $PACKER_VCC_NET -.sym 21365 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21367 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 21368 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21369 rx_fifo.rd_addr[2] -.sym 21373 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 21374 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 21375 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21376 rx_fifo.mem_i.0.1_WDATA -.sym 21380 rx_fifo.mem_i.0.1_WDATA_1 -.sym 21383 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 21387 io_pmod[1]$SB_IO_IN -.sym 21389 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 21392 w_cs[1] -.sym 21396 w_cs[2] -.sym 21397 w_cs[3] -.sym 21408 rx_fifo.rd_addr[2] -.sym 21409 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 21411 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21412 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21413 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21414 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 21415 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 21416 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21417 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 21418 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 21419 r_counter_$glb_clk -.sym 21420 io_pmod[1]$SB_IO_IN +.sym 21330 w_tx_fifo_pulled_data[13] +.sym 21335 lvds_tx_inst.r_fifo_data[28] +.sym 21345 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21348 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 21350 w_tx_fifo_pulled_data[15] +.sym 21351 w_tx_fifo_data[4] +.sym 21354 w_tx_fifo_pulled_data[25] +.sym 21355 w_tx_fifo_pull +.sym 21365 tx_fifo.rd_addr[0] +.sym 21366 w_tx_fifo_data[31] +.sym 21367 tx_fifo.rd_addr[5] +.sym 21368 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21369 tx_fifo.rd_addr[2] +.sym 21372 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21373 tx_fifo.rd_addr[1] +.sym 21375 w_tx_fifo_data[29] +.sym 21378 w_tx_fifo_pull +.sym 21380 $PACKER_VCC_NET +.sym 21381 tx_fifo.rd_addr[7] +.sym 21382 tx_fifo.rd_addr[6] +.sym 21385 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21391 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21392 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[1] +.sym 21393 lvds_tx_inst.r_fifo_data[16] +.sym 21394 lvds_tx_inst.r_fifo_data[20] +.sym 21395 lvds_tx_inst.r_fifo_data[27] +.sym 21396 lvds_tx_inst.r_fifo_data[18] +.sym 21397 lvds_tx_inst.r_fifo_data[26] +.sym 21398 lvds_tx_inst.r_fifo_data[5] +.sym 21399 lvds_tx_inst.r_fifo_data[25] +.sym 21408 tx_fifo.rd_addr[2] +.sym 21409 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21411 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21412 tx_fifo.rd_addr[5] +.sym 21413 tx_fifo.rd_addr[6] +.sym 21414 tx_fifo.rd_addr[7] +.sym 21415 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21416 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21417 tx_fifo.rd_addr[1] +.sym 21418 tx_fifo.rd_addr[0] +.sym 21419 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 21420 w_tx_fifo_pull .sym 21421 $PACKER_VCC_NET -.sym 21425 rx_fifo.mem_i.0.1_WDATA -.sym 21429 rx_fifo.mem_i.0.1_WDATA_1 -.sym 21436 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21440 $PACKER_VCC_NET -.sym 21441 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21446 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 21448 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 21450 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 21452 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 21454 i_rst_b$SB_IO_IN -.sym 21455 w_cs[1] -.sym 21457 i_rst_b$SB_IO_IN -.sym 21462 rx_fifo.mem_i.0.2_WDATA_2 -.sym 21463 rx_fifo.wr_addr[3] -.sym 21465 rx_fifo.wr_addr[7] -.sym 21466 rx_fifo.wr_addr[2] -.sym 21471 rx_fifo.wr_addr[4] -.sym 21472 rx_fifo.wr_addr[9] -.sym 21473 rx_fifo.mem_i.0.2_WDATA_3 -.sym 21474 rx_fifo.wr_addr[5] -.sym 21475 rx_fifo.wr_addr[1] -.sym 21480 rx_fifo.wr_addr[8] +.sym 21425 w_tx_fifo_data[31] +.sym 21429 w_tx_fifo_data[29] +.sym 21437 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 21438 w_rx_24_fifo_data[5] +.sym 21439 tx_fifo.rd_addr_gray_wr[0] +.sym 21442 w_tx_fifo_data[31] +.sym 21446 tx_fifo.wr_addr[5] +.sym 21448 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 21449 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21450 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21451 w_tx_fifo_data[5] +.sym 21453 w_tx_fifo_pulled_data[16] +.sym 21455 $PACKER_VCC_NET +.sym 21457 w_tx_fifo_data[7] +.sym 21462 tx_fifo.wr_addr[2] +.sym 21463 tx_fifo.wr_addr[5] +.sym 21465 tx_fifo.wr_addr[7] +.sym 21466 w_tx_fifo_data[6] +.sym 21467 tx_fifo.wr_addr[3] +.sym 21468 tx_fifo.wr_addr[6] +.sym 21471 tx_fifo.wr_addr[8] +.sym 21472 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21473 w_tx_fifo_push +.sym 21475 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21477 tx_fifo.wr_addr[4] .sym 21482 $PACKER_VCC_NET -.sym 21484 rx_fifo.wr_addr[6] -.sym 21485 rx_fifo.wr_addr[0] -.sym 21489 io_pmod[0]$SB_IO_IN -.sym 21494 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 21495 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 21496 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 21497 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 21498 spi_if_ins.o_cs_SB_LUT4_I3_1_O[0] -.sym 21499 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 21500 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 21501 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 21510 rx_fifo.wr_addr[2] -.sym 21511 rx_fifo.wr_addr[3] -.sym 21513 rx_fifo.wr_addr[4] -.sym 21514 rx_fifo.wr_addr[5] -.sym 21515 rx_fifo.wr_addr[6] -.sym 21516 rx_fifo.wr_addr[7] -.sym 21517 rx_fifo.wr_addr[8] -.sym 21518 rx_fifo.wr_addr[9] -.sym 21519 rx_fifo.wr_addr[1] -.sym 21520 rx_fifo.wr_addr[0] -.sym 21521 lvds_clock_$glb_clk -.sym 21522 io_pmod[0]$SB_IO_IN -.sym 21524 rx_fifo.mem_i.0.2_WDATA_3 -.sym 21528 rx_fifo.mem_i.0.2_WDATA_2 +.sym 21485 tx_fifo.wr_addr[9] +.sym 21489 w_tx_fifo_data[4] +.sym 21494 lvds_tx_inst.r_fifo_data[1] +.sym 21495 lvds_tx_inst.r_fifo_data[17] +.sym 21496 lvds_tx_inst.r_fifo_data[23] +.sym 21497 lvds_tx_inst.r_fifo_data[21] +.sym 21498 lvds_tx_inst.r_fifo_data[19] +.sym 21499 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 21500 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[1] +.sym 21501 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[3] +.sym 21510 tx_fifo.wr_addr[2] +.sym 21511 tx_fifo.wr_addr[3] +.sym 21513 tx_fifo.wr_addr[4] +.sym 21514 tx_fifo.wr_addr[5] +.sym 21515 tx_fifo.wr_addr[6] +.sym 21516 tx_fifo.wr_addr[7] +.sym 21517 tx_fifo.wr_addr[8] +.sym 21518 tx_fifo.wr_addr[9] +.sym 21519 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21520 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21521 r_counter_$glb_clk +.sym 21522 w_tx_fifo_push +.sym 21524 w_tx_fifo_data[4] +.sym 21528 w_tx_fifo_data[6] .sym 21531 $PACKER_VCC_NET -.sym 21536 rx_fifo.mem_i.0.2_WDATA_2 -.sym 21537 rx_fifo.wr_addr[4] -.sym 21539 $io_pmod[3]$iobuf_i -.sym 21540 rx_fifo.wr_addr[9] -.sym 21541 rx_fifo.mem_i.0.2_WDATA_3 -.sym 21542 rx_fifo.wr_addr[2] -.sym 21543 rx_fifo.wr_addr[1] -.sym 21546 io_pmod[3]$SB_IO_IN -.sym 21549 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21550 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21552 w_tx_data_smi[1] -.sym 21554 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 21556 rx_fifo.wr_addr[3] -.sym 21558 rx_fifo.mem_i.0.3_RDATA[0] -.sym 21559 w_tx_data_io[1] -.sym 21565 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21566 rx_fifo.rd_addr[2] -.sym 21570 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 21571 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21572 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 21573 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21574 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 21575 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 21577 $PACKER_VCC_NET -.sym 21578 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 21582 rx_fifo.mem_i.0.2_WDATA -.sym 21591 io_pmod[1]$SB_IO_IN -.sym 21593 rx_fifo.mem_i.0.2_WDATA_1 -.sym 21595 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21596 r_tx_data[4] -.sym 21597 r_tx_data[1] -.sym 21598 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 21599 r_tx_data[6] -.sym 21600 r_tx_data[5] -.sym 21602 r_tx_data[7] -.sym 21603 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 21612 rx_fifo.rd_addr[2] -.sym 21613 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 21615 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21616 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21617 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21618 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 21619 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 21620 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21621 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 21622 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 21623 r_counter_$glb_clk -.sym 21624 io_pmod[1]$SB_IO_IN +.sym 21538 w_tx_fifo_pulled_data[6] +.sym 21540 w_tx_fifo_pulled_data[4] +.sym 21543 w_tx_fifo_pulled_data[18] +.sym 21545 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 21548 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 21549 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21550 w_tx_fifo_pulled_data[17] +.sym 21551 w_tx_fifo_pulled_data[19] +.sym 21553 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 21554 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21555 w_tx_fifo_pulled_data[20] +.sym 21557 tx_fifo.rd_addr[7] +.sym 21558 tx_fifo.rd_addr[7] +.sym 21565 tx_fifo.rd_addr[5] +.sym 21566 tx_fifo.rd_addr[1] +.sym 21568 $PACKER_VCC_NET +.sym 21569 tx_fifo.rd_addr[0] +.sym 21571 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21573 tx_fifo.rd_addr[2] +.sym 21575 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21579 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21582 w_tx_fifo_pull +.sym 21583 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21587 tx_fifo.rd_addr[7] +.sym 21589 w_tx_fifo_data[5] +.sym 21593 tx_fifo.rd_addr[6] +.sym 21595 w_tx_fifo_data[7] +.sym 21597 int_miso +.sym 21598 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E +.sym 21600 i_rst_b_SB_LUT4_I3_O +.sym 21602 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 21603 lvds_rx_24_inst.r_phase_count[1] +.sym 21612 tx_fifo.rd_addr[2] +.sym 21613 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21615 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21616 tx_fifo.rd_addr[5] +.sym 21617 tx_fifo.rd_addr[6] +.sym 21618 tx_fifo.rd_addr[7] +.sym 21619 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21620 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21621 tx_fifo.rd_addr[1] +.sym 21622 tx_fifo.rd_addr[0] +.sym 21623 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 21624 w_tx_fifo_pull .sym 21625 $PACKER_VCC_NET -.sym 21629 rx_fifo.mem_i.0.2_WDATA -.sym 21633 rx_fifo.mem_i.0.2_WDATA_1 -.sym 21639 io_pmod[0]$SB_IO_IN -.sym 21646 rx_fifo.mem_i.0.0_RDATA[1] -.sym 21647 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 21649 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 21650 w_cs[0] -.sym 21656 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 21657 io_pmod[1]$SB_IO_IN -.sym 21659 w_cs[0] -.sym 21660 spi_if_ins.r_tx_byte[1] -.sym 21669 rx_fifo.wr_addr[0] -.sym 21670 $PACKER_VCC_NET -.sym 21675 rx_fifo.mem_i.0.3_WDATA_2 -.sym 21677 rx_fifo.wr_addr[8] -.sym 21678 rx_fifo.wr_addr[5] -.sym 21679 rx_fifo.wr_addr[6] -.sym 21681 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21685 rx_fifo.wr_addr[7] -.sym 21688 rx_fifo.wr_addr[2] -.sym 21691 rx_fifo.wr_addr[1] -.sym 21693 io_pmod[0]$SB_IO_IN -.sym 21694 rx_fifo.wr_addr[3] -.sym 21695 rx_fifo.wr_addr[4] -.sym 21696 rx_fifo.wr_addr[9] -.sym 21701 spi_if_ins.r_tx_byte[1] -.sym 21714 rx_fifo.wr_addr[2] -.sym 21715 rx_fifo.wr_addr[3] -.sym 21717 rx_fifo.wr_addr[4] -.sym 21718 rx_fifo.wr_addr[5] -.sym 21719 rx_fifo.wr_addr[6] -.sym 21720 rx_fifo.wr_addr[7] -.sym 21721 rx_fifo.wr_addr[8] -.sym 21722 rx_fifo.wr_addr[9] -.sym 21723 rx_fifo.wr_addr[1] -.sym 21724 rx_fifo.wr_addr[0] -.sym 21725 lvds_clock_$glb_clk -.sym 21726 io_pmod[0]$SB_IO_IN -.sym 21728 rx_fifo.mem_i.0.3_WDATA_3 -.sym 21732 rx_fifo.mem_i.0.3_WDATA_2 +.sym 21629 w_tx_fifo_data[7] +.sym 21633 w_tx_fifo_data[5] +.sym 21639 tx_fifo.rd_addr[5] +.sym 21640 tx_fifo.rd_addr[1] +.sym 21641 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21642 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 21643 w_tx_fifo_pulled_data[3] +.sym 21644 i_glob_clock$SB_IO_IN +.sym 21646 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 21647 w_tx_fifo_pulled_data[23] +.sym 21649 tx_fifo.rd_addr[2] +.sym 21650 tx_fifo.wr_addr[8] +.sym 21652 w_tx_fifo_pulled_data[0] +.sym 21655 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 21657 w_tx_fifo_pulled_data[21] +.sym 21660 w_tx_fifo_pulled_data[14] +.sym 21666 w_tx_fifo_data[22] +.sym 21668 tx_fifo.wr_addr[8] +.sym 21669 tx_fifo.wr_addr[3] +.sym 21670 w_tx_fifo_data[20] +.sym 21672 tx_fifo.wr_addr[6] +.sym 21674 tx_fifo.wr_addr[7] +.sym 21676 tx_fifo.wr_addr[9] +.sym 21677 w_tx_fifo_push +.sym 21678 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21679 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21681 tx_fifo.wr_addr[4] +.sym 21682 tx_fifo.wr_addr[2] +.sym 21683 tx_fifo.wr_addr[5] +.sym 21695 $PACKER_VCC_NET +.sym 21701 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 21703 w_load +.sym 21704 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 21714 tx_fifo.wr_addr[2] +.sym 21715 tx_fifo.wr_addr[3] +.sym 21717 tx_fifo.wr_addr[4] +.sym 21718 tx_fifo.wr_addr[5] +.sym 21719 tx_fifo.wr_addr[6] +.sym 21720 tx_fifo.wr_addr[7] +.sym 21721 tx_fifo.wr_addr[8] +.sym 21722 tx_fifo.wr_addr[9] +.sym 21723 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21724 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21725 r_counter_$glb_clk +.sym 21726 w_tx_fifo_push +.sym 21728 w_tx_fifo_data[20] +.sym 21732 w_tx_fifo_data[22] .sym 21735 $PACKER_VCC_NET -.sym 21743 rx_fifo.wr_addr[8] -.sym 21744 w_tx_data_io[5] -.sym 21745 w_tx_data_io[7] -.sym 21747 rx_fifo.wr_addr[6] -.sym 21748 $PACKER_VCC_NET -.sym 21752 $PACKER_VCC_NET -.sym 21753 rx_fifo.wr_addr[0] -.sym 21757 rx_fifo.wr_addr[4] -.sym 21763 io_pmod[0]$SB_IO_IN -.sym 21768 rx_fifo.mem_i.0.3_WDATA -.sym 21769 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21770 rx_fifo.rd_addr[2] -.sym 21771 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 21772 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 21776 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21779 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21781 $PACKER_VCC_NET -.sym 21782 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 21783 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21790 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21791 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 21793 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 21795 io_pmod[1]$SB_IO_IN -.sym 21803 io_pmod[1]$SB_IO_IN -.sym 21816 rx_fifo.rd_addr[2] -.sym 21817 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 21819 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21820 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21821 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21822 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 21823 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 21824 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21825 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 21826 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 21827 r_counter_$glb_clk -.sym 21828 io_pmod[1]$SB_IO_IN +.sym 21742 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[1] +.sym 21745 $PACKER_VCC_NET +.sym 21749 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 21750 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 21753 tx_fifo.rd_addr[7] +.sym 21754 w_tx_fifo_pulled_data[1] +.sym 21755 w_load +.sym 21758 w_tx_fifo_data[3] +.sym 21759 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21761 tx_fifo.rd_addr[6] +.sym 21762 w_tx_fifo_pulled_data[15] +.sym 21763 w_tx_fifo_pull +.sym 21771 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21774 w_tx_fifo_data[23] +.sym 21776 tx_fifo.rd_addr[0] +.sym 21777 w_tx_fifo_data[21] +.sym 21780 tx_fifo.rd_addr[5] +.sym 21781 tx_fifo.rd_addr[1] +.sym 21782 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21783 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21784 tx_fifo.rd_addr[6] +.sym 21786 w_tx_fifo_pull +.sym 21787 tx_fifo.rd_addr[7] +.sym 21788 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21793 tx_fifo.rd_addr[2] +.sym 21797 $PACKER_VCC_NET +.sym 21800 w_rx_data[6] +.sym 21801 w_rx_data[1] +.sym 21802 w_rx_data[7] +.sym 21803 w_rx_data[0] +.sym 21804 w_rx_data[5] +.sym 21805 w_rx_data[4] +.sym 21806 w_rx_data[3] +.sym 21807 w_rx_data[2] +.sym 21816 tx_fifo.rd_addr[2] +.sym 21817 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21819 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21820 tx_fifo.rd_addr[5] +.sym 21821 tx_fifo.rd_addr[6] +.sym 21822 tx_fifo.rd_addr[7] +.sym 21823 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21824 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21825 tx_fifo.rd_addr[1] +.sym 21826 tx_fifo.rd_addr[0] +.sym 21827 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 21828 w_tx_fifo_pull .sym 21829 $PACKER_VCC_NET -.sym 21833 rx_fifo.mem_i.0.3_WDATA -.sym 21837 rx_fifo.mem_i.0.3_WDATA_1 -.sym 21849 $PACKER_VCC_NET -.sym 21852 rx_fifo.mem_i.0.3_WDATA -.sym 21859 w_tx_data_io[6] -.sym 21870 rx_fifo.wr_addr[8] -.sym 21871 rx_fifo.wr_addr[9] -.sym 21873 rx_fifo.wr_addr[7] -.sym 21876 rx_fifo.wr_addr[1] -.sym 21878 rx_fifo.wr_addr[3] -.sym 21881 io_pmod[0]$SB_IO_IN -.sym 21884 rx_fifo.wr_addr[5] -.sym 21886 rx_fifo.mem_q.0.3_WDATA_2 -.sym 21888 rx_fifo.wr_addr[2] -.sym 21890 $PACKER_VCC_NET -.sym 21891 rx_fifo.wr_addr[0] -.sym 21892 rx_fifo.mem_q.0.3_WDATA_3 -.sym 21895 rx_fifo.wr_addr[4] -.sym 21901 rx_fifo.wr_addr[6] -.sym 21918 rx_fifo.wr_addr[2] -.sym 21919 rx_fifo.wr_addr[3] -.sym 21921 rx_fifo.wr_addr[4] -.sym 21922 rx_fifo.wr_addr[5] -.sym 21923 rx_fifo.wr_addr[6] -.sym 21924 rx_fifo.wr_addr[7] -.sym 21925 rx_fifo.wr_addr[8] -.sym 21926 rx_fifo.wr_addr[9] -.sym 21927 rx_fifo.wr_addr[1] -.sym 21928 rx_fifo.wr_addr[0] -.sym 21929 lvds_clock_$glb_clk -.sym 21930 io_pmod[0]$SB_IO_IN -.sym 21932 rx_fifo.mem_q.0.3_WDATA_3 -.sym 21936 rx_fifo.mem_q.0.3_WDATA_2 +.sym 21833 w_tx_fifo_data[23] +.sym 21837 w_tx_fifo_data[21] +.sym 21842 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 21854 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21856 w_tx_fifo_pulled_data[16] +.sym 21857 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21859 tx_fifo.wr_addr[5] +.sym 21862 w_ioc[1] +.sym 21864 w_cs[0] +.sym 21870 tx_fifo.wr_addr[2] +.sym 21871 tx_fifo.wr_addr[5] +.sym 21872 w_tx_fifo_push +.sym 21873 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21874 w_tx_fifo_data[2] +.sym 21876 tx_fifo.wr_addr[6] +.sym 21877 tx_fifo.wr_addr[7] +.sym 21878 tx_fifo.wr_addr[3] +.sym 21879 tx_fifo.wr_addr[8] +.sym 21880 tx_fifo.wr_addr[9] +.sym 21881 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21883 tx_fifo.wr_addr[4] +.sym 21899 $PACKER_VCC_NET +.sym 21904 w_ioc[1] +.sym 21905 w_cs[0] +.sym 21906 w_ioc[0] +.sym 21907 w_ioc[4] +.sym 21908 w_ioc[3] +.sym 21909 w_ioc[2] +.sym 21918 tx_fifo.wr_addr[2] +.sym 21919 tx_fifo.wr_addr[3] +.sym 21921 tx_fifo.wr_addr[4] +.sym 21922 tx_fifo.wr_addr[5] +.sym 21923 tx_fifo.wr_addr[6] +.sym 21924 tx_fifo.wr_addr[7] +.sym 21925 tx_fifo.wr_addr[8] +.sym 21926 tx_fifo.wr_addr[9] +.sym 21927 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21928 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 21929 r_counter_$glb_clk +.sym 21930 w_tx_fifo_push +.sym 21936 w_tx_fifo_data[2] .sym 21939 $PACKER_VCC_NET -.sym 21944 rx_fifo.wr_addr[8] -.sym 21948 rx_fifo.mem_q.0.3_RDATA_3[1] -.sym 21955 rx_fifo.wr_addr[9] -.sym 21972 rx_fifo.mem_q.0.3_WDATA -.sym 21974 rx_fifo.rd_addr[2] -.sym 21975 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 21976 $PACKER_VCC_NET -.sym 21977 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 21978 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 21979 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 21980 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 21981 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 21983 io_pmod[1]$SB_IO_IN -.sym 21984 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 21985 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 21987 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 21999 rx_fifo.mem_q.0.3_WDATA_1 -.sym 22020 rx_fifo.rd_addr[2] -.sym 22021 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 22023 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 22024 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 22025 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 22026 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 22027 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 22028 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 22029 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 22030 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 22031 r_counter_$glb_clk -.sym 22032 io_pmod[1]$SB_IO_IN +.sym 21944 spi_if_ins.w_rx_data[5] +.sym 21947 w_rx_data[0] +.sym 21955 w_rx_data[7] +.sym 21956 $PACKER_VCC_NET +.sym 21958 w_tx_fifo_pulled_data[17] +.sym 21960 tx_fifo.rd_addr[6] +.sym 21961 tx_fifo.rd_addr[7] +.sym 21962 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21965 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21966 w_tx_fifo_pulled_data[19] +.sym 21967 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 21972 tx_fifo.rd_addr[1] +.sym 21977 tx_fifo.rd_addr[5] +.sym 21978 w_tx_fifo_data[1] +.sym 21979 tx_fifo.rd_addr[0] +.sym 21980 tx_fifo.rd_addr[7] +.sym 21981 tx_fifo.rd_addr[2] +.sym 21983 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 21984 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 21985 $PACKER_VCC_NET +.sym 21986 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 21987 w_tx_fifo_data[3] +.sym 21988 tx_fifo.rd_addr[6] +.sym 21990 w_tx_fifo_pull +.sym 21992 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 22004 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 22005 i_button_SB_LUT4_I0_I1[0] +.sym 22007 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 22008 w_tx_data_io[0] +.sym 22009 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 22010 w_tx_data_io[3] +.sym 22011 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[0] +.sym 22020 tx_fifo.rd_addr[2] +.sym 22021 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 22023 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 22024 tx_fifo.rd_addr[5] +.sym 22025 tx_fifo.rd_addr[6] +.sym 22026 tx_fifo.rd_addr[7] +.sym 22027 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 22028 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 22029 tx_fifo.rd_addr[1] +.sym 22030 tx_fifo.rd_addr[0] +.sym 22031 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 22032 w_tx_fifo_pull .sym 22033 $PACKER_VCC_NET -.sym 22037 rx_fifo.mem_q.0.3_WDATA -.sym 22041 rx_fifo.mem_q.0.3_WDATA_1 -.sym 22046 io_pmod[0]$SB_IO_IN -.sym 22157 o_rx_h_tx_l$SB_IO_OUT -.sym 22253 o_tr_vc2$SB_IO_OUT +.sym 22037 w_tx_fifo_data[3] +.sym 22041 w_tx_fifo_data[1] +.sym 22058 tx_fifo.wr_addr[8] +.sym 22059 spi_if_ins.w_rx_data[2] +.sym 22060 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 22061 spi_if_ins.w_rx_data[1] +.sym 22065 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 22067 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 22068 w_tx_fifo_pulled_data[14] +.sym 22074 tx_fifo.wr_addr[8] +.sym 22076 w_tx_fifo_push +.sym 22078 tx_fifo.wr_addr[4] +.sym 22079 tx_fifo.wr_addr[7] +.sym 22080 tx_fifo.wr_addr[6] +.sym 22081 tx_fifo.wr_addr[3] +.sym 22083 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22084 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 22086 tx_fifo.wr_addr[5] +.sym 22087 w_tx_fifo_data[16] +.sym 22088 tx_fifo.wr_addr[9] +.sym 22089 w_tx_fifo_data[18] +.sym 22090 tx_fifo.wr_addr[2] +.sym 22094 $PACKER_VCC_NET +.sym 22106 o_tr_vc2$SB_IO_OUT +.sym 22107 io_ctrl_ins.mixer_en_state +.sym 22109 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[2] +.sym 22110 o_shdn_rx_lna$SB_IO_OUT +.sym 22113 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 22122 tx_fifo.wr_addr[2] +.sym 22123 tx_fifo.wr_addr[3] +.sym 22125 tx_fifo.wr_addr[4] +.sym 22126 tx_fifo.wr_addr[5] +.sym 22127 tx_fifo.wr_addr[6] +.sym 22128 tx_fifo.wr_addr[7] +.sym 22129 tx_fifo.wr_addr[8] +.sym 22130 tx_fifo.wr_addr[9] +.sym 22131 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22132 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 22133 r_counter_$glb_clk +.sym 22134 w_tx_fifo_push +.sym 22136 w_tx_fifo_data[16] +.sym 22140 w_tx_fifo_data[18] +.sym 22143 $PACKER_VCC_NET +.sym 22151 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 22157 i_button_SB_LUT4_I0_I1[0] +.sym 22159 i_config[0]$SB_IO_IN +.sym 22168 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 22169 tx_fifo.rd_addr[6] +.sym 22170 w_tx_fifo_pulled_data[15] +.sym 22171 w_tx_fifo_pull +.sym 22178 tx_fifo.rd_addr[2] +.sym 22182 tx_fifo.rd_addr[1] +.sym 22183 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 22185 w_tx_fifo_data[17] +.sym 22186 tx_fifo.rd_addr[0] +.sym 22187 w_tx_fifo_data[19] +.sym 22188 tx_fifo.rd_addr[7] +.sym 22189 tx_fifo.rd_addr[6] +.sym 22190 tx_fifo.rd_addr[5] +.sym 22191 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 22192 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 22193 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 22194 w_tx_fifo_pull +.sym 22205 $PACKER_VCC_NET +.sym 22208 io_ctrl_ins.rf_pin_state[7] +.sym 22209 io_ctrl_ins.rf_pin_state[5] +.sym 22210 io_ctrl_ins.rf_pin_state[0] +.sym 22211 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 22212 io_ctrl_ins.rf_pin_state[3] +.sym 22213 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 22214 io_ctrl_ins.rf_pin_state[1] +.sym 22215 io_ctrl_ins.rf_pin_state[4] +.sym 22224 tx_fifo.rd_addr[2] +.sym 22225 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 22227 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 22228 tx_fifo.rd_addr[5] +.sym 22229 tx_fifo.rd_addr[6] +.sym 22230 tx_fifo.rd_addr[7] +.sym 22231 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 22232 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 22233 tx_fifo.rd_addr[1] +.sym 22234 tx_fifo.rd_addr[0] +.sym 22235 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 22236 w_tx_fifo_pull +.sym 22237 $PACKER_VCC_NET +.sym 22241 w_tx_fifo_data[19] +.sym 22245 w_tx_fifo_data[17] +.sym 22249 w_tx_fifo_data[14] +.sym 22266 o_led0$SB_IO_OUT +.sym 22278 tx_fifo.wr_addr[2] +.sym 22279 tx_fifo.wr_addr[9] +.sym 22282 w_tx_fifo_data[12] +.sym 22283 tx_fifo.wr_addr[5] +.sym 22284 tx_fifo.wr_addr[6] +.sym 22285 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 22287 tx_fifo.wr_addr[8] +.sym 22288 tx_fifo.wr_addr[7] +.sym 22289 w_tx_fifo_push +.sym 22290 tx_fifo.wr_addr[3] +.sym 22291 tx_fifo.wr_addr[4] +.sym 22293 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22307 $PACKER_VCC_NET +.sym 22309 w_tx_fifo_data[14] +.sym 22310 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[2] +.sym 22311 io_ctrl_ins.rf_pin_state[6] +.sym 22313 io_ctrl_ins.rx_h_state_SB_LUT4_I1_O[2] +.sym 22326 tx_fifo.wr_addr[2] +.sym 22327 tx_fifo.wr_addr[3] +.sym 22329 tx_fifo.wr_addr[4] +.sym 22330 tx_fifo.wr_addr[5] +.sym 22331 tx_fifo.wr_addr[6] +.sym 22332 tx_fifo.wr_addr[7] +.sym 22333 tx_fifo.wr_addr[8] +.sym 22334 tx_fifo.wr_addr[9] +.sym 22335 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22336 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 22337 r_counter_$glb_clk +.sym 22338 w_tx_fifo_push +.sym 22340 w_tx_fifo_data[12] +.sym 22344 w_tx_fifo_data[14] +.sym 22347 $PACKER_VCC_NET +.sym 22357 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 22364 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 22370 tx_fifo.rd_addr[7] +.sym 22384 tx_fifo.rd_addr[2] +.sym 22385 tx_fifo.rd_addr[5] +.sym 22387 tx_fifo.rd_addr[7] +.sym 22388 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 22389 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 22391 tx_fifo.rd_addr[1] +.sym 22393 $PACKER_VCC_NET +.sym 22394 tx_fifo.rd_addr[0] +.sym 22395 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 22396 tx_fifo.rd_addr[6] +.sym 22397 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 22398 w_tx_fifo_pull +.sym 22405 w_tx_fifo_data[13] +.sym 22424 tx_fifo.rd_addr[2] +.sym 22425 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 22427 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 22428 tx_fifo.rd_addr[5] +.sym 22429 tx_fifo.rd_addr[6] +.sym 22430 tx_fifo.rd_addr[7] +.sym 22431 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 22432 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 22433 tx_fifo.rd_addr[1] +.sym 22434 tx_fifo.rd_addr[0] +.sym 22435 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 22436 w_tx_fifo_pull +.sym 22437 $PACKER_VCC_NET +.sym 22445 w_tx_fifo_data[13] .sym 22487 o_led1$SB_IO_OUT -.sym 22498 o_led1$SB_IO_OUT +.sym 22509 o_led1$SB_IO_OUT .sym 22517 int_miso -.sym 22519 i_ss_SB_LUT4_I3_O -.sym 22531 i_ss_SB_LUT4_I3_O -.sym 22535 int_miso -.sym 22574 i_smi_a2$rename$0 -.sym 22575 int_miso +.sym 22519 o_miso_$_TBUF__Y_E +.sym 22528 int_miso +.sym 22531 o_miso_$_TBUF__Y_E +.sym 22560 int_miso +.sym 22563 i_mosi$SB_IO_IN +.sym 22576 i_mosi$SB_IO_IN +.sym 22588 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R +.sym 22594 w_smi_data_input[7] +.sym 22647 w_smi_data_input[7] +.sym 22664 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 22665 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R .sym 22666 i_sck$SB_IO_IN .sym 22668 i_ss$SB_IO_IN -.sym 22694 i_sck$SB_IO_IN -.sym 22698 i_ss$SB_IO_IN +.sym 22681 w_tx_fifo_pull +.sym 22688 smi_ctrl_ins.w_fifo_push_trigger_SB_DFFNSR_Q_R .sym 22702 i_sck$SB_IO_IN -.sym 22711 i_sck$SB_IO_IN -.sym 22715 i_ss$SB_IO_IN .sym 22720 i_sck$SB_IO_IN -.sym 22978 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 22982 int_miso -.sym 22995 spi_if_ins.state_if_SB_DFFESR_Q_E[1] -.sym 23003 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 23004 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23005 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 23006 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23008 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 23011 spi_if_ins.state_if[1] -.sym 23022 spi_if_ins.state_if[0] -.sym 23023 spi_if_ins.state_if_SB_DFFESR_Q_D[1] -.sym 23038 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23039 spi_if_ins.state_if_SB_DFFESR_Q_D[1] -.sym 23040 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23045 spi_if_ins.state_if[1] -.sym 23047 spi_if_ins.state_if[0] -.sym 23057 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 23058 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 23059 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23062 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 23063 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 23065 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 23069 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23072 spi_if_ins.state_if_SB_DFFESR_Q_E[1] -.sym 23073 r_counter_$glb_clk -.sym 23074 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 23075 $io_pmod[1]$iobuf_i -.sym 23081 smi_ctrl_ins.r_fifo_pull_1 -.sym 23082 smi_ctrl_ins.r_fifo_pull -.sym 23086 rx_fifo.wr_addr[4] -.sym 23087 io_pmod[1]$SB_IO_IN -.sym 23090 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23095 $io_pmod[4]$iobuf_i -.sym 23099 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23101 i_sck$SB_IO_IN -.sym 23102 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23108 $io_pmod[1]$iobuf_i -.sym 23116 i_rst_b$SB_IO_IN -.sym 23118 i_rst_b$SB_IO_IN -.sym 23121 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23124 w_debug_smi_test -.sym 23126 spi_if_ins.state_if[1] -.sym 23127 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 23129 spi_if_ins.state_if[0] -.sym 23131 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23132 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[2] -.sym 23135 smi_ctrl_ins.int_cnt[4] -.sym 23140 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23146 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 23147 smi_ctrl_ins.int_cnt[3] -.sym 23149 spi_if_ins.state_if[0] -.sym 23150 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23151 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23152 spi_if_ins.state_if[1] -.sym 23161 i_rst_b$SB_IO_IN -.sym 23162 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 23163 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[2] -.sym 23164 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23167 smi_ctrl_ins.int_cnt[4] -.sym 23168 smi_ctrl_ins.int_cnt[3] -.sym 23169 w_debug_smi_test -.sym 23173 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 23175 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23179 spi_if_ins.state_if[1] -.sym 23180 spi_if_ins.state_if[0] -.sym 23181 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23182 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23185 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23186 spi_if_ins.state_if[1] -.sym 23187 spi_if_ins.state_if[0] -.sym 23191 spi_if_ins.state_if[1] -.sym 23192 spi_if_ins.state_if[0] -.sym 23194 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 23195 i_rst_b$SB_IO_IN -.sym 23196 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 23198 spi_if_ins.r_tx_data_valid -.sym 23204 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23212 i_rst_b$SB_IO_IN -.sym 23220 w_debug_smi_test -.sym 23228 io_pmod_SB_DFFE_Q_E -.sym 23229 io_pmod[4]$SB_IO_IN -.sym 23241 spi_if_ins.state_if_SB_DFFESR_Q_E[1] -.sym 23244 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23253 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 23256 rx_fifo.mem_i.0.2_RDATA_3[0] -.sym 23258 rx_fifo.mem_i.0.2_RDATA[0] -.sym 23259 i_rst_b$SB_IO_IN -.sym 23262 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23264 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23266 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 23267 i_rst_b$SB_IO_IN -.sym 23270 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 23272 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 23274 i_rst_b$SB_IO_IN -.sym 23275 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23278 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 23279 i_rst_b$SB_IO_IN -.sym 23280 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 23296 spi_if_ins.state_if_SB_DFFESR_Q_E[1] -.sym 23297 i_rst_b$SB_IO_IN -.sym 23298 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 23302 rx_fifo.mem_i.0.2_RDATA[0] -.sym 23304 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23314 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23316 rx_fifo.mem_i.0.2_RDATA_3[0] -.sym 23318 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 23319 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 23320 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 23322 $io_pmod[5]$iobuf_i -.sym 23324 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 23325 $io_pmod[6]$iobuf_i -.sym 23346 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 23353 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 23356 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 23366 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 23367 spi_if_ins.w_rx_data[5] -.sym 23380 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 23391 spi_if_ins.w_rx_data[6] -.sym 23395 spi_if_ins.w_rx_data[6] -.sym 23398 spi_if_ins.w_rx_data[5] -.sym 23419 spi_if_ins.w_rx_data[6] -.sym 23422 spi_if_ins.w_rx_data[5] -.sym 23427 spi_if_ins.w_rx_data[5] -.sym 23428 spi_if_ins.w_rx_data[6] -.sym 23441 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 23442 r_counter_$glb_clk -.sym 23443 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 23450 int_miso -.sym 23456 w_cs[1] -.sym 23462 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 23467 channel -.sym 23473 int_miso -.sym 23475 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 23479 w_rx_data[0] -.sym 23485 w_cs[1] -.sym 23488 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23489 w_cs[2] -.sym 23490 w_cs[3] -.sym 23493 w_cs[1] -.sym 23496 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 23497 w_cs[2] -.sym 23498 w_cs[3] -.sym 23505 w_cs[0] -.sym 23506 rx_fifo.mem_i.0.3_RDATA_2[1] -.sym 23510 rx_fifo.mem_i.0.3_RDATA_3[1] -.sym 23512 rx_fifo.mem_i.0.3_RDATA[0] -.sym 23513 w_cs[0] -.sym 23514 w_cs[0] -.sym 23518 w_cs[2] -.sym 23519 w_cs[3] -.sym 23520 w_cs[1] -.sym 23521 w_cs[0] -.sym 23524 w_cs[3] -.sym 23525 w_cs[1] -.sym 23526 w_cs[2] -.sym 23527 w_cs[0] -.sym 23530 rx_fifo.mem_i.0.3_RDATA_3[1] -.sym 23533 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23536 rx_fifo.mem_i.0.3_RDATA_2[1] -.sym 23538 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23542 w_cs[0] -.sym 23543 w_cs[3] -.sym 23544 w_cs[1] -.sym 23545 w_cs[2] -.sym 23548 w_cs[2] -.sym 23549 w_cs[0] -.sym 23550 w_cs[1] -.sym 23551 w_cs[3] -.sym 23554 w_cs[1] -.sym 23555 w_cs[2] -.sym 23556 w_cs[0] -.sym 23557 w_cs[3] -.sym 23561 rx_fifo.mem_i.0.3_RDATA[0] -.sym 23562 rx_fifo.mem_i.0.0_RDATA[1] -.sym 23564 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 23565 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 22724 i_ss$SB_IO_IN +.sym 22728 i_ss$SB_IO_IN +.sym 22729 i_sck$SB_IO_IN +.sym 22735 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 22740 i_sck$SB_IO_IN +.sym 22751 i_rst_b$SB_IO_IN +.sym 22752 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 22753 w_smi_data_input[7] +.sym 22754 smi_ctrl_ins.tx_reg_state[1] +.sym 22757 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0[0] +.sym 22766 smi_ctrl_ins.tx_reg_state[2] +.sym 22771 smi_ctrl_ins.tx_reg_state[0] +.sym 22780 i_rst_b$SB_IO_IN +.sym 22781 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 22782 w_smi_data_input[7] +.sym 22783 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0[0] +.sym 22792 i_rst_b$SB_IO_IN +.sym 22794 w_smi_data_input[7] +.sym 22795 smi_ctrl_ins.tx_reg_state[1] +.sym 22799 w_smi_data_input[7] +.sym 22800 smi_ctrl_ins.tx_reg_state[0] +.sym 22801 i_rst_b$SB_IO_IN +.sym 22822 smi_ctrl_ins.tx_reg_state[2] +.sym 22823 w_smi_data_input[7] +.sym 22825 i_rst_b$SB_IO_IN +.sym 22827 smi_ctrl_ins.swe_and_reset_$glb_clk +.sym 22845 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0[0] +.sym 22848 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 22854 i_ss$SB_IO_IN +.sym 22857 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 22858 i_sck$SB_IO_IN +.sym 22890 w_tx_fifo_pull +.sym 22915 w_tx_fifo_pull +.sym 22952 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 22957 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 22963 w_rx_data[5] +.sym 22976 i_sck$SB_IO_IN +.sym 22979 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 22985 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 22995 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 22998 w_rx_24_fifo_data[7] +.sym 23009 w_rx_24_fifo_data[13] +.sym 23014 w_rx_24_fifo_data[9] +.sym 23017 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23034 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23035 w_rx_24_fifo_data[13] +.sym 23056 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23058 w_rx_24_fifo_data[7] +.sym 23068 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23070 w_rx_24_fifo_data[9] +.sym 23072 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 23073 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 23074 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 23082 r_counter +.sym 23085 w_rx_data[4] +.sym 23086 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23089 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 23094 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23099 w_rx_24_fifo_data[20] +.sym 23100 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 23101 w_tx_fifo_pulled_data[24] +.sym 23104 w_rx_24_fifo_data[22] +.sym 23105 w_rx_24_fifo_data[24] +.sym 23107 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[0] +.sym 23108 i_sck$SB_IO_IN +.sym 23110 w_rx_24_fifo_data[1] +.sym 23117 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 23122 w_tx_fifo_pulled_data[11] +.sym 23124 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23125 w_tx_fifo_pulled_data[28] +.sym 23132 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 23133 w_tx_fifo_pulled_data[29] +.sym 23134 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 23135 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23139 lvds_tx_inst.r_fifo_data[31] +.sym 23140 i_smi_a2$SB_IO_IN +.sym 23141 lvds_tx_inst.r_fifo_data[29] +.sym 23142 w_tx_fifo_pulled_data[15] +.sym 23143 w_tx_fifo_pulled_data[14] +.sym 23145 w_tx_fifo_pulled_data[31] +.sym 23147 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23149 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23150 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23151 lvds_tx_inst.r_fifo_data[29] +.sym 23152 lvds_tx_inst.r_fifo_data[31] +.sym 23155 i_smi_a2$SB_IO_IN +.sym 23157 w_tx_fifo_pulled_data[29] +.sym 23162 w_tx_fifo_pulled_data[15] +.sym 23164 i_smi_a2$SB_IO_IN +.sym 23168 w_tx_fifo_pulled_data[28] +.sym 23169 i_smi_a2$SB_IO_IN +.sym 23174 i_smi_a2$SB_IO_IN +.sym 23175 w_tx_fifo_pulled_data[11] +.sym 23179 i_smi_a2$SB_IO_IN +.sym 23182 w_tx_fifo_pulled_data[14] +.sym 23186 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 23187 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 23188 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23192 w_tx_fifo_pulled_data[31] +.sym 23193 i_smi_a2$SB_IO_IN +.sym 23195 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 23196 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 23197 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 23199 w_rx_24_fifo_data[24] +.sym 23200 w_rx_24_fifo_data[3] +.sym 23202 w_rx_24_fifo_data[18] +.sym 23203 w_rx_24_fifo_data[5] +.sym 23204 w_rx_24_fifo_data[20] +.sym 23209 w_rx_data[3] +.sym 23212 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 23224 tx_fifo.rd_addr_gray_wr_r[2] +.sym 23225 w_tx_fifo_pulled_data[7] +.sym 23226 i_sck$SB_IO_IN +.sym 23227 i_glob_clock$SB_IO_IN +.sym 23230 i_ss$SB_IO_IN +.sym 23231 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 23232 r_counter +.sym 23239 tx_fifo.rd_addr_gray[1] +.sym 23244 lvds_tx_inst.r_fifo_data[26] +.sym 23247 tx_fifo.rd_addr_gray_wr[2] +.sym 23248 tx_fifo.rd_addr_gray_wr[3] +.sym 23253 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23256 tx_fifo.rd_addr_gray[5] +.sym 23261 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23262 tx_fifo.rd_addr_gray[0] +.sym 23264 lvds_tx_inst.r_fifo_data[24] +.sym 23268 tx_fifo.rd_addr_gray[2] +.sym 23270 tx_fifo.rd_addr_gray[3] +.sym 23272 tx_fifo.rd_addr_gray[2] +.sym 23281 tx_fifo.rd_addr_gray[3] +.sym 23286 tx_fifo.rd_addr_gray[1] +.sym 23290 tx_fifo.rd_addr_gray[5] +.sym 23296 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23297 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23298 lvds_tx_inst.r_fifo_data[24] +.sym 23299 lvds_tx_inst.r_fifo_data[26] +.sym 23304 tx_fifo.rd_addr_gray_wr[2] +.sym 23308 tx_fifo.rd_addr_gray_wr[3] +.sym 23314 tx_fifo.rd_addr_gray[0] +.sym 23319 r_counter_$glb_clk +.sym 23321 lvds_tx_inst.r_fifo_data[0] +.sym 23322 lvds_tx_inst.r_fifo_data[24] +.sym 23323 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[0] +.sym 23324 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] +.sym 23325 i_smi_a2$SB_IO_IN +.sym 23326 lvds_tx_inst.r_fifo_data[4] +.sym 23327 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[3] +.sym 23328 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[0] +.sym 23336 tx_fifo.rd_addr[7] +.sym 23343 tx_fifo.rd_addr_gray[1] +.sym 23344 w_rx_24_fifo_data[3] +.sym 23346 tx_fifo.rd_addr_gray_wr[1] +.sym 23347 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23348 tx_fifo.rd_addr_gray_wr[5] +.sym 23349 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 23350 i_sck$SB_IO_IN +.sym 23354 i_ss$SB_IO_IN +.sym 23355 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23356 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23362 w_tx_fifo_pulled_data[18] +.sym 23364 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23365 lvds_tx_inst.r_fifo_data[27] +.sym 23366 i_smi_a2$SB_IO_IN +.sym 23368 w_tx_fifo_pulled_data[25] +.sym 23370 w_tx_fifo_pulled_data[26] +.sym 23376 w_tx_fifo_pulled_data[27] +.sym 23377 lvds_tx_inst.r_fifo_data[25] +.sym 23379 w_tx_fifo_pulled_data[5] +.sym 23380 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 23381 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23389 w_tx_fifo_pulled_data[20] +.sym 23392 w_tx_fifo_pulled_data[16] +.sym 23395 lvds_tx_inst.r_fifo_data[25] +.sym 23396 lvds_tx_inst.r_fifo_data[27] +.sym 23397 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23398 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23401 w_tx_fifo_pulled_data[16] +.sym 23404 i_smi_a2$SB_IO_IN +.sym 23407 i_smi_a2$SB_IO_IN +.sym 23409 w_tx_fifo_pulled_data[20] +.sym 23414 i_smi_a2$SB_IO_IN +.sym 23415 w_tx_fifo_pulled_data[27] +.sym 23419 w_tx_fifo_pulled_data[18] +.sym 23421 i_smi_a2$SB_IO_IN +.sym 23425 w_tx_fifo_pulled_data[26] +.sym 23428 i_smi_a2$SB_IO_IN +.sym 23431 i_smi_a2$SB_IO_IN +.sym 23432 w_tx_fifo_pulled_data[5] +.sym 23438 i_smi_a2$SB_IO_IN +.sym 23440 w_tx_fifo_pulled_data[25] +.sym 23441 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 23442 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 23443 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 23446 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[1] +.sym 23455 w_rx_data[6] +.sym 23456 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[1] +.sym 23461 w_tx_fifo_pulled_data[0] +.sym 23472 spi_if_ins.r_tx_byte[7] +.sym 23473 i_sck$SB_IO_IN +.sym 23485 w_tx_fifo_pulled_data[1] +.sym 23487 w_tx_fifo_pulled_data[23] +.sym 23491 w_tx_fifo_pulled_data[3] +.sym 23492 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[3] +.sym 23496 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 23497 i_smi_a2$SB_IO_IN +.sym 23499 lvds_tx_inst.r_fifo_data[5] +.sym 23500 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[0] +.sym 23501 lvds_tx_inst.r_fifo_data[1] +.sym 23503 w_tx_fifo_pulled_data[19] +.sym 23504 w_tx_fifo_pulled_data[21] +.sym 23507 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[1] +.sym 23512 w_tx_fifo_pulled_data[17] +.sym 23515 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23516 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23518 w_tx_fifo_pulled_data[1] +.sym 23519 i_smi_a2$SB_IO_IN +.sym 23525 w_tx_fifo_pulled_data[17] +.sym 23526 i_smi_a2$SB_IO_IN +.sym 23532 w_tx_fifo_pulled_data[23] +.sym 23533 i_smi_a2$SB_IO_IN +.sym 23536 w_tx_fifo_pulled_data[21] +.sym 23538 i_smi_a2$SB_IO_IN +.sym 23542 w_tx_fifo_pulled_data[19] +.sym 23543 i_smi_a2$SB_IO_IN +.sym 23548 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[3] +.sym 23549 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[0] +.sym 23550 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23551 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[1] +.sym 23555 i_smi_a2$SB_IO_IN +.sym 23556 w_tx_fifo_pulled_data[3] +.sym 23560 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 23561 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 23562 lvds_tx_inst.r_fifo_data[5] +.sym 23563 lvds_tx_inst.r_fifo_data[1] +.sym 23564 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 23565 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk .sym 23566 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 23568 i_glob_clock$SB_IO_IN -.sym 23571 spi_if_ins.r_tx_byte[4] -.sym 23572 spi_if_ins.r_tx_byte[7] -.sym 23574 spi_if_ins.r_tx_byte[6] -.sym 23579 io_pmod[1]$SB_IO_IN -.sym 23580 $PACKER_VCC_NET -.sym 23584 sys_ctrl_ins.debug_smi_test_SB_LUT4_I1_O -.sym 23593 w_debug_smi_test -.sym 23597 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 23598 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 23600 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 23601 $io_pmod[1]$iobuf_i -.sym 23608 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 23609 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 23610 i_rst_b$SB_IO_IN -.sym 23612 spi_if_ins.o_cs_SB_LUT4_I3_1_O[0] -.sym 23613 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 23615 w_tx_data_io[5] -.sym 23616 w_tx_data_smi[1] -.sym 23617 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 23620 w_tx_data_io[6] -.sym 23621 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 23622 w_tx_data_io[7] -.sym 23623 w_tx_data_io[1] -.sym 23626 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 23633 i_glob_clock$SB_IO_IN -.sym 23637 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 23638 w_tx_data_io[4] -.sym 23639 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 23643 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 23644 w_tx_data_io[4] -.sym 23647 w_tx_data_smi[1] -.sym 23648 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 23649 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 23650 w_tx_data_io[1] -.sym 23655 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 23659 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 23661 w_tx_data_io[6] -.sym 23666 w_tx_data_io[5] -.sym 23667 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 23668 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 23678 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 23679 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 23680 w_tx_data_io[7] -.sym 23684 i_rst_b$SB_IO_IN -.sym 23686 spi_if_ins.o_cs_SB_LUT4_I3_1_O[0] -.sym 23687 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 23688 i_glob_clock$SB_IO_IN -.sym 23689 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 23693 r_counter -.sym 23708 w_tx_data_io[6] -.sym 23716 r_counter -.sym 23722 io_pmod[4]$SB_IO_IN -.sym 23733 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 23740 r_tx_data[1] -.sym 23785 r_tx_data[1] -.sym 23810 spi_if_ins.r_tx_byte_SB_DFFE_Q_E +.sym 23567 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 23568 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3 +.sym 23570 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 23573 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E +.sym 23577 w_rx_data[1] +.sym 23589 w_tx_fifo_pulled_data[1] +.sym 23594 w_tx_fifo_pulled_data[2] +.sym 23597 w_rx_24_fifo_data[1] +.sym 23600 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 23601 i_sck$SB_IO_IN +.sym 23608 i_rst_b$SB_IO_IN +.sym 23610 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 23617 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 23624 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 23625 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 23627 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 23632 spi_if_ins.r_tx_byte[7] +.sym 23633 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3 +.sym 23638 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E +.sym 23647 spi_if_ins.r_tx_byte[7] +.sym 23649 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 23650 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 23654 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E +.sym 23665 i_rst_b$SB_IO_IN +.sym 23677 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3 +.sym 23679 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 23680 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 23686 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3 +.sym 23687 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 23688 r_counter_$glb_clk +.sym 23701 w_rx_data[7] +.sym 23712 i_rst_b_SB_LUT4_I3_O +.sym 23715 i_glob_clock$SB_IO_IN +.sym 23723 w_rx_data[7] +.sym 23731 i_rst_b$SB_IO_IN +.sym 23744 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 23745 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23750 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 23754 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 23758 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 23760 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 23782 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 23783 i_rst_b$SB_IO_IN +.sym 23784 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 23795 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 23801 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 23802 i_rst_b$SB_IO_IN +.sym 23803 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23810 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .sym 23811 r_counter_$glb_clk -.sym 23816 $io_pmod[2]$iobuf_i -.sym 23863 io_pmod[1]$SB_IO_IN -.sym 23906 io_pmod[1]$SB_IO_IN -.sym 23942 $PACKER_GND_NET -.sym 23949 io_pmod[1]$SB_IO_IN -.sym 24078 io_pmod[0]$SB_IO_IN -.sym 24202 o_rx_h_tx_l_b$SB_IO_OUT -.sym 24321 o_tr_vc1$SB_IO_OUT -.sym 24444 o_tr_vc1_b$SB_IO_OUT +.sym 23812 spi_if_ins.o_load_cmd_SB_DFFESR_Q_R +.sym 23823 w_rx_data[0] +.sym 23833 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 23835 i_rst_b$SB_IO_IN +.sym 23847 w_rx_data[1] +.sym 23857 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23859 spi_if_ins.w_rx_data[1] +.sym 23864 spi_if_ins.w_rx_data[2] +.sym 23866 spi_if_ins.w_rx_data[6] +.sym 23867 spi_if_ins.w_rx_data[5] +.sym 23873 spi_if_ins.w_rx_data[4] +.sym 23877 spi_if_ins.w_rx_data[0] +.sym 23881 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23883 spi_if_ins.w_rx_data[3] +.sym 23890 spi_if_ins.w_rx_data[6] +.sym 23893 spi_if_ins.w_rx_data[1] +.sym 23900 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23907 spi_if_ins.w_rx_data[0] +.sym 23911 spi_if_ins.w_rx_data[5] +.sym 23917 spi_if_ins.w_rx_data[4] +.sym 23925 spi_if_ins.w_rx_data[3] +.sym 23929 spi_if_ins.w_rx_data[2] +.sym 23933 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 23934 r_counter_$glb_clk +.sym 23938 r_tx_data[3] +.sym 23940 $PACKER_GND_NET +.sym 23946 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 23950 spi_if_ins.w_rx_data[2] +.sym 23953 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 23954 spi_if_ins.w_rx_data[6] +.sym 23955 spi_if_ins.w_rx_data[1] +.sym 23960 w_ioc[0] +.sym 23963 w_rx_data[0] +.sym 23965 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 23967 w_rx_data[4] +.sym 23971 w_rx_data[2] +.sym 23979 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 23995 spi_if_ins.w_rx_data[3] +.sym 23999 spi_if_ins.w_rx_data[0] +.sym 24005 spi_if_ins.w_rx_data[4] +.sym 24006 spi_if_ins.w_rx_data[2] +.sym 24007 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 24008 spi_if_ins.w_rx_data[1] +.sym 24024 spi_if_ins.w_rx_data[1] +.sym 24030 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 24034 spi_if_ins.w_rx_data[0] +.sym 24040 spi_if_ins.w_rx_data[4] +.sym 24048 spi_if_ins.w_rx_data[3] +.sym 24055 spi_if_ins.w_rx_data[2] +.sym 24056 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 24057 r_counter_$glb_clk +.sym 24062 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 24073 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 24078 w_tx_fifo_pull +.sym 24079 r_tx_data_SB_DFFE_Q_E +.sym 24084 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 24085 spi_if_ins.w_rx_data[0] +.sym 24086 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24088 w_ioc[0] +.sym 24091 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 24093 i_button_SB_LUT4_I0_I1[0] +.sym 24101 i_button_SB_LUT4_I0_I1[0] +.sym 24102 w_ioc[1] +.sym 24103 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[2] +.sym 24104 w_ioc[0] +.sym 24105 w_ioc[4] +.sym 24106 w_ioc[3] +.sym 24107 w_ioc[2] +.sym 24108 o_led0$SB_IO_OUT +.sym 24109 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 24110 w_ioc[1] +.sym 24112 i_config[0]$SB_IO_IN +.sym 24113 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 24114 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 24115 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 24120 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 24124 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 24125 i_button_SB_LUT4_I0_I1[0] +.sym 24127 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 24131 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[3] +.sym 24133 w_ioc[3] +.sym 24134 w_ioc[2] +.sym 24135 w_ioc[1] +.sym 24136 w_ioc[4] +.sym 24139 w_ioc[1] +.sym 24140 w_ioc[0] +.sym 24142 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 24151 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 24152 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 24153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 24157 i_button_SB_LUT4_I0_I1[0] +.sym 24158 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[2] +.sym 24159 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[3] +.sym 24160 o_led0$SB_IO_OUT +.sym 24163 w_ioc[2] +.sym 24164 w_ioc[3] +.sym 24165 w_ioc[4] +.sym 24169 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 24170 i_button_SB_LUT4_I0_I1[0] +.sym 24171 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 24172 i_config[0]$SB_IO_IN +.sym 24175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 24176 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 24177 w_ioc[1] +.sym 24178 w_ioc[0] +.sym 24179 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 24180 r_counter_$glb_clk +.sym 24181 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 24196 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 24204 o_led0$SB_IO_OUT +.sym 24205 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 24207 w_tx_data_io[6] +.sym 24208 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 24209 w_tx_data_io[5] +.sym 24213 w_tx_data_io[7] +.sym 24216 w_rx_data[7] +.sym 24225 io_ctrl_ins.rf_pin_state[0] +.sym 24227 io_ctrl_ins.rf_pin_state[3] +.sym 24229 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24231 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 24232 io_ctrl_ins.mixer_en_state +.sym 24234 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 24237 io_ctrl_ins.rf_pin_state[1] +.sym 24239 io_ctrl_ins.o_pmod[3] +.sym 24244 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 24246 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24247 o_tr_vc2$SB_IO_OUT +.sym 24248 w_ioc[0] +.sym 24249 io_ctrl_ins.o_pmod[0] +.sym 24256 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24257 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24258 io_ctrl_ins.rf_pin_state[3] +.sym 24259 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 24262 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24263 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24264 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 24265 io_ctrl_ins.rf_pin_state[0] +.sym 24274 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 24275 w_ioc[0] +.sym 24276 io_ctrl_ins.o_pmod[0] +.sym 24277 io_ctrl_ins.mixer_en_state +.sym 24281 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24282 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24283 io_ctrl_ins.rf_pin_state[1] +.sym 24298 o_tr_vc2$SB_IO_OUT +.sym 24299 w_ioc[0] +.sym 24300 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 24301 io_ctrl_ins.o_pmod[3] +.sym 24302 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 24303 r_counter_$glb_clk +.sym 24305 o_rx_h_tx_l_b$SB_IO_OUT +.sym 24306 o_rx_h_tx_l$SB_IO_OUT +.sym 24307 o_tr_vc1$SB_IO_OUT +.sym 24308 o_tr_vc1_b$SB_IO_OUT +.sym 24310 io_ctrl_ins.rx_h_state_SB_LUT4_I1_O[3] +.sym 24311 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[3] +.sym 24312 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R +.sym 24317 o_tr_vc2$SB_IO_OUT +.sym 24338 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 24340 o_rx_h_tx_l$SB_IO_OUT +.sym 24352 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24362 w_rx_data[5] +.sym 24364 w_rx_data[4] +.sym 24365 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 24366 w_rx_data[7] +.sym 24367 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24372 w_rx_data[1] +.sym 24373 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 24374 w_rx_data[3] +.sym 24375 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 24376 w_rx_data[0] +.sym 24379 w_rx_data[7] +.sym 24386 w_rx_data[5] +.sym 24394 w_rx_data[0] +.sym 24397 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 24398 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 24399 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24400 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24406 w_rx_data[3] +.sym 24409 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 24410 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 24411 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 24412 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24416 w_rx_data[1] +.sym 24422 w_rx_data[4] +.sym 24425 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 24426 r_counter_$glb_clk +.sym 24428 w_tx_data_io[6] +.sym 24429 w_tx_data_io[5] +.sym 24431 w_tx_data_io[7] +.sym 24445 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24448 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 24453 i_config[2]$SB_IO_IN +.sym 24454 o_tr_vc1_b$SB_IO_OUT +.sym 24493 io_ctrl_ins.pmod_dir_state[7] +.sym 24496 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 24498 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 24499 io_ctrl_ins.pmod_dir_state[5] +.sym 24500 w_rx_data[6] +.sym 24502 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 24505 io_ctrl_ins.pmod_dir_state[5] +.sym 24509 w_rx_data[6] +.sym 24521 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 24522 io_ctrl_ins.pmod_dir_state[7] +.sym 24548 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 24549 r_counter_$glb_clk +.sym 24574 i_button_SB_LUT4_I0_I1[0] +.sym 24578 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E .sym 24596 o_led0$SB_IO_OUT .sym 24618 o_led0$SB_IO_OUT -.sym 24655 i_ss$SB_IO_IN -.sym 24785 r_counter -.sym 24949 i_sck$SB_IO_IN -.sym 24951 int_miso -.sym 25089 io_pmod[4]$SB_IO_IN -.sym 25252 io_pmod[4]$SB_IO_IN -.sym 25325 io_pmod[4]$SB_IO_IN -.sym 25328 smi_ctrl_ins.w_fifo_pull_trigger -.sym 25339 smi_ctrl_ins.r_fifo_pull_1 -.sym 25348 smi_ctrl_ins.r_fifo_pull -.sym 25350 smi_ctrl_ins.r_fifo_pull_1 -.sym 25351 io_pmod[4]$SB_IO_IN -.sym 25352 smi_ctrl_ins.r_fifo_pull -.sym 25388 smi_ctrl_ins.r_fifo_pull -.sym 25395 smi_ctrl_ins.w_fifo_pull_trigger -.sym 25397 r_counter_$glb_clk +.sym 24658 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 24660 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 24677 i_ss$SB_IO_IN +.sym 25104 o_smi_read_req$SB_IO_OUT +.sym 25162 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25173 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 25183 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 25190 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 25196 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 25197 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25198 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 25225 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 25226 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25227 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 25241 lvds_rx_24_inst.r_state_if_SB_DFFER_Q_E +.sym 25242 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 25243 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 25252 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25342 i_glob_clock$SB_IO_IN +.sym 25348 r_counter +.sym 25393 r_counter +.sym 25397 i_glob_clock$SB_IO_IN .sym 25398 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 25399 i_smi_a2$rename$0 -.sym 25480 spi_if_ins.r_tx_data_valid -.sym 25483 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 25491 i_ss$SB_IO_IN -.sym 25492 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 25502 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 25506 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 25542 spi_if_ins.r_tx_data_valid -.sym 25544 i_ss$SB_IO_IN -.sym 25551 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 25552 r_counter_$glb_clk -.sym 25553 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 25554 io_pmod[3]$SB_IO_IN -.sym 25556 channel -.sym 25629 io_pmod_SB_DFFE_Q_E -.sym 25634 $io_pmod[5]$iobuf_i -.sym 25650 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 25658 w_rx_data[0] -.sym 25668 $io_pmod[5]$iobuf_i -.sym 25678 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 25684 w_rx_data[0] -.sym 25706 io_pmod_SB_DFFE_Q_E -.sym 25707 r_counter_$glb_clk +.sym 25472 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25474 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 25475 w_rx_24_fifo_data[16] +.sym 25479 w_rx_24_fifo_data[1] +.sym 25480 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25481 w_rx_24_fifo_data[22] +.sym 25492 w_rx_24_fifo_data[18] +.sym 25498 w_rx_24_fifo_data[3] +.sym 25511 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25512 w_rx_24_fifo_data[22] +.sym 25518 w_rx_24_fifo_data[1] +.sym 25519 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25530 w_rx_24_fifo_data[16] +.sym 25531 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25536 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25537 w_rx_24_fifo_data[3] +.sym 25541 w_rx_24_fifo_data[18] +.sym 25543 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25551 w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 25552 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 25553 lvds_rx_24_inst.o_fifo_data_SB_DFFESR_Q_R_$glb_sr +.sym 25565 w_rx_24_fifo_data[16] +.sym 25566 w_rx_24_fifo_data[24] +.sym 25629 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[1] +.sym 25630 w_tx_fifo_pulled_data[24] +.sym 25633 w_tx_fifo_pulled_data[0] +.sym 25634 i_smi_a2$SB_IO_IN +.sym 25637 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[0] +.sym 25638 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 25642 w_tx_fifo_pulled_data[7] +.sym 25643 lvds_tx_inst.r_fifo_data[0] +.sym 25645 w_tx_fifo_pulled_data[4] +.sym 25646 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 25648 lvds_tx_inst.r_fifo_data[4] +.sym 25653 w_tx_fifo_pulled_data[6] +.sym 25654 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 25657 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[3] +.sym 25660 w_tx_fifo_pulled_data[0] +.sym 25663 i_smi_a2$SB_IO_IN +.sym 25666 w_tx_fifo_pulled_data[24] +.sym 25668 i_smi_a2$SB_IO_IN +.sym 25673 i_smi_a2$SB_IO_IN +.sym 25675 w_tx_fifo_pulled_data[6] +.sym 25678 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[3] +.sym 25679 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 25680 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[0] +.sym 25681 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[1] +.sym 25685 i_smi_a2$SB_IO_IN +.sym 25692 i_smi_a2$SB_IO_IN +.sym 25693 w_tx_fifo_pulled_data[4] +.sym 25696 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 25697 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 25698 lvds_tx_inst.r_fifo_data[0] +.sym 25699 lvds_tx_inst.r_fifo_data[4] +.sym 25704 i_smi_a2$SB_IO_IN +.sym 25705 w_tx_fifo_pulled_data[7] +.sym 25706 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 25707 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 25708 i_rst_b_SB_LUT4_I3_O_$glb_sr .sym 25711 i_glob_clock$SB_IO_IN -.sym 25718 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 25786 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 25787 spi_if_ins.r_tx_byte[7] -.sym 25793 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 25796 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 25852 spi_if_ins.r_tx_byte[7] -.sym 25853 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 25854 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 25861 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 25862 r_counter_$glb_clk -.sym 25877 r_counter -.sym 25880 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 25881 io_pmod_SB_DFFE_Q_E -.sym 25937 r_tx_data[4] -.sym 25940 r_tx_data[6] -.sym 25943 r_tx_data[7] -.sym 25947 i_glob_clock$SB_IO_IN -.sym 25948 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 25978 i_glob_clock$SB_IO_IN -.sym 25994 r_tx_data[4] -.sym 26003 r_tx_data[7] -.sym 26012 r_tx_data[6] -.sym 26016 spi_if_ins.r_tx_byte_SB_DFFE_Q_E -.sym 26017 r_counter_$glb_clk -.sym 26033 lvds_clock -.sym 26101 i_glob_clock$SB_IO_IN -.sym 26119 r_counter -.sym 26144 r_counter -.sym 26172 i_glob_clock$SB_IO_IN -.sym 26173 i_rst_b_SB_LUT4_I3_O_$glb_sr -.sym 26174 o_smi_read_req$SB_IO_OUT -.sym 26176 io_pmod[1]$SB_IO_IN -.sym 26251 io_pmod[4]$SB_IO_IN -.sym 26258 w_debug_smi_test -.sym 26299 io_pmod[4]$SB_IO_IN -.sym 26301 w_debug_smi_test -.sym 26329 io_pmod[0]$SB_IO_IN -.sym 26340 $io_pmod[1]$iobuf_i -.sym 27217 o_rx_h_tx_l_b$SB_IO_OUT -.sym 27245 o_smi_read_req$SB_IO_OUT -.sym 27275 i_smi_a2$rename$0 +.sym 25722 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 25794 i_smi_a2$SB_IO_IN +.sym 25800 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 25813 w_tx_fifo_pulled_data[2] +.sym 25827 w_tx_fifo_pulled_data[2] +.sym 25830 i_smi_a2$SB_IO_IN +.sym 25861 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 25862 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 25863 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 25875 r_counter +.sym 25878 i_glob_clock$SB_IO_IN +.sym 25939 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E +.sym 25942 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25950 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25951 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 25955 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[1] +.sym 25956 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 25960 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 25961 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[2] +.sym 25962 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 25970 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 25971 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[2] +.sym 25972 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25973 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 25976 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25977 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[1] +.sym 25978 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 25979 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 25988 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 25989 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 25990 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 25991 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 26006 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 26007 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] +.sym 26008 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 26009 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 26016 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E +.sym 26017 o_iq_tx_clk_p$SB_IO_OUT_$glb_clk +.sym 26018 i_rst_b_SB_LUT4_I3_O_$glb_sr +.sym 26180 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R +.sym 26402 i_glob_clock$SB_IO_IN +.sym 26411 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 26413 r_tx_data_SB_DFFE_Q_E +.sym 26431 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 26432 w_tx_data_io[3] +.sym 26447 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 26450 w_tx_data_io[3] +.sym 26481 r_tx_data_SB_DFFE_Q_E +.sym 26482 i_glob_clock$SB_IO_IN +.sym 26483 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 26493 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 26572 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[0] +.sym 26584 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 26609 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 26611 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[0] +.sym 26652 o_rx_h_tx_l$SB_IO_OUT +.sym 26868 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 26869 io_ctrl_ins.o_pmod[5] +.sym 26870 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26871 io_ctrl_ins.o_pmod[7] +.sym 26873 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 26875 io_ctrl_ins.rf_pin_state[7] +.sym 26876 io_ctrl_ins.rf_pin_state[5] +.sym 26878 i_button_SB_LUT4_I0_I1[0] +.sym 26879 w_ioc[0] +.sym 26880 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26882 io_ctrl_ins.rf_pin_state[4] +.sym 26883 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 26884 io_ctrl_ins.rf_pin_state[6] +.sym 26885 o_tr_vc1$SB_IO_OUT +.sym 26892 o_rx_h_tx_l$SB_IO_OUT +.sym 26894 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 26900 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26901 io_ctrl_ins.rf_pin_state[6] +.sym 26902 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 26907 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 26908 io_ctrl_ins.rf_pin_state[7] +.sym 26909 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26912 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 26914 io_ctrl_ins.rf_pin_state[5] +.sym 26915 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26918 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 26919 io_ctrl_ins.rf_pin_state[4] +.sym 26921 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 26930 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 26931 o_rx_h_tx_l$SB_IO_OUT +.sym 26932 w_ioc[0] +.sym 26933 io_ctrl_ins.o_pmod[7] +.sym 26936 o_tr_vc1$SB_IO_OUT +.sym 26937 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 26938 io_ctrl_ins.o_pmod[5] +.sym 26939 w_ioc[0] +.sym 26943 i_button_SB_LUT4_I0_I1[0] +.sym 26944 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 26945 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 26946 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 26947 r_counter_$glb_clk +.sym 26957 o_rx_h_tx_l_b$SB_IO_OUT +.sym 26961 io_ctrl_ins.o_pmod[5] +.sym 26963 io_ctrl_ins.o_pmod[7] +.sym 26965 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E +.sym 27022 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[2] +.sym 27024 i_button$SB_IO_IN +.sym 27025 io_ctrl_ins.rx_h_state_SB_LUT4_I1_O[2] +.sym 27027 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 27033 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 27035 io_ctrl_ins.rx_h_state_SB_LUT4_I1_O[3] +.sym 27036 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[3] +.sym 27038 i_config[2]$SB_IO_IN +.sym 27045 i_button_SB_LUT4_I0_I1[0] +.sym 27049 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 27051 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R +.sym 27053 io_ctrl_ins.pmod_dir_state[6] +.sym 27055 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 27057 io_ctrl_ins.pmod_dir_state[6] +.sym 27058 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 27061 i_button_SB_LUT4_I0_I1[0] +.sym 27062 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[2] +.sym 27063 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[3] +.sym 27064 i_config[2]$SB_IO_IN +.sym 27073 i_button_SB_LUT4_I0_I1[0] +.sym 27074 i_button$SB_IO_IN +.sym 27075 io_ctrl_ins.rx_h_state_SB_LUT4_I1_O[2] +.sym 27076 io_ctrl_ins.rx_h_state_SB_LUT4_I1_O[3] +.sym 27101 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 27102 r_counter_$glb_clk +.sym 27103 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R +.sym 27120 i_button$SB_IO_IN +.sym 27247 i_ss$SB_IO_IN +.sym 27277 i_mosi$SB_IO_IN .sym 27283 o_smi_read_req$SB_IO_OUT -.sym 27297 o_smi_read_req$SB_IO_OUT -.sym 27305 i_smi_a2$rename$0 -.sym 27310 $io_pmod[4]$iobuf_i -.sym 27330 $io_pmod[4]$iobuf_i -.sym 27335 i_smi_a2$rename$0 -.sym 27337 io_pmod[1]$SB_IO_IN -.sym 27365 o_smi_read_req$SB_IO_OUT -.sym 27370 $io_pmod[5]$iobuf_i -.sym 27388 $io_pmod[5]$iobuf_i -.sym 27400 $io_pmod[3]$iobuf_i -.sym 27403 $io_pmod[6]$iobuf_i -.sym 27420 $io_pmod[3]$iobuf_i -.sym 27421 $io_pmod[6]$iobuf_i -.sym 27427 i_glob_clock$SB_IO_IN +.sym 27294 o_smi_read_req$SB_IO_OUT +.sym 27307 i_ss$SB_IO_IN +.sym 27367 i_ss$SB_IO_IN +.sym 27397 i_mosi$SB_IO_IN .sym 27429 r_counter .sym 27442 r_counter -.sym 27455 io_pmod[0]$SB_IO_IN -.sym 27457 io_pmod[1]$SB_IO_IN -.sym 27459 lvds_clock +.sym 27459 i_rst_b_SB_LUT4_I3_O .sym 27460 $PACKER_VCC_NET -.sym 27475 $PACKER_VCC_NET -.sym 27481 lvds_clock -.sym 27485 o_smi_read_req$SB_IO_OUT -.sym 27519 $io_pmod[2]$iobuf_i -.sym 27522 $io_pmod[1]$iobuf_i -.sym 27531 $io_pmod[1]$iobuf_i -.sym 27539 $io_pmod[2]$iobuf_i -.sym 27549 $io_pmod[0]$iobuf_i +.sym 27474 i_rst_b_SB_LUT4_I3_O +.sym 27480 $PACKER_VCC_NET .sym 27552 $PACKER_GND_NET -.sym 27572 $PACKER_GND_NET -.sym 27573 $io_pmod[0]$iobuf_i +.sym 27570 $PACKER_GND_NET .sym 27582 o_rx_h_tx_l$SB_IO_OUT -.sym 27595 o_rx_h_tx_l$SB_IO_OUT +.sym 27591 o_rx_h_tx_l$SB_IO_OUT .sym 27605 o_tr_vc1$SB_IO_OUT .sym 27608 o_tr_vc2$SB_IO_OUT -.sym 27617 o_tr_vc2$SB_IO_OUT -.sym 27629 o_tr_vc1$SB_IO_OUT +.sym 27616 o_tr_vc1$SB_IO_OUT +.sym 27619 o_tr_vc2$SB_IO_OUT .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT .sym 27634 o_tr_vc1_b$SB_IO_OUT -.sym 27647 o_tr_vc1_b$SB_IO_OUT -.sym 27651 o_rx_h_tx_l_b$SB_IO_OUT -.sym 27742 rx_fifo.wr_addr_gray[1] -.sym 27747 rx_fifo.wr_addr[0] -.sym 27752 rx_fifo.wr_addr[1] -.sym 27753 rx_fifo.wr_addr[0] -.sym 27756 rx_fifo.wr_addr[2] -.sym 27757 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] -.sym 27760 rx_fifo.wr_addr[3] -.sym 27761 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] -.sym 27764 rx_fifo.wr_addr[4] -.sym 27765 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] -.sym 27768 rx_fifo.wr_addr[5] -.sym 27769 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] -.sym 27772 rx_fifo.wr_addr[6] -.sym 27773 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] -.sym 27776 rx_fifo.wr_addr[7] -.sym 27777 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] -.sym 27780 rx_fifo.wr_addr[8] -.sym 27781 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] -.sym 27784 rx_fifo.wr_addr[9] -.sym 27785 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[9] -.sym 27786 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 27791 rx_fifo.rd_addr_gray_wr_r[7] -.sym 27792 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 27793 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 27794 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 27800 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 27801 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 27802 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 27806 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 27814 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 27815 rx_fifo.rd_addr_gray_wr_r[8] -.sym 27816 rx_fifo.rd_addr_gray_wr_r[4] -.sym 27817 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 27826 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 27827 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 27828 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 27829 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 27840 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 27841 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 27842 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 27843 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 27844 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 27845 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 27847 rx_fifo.rd_addr_gray_wr_r[7] -.sym 27848 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 27849 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] -.sym 27850 rx_fifo.rd_addr_gray_wr[7] -.sym 27854 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 27855 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 27856 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 27857 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 27859 rx_fifo.rd_addr_gray_wr_r[4] -.sym 27860 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 27861 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] -.sym 27862 rx_fifo.rd_addr_gray[7] -.sym 27866 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 27867 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 27868 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 27869 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 27872 rx_fifo.rd_addr_gray_wr_r[5] -.sym 27873 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[4] -.sym 27875 rx_fifo.wr_addr[1] -.sym 27880 rx_fifo.wr_addr[2] -.sym 27881 rx_fifo.wr_addr[1] -.sym 27884 rx_fifo.wr_addr[3] -.sym 27885 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] -.sym 27888 rx_fifo.wr_addr[4] -.sym 27889 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] -.sym 27892 rx_fifo.wr_addr[5] -.sym 27893 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] -.sym 27896 rx_fifo.wr_addr[6] -.sym 27897 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] -.sym 27900 rx_fifo.wr_addr[7] -.sym 27901 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] -.sym 27904 rx_fifo.wr_addr[8] -.sym 27905 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] -.sym 27908 rx_fifo.wr_addr[9] -.sym 27909 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] -.sym 27910 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 27914 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 27922 rx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 27926 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 27933 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 27934 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[8] -.sym 27948 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27949 w_rx_09_fifo_data[1] -.sym 27978 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 27979 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 27980 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 27981 i_rst_b$SB_IO_IN -.sym 27997 w_lvds_rx_24_d1 -.sym 28002 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28003 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28004 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] -.sym 28005 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 28007 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28008 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28009 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28011 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28012 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28013 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28024 w_lvds_rx_09_d0 -.sym 28025 w_lvds_rx_09_d1 -.sym 28040 w_lvds_rx_09_d1 -.sym 28041 w_lvds_rx_09_d0 -.sym 28042 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 28043 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28044 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28045 w_lvds_rx_24_d0 -.sym 28071 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28072 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 28073 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 28075 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28076 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28077 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 28080 w_lvds_rx_24_d0 -.sym 28081 w_lvds_rx_24_d1 -.sym 28083 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28084 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 28085 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28086 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28087 w_lvds_rx_24_d1 -.sym 28088 w_lvds_rx_24_d0 -.sym 28089 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28094 w_lvds_rx_24_d0_SB_LUT4_I2_O[0] -.sym 28095 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 28096 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28097 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28106 w_lvds_rx_09_d1_SB_LUT4_I2_O[0] -.sym 28107 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28108 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 28109 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28111 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28112 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 28113 w_lvds_rx_09_d0 -.sym 28118 w_lvds_rx_09_d1 -.sym 28142 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28143 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28144 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28145 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 28194 rx_fifo.wr_addr_gray_rd[2] -.sym 28202 rx_fifo.wr_addr_gray_rd[3] -.sym 28206 rx_fifo.wr_addr_gray[0] -.sym 28210 rx_fifo.wr_addr_gray_rd[0] -.sym 28214 rx_fifo.wr_addr_gray[3] -.sym 28222 rx_fifo.wr_addr_gray[2] -.sym 28228 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 28229 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 28230 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 28234 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 28240 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 28241 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 28244 rx_fifo.wr_addr[0] -.sym 28245 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 28249 rx_fifo.wr_addr[0] -.sym 28254 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -.sym 28260 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 28261 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 28264 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 28265 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 28268 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 28269 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1] -.sym 28270 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 28274 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[7] -.sym 28280 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[3] -.sym 28281 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 28284 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 28285 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 28286 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0] -.sym 28292 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[4] -.sym 28293 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 28294 rx_fifo.wr_addr_gray[5] -.sym 28298 rx_fifo.wr_addr_gray[6] -.sym 28303 rx_fifo.rd_addr_gray_wr_r[5] -.sym 28304 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[5] -.sym 28305 rx_fifo.wr_addr_gray_SB_LUT4_I2_O[6] -.sym 28306 rx_fifo.rd_addr_gray_wr_r[1] -.sym 28307 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[1] -.sym 28308 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[2] -.sym 28309 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O_SB_LUT4_O_I3[3] -.sym 28310 rx_fifo.wr_addr_gray[4] -.sym 28314 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[0] -.sym 28315 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[1] -.sym 28316 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[2] -.sym 28317 rx_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_I2_O[3] -.sym 28318 rx_fifo.wr_addr_gray[7] -.sym 28322 rx_fifo.rd_addr_gray_wr[3] -.sym 28326 rx_fifo.rd_addr_gray[4] -.sym 28330 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[0] -.sym 28331 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 28332 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[2] -.sym 28333 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[3] -.sym 28334 rx_fifo.rd_addr_gray[1] -.sym 28338 rx_fifo.rd_addr_gray_wr[1] -.sym 28342 rx_fifo.rd_addr_gray[3] -.sym 28346 rx_fifo.rd_addr_gray_wr[4] -.sym 28350 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 28351 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28352 rx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] -.sym 28353 rx_fifo.rd_addr_gray_wr_r[3] -.sym 28356 rx_fifo.wr_addr[1] -.sym 28357 rx_fifo.rd_addr_gray_wr_r[1] -.sym 28358 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 28359 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 28360 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 28361 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 28363 rx_fifo.wr_addr[0] -.sym 28364 rx_fifo.wr_addr[1] -.sym 28365 rx_fifo.rd_addr_gray_wr_r[0] -.sym 28368 rx_fifo.mem_i.0.0_RDATA[0] -.sym 28369 rx_fifo.mem_i.0.0_RDATA[1] -.sym 28372 rx_fifo.rd_addr_gray_wr_r[3] -.sym 28373 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 28379 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] -.sym 28380 io_pmod[0]$SB_IO_IN -.sym 28381 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] -.sym 28384 rx_fifo.mem_i.0.0_RDATA_2[0] -.sym 28385 rx_fifo.mem_i.0.0_RDATA[1] -.sym 28386 rx_fifo.rd_addr_gray_wr_r[8] -.sym 28387 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I0_O[1] -.sym 28388 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[8] -.sym 28389 io_pmod_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[7] +.sym 27640 o_rx_h_tx_l_b$SB_IO_OUT +.sym 27643 o_tr_vc1_b$SB_IO_OUT +.sym 27724 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27725 w_rx_09_fifo_data[8] +.sym 27732 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27733 w_rx_09_fifo_data[11] +.sym 27746 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 27747 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 27748 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] +.sym 27749 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27758 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 27759 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 27760 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 27761 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27764 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 27765 i_rst_b$SB_IO_IN +.sym 27774 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 27775 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 27776 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] +.sym 27777 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27778 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 27779 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 27780 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27781 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 27793 o_iq_tx_clk_p$SB_IO_OUT +.sym 27794 w_rx_fifo_pulled_data[13] +.sym 27798 w_rx_fifo_pulled_data[2] +.sym 27803 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 27804 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 27805 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 27806 w_rx_fifo_pulled_data[15] +.sym 27812 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27813 w_rx_09_fifo_data[25] +.sym 27817 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] +.sym 27820 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27821 w_rx_09_fifo_data[21] +.sym 27824 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27825 w_rx_09_fifo_data[29] +.sym 27826 smi_ctrl_ins.r_fifo_pulled_data[13] +.sym 27827 smi_ctrl_ins.r_fifo_pulled_data[29] +.sym 27828 smi_ctrl_ins.int_cnt_rx[3] +.sym 27829 smi_ctrl_ins.int_cnt_rx[4] +.sym 27832 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27833 w_rx_09_fifo_data[23] +.sym 27836 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27837 w_rx_09_fifo_data[27] +.sym 27838 smi_ctrl_ins.r_fifo_pulled_data[15] +.sym 27839 smi_ctrl_ins.r_fifo_pulled_data[31] +.sym 27840 smi_ctrl_ins.int_cnt_rx[3] +.sym 27841 smi_ctrl_ins.int_cnt_rx[4] +.sym 27843 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] +.sym 27847 lvds_rx_09_inst.r_phase_count[1] +.sym 27848 $PACKER_VCC_NET +.sym 27849 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] +.sym 27850 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[2] +.sym 27852 $PACKER_VCC_NET +.sym 27853 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] +.sym 27869 w_lvds_rx_09_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] +.sym 27870 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[0] +.sym 27871 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[1] +.sym 27872 smi_ctrl_ins.int_cnt_rx[3] +.sym 27873 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I3[3] +.sym 27874 w_rx_fifo_pulled_data[23] +.sym 27878 smi_ctrl_ins.r_fifo_pulled_data[11] +.sym 27879 smi_ctrl_ins.r_fifo_pulled_data[27] +.sym 27880 smi_ctrl_ins.int_cnt_rx[3] +.sym 27881 smi_ctrl_ins.int_cnt_rx[4] +.sym 27886 smi_ctrl_ins.r_fifo_pulled_data[10] +.sym 27887 smi_ctrl_ins.r_fifo_pulled_data[26] +.sym 27888 smi_ctrl_ins.int_cnt_rx[3] +.sym 27889 smi_ctrl_ins.int_cnt_rx[4] +.sym 27891 smi_ctrl_ins.int_cnt_rx[3] +.sym 27892 smi_ctrl_ins.int_cnt_rx[4] +.sym 27893 i_rst_b$SB_IO_IN +.sym 27898 w_rx_fifo_pulled_data[11] +.sym 27902 w_rx_fifo_pulled_data[10] +.sym 27910 rx_fifo.rd_data_o[27] +.sym 27914 rx_fifo.rd_data_o[26] +.sym 27921 smi_ctrl_ins.r_fifo_pulled_data_SB_DFFNESR_Q_E +.sym 27929 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27930 rx_fifo.rd_data_o[25] +.sym 27935 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27936 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 27937 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 27950 w_lvds_rx_09_d0 +.sym 27960 w_lvds_rx_09_d0 +.sym 27961 w_lvds_rx_09_d1 +.sym 27962 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 27963 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27964 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 27965 w_lvds_rx_09_d1 +.sym 27970 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 27971 w_lvds_rx_09_d1 +.sym 27972 w_lvds_rx_09_d0 +.sym 27973 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 27977 w_lvds_tx_d0 +.sym 27995 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[0] +.sym 27996 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1[1] +.sym 27997 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 28001 w_lvds_tx_d1 +.sym 28002 w_lvds_rx_24_d0 +.sym 28020 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28021 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28026 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 28027 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 28028 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 28029 w_lvds_rx_24_d1 +.sym 28035 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 28040 rx_fifo.wr_addr[2] +.sym 28044 rx_fifo.wr_addr[3] +.sym 28045 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 28048 rx_fifo.wr_addr[4] +.sym 28049 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 28052 rx_fifo.wr_addr[5] +.sym 28053 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 28056 rx_fifo.wr_addr[6] +.sym 28057 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 28060 rx_fifo.wr_addr[7] +.sym 28061 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 28064 rx_fifo.wr_addr[8] +.sym 28065 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 28068 rx_fifo.wr_addr[9] +.sym 28069 rx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 28072 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 28073 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 28076 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 28077 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 28078 rx_fifo.rd_addr_gray_wr[4] +.sym 28082 rx_fifo.rd_addr_gray[5] +.sym 28088 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 28089 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 28090 rx_fifo.rd_addr_gray_wr[5] +.sym 28094 rx_fifo.rd_addr_gray[4] +.sym 28099 rx_fifo.wr_addr[0] +.sym 28104 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 28105 rx_fifo.wr_addr[0] +.sym 28108 rx_fifo.wr_addr[2] +.sym 28109 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 28112 rx_fifo.wr_addr[3] +.sym 28113 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 28116 rx_fifo.wr_addr[4] +.sym 28117 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 28120 rx_fifo.wr_addr[5] +.sym 28121 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 28124 rx_fifo.wr_addr[6] +.sym 28125 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 28128 rx_fifo.wr_addr[7] +.sym 28129 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 28132 rx_fifo.wr_addr[8] +.sym 28133 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 28136 rx_fifo.wr_addr[9] +.sym 28137 rx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 28140 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 28141 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 28145 rx_fifo.wr_addr[0] +.sym 28150 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 28214 w_rx_fifo_pulled_data[12] +.sym 28228 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28229 w_rx_09_fifo_data[15] +.sym 28232 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28233 w_rx_09_fifo_data[13] +.sym 28236 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28237 w_rx_09_fifo_data[14] +.sym 28240 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28241 w_rx_09_fifo_data[5] +.sym 28244 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28245 w_rx_09_fifo_data[10] +.sym 28248 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28249 w_rx_09_fifo_data[3] +.sym 28252 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28253 w_rx_09_fifo_data[12] +.sym 28256 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28257 w_rx_09_fifo_data[6] +.sym 28260 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28261 w_rx_09_fifo_data[4] +.sym 28264 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28265 w_rx_09_fifo_data[0] +.sym 28268 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28269 w_rx_09_fifo_data[1] +.sym 28272 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28273 w_rx_09_fifo_data[2] +.sym 28276 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28277 w_rx_09_fifo_data[17] +.sym 28280 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28281 w_rx_09_fifo_data[19] +.sym 28284 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28285 w_rx_09_fifo_data[9] +.sym 28288 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28289 w_rx_09_fifo_data[7] +.sym 28290 w_rx_fifo_pulled_data[7] +.sym 28295 w_rx_09_fifo_data[7] +.sym 28296 w_rx_24_fifo_data[7] +.sym 28297 channel +.sym 28298 smi_ctrl_ins.r_fifo_pulled_data[12] +.sym 28299 smi_ctrl_ins.r_fifo_pulled_data[28] +.sym 28300 smi_ctrl_ins.int_cnt_rx[3] +.sym 28301 smi_ctrl_ins.int_cnt_rx[4] +.sym 28302 w_rx_fifo_pulled_data[14] +.sym 28306 rx_fifo.rd_data_o[28] +.sym 28310 rx_fifo.rd_data_o[29] +.sym 28314 rx_fifo.rd_data_o[31] +.sym 28318 rx_fifo.rd_data_o[30] +.sym 28324 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28325 w_rx_09_fifo_data[22] +.sym 28326 smi_ctrl_ins.r_fifo_pulled_data[14] +.sym 28327 smi_ctrl_ins.r_fifo_pulled_data[30] +.sym 28328 smi_ctrl_ins.int_cnt_rx[3] +.sym 28329 smi_ctrl_ins.int_cnt_rx[4] +.sym 28332 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28333 w_rx_09_fifo_data[20] +.sym 28336 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28337 w_rx_09_fifo_data[26] +.sym 28340 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28341 w_rx_09_fifo_data[16] +.sym 28344 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28345 w_rx_09_fifo_data[24] +.sym 28348 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28349 w_rx_09_fifo_data[28] +.sym 28352 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28353 w_rx_09_fifo_data[18] +.sym 28360 smi_ctrl_ins.int_cnt_rx[3] +.sym 28361 smi_ctrl_ins.int_cnt_rx[4] +.sym 28367 w_rx_09_fifo_data[29] +.sym 28368 w_rx_24_fifo_data[29] +.sym 28369 channel +.sym 28370 smi_ctrl_ins.r_fifo_pulled_data[8] +.sym 28371 smi_ctrl_ins.r_fifo_pulled_data[24] +.sym 28372 smi_ctrl_ins.int_cnt_rx[3] +.sym 28373 smi_ctrl_ins.int_cnt_rx[4] +.sym 28377 smi_ctrl_ins.int_cnt_rx[3] +.sym 28379 lvds_rx_09_inst.o_fifo_data[31] +.sym 28380 w_rx_24_fifo_data[31] +.sym 28381 channel +.sym 28383 w_rx_09_fifo_data[18] +.sym 28384 w_rx_24_fifo_data[18] +.sym 28385 channel +.sym 28386 w_rx_fifo_pulled_data[19] +.sym 28390 w_rx_fifo_pulled_data[8] +.sym 28395 w_rx_09_fifo_data[19] +.sym 28396 w_rx_24_fifo_data[19] .sym 28397 channel -.sym 28401 rx_fifo.wr_addr_SB_DFFESR_Q_E -.sym 28404 io_pmod[0]$SB_IO_IN -.sym 28405 i_rst_b$SB_IO_IN -.sym 28410 rx_fifo.rd_addr_gray_wr[9] -.sym 28414 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 28418 w_rx_09_fifo_data[0] -.sym 28419 w_rx_24_fifo_data[0] -.sym 28420 channel -.sym 28421 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28422 rx_fifo.wr_addr[9] -.sym 28426 w_rx_09_fifo_data[3] -.sym 28427 w_rx_24_fifo_data[3] -.sym 28428 channel -.sym 28429 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28430 w_rx_09_fifo_data[2] -.sym 28431 w_rx_24_fifo_data[2] -.sym 28432 channel -.sym 28433 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28434 w_rx_09_fifo_data[1] -.sym 28435 w_rx_24_fifo_data[1] -.sym 28436 channel -.sym 28437 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28442 rx_fifo.wr_addr_gray[8] -.sym 28449 rx_fifo.wr_addr[9] -.sym 28452 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28453 w_rx_09_fifo_data[4] -.sym 28454 w_rx_09_fifo_data[5] -.sym 28455 w_rx_24_fifo_data[5] -.sym 28456 channel -.sym 28457 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28460 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28461 w_rx_09_fifo_data[2] -.sym 28464 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28465 w_rx_09_fifo_data[5] -.sym 28466 w_rx_09_fifo_data[6] -.sym 28467 w_rx_24_fifo_data[6] -.sym 28468 channel -.sym 28469 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28472 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28473 w_rx_09_fifo_data[0] -.sym 28476 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28477 w_rx_09_fifo_data[3] -.sym 28478 w_rx_09_fifo_data[4] -.sym 28479 w_rx_24_fifo_data[4] -.sym 28480 channel -.sym 28481 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28484 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28485 w_rx_24_fifo_data[4] -.sym 28488 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28489 w_rx_24_fifo_data[5] -.sym 28492 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28493 w_rx_24_fifo_data[0] -.sym 28500 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28501 w_rx_24_fifo_data[1] -.sym 28504 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28505 w_rx_24_fifo_data[3] -.sym 28508 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28509 w_rx_24_fifo_data[2] -.sym 28525 io_pmod[1]$SB_IO_IN -.sym 28528 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28529 w_rx_24_fifo_data[6] -.sym 28536 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28537 w_rx_24_fifo_data[8] -.sym 28551 w_rx_24_fifo_push -.sym 28552 w_rx_09_fifo_push -.sym 28553 channel -.sym 28556 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28557 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28566 io_pmod[3]$SB_IO_IN -.sym 28567 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28568 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28569 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 28574 w_rx_24_fifo_push -.sym 28575 w_rx_09_fifo_push -.sym 28576 channel -.sym 28577 io_pmod[3]$SB_IO_IN -.sym 28579 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 28583 lvds_rx_24_inst.r_phase_count[1] -.sym 28584 $PACKER_VCC_NET -.sym 28585 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 28586 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 28588 $PACKER_VCC_NET -.sym 28589 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 28591 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 28592 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 28593 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28594 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28595 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 28596 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 28597 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28601 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28602 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28603 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 28604 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28605 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28606 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] -.sym 28607 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] -.sym 28608 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 28609 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28629 w_lvds_rx_24_d0_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 28636 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28637 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28639 io_pmod[3]$SB_IO_IN -.sym 28640 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28641 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 28643 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 28647 lvds_rx_09_inst.r_phase_count[1] -.sym 28648 $PACKER_VCC_NET -.sym 28649 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[1] -.sym 28650 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 28652 $PACKER_VCC_NET -.sym 28653 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q_SB_LUT4_O_I3[2] -.sym 28657 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28658 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28659 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 28660 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[2] -.sym 28661 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28662 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 28663 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[1] -.sym 28664 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28665 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[0] -.sym 28669 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_Q[0] -.sym 28670 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] -.sym 28671 w_lvds_rx_09_d0_SB_LUT4_I3_I2[2] -.sym 28672 w_lvds_rx_09_d1_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_DFFER_E_2_Q[1] -.sym 28673 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28706 rx_fifo.rd_addr_gray[6] -.sym 28710 rx_fifo.rd_addr_gray[2] -.sym 28718 rx_fifo.rd_addr_gray_wr[2] -.sym 28722 rx_fifo.rd_addr_gray_wr[6] -.sym 28726 rx_fifo.rd_addr_gray_wr[5] -.sym 28734 rx_fifo.rd_addr_gray[5] -.sym 28738 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 28742 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 28750 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] -.sym 28751 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 28752 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 28753 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 28756 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 28757 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 28760 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 28761 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 28762 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 28766 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 28776 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 28777 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 28780 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] -.sym 28781 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 28782 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 28783 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 28784 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] -.sym 28785 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 28786 rx_fifo.wr_addr_gray_rd[1] -.sym 28790 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] -.sym 28791 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] -.sym 28792 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2] -.sym 28793 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] -.sym 28796 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 28797 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 28798 rx_fifo.wr_addr_gray_rd[4] -.sym 28803 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] -.sym 28804 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 28805 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 28806 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 28807 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 28808 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 28809 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 28810 rx_fifo.wr_addr_gray_rd[5] -.sym 28815 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 28816 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 28817 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 28818 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] -.sym 28819 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[0] -.sym 28820 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2] -.sym 28821 io_pmod[1]$SB_IO_IN -.sym 28822 rx_fifo.wr_addr_gray_rd[6] -.sym 28826 rx_fifo.wr_addr_gray_rd[7] -.sym 28830 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[0] -.sym 28831 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 28832 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 28833 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[3] -.sym 28834 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] -.sym 28841 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 28844 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 28845 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 28848 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 28849 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 28850 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 28854 rx_fifo.wr_addr_gray_rd_r[8] -.sym 28855 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 28856 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 28857 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] -.sym 28860 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 28861 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 28863 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3] -.sym 28864 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 28865 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 28866 w_rx_09_fifo_data[18] -.sym 28867 w_rx_24_fifo_data[18] -.sym 28868 channel -.sym 28869 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28870 rx_fifo.wr_addr_gray_rd[8] -.sym 28874 w_rx_09_fifo_data[19] -.sym 28875 w_rx_24_fifo_data[19] -.sym 28876 channel -.sym 28877 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28881 rx_fifo.rd_addr_SB_DFFESR_Q_E -.sym 28886 rx_fifo.wr_addr_gray_rd[9] -.sym 28900 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28901 w_rx_24_fifo_data[18] -.sym 28904 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28905 w_rx_24_fifo_data[15] -.sym 28908 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28909 w_rx_24_fifo_data[27] -.sym 28910 w_rx_09_fifo_data[17] -.sym 28911 w_rx_24_fifo_data[17] -.sym 28912 channel -.sym 28913 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28914 w_rx_09_fifo_data[16] -.sym 28915 w_rx_24_fifo_data[16] -.sym 28916 channel -.sym 28917 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28920 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28921 w_rx_24_fifo_data[16] -.sym 28924 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28925 w_rx_24_fifo_data[17] -.sym 28928 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 28929 w_rx_24_fifo_data[14] -.sym 28940 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28941 w_rx_09_fifo_data[16] -.sym 28952 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28953 w_rx_09_fifo_data[15] -.sym 28956 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 28957 w_rx_09_fifo_data[17] -.sym 28964 rx_fifo.mem_q.0.0_RDATA_3[0] -.sym 28965 rx_fifo.mem_i.0.0_RDATA[1] -.sym 28972 rx_fifo.mem_i.0.0_RDATA[1] -.sym 28973 rx_fifo.mem_q.0.1_RDATA[1] -.sym 28974 w_rx_09_fifo_data[7] -.sym 28975 w_rx_24_fifo_data[7] -.sym 28976 channel -.sym 28977 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 28980 rx_fifo.mem_i.0.0_RDATA[1] -.sym 28981 rx_fifo.mem_q.0.1_RDATA_2[1] -.sym 28984 rx_fifo.mem_i.0.0_RDATA[1] -.sym 28985 rx_fifo.mem_q.0.1_RDATA_1[1] -.sym 28986 w_rx_09_fifo_data[15] -.sym 28987 w_rx_24_fifo_data[15] -.sym 28988 channel -.sym 28989 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29008 rx_fifo.mem_q.0.2_RDATA_2[0] -.sym 29009 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29012 rx_fifo.mem_q.0.2_RDATA_3[0] -.sym 29013 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29024 rx_fifo.mem_q.0.2_RDATA_1[0] -.sym 29025 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29028 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29029 w_rx_09_fifo_data[7] -.sym 29030 w_rx_09_fifo_data[8] -.sym 29031 w_rx_24_fifo_data[8] -.sym 29032 channel -.sym 29033 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29034 w_rx_09_fifo_data[9] -.sym 29035 w_rx_24_fifo_data[9] -.sym 29036 channel -.sym 29037 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29038 w_rx_09_fifo_data[10] -.sym 29039 w_rx_24_fifo_data[10] -.sym 29040 channel -.sym 29041 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29044 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29045 w_rx_09_fifo_data[6] -.sym 29048 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29049 w_rx_09_fifo_data[9] -.sym 29050 w_rx_09_fifo_data[11] -.sym 29051 w_rx_24_fifo_data[11] -.sym 29052 channel -.sym 29053 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29060 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29061 w_rx_24_fifo_data[7] -.sym 29064 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29065 w_rx_24_fifo_data[13] -.sym 29068 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29069 w_rx_24_fifo_data[9] -.sym 29076 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29077 w_rx_24_fifo_data[11] -.sym 29080 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29081 w_rx_24_fifo_data[10] -.sym 29251 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] -.sym 29252 rx_fifo.rd_addr[2] -.sym 29253 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 29254 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 29261 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 29263 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 29264 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[3] -.sym 29265 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 29266 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] -.sym 29270 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 29276 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 29277 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 29278 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[4] -.sym 29283 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 29288 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 29289 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 29292 rx_fifo.rd_addr[2] -.sym 29293 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] -.sym 29296 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 29297 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] -.sym 29300 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 29301 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] -.sym 29304 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[1] -.sym 29305 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] -.sym 29308 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_1_I3[2] -.sym 29309 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] -.sym 29312 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 29313 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] -.sym 29316 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 29317 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] -.sym 29320 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 29321 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] -.sym 29322 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] -.sym 29323 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] -.sym 29324 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] -.sym 29325 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] -.sym 29326 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 29330 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] -.sym 29334 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] -.sym 29338 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 29339 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 29340 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 29341 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[3] -.sym 29342 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] -.sym 29348 smi_ctrl_ins.int_cnt[3] -.sym 29349 smi_ctrl_ins.int_cnt[4] -.sym 29350 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 29351 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 29352 rx_fifo.wr_addr_gray_rd_r[8] -.sym 29353 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 29357 smi_ctrl_ins.int_cnt[3] -.sym 29359 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 29360 rx_fifo.rd_addr[2] -.sym 29361 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29364 io_pmod[1]$SB_IO_IN -.sym 29365 i_rst_b$SB_IO_IN -.sym 29370 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[0] -.sym 29371 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[1] -.sym 29372 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_2_I0[2] -.sym 29373 io_pmod[4]$SB_IO_IN -.sym 29375 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 29376 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 29377 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 29378 rx_fifo.rd_addr_gray[8] -.sym 29384 i_rst_b$SB_IO_IN -.sym 29385 w_debug_smi_test -.sym 29390 rx_fifo.rd_addr_gray_wr[0] -.sym 29394 rx_fifo.rd_addr_gray_wr[8] -.sym 29402 rx_fifo.rd_addr_gray[0] -.sym 29422 $PACKER_VCC_NET -.sym 29444 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29445 w_rx_09_fifo_data[28] -.sym 29448 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29449 w_rx_09_fifo_data[26] -.sym 29452 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29453 w_rx_09_fifo_data[24] -.sym 29456 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29457 w_rx_09_fifo_data[27] -.sym 29460 w_debug_fifo_push -.sym 29461 io_pmod[0]$SB_IO_IN -.sym 29465 w_rx_24_fifo_data[29] -.sym 29468 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29469 w_rx_09_fifo_data[14] -.sym 29472 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29473 w_rx_09_fifo_data[29] -.sym 29476 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29477 w_rx_24_fifo_data[12] -.sym 29478 w_rx_09_fifo_data[28] -.sym 29479 w_rx_24_fifo_data[28] -.sym 29480 channel -.sym 29481 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29482 w_rx_09_fifo_data[30] -.sym 29483 w_rx_24_fifo_data[30] -.sym 29484 channel -.sym 29485 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29488 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29489 w_rx_24_fifo_data[26] -.sym 29490 smi_ctrl_ins.r_fifo_pulled_data[0] -.sym 29491 smi_ctrl_ins.r_fifo_pulled_data[8] -.sym 29492 smi_ctrl_ins.int_cnt[4] -.sym 29493 smi_ctrl_ins.int_cnt[3] -.sym 29496 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29497 w_rx_24_fifo_data[28] -.sym 29500 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 29501 w_rx_24_fifo_data[29] -.sym 29502 lvds_rx_09_inst.o_fifo_data[31] -.sym 29503 w_rx_24_fifo_data[31] -.sym 29504 channel -.sym 29505 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29508 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29509 rx_fifo.mem_q.0.3_RDATA_3[1] -.sym 29518 smi_ctrl_ins.r_fifo_pulled_data[5] -.sym 29519 smi_ctrl_ins.r_fifo_pulled_data[13] -.sym 29520 smi_ctrl_ins.int_cnt[4] -.sym 29521 smi_ctrl_ins.int_cnt[3] -.sym 29528 rx_fifo.mem_q.0.3_RDATA_1[0] -.sym 29529 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29530 smi_ctrl_ins.r_fifo_pulled_data[1] -.sym 29531 smi_ctrl_ins.r_fifo_pulled_data[9] -.sym 29532 smi_ctrl_ins.int_cnt[4] -.sym 29533 smi_ctrl_ins.int_cnt[3] -.sym 29538 smi_ctrl_ins.r_fifo_pulled_data[2] -.sym 29539 smi_ctrl_ins.r_fifo_pulled_data[10] -.sym 29540 smi_ctrl_ins.int_cnt[4] -.sym 29541 smi_ctrl_ins.int_cnt[3] -.sym 29548 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29549 w_rx_09_fifo_data[10] -.sym 29552 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29553 w_rx_09_fifo_data[13] -.sym 29556 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29557 w_rx_09_fifo_data[12] -.sym 29564 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29565 w_rx_09_fifo_data[11] -.sym 29568 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29569 w_rx_09_fifo_data[8] -.sym 29576 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29577 rx_fifo.mem_q.0.0_RDATA_1[1] -.sym 29580 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29581 rx_fifo.mem_q.0.1_RDATA_3[1] -.sym 29592 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29593 rx_fifo.mem_q.0.0_RDATA_2[1] -.sym 29600 rx_fifo.mem_q.0.2_RDATA[0] -.sym 29601 rx_fifo.mem_i.0.0_RDATA[1] -.sym 29766 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 29794 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[0] -.sym 29795 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[1] -.sym 29796 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[2] -.sym 29797 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I3[3] -.sym 29798 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] -.sym 29799 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] -.sym 29800 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] -.sym 29801 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] -.sym 29802 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] -.sym 29803 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] -.sym 29804 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] -.sym 29805 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 29808 w_debug_smi_test -.sym 29809 i_rst_b$SB_IO_IN -.sym 29810 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] -.sym 29811 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] -.sym 29812 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[2] -.sym 29813 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[3] -.sym 29823 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29824 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] -.sym 29825 rx_fifo.rd_addr[2] -.sym 29826 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] -.sym 29827 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] -.sym 29828 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 29829 w_debug_smi_test -.sym 29837 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_E -.sym 29839 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[1] -.sym 29840 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[2] -.sym 29841 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0_SB_LUT4_O_3_I3[0] -.sym 29842 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] -.sym 29843 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] -.sym 29844 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 29845 w_debug_smi_test -.sym 29846 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] -.sym 29847 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] -.sym 29848 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 29849 w_debug_smi_test -.sym 29860 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29861 w_rx_09_fifo_data[22] -.sym 29864 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29865 w_rx_09_fifo_data[25] -.sym 29868 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29869 w_rx_09_fifo_data[18] -.sym 29870 smi_ctrl_ins.r_fifo_pulled_data[7] -.sym 29871 smi_ctrl_ins.r_fifo_pulled_data[15] -.sym 29872 smi_ctrl_ins.int_cnt[4] -.sym 29873 smi_ctrl_ins.int_cnt[3] -.sym 29876 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29877 w_rx_09_fifo_data[19] -.sym 29884 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 29885 w_rx_09_fifo_data[23] -.sym 29890 smi_ctrl_ins.r_fifo_pulled_data[4] -.sym 29891 smi_ctrl_ins.r_fifo_pulled_data[12] -.sym 29892 smi_ctrl_ins.int_cnt[4] -.sym 29893 smi_ctrl_ins.int_cnt[3] -.sym 29902 smi_ctrl_ins.r_fifo_pulled_data[6] -.sym 29903 smi_ctrl_ins.r_fifo_pulled_data[14] -.sym 29904 smi_ctrl_ins.int_cnt[4] -.sym 29905 smi_ctrl_ins.int_cnt[3] -.sym 29906 smi_ctrl_ins.r_fifo_pulled_data[18] -.sym 29907 smi_ctrl_ins.r_fifo_pulled_data[26] -.sym 29908 smi_ctrl_ins.int_cnt[3] -.sym 29909 smi_ctrl_ins.int_cnt[4] -.sym 29910 w_rx_data[2] -.sym 29914 smi_ctrl_ins.r_fifo_pulled_data[3] -.sym 29915 smi_ctrl_ins.r_fifo_pulled_data[11] -.sym 29916 smi_ctrl_ins.int_cnt[4] -.sym 29917 smi_ctrl_ins.int_cnt[3] -.sym 29918 smi_ctrl_ins.int_cnt[4] -.sym 29919 w_debug_smi_test -.sym 29920 smi_ctrl_ins.int_cnt[3] -.sym 29921 i_rst_b$SB_IO_IN -.sym 29922 w_rx_09_fifo_data[24] -.sym 29923 w_rx_24_fifo_data[24] -.sym 29924 channel -.sym 29925 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29926 w_rx_09_fifo_data[27] -.sym 29927 w_rx_24_fifo_data[27] -.sym 29928 channel -.sym 29929 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29930 w_rx_09_fifo_data[26] -.sym 29931 w_rx_24_fifo_data[26] -.sym 29932 channel -.sym 29933 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29934 w_rx_data[1] -.sym 29942 w_rx_data[2] -.sym 29946 w_rx_09_fifo_data[25] -.sym 29947 w_rx_24_fifo_data[25] -.sym 29948 channel -.sym 29949 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 29950 w_rx_data[0] -.sym 29954 spi_if_ins.w_rx_data[4] -.sym 29966 spi_if_ins.w_rx_data[3] -.sym 29978 spi_if_ins.w_rx_data[1] -.sym 29986 i_button_SB_LUT4_I0_I1[2] -.sym 29997 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 29998 w_rx_09_fifo_data[12] -.sym 29999 w_rx_24_fifo_data[12] -.sym 30000 channel -.sym 30001 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 30002 w_rx_09_fifo_data[14] -.sym 30003 w_rx_24_fifo_data[14] -.sym 30004 channel -.sym 30005 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 30006 w_rx_09_fifo_data[29] -.sym 30007 w_rx_24_fifo_data[29] -.sym 30008 channel -.sym 30009 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 30022 w_rx_data[2] -.sym 30029 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 30030 w_rx_data[4] -.sym 30034 w_rx_data[1] -.sym 30042 w_rx_data[0] -.sym 30046 w_rx_data[3] -.sym 30052 io_ctrl_ins.debug_mode[0] -.sym 30053 io_ctrl_ins.debug_mode[1] -.sym 30058 channel -.sym 30072 io_ctrl_ins.debug_mode[1] -.sym 30073 io_ctrl_ins.debug_mode_SB_LUT4_I0_O[1] -.sym 30074 io_pmod[4]$SB_IO_IN -.sym 30078 io_ctrl_ins.debug_mode[0] -.sym 30079 i_button_SB_LUT4_I0_I2[3] -.sym 30080 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30081 i_rst_b$SB_IO_IN -.sym 30082 w_rx_data[2] -.sym 30086 w_rx_data[0] -.sym 30090 w_rx_data[4] -.sym 30094 w_rx_data[1] -.sym 30098 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30099 io_ctrl_ins.rf_mode[0] -.sym 30100 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30101 i_button_SB_LUT4_I0_I2[3] -.sym 30104 io_ctrl_ins.rf_mode[0] -.sym 30105 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30110 w_rx_data[3] -.sym 30114 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] -.sym 30115 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30116 i_button_SB_LUT4_I0_I2[3] -.sym 30117 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30118 io_ctrl_ins.rf_pin_state[0] -.sym 30119 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30120 i_button_SB_LUT4_I0_I2[3] -.sym 30121 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30123 io_ctrl_ins.rf_pin_state[7] -.sym 30124 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30125 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 30127 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30128 io_ctrl_ins.rf_pin_state[6] -.sym 30129 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 30131 io_ctrl_ins.rf_pin_state[1] -.sym 30132 i_button_SB_LUT4_I0_I2[3] -.sym 30133 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30134 i_button_SB_LUT4_I0_I2[3] -.sym 30135 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30136 io_ctrl_ins.rf_pin_state[2] -.sym 30137 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30138 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 30139 i_button_SB_LUT4_I0_I2[3] -.sym 30140 io_ctrl_ins.rf_pin_state[4] -.sym 30141 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30142 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0] -.sym 30143 i_button_SB_LUT4_I0_I2[3] -.sym 30144 io_ctrl_ins.rf_pin_state[5] -.sym 30145 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] -.sym 30225 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 30232 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] -.sym 30233 i_rst_b$SB_IO_IN -.sym 30261 i_rst_b$SB_IO_IN -.sym 30274 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 30280 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 30281 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 30284 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 30285 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 30288 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 30289 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 30290 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 30300 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 30301 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 30304 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 30305 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 30306 spi_if_ins.spi.r_rx_byte[0] -.sym 30310 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 30311 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 30312 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 30313 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] -.sym 30314 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 30315 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 30316 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] -.sym 30317 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 30318 spi_if_ins.spi.r_rx_byte[2] -.sym 30326 spi_if_ins.spi.r_rx_byte[1] -.sym 30333 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] -.sym 30336 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[0] -.sym 30337 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2[1] -.sym 30338 spi_if_ins.spi.r_rx_byte[5] -.sym 30346 spi_if_ins.spi.r_rx_byte[4] -.sym 30350 spi_if_ins.spi.r_rx_byte[7] -.sym 30359 w_debug_smi_test -.sym 30360 smi_ctrl_ins.r_smi_test_count_SB_DFFNESS_Q_D_SB_LUT4_O_I2[1] -.sym 30361 i_rst_b$SB_IO_IN -.sym 30362 spi_if_ins.spi.r_rx_byte[6] -.sym 30366 spi_if_ins.spi.r_rx_byte[3] -.sym 30370 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] -.sym 30371 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] -.sym 30372 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] -.sym 30373 w_debug_smi_test -.sym 30374 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] -.sym 30375 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] -.sym 30376 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] -.sym 30377 w_debug_smi_test -.sym 30378 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 30379 smi_ctrl_ins.r_fifo_pulled_data[31] -.sym 30380 smi_ctrl_ins.int_cnt[3] -.sym 30381 smi_ctrl_ins.int_cnt[4] -.sym 30382 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] -.sym 30383 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] -.sym 30384 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] -.sym 30385 w_debug_smi_test -.sym 30386 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] -.sym 30387 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] -.sym 30388 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] -.sym 30389 w_debug_smi_test -.sym 30398 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] -.sym 30399 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] -.sym 30400 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] -.sym 30401 w_debug_smi_test -.sym 30404 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 30405 w_rx_24_fifo_data[21] -.sym 30408 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 30409 w_rx_24_fifo_data[22] -.sym 30412 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 30413 w_rx_24_fifo_data[25] -.sym 30416 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 30417 w_rx_24_fifo_data[20] -.sym 30420 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 30421 w_rx_24_fifo_data[23] -.sym 30424 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 30425 w_rx_24_fifo_data[24] -.sym 30428 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] -.sym 30429 w_rx_24_fifo_data[19] -.sym 30430 smi_ctrl_ins.r_fifo_pulled_data[19] -.sym 30431 smi_ctrl_ins.r_fifo_pulled_data[27] -.sym 30432 smi_ctrl_ins.int_cnt[3] -.sym 30433 smi_ctrl_ins.int_cnt[4] -.sym 30434 spi_if_ins.w_rx_data[2] -.sym 30438 spi_if_ins.w_rx_data[3] -.sym 30446 spi_if_ins.w_rx_data[0] -.sym 30450 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 30454 spi_if_ins.w_rx_data[1] -.sym 30458 spi_if_ins.w_rx_data[4] -.sym 30465 i_rst_b$SB_IO_IN -.sym 30466 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 30467 w_ioc[4] -.sym 30468 w_ioc[3] -.sym 30469 w_ioc[2] -.sym 30471 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 30472 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 30473 w_cs[0] -.sym 30475 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 30476 w_cs[0] -.sym 30477 w_fetch -.sym 30481 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E -.sym 30484 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 30485 w_ioc[0] -.sym 30486 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 30495 w_ioc[2] -.sym 30496 w_ioc[4] -.sym 30497 w_ioc[3] -.sym 30500 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 30501 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 30508 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 30509 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 30510 io_ctrl_ins.o_pmod[2] -.sym 30511 o_shdn_tx_lna$SB_IO_OUT -.sym 30512 w_ioc[0] -.sym 30513 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 30514 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 30515 i_rst_b$SB_IO_IN -.sym 30516 w_cs[2] -.sym 30517 w_fetch -.sym 30523 w_ioc[0] -.sym 30524 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 30525 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 30527 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[0] -.sym 30528 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 30529 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 30530 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] -.sym 30531 i_button_SB_LUT4_I0_I1[2] -.sym 30532 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] -.sym 30533 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] -.sym 30534 i_button_SB_LUT4_I0_I1[0] -.sym 30535 o_led0$SB_IO_OUT -.sym 30536 i_button_SB_LUT4_I0_I2[2] -.sym 30537 io_ctrl_ins.debug_mode[0] -.sym 30538 io_ctrl_ins.debug_mode[1] -.sym 30539 i_button_SB_LUT4_I0_I2[2] -.sym 30540 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] -.sym 30541 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] -.sym 30543 i_button_SB_LUT4_I0_I2[2] -.sym 30544 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 30545 w_cs[1] -.sym 30547 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 30548 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 30549 w_ioc[0] -.sym 30550 i_button_SB_LUT4_I0_I1[2] -.sym 30551 io_ctrl_ins.pmod_dir_state[2] -.sym 30552 i_button_SB_LUT4_I0_I2[2] -.sym 30553 io_ctrl_ins.rf_mode[0] -.sym 30557 i_button_SB_LUT4_I0_I1[2] -.sym 30558 i_button_SB_LUT4_I0_I1[0] -.sym 30559 o_led1$SB_IO_OUT -.sym 30560 i_button_SB_LUT4_I0_I1[2] -.sym 30561 i_button_SB_LUT4_I0_I1[3] -.sym 30562 w_rx_data[1] -.sym 30566 w_rx_data[3] -.sym 30573 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_1_O -.sym 30574 w_rx_data[0] -.sym 30578 w_rx_data[4] -.sym 30582 i_button_SB_LUT4_I0_I1[2] -.sym 30583 i_button_SB_LUT4_I0_I2[1] -.sym 30584 i_button_SB_LUT4_I0_I2[2] -.sym 30585 i_button_SB_LUT4_I0_I2[3] -.sym 30586 w_rx_data[2] -.sym 30590 i_button_SB_LUT4_I0_I1[2] -.sym 30591 io_ctrl_ins.pmod_dir_state[4] -.sym 30592 i_button_SB_LUT4_I0_I2[2] -.sym 30593 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] -.sym 30594 w_rx_data[0] -.sym 30598 w_rx_data[1] -.sym 30602 w_rx_data[3] -.sym 30606 io_ctrl_ins.o_pmod[0] -.sym 30607 io_ctrl_ins.mixer_en_state -.sym 30608 w_ioc[0] -.sym 30609 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 30612 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 30613 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[1] -.sym 30614 io_ctrl_ins.o_pmod[3] -.sym 30615 o_tr_vc2$SB_IO_OUT -.sym 30616 w_ioc[0] -.sym 30617 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 30619 w_ioc[0] -.sym 30620 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 30621 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 30622 w_rx_data[4] -.sym 30630 w_rx_data[5] -.sym 30637 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O -.sym 30638 w_rx_data[7] -.sym 30642 w_rx_data[6] -.sym 30646 io_ctrl_ins.o_pmod[1] -.sym 30647 o_shdn_rx_lna$SB_IO_OUT -.sym 30648 w_ioc[0] -.sym 30649 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 30758 spi_if_ins.spi.r_rx_done -.sym 30764 i_rst_b$SB_IO_IN -.sym 30765 i_smi_soe_se$SB_IO_IN -.sym 30786 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 30790 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 30798 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 30802 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 30806 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 30810 i_mosi$SB_IO_IN -.sym 30814 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 30818 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 30822 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 30826 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 30830 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 30834 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 30838 i_mosi$SB_IO_IN -.sym 30842 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 30846 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 30856 spi_if_ins.spi.r3_rx_done -.sym 30857 spi_if_ins.spi.r2_rx_done -.sym 30861 smi_ctrl_ins.r_fifo_pulled_data[23] -.sym 30865 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 30870 spi_if_ins.spi.r2_rx_done -.sym 30878 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 30886 smi_ctrl_ins.r_fifo_pulled_data[21] -.sym 30887 smi_ctrl_ins.r_fifo_pulled_data[29] -.sym 30888 smi_ctrl_ins.int_cnt[3] -.sym 30889 smi_ctrl_ins.int_cnt[4] -.sym 30890 smi_ctrl_ins.r_fifo_pulled_data[17] -.sym 30891 smi_ctrl_ins.r_fifo_pulled_data[25] -.sym 30892 smi_ctrl_ins.int_cnt[3] -.sym 30893 smi_ctrl_ins.int_cnt[4] -.sym 30896 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 30897 w_rx_09_fifo_data[20] -.sym 30900 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] -.sym 30901 w_rx_09_fifo_data[21] -.sym 30902 smi_ctrl_ins.r_fifo_pulled_data[22] -.sym 30903 smi_ctrl_ins.r_fifo_pulled_data[30] -.sym 30904 smi_ctrl_ins.int_cnt[3] -.sym 30905 smi_ctrl_ins.int_cnt[4] -.sym 30906 smi_ctrl_ins.r_fifo_pulled_data[16] -.sym 30907 smi_ctrl_ins.r_fifo_pulled_data[24] -.sym 30908 smi_ctrl_ins.int_cnt[3] -.sym 30909 smi_ctrl_ins.int_cnt[4] -.sym 30914 spi_if_ins.w_rx_data[6] -.sym 30918 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 30919 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30920 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 30921 i_rst_b$SB_IO_IN -.sym 30922 spi_if_ins.w_rx_data[5] -.sym 30930 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 30934 spi_if_ins.w_rx_data[0] -.sym 30938 spi_if_ins.w_rx_data[2] -.sym 30943 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 30944 i_rst_b$SB_IO_IN -.sym 30945 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 30950 spi_if_ins.r_tx_byte[1] -.sym 30954 spi_if_ins.r_tx_byte[6] -.sym 30961 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 30965 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 30972 spi_if_ins.w_rx_data[5] -.sym 30973 spi_if_ins.w_rx_data[6] -.sym 30983 w_ioc[0] -.sym 30984 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 30985 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 30986 i_button_SB_LUT4_I0_I1[0] -.sym 30987 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 30988 i_rst_b$SB_IO_IN -.sym 30989 w_cs[2] -.sym 30992 w_fetch -.sym 30993 w_load -.sym 30998 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 31011 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 31012 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 31013 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 31018 w_tx_data_smi[0] -.sym 31019 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 31020 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 31021 w_tx_data_io[0] -.sym 31034 w_tx_data_sys[0] -.sym 31035 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 31036 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 31037 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 31039 i_rst_b$SB_IO_IN -.sym 31040 w_cs[1] -.sym 31041 w_fetch -.sym 31049 w_tx_data_io[2] -.sym 31053 io_ctrl_ins.led1_state_SB_DFFER_Q_E -.sym 31057 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 31062 w_rx_data[0] -.sym 31066 w_rx_data[1] -.sym 31071 i_button_SB_LUT4_I0_I1[0] -.sym 31072 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 31073 w_cs[1] -.sym 31075 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 31076 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 31077 w_ioc[0] -.sym 31079 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 31080 i_rst_b$SB_IO_IN -.sym 31081 w_cs[1] -.sym 31082 i_config[0]$SB_IO_IN -.sym 31083 i_button_SB_LUT4_I0_I1[0] -.sym 31084 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] -.sym 31085 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] -.sym 31087 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 31088 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[1] -.sym 31089 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 31090 i_config[1]$SB_IO_IN -.sym 31091 i_button_SB_LUT4_I0_I1[0] -.sym 31092 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] -.sym 31093 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] -.sym 31096 i_button_SB_LUT4_I0_I1[2] -.sym 31097 sys_ctrl_ins.debug_smi_test_SB_DFFER_Q_E_SB_LUT4_O_I1[0] -.sym 31100 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 31101 i_button_SB_LUT4_I0_I2[2] -.sym 31106 w_rx_data[7] -.sym 31110 w_rx_data[5] -.sym 31114 i_config[2]$SB_IO_IN -.sym 31115 i_button_SB_LUT4_I0_I1[0] -.sym 31116 i_button_SB_LUT4_I0_I1[2] -.sym 31117 io_ctrl_ins.pmod_dir_state[5] -.sym 31118 i_button$SB_IO_IN -.sym 31119 i_button_SB_LUT4_I0_I1[0] -.sym 31120 i_button_SB_LUT4_I0_I1[2] -.sym 31121 io_ctrl_ins.pmod_dir_state[7] -.sym 31122 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 31123 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[0] -.sym 31124 w_ioc[0] -.sym 31125 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[3] -.sym 31126 w_rx_data[6] -.sym 31130 io_ctrl_ins.o_pmod[4] -.sym 31131 o_tr_vc1_b$SB_IO_OUT -.sym 31132 w_ioc[0] -.sym 31133 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 31134 i_config[3]$SB_IO_IN -.sym 31135 i_button_SB_LUT4_I0_I1[0] -.sym 31136 i_button_SB_LUT4_I0_I1[2] -.sym 31137 io_ctrl_ins.pmod_dir_state[6] -.sym 31138 w_rx_data[6] -.sym 31142 w_rx_data[7] -.sym 31146 w_rx_data[5] -.sym 31154 io_ctrl_ins.o_pmod[6] -.sym 31155 o_rx_h_tx_l_b$SB_IO_OUT -.sym 31156 w_ioc[0] -.sym 31157 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 31158 io_ctrl_ins.o_pmod[7] -.sym 31159 o_rx_h_tx_l$SB_IO_OUT -.sym 31160 w_ioc[0] -.sym 31161 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 31166 io_ctrl_ins.o_pmod[5] -.sym 31167 o_tr_vc1$SB_IO_OUT -.sym 31168 w_ioc[0] -.sym 31169 i_button_SB_LUT4_I0_I1_SB_LUT4_O_I3[2] -.sym 31281 i_ss$SB_IO_IN -.sym 31294 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 31299 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31304 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31308 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31309 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 31311 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31312 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31313 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31317 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31320 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31321 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31322 i_ss$SB_IO_IN -.sym 31323 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31324 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31325 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31356 i_ss$SB_IO_IN -.sym 31357 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 31369 rx_fifo.wr_addr[4] -.sym 31371 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31372 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31373 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 31380 rx_fifo.mem_i.0.1_RDATA[0] -.sym 31381 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31386 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 31387 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] -.sym 31388 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 31389 i_rst_b$SB_IO_IN -.sym 31394 w_rx_09_fifo_data[23] -.sym 31395 w_rx_24_fifo_data[23] -.sym 31396 channel -.sym 31397 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 31400 rx_fifo.mem_i.0.1_RDATA_2[0] -.sym 31401 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31402 w_rx_09_fifo_data[20] -.sym 31403 w_rx_24_fifo_data[20] -.sym 31404 channel -.sym 31405 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 31406 w_rx_09_fifo_data[22] -.sym 31407 w_rx_24_fifo_data[22] -.sym 31408 channel -.sym 31409 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 31410 w_rx_09_fifo_data[21] -.sym 31411 w_rx_24_fifo_data[21] -.sym 31412 channel -.sym 31413 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 31416 rx_fifo.mem_i.0.0_RDATA_3[0] -.sym 31417 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31420 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31421 rx_fifo.mem_i.0.1_RDATA_1[1] -.sym 31424 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31425 rx_fifo.mem_i.0.0_RDATA_1[1] -.sym 31428 rx_fifo.mem_q.0.3_RDATA_2[0] -.sym 31429 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31430 smi_ctrl_ins.r_fifo_pulled_data[20] -.sym 31431 smi_ctrl_ins.r_fifo_pulled_data[28] -.sym 31432 smi_ctrl_ins.int_cnt[3] -.sym 31433 smi_ctrl_ins.int_cnt[4] -.sym 31436 rx_fifo.mem_q.0.3_RDATA[0] -.sym 31437 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31440 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31441 rx_fifo.mem_q.0.0_RDATA[1] -.sym 31444 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31445 rx_fifo.mem_i.0.1_RDATA_3[1] -.sym 31448 rx_fifo.mem_i.0.2_RDATA_1[0] -.sym 31449 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31452 rx_fifo.mem_i.0.3_RDATA_1[0] -.sym 31453 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31456 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31457 rx_fifo.mem_i.0.2_RDATA_2[1] -.sym 31462 i_sck$SB_IO_IN -.sym 31466 spi_if_ins.spi.SCKr[0] -.sym 31471 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 31472 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 31473 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 31474 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 31475 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31476 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31477 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 31479 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] -.sym 31480 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 31481 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 31482 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] -.sym 31489 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 31491 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31495 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 31496 $PACKER_VCC_NET -.sym 31499 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31500 $PACKER_VCC_NET -.sym 31501 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 31503 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 31504 $PACKER_VCC_NET -.sym 31505 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31509 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31510 spi_if_ins.spi.r_tx_byte[2] -.sym 31511 spi_if_ins.spi.r_tx_byte[6] -.sym 31512 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31513 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31514 spi_if_ins.spi.r_tx_byte[1] -.sym 31515 spi_if_ins.spi.r_tx_byte[5] -.sym 31516 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31517 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31518 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 31519 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 31520 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] -.sym 31521 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 31522 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 31523 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] -.sym 31524 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31525 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] -.sym 31526 spi_if_ins.r_tx_byte[5] -.sym 31530 spi_if_ins.spi.r_tx_byte[3] -.sym 31531 spi_if_ins.spi.r_tx_byte[7] -.sym 31532 spi_if_ins.spi.r_tx_bit_count[2] -.sym 31533 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 31534 spi_if_ins.r_tx_byte[0] -.sym 31538 spi_if_ins.r_tx_byte[4] -.sym 31542 spi_if_ins.r_tx_byte[2] -.sym 31546 spi_if_ins.r_tx_byte[7] -.sym 31550 spi_if_ins.r_tx_byte[3] -.sym 31554 r_tx_data[5] -.sym 31558 r_tx_data[2] -.sym 31566 r_tx_data[0] -.sym 31582 r_tx_data[3] -.sym 31591 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 31592 w_tx_data_io[2] -.sym 31593 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 31596 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 31597 w_tx_data_io[3] -.sym 31598 w_rx_09_fifo_data[13] -.sym 31599 w_rx_24_fifo_data[13] -.sym 31600 channel -.sym 31601 sys_ctrl_ins.debug_fifo_push_SB_LUT4_I2_O[3] -.sym 31629 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E -.sym 31632 i_button_SB_LUT4_I0_O[0] -.sym 31633 i_button_SB_LUT4_I0_O[1] -.sym 31637 io_ctrl_ins.led0_state_SB_LUT4_I1_I2[0] -.sym 31648 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[0] -.sym 31649 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O[1] -.sym 31676 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[0] -.sym 31677 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[1] -.sym 31883 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 31884 spi_if_ins.state_if_SB_DFFESR_Q_D[1] -.sym 31885 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 31888 spi_if_ins.state_if[0] -.sym 31889 spi_if_ins.state_if[1] -.sym 31895 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31896 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 31897 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 31899 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] -.sym 31900 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] -.sym 31901 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] -.sym 31902 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 31906 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31907 spi_if_ins.state_if[0] -.sym 31908 spi_if_ins.state_if[1] -.sym 31909 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 31914 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 31915 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 31916 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[2] -.sym 31917 i_rst_b$SB_IO_IN -.sym 31919 w_debug_smi_test -.sym 31920 smi_ctrl_ins.int_cnt[3] -.sym 31921 smi_ctrl_ins.int_cnt[4] -.sym 31924 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 31925 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31926 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31927 spi_if_ins.state_if[1] -.sym 31928 spi_if_ins.state_if[0] -.sym 31929 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 31931 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31932 spi_if_ins.state_if[0] -.sym 31933 spi_if_ins.state_if[1] -.sym 31935 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 31936 spi_if_ins.state_if[0] -.sym 31937 spi_if_ins.state_if[1] -.sym 31939 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 31940 i_rst_b$SB_IO_IN -.sym 31941 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] -.sym 31943 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] -.sym 31944 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 31945 i_rst_b$SB_IO_IN -.sym 31955 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] -.sym 31956 spi_if_ins.state_if_SB_DFFESR_Q_E[1] -.sym 31957 i_rst_b$SB_IO_IN -.sym 31960 rx_fifo.mem_i.0.2_RDATA[0] -.sym 31961 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31968 rx_fifo.mem_i.0.2_RDATA_3[0] -.sym 31969 rx_fifo.mem_i.0.0_RDATA[1] -.sym 31972 spi_if_ins.w_rx_data[6] -.sym 31973 spi_if_ins.w_rx_data[5] -.sym 31988 spi_if_ins.w_rx_data[5] -.sym 31989 spi_if_ins.w_rx_data[6] -.sym 31992 spi_if_ins.w_rx_data[5] -.sym 31993 spi_if_ins.w_rx_data[6] -.sym 32002 w_cs[0] -.sym 32003 w_cs[1] -.sym 32004 w_cs[3] -.sym 32005 w_cs[2] -.sym 32006 w_cs[0] -.sym 32007 w_cs[2] -.sym 32008 w_cs[3] -.sym 32009 w_cs[1] -.sym 32012 rx_fifo.mem_i.0.0_RDATA[1] -.sym 32013 rx_fifo.mem_i.0.3_RDATA_3[1] -.sym 32016 rx_fifo.mem_i.0.0_RDATA[1] -.sym 32017 rx_fifo.mem_i.0.3_RDATA_2[1] -.sym 32018 w_cs[0] -.sym 32019 w_cs[1] -.sym 32020 w_cs[2] -.sym 32021 w_cs[3] -.sym 32022 w_cs[0] -.sym 32023 w_cs[1] -.sym 32024 w_cs[2] -.sym 32025 w_cs[3] -.sym 32026 w_cs[1] -.sym 32027 w_cs[2] -.sym 32028 w_cs[3] -.sym 32029 w_cs[0] -.sym 32032 rx_fifo.mem_i.0.3_RDATA[0] -.sym 32033 rx_fifo.mem_i.0.0_RDATA[1] -.sym 32036 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 32037 w_tx_data_io[4] -.sym 32038 w_tx_data_smi[1] -.sym 32039 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 32040 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 32041 w_tx_data_io[1] -.sym 32045 spi_if_ins.o_cs_SB_LUT4_I3_1_O_SB_LUT4_I2_O -.sym 32048 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 32049 w_tx_data_io[6] -.sym 32051 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 32052 w_tx_data_io[5] -.sym 32053 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 32059 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 32060 w_tx_data_io[7] -.sym 32061 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 32064 spi_if_ins.o_cs_SB_LUT4_I3_1_O[0] -.sym 32065 i_rst_b$SB_IO_IN -.sym 32078 r_tx_data[1] -.sym 32113 io_pmod[1]$SB_IO_IN -.sym 32419 io_pmod[4]$SB_IO_IN -.sym 32420 smi_ctrl_ins.r_fifo_pull_1 -.sym 32421 smi_ctrl_ins.r_fifo_pull -.sym 32442 smi_ctrl_ins.r_fifo_pull -.sym 32446 smi_ctrl_ins.w_fifo_pull_trigger -.sym 32450 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0] -.sym 32476 i_ss$SB_IO_IN -.sym 32477 spi_if_ins.r_tx_data_valid -.sym 32489 $io_pmod[5]$iobuf_i -.sym 32497 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 32498 w_rx_data[0] -.sym 32539 spi_if_ins.r_tx_byte[7] -.sym 32540 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 32541 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] -.sym 32553 i_glob_clock$SB_IO_IN -.sym 32562 r_tx_data[4] -.sym 32566 r_tx_data[7] -.sym 32574 r_tx_data[6] -.sym 32593 r_counter -.sym 32624 w_debug_smi_test -.sym 32625 io_pmod[4]$SB_IO_IN +.sym 28398 w_rx_fifo_pulled_data[20] +.sym 28402 smi_ctrl_ins.r_fifo_pulled_data[9] +.sym 28403 smi_ctrl_ins.r_fifo_pulled_data[25] +.sym 28404 smi_ctrl_ins.int_cnt_rx[3] +.sym 28405 smi_ctrl_ins.int_cnt_rx[4] +.sym 28406 w_rx_fifo_pulled_data[22] +.sym 28410 w_rx_fifo_pulled_data[24] +.sym 28414 w_rx_fifo_pulled_data[9] +.sym 28439 w_rx_09_fifo_data[23] +.sym 28440 w_rx_24_fifo_data[23] +.sym 28441 channel +.sym 28443 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28444 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 28445 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28447 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28448 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28449 w_lvds_rx_09_d0_SB_LUT4_I2_O[1] +.sym 28450 rx_fifo.rd_addr_gray_wr[2] +.sym 28454 rx_fifo.rd_addr_gray[1] +.sym 28463 w_rx_09_fifo_data[10] +.sym 28464 w_rx_24_fifo_data[10] +.sym 28465 channel +.sym 28470 rx_fifo.rd_addr_gray[2] +.sym 28474 rx_fifo.rd_addr_gray[6] +.sym 28491 w_rx_09_fifo_data[1] +.sym 28492 w_rx_24_fifo_data[1] +.sym 28493 channel +.sym 28495 w_rx_09_fifo_data[0] +.sym 28496 w_rx_24_fifo_data[0] +.sym 28497 channel +.sym 28500 spi_if_ins.w_rx_data[5] +.sym 28501 spi_if_ins.w_rx_data[6] +.sym 28504 spi_if_ins.w_rx_data[6] +.sym 28505 spi_if_ins.w_rx_data[5] +.sym 28512 spi_if_ins.w_rx_data[5] +.sym 28513 spi_if_ins.w_rx_data[6] +.sym 28514 w_rx_fifo_full +.sym 28515 w_lvds_rx_09_d0_SB_LUT4_I2_O[2] +.sym 28516 w_lvds_rx_09_d0_SB_LUT4_I2_O[0] +.sym 28517 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 28519 w_rx_09_fifo_data[2] +.sym 28520 w_rx_24_fifo_data[2] +.sym 28521 channel +.sym 28522 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 28523 w_lvds_rx_24_d1 +.sym 28524 w_lvds_rx_24_d0 +.sym 28525 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 28527 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[0] +.sym 28528 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[1] +.sym 28529 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1[2] +.sym 28531 w_rx_09_fifo_data[27] +.sym 28532 w_rx_24_fifo_data[27] +.sym 28533 channel +.sym 28536 rx_fifo.rd_addr_gray_wr_r[7] +.sym 28537 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 28539 w_rx_09_fifo_data[8] +.sym 28540 w_rx_24_fifo_data[8] +.sym 28541 channel +.sym 28544 spi_if_ins.w_rx_data[5] +.sym 28545 spi_if_ins.w_rx_data[6] +.sym 28548 rx_fifo.rd_addr_gray_wr_r[5] +.sym 28549 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 28550 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 28555 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 28556 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 28557 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 28558 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 28562 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 28566 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 28567 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 28568 rx_fifo.rd_addr_gray_wr_r[2] +.sym 28569 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 28578 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 28582 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 28587 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[0] +.sym 28588 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1] +.sym 28589 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[2] +.sym 28590 rx_fifo.full_o_SB_LUT4_I3_I1[4] +.sym 28594 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 28598 rx_fifo.full_o_SB_LUT4_I3_I1[3] +.sym 28602 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 28603 rx_fifo.rd_addr_gray_wr_r[3] +.sym 28604 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 28605 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[2] +.sym 28606 rx_fifo.full_o_SB_LUT4_I3_I1[5] +.sym 28610 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 28614 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 28620 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 28621 rx_fifo.full_o_SB_LUT4_I3_I1[2] +.sym 28628 rx_fifo.full_o_SB_LUT4_I3_I1[6] +.sym 28629 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 28630 rx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 28634 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 28638 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 28639 rx_fifo.rd_addr_gray_wr_r[7] +.sym 28640 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 28641 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[3] +.sym 28644 rx_fifo.full_o_SB_LUT4_I3_I1[7] +.sym 28645 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 28648 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 28649 rx_fifo.full_o_SB_LUT4_I3_I1[8] +.sym 28650 rx_fifo.rd_addr_gray_wr[6] +.sym 28654 rx_fifo.rd_addr_gray_wr[1] +.sym 28658 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 28659 rx_fifo.rd_addr_gray_wr_r[8] +.sym 28660 rx_fifo.rd_addr_gray_wr_r[5] +.sym 28661 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 28662 rx_fifo.rd_addr_gray_wr[7] +.sym 28672 w_rx_fifo_push +.sym 28673 i_rst_b$SB_IO_IN +.sym 28682 rx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 28686 rx_fifo.wr_addr_gray_SB_DFFESR_Q_8_D[0] +.sym 28694 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 28702 rx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 28743 w_rx_09_fifo_data[13] +.sym 28744 w_rx_24_fifo_data[13] +.sym 28745 channel +.sym 28746 smi_ctrl_ins.r_fifo_pushed_data[14] +.sym 28751 w_rx_09_fifo_data[12] +.sym 28752 w_rx_24_fifo_data[12] +.sym 28753 channel +.sym 28755 w_rx_09_fifo_data[14] +.sym 28756 w_rx_24_fifo_data[14] +.sym 28757 channel +.sym 28759 w_rx_09_fifo_data[15] +.sym 28760 w_rx_24_fifo_data[15] +.sym 28761 channel +.sym 28766 smi_ctrl_ins.r_fifo_pushed_data[26] +.sym 28770 w_rx_fifo_pulled_data[6] +.sym 28775 w_rx_09_fifo_data[6] +.sym 28776 w_rx_24_fifo_data[6] +.sym 28777 channel +.sym 28782 w_rx_fifo_pulled_data[4] +.sym 28787 w_rx_09_fifo_data[4] +.sym 28788 w_rx_24_fifo_data[4] +.sym 28789 channel +.sym 28790 w_rx_fifo_pulled_data[5] +.sym 28799 w_rx_09_fifo_data[5] +.sym 28800 w_rx_24_fifo_data[5] +.sym 28801 channel +.sym 28803 w_rx_09_fifo_data[9] +.sym 28804 w_rx_24_fifo_data[9] +.sym 28805 channel +.sym 28814 w_smi_data_input[0] +.sym 28835 lvds_tx_inst.r_phase_count[1] +.sym 28839 lvds_tx_inst.r_phase_count[2] +.sym 28840 $PACKER_VCC_NET +.sym 28841 lvds_tx_inst.r_phase_count[1] +.sym 28843 lvds_tx_inst.r_phase_count[3] +.sym 28844 $PACKER_VCC_NET +.sym 28845 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 28846 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 28848 $PACKER_VCC_NET +.sym 28849 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO[3] +.sym 28853 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 28855 w_rx_09_fifo_data[28] +.sym 28856 w_rx_24_fifo_data[28] +.sym 28857 channel +.sym 28861 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 28862 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 28863 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 28864 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 28865 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 28866 smi_ctrl_ins.w_fifo_pull_trigger +.sym 28874 smi_ctrl_ins.r_fifo_pull +.sym 28881 w_rx_fifo_pull +.sym 28883 smi_ctrl_ins.r_fifo_pull_1 +.sym 28884 w_rx_fifo_empty +.sym 28885 smi_ctrl_ins.r_fifo_pull +.sym 28887 w_rx_09_fifo_data[30] +.sym 28888 w_rx_24_fifo_data[30] +.sym 28889 channel +.sym 28891 w_rx_09_fifo_data[3] +.sym 28892 w_rx_24_fifo_data[3] +.sym 28893 channel +.sym 28894 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 28895 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 28896 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 28897 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 28899 w_rx_09_fifo_data[22] +.sym 28900 w_rx_24_fifo_data[22] +.sym 28901 channel +.sym 28903 w_rx_09_fifo_data[17] +.sym 28904 w_rx_24_fifo_data[17] +.sym 28905 channel +.sym 28907 w_rx_09_fifo_data[16] +.sym 28908 w_rx_24_fifo_data[16] +.sym 28909 channel +.sym 28911 w_rx_09_fifo_data[21] +.sym 28912 w_rx_24_fifo_data[21] +.sym 28913 channel +.sym 28915 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[0] +.sym 28916 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[1] +.sym 28917 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 28919 w_rx_09_fifo_data[11] +.sym 28920 w_rx_24_fifo_data[11] +.sym 28921 channel +.sym 28923 w_rx_09_fifo_data[20] +.sym 28924 w_rx_24_fifo_data[20] +.sym 28925 channel +.sym 28927 w_rx_09_fifo_data[24] +.sym 28928 w_rx_24_fifo_data[24] +.sym 28929 channel +.sym 28930 w_rx_fifo_pulled_data[16] +.sym 28934 w_rx_fifo_pulled_data[1] +.sym 28938 w_rx_fifo_pulled_data[3] +.sym 28943 w_rx_09_fifo_data[25] +.sym 28944 w_rx_24_fifo_data[25] +.sym 28945 channel +.sym 28946 w_rx_fifo_pulled_data[0] +.sym 28950 w_rx_fifo_pulled_data[21] +.sym 28954 w_rx_fifo_pulled_data[18] +.sym 28958 w_rx_fifo_pulled_data[17] +.sym 28962 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 28966 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 28970 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 28971 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 28972 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 28973 w_rx_fifo_pull +.sym 28976 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 28977 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 28981 rx_fifo.rd_addr[0] +.sym 28982 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 28988 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 28989 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 28990 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 28995 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 28996 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 28997 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 28998 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[0] +.sym 28999 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[1] +.sym 29000 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[2] +.sym 29001 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O[3] +.sym 29004 rx_fifo.wr_addr_gray_rd_r[2] +.sym 29005 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 29006 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 29012 rx_fifo.rd_addr[0] +.sym 29013 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[1] +.sym 29014 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 29015 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 29016 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 29017 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 29020 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 29021 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 29023 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 29024 spi_if_ins.state_if_SB_DFFESR_Q_1_D_SB_LUT4_O_I2[1] +.sym 29025 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 29028 rx_fifo.wr_addr_gray_rd_r[2] +.sym 29029 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 29032 w_rx_fifo_pull +.sym 29033 i_rst_b$SB_IO_IN +.sym 29034 w_rx_data[0] +.sym 29038 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[0] +.sym 29039 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 29040 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[2] +.sym 29041 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 29042 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 29043 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 29044 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 29045 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 29047 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 29048 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 29049 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 29051 w_rx_09_fifo_data[26] +.sym 29052 w_rx_24_fifo_data[26] +.sym 29053 channel +.sym 29056 w_lvds_rx_24_d0 +.sym 29057 w_lvds_rx_24_d1 +.sym 29058 rx_fifo.wr_addr_gray_rd[1] +.sym 29062 rx_fifo.wr_addr_gray_rd[9] +.sym 29066 rx_fifo.wr_addr_gray[1] +.sym 29070 rx_fifo.wr_addr_gray[3] +.sym 29074 rx_fifo.wr_addr_gray[2] +.sym 29078 rx_fifo.wr_addr_gray_rd[2] +.sym 29082 rx_fifo.wr_addr_gray_rd[3] +.sym 29086 rx_fifo.wr_addr_gray_rd[6] +.sym 29091 rx_fifo.rd_addr_gray_wr_r[2] +.sym 29092 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 29093 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 29095 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[0] +.sym 29096 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2[1] +.sym 29097 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3[2] +.sym 29098 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[0] +.sym 29099 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[1] +.sym 29100 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 29101 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[3] +.sym 29102 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29107 rx_fifo.rd_addr_gray_wr_r[3] +.sym 29108 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 29109 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I0[2] +.sym 29110 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 29114 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 29115 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 29116 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 29117 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 29118 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[0] +.sym 29119 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[1] +.sym 29120 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[2] +.sym 29121 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O[3] +.sym 29122 rx_fifo.wr_addr_gray[4] +.sym 29128 rx_fifo.wr_addr[2] +.sym 29129 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 29130 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0] +.sym 29131 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1] +.sym 29132 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[2] +.sym 29133 w_rx_fifo_push +.sym 29134 rx_fifo.wr_addr_gray_rd[4] +.sym 29139 w_rx_24_fifo_push +.sym 29140 w_rx_09_fifo_push +.sym 29141 channel +.sym 29144 rx_fifo.rd_addr[0] +.sym 29145 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 29146 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[0] +.sym 29147 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 29148 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[2] +.sym 29149 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 29152 rx_fifo.rd_addr_gray_wr_r[8] +.sym 29153 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[7] +.sym 29158 rx_fifo.wr_addr[9] +.sym 29162 w_rx_fifo_push +.sym 29163 rx_fifo.full_o_SB_LUT4_I3_I1[9] +.sym 29164 rx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I2[0] +.sym 29165 w_rx_fifo_full +.sym 29166 rx_fifo.wr_addr_gray_rd[0] +.sym 29172 rx_fifo.wr_addr[0] +.sym 29173 rx_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 29174 rx_fifo.full_o_SB_LUT4_I3_O[0] +.sym 29175 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 29176 rx_fifo.full_o_SB_LUT4_I3_O[2] +.sym 29177 rx_fifo.full_o_SB_LUT4_I3_O[3] +.sym 29180 rx_fifo.wr_addr[0] +.sym 29181 rx_fifo.full_o_SB_LUT4_I3_O[1] +.sym 29194 rx_fifo.wr_addr_gray[7] +.sym 29198 rx_fifo.wr_addr_gray[6] +.sym 29202 rx_fifo.wr_addr_gray[0] +.sym 29206 rx_fifo.wr_addr_gray[8] +.sym 29222 w_smi_data_input[3] +.sym 29230 w_smi_data_input[0] +.sym 29234 w_smi_data_input[1] +.sym 29238 $PACKER_VCC_NET +.sym 29246 w_smi_data_input[2] +.sym 29258 w_smi_data_input[0] +.sym 29265 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0_SB_LUT4_I2_O +.sym 29266 w_smi_data_input[4] +.sym 29278 w_smi_data_input[1] +.sym 29282 w_smi_data_input[3] +.sym 29292 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 29293 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[1] +.sym 29294 w_smi_data_input[2] +.sym 29302 $PACKER_VCC_NET +.sym 29307 w_rx_fifo_empty +.sym 29308 w_tx_fifo_full +.sym 29309 i_smi_a2$SB_IO_IN +.sym 29314 smi_ctrl_ins.r_fifo_pushed_data[31] +.sym 29318 w_smi_data_input[3] +.sym 29322 smi_ctrl_ins.r_fifo_pushed_data[22] +.sym 29326 w_smi_data_input[0] +.sym 29330 w_smi_data_input[1] +.sym 29334 smi_ctrl_ins.r_fifo_pushed_data[20] +.sym 29342 smi_ctrl_ins.r_fifo_pushed_data[18] +.sym 29347 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 29348 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 29349 tx_fifo.rd_addr[5] +.sym 29353 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 29358 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 29359 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29360 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 29361 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 29363 w_tx_fifo_pull +.sym 29364 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[1] +.sym 29365 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2] +.sym 29368 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 29369 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 29374 lvds_tx_inst.r_phase_count[1] +.sym 29381 tx_fifo.rd_addr[0] +.sym 29382 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 29386 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 29387 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 29388 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 29389 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 29390 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 29394 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 29399 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 29400 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 29401 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 29402 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 29406 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 29414 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 29415 lvds_tx_inst.r_phase_count_SB_LUT4_I1_1_O_SB_DFFSR_D_Q_SB_LUT4_I3_O[1] +.sym 29416 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 29417 i_rst_b$SB_IO_IN +.sym 29418 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 29422 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 29423 tx_fifo.rd_addr[1] +.sym 29424 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[3] +.sym 29425 tx_fifo.rd_addr[2] +.sym 29432 tx_fifo.rd_addr[0] +.sym 29433 tx_fifo.wr_addr_gray_rd_r[0] +.sym 29436 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 29437 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 29439 i_rst_b$SB_IO_IN +.sym 29440 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1[2] +.sym 29441 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 29444 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 29445 w_rx_24_fifo_data[4] +.sym 29452 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 29453 w_rx_24_fifo_data[17] +.sym 29456 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 29457 w_rx_24_fifo_data[21] +.sym 29464 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 29465 w_rx_24_fifo_data[15] +.sym 29472 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 29473 w_rx_24_fifo_data[29] +.sym 29475 rx_fifo.rd_addr[0] +.sym 29480 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[1] +.sym 29481 rx_fifo.rd_addr[0] +.sym 29484 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_I0[3] +.sym 29485 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 29488 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[1] +.sym 29489 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 29492 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 29493 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 29496 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 29497 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 29500 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 29501 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 29504 rx_fifo.rd_addr[7] +.sym 29505 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 29508 rx_fifo.rd_addr[8] +.sym 29509 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 29512 rx_fifo.rd_addr[9] +.sym 29513 rx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 29515 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 29516 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 29517 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 29518 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[2] +.sym 29524 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 29525 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 29526 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 29532 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 29533 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 29534 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 29538 rx_fifo.wr_addr_gray_rd_r[8] +.sym 29539 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 29540 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 29541 rx_fifo.wr_addr_gray_rd_r[9] +.sym 29543 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 29544 spi_if_ins.state_if[0] +.sym 29545 spi_if_ins.state_if[1] +.sym 29546 r_tx_data[0] +.sym 29553 rx_fifo.rd_en_i_SB_LUT4_I2_O +.sym 29555 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 29556 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 29557 rx_fifo.wr_addr_gray_rd_r[8] +.sym 29558 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 29559 spi_if_ins.state_if[1] +.sym 29560 spi_if_ins.state_if[0] +.sym 29561 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 29562 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[0] +.sym 29563 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 29564 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 29565 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[3] +.sym 29567 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0] +.sym 29568 rx_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 29569 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 29570 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 29574 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[7] +.sym 29578 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 29582 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[2] +.sym 29587 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[0] +.sym 29588 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 29589 rx_fifo.rd_addr[7] +.sym 29590 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 29596 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[1] +.sym 29597 rx_fifo.rd_addr_gray_SB_DFFESR_Q_9_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 29600 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[9] +.sym 29601 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[8] +.sym 29602 channel +.sym 29606 rx_fifo.empty_o_SB_LUT4_I2_I0[0] +.sym 29607 rx_fifo.empty_o_SB_LUT4_I2_I0[1] +.sym 29608 w_rx_fifo_empty +.sym 29609 rx_fifo.empty_o_SB_LUT4_I2_I0[3] +.sym 29610 rx_fifo.wr_addr_gray_rd_r[8] +.sym 29611 rx_fifo.rd_addr[9] +.sym 29612 rx_fifo.wr_addr_gray_rd_r[9] +.sym 29613 rx_fifo.rd_addr[8] +.sym 29614 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[0] +.sym 29615 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1] +.sym 29616 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2] +.sym 29617 rx_fifo.empty_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3] +.sym 29619 rx_fifo.empty_o_SB_LUT4_I2_O[0] +.sym 29620 rx_fifo.empty_o_SB_LUT4_I2_O[1] +.sym 29621 rx_fifo.empty_o_SB_LUT4_I2_O[2] +.sym 29623 rx_fifo.rd_addr_gray_SB_DFFESR_Q_2_D[1] +.sym 29624 rx_fifo.rd_addr[7] +.sym 29625 rx_fifo.rd_addr[8] +.sym 29626 w_rx_fifo_empty +.sym 29630 w_tx_fifo_full +.sym 29634 rx_fifo.wr_addr_gray_rd[5] +.sym 29638 rx_fifo.wr_addr_gray_rd[8] +.sym 29642 rx_fifo.wr_addr_gray[5] +.sym 29658 rx_fifo.wr_addr_gray_rd[7] +.sym 29664 rx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 29665 rx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I0[3] +.sym 29670 rx_fifo.rd_addr_gray_wr[8] +.sym 29674 rx_fifo.rd_addr_gray[8] +.sym 29678 rx_fifo.rd_addr_gray_wr[9] +.sym 29682 rx_fifo.rd_addr_gray_wr[0] +.sym 29686 rx_fifo.rd_addr_gray[0] +.sym 29690 rx_fifo.rd_addr_gray[7] +.sym 29694 rx_fifo.rd_addr[9] +.sym 29730 smi_ctrl_ins.r_fifo_pushed_data[8] +.sym 29734 smi_ctrl_ins.r_fifo_pushed_data[9] +.sym 29738 smi_ctrl_ins.r_fifo_pushed_data[10] +.sym 29750 smi_ctrl_ins.r_fifo_pushed_data[11] +.sym 29763 smi_ctrl_ins.tx_reg_state[0] +.sym 29764 w_smi_data_input[7] +.sym 29765 i_rst_b$SB_IO_IN +.sym 29766 smi_ctrl_ins.r_fifo_pushed_data[17] +.sym 29770 smi_ctrl_ins.r_fifo_pushed_data[16] +.sym 29774 smi_ctrl_ins.r_fifo_pushed_data[13] +.sym 29778 w_smi_data_input[4] +.sym 29782 smi_ctrl_ins.r_fifo_pushed_data[12] +.sym 29786 smi_ctrl_ins.r_fifo_pushed_data[25] +.sym 29790 smi_ctrl_ins.r_fifo_pushed_data[29] +.sym 29794 smi_ctrl_ins.r_fifo_pushed_data[27] +.sym 29798 w_smi_data_input[6] +.sym 29802 w_smi_data_input[5] +.sym 29806 w_smi_data_input[2] +.sym 29810 smi_ctrl_ins.r_fifo_pushed_data[24] +.sym 29814 smi_ctrl_ins.r_fifo_pushed_data[23] +.sym 29818 smi_ctrl_ins.r_fifo_pushed_data[28] +.sym 29822 smi_ctrl_ins.r_fifo_pushed_data[21] +.sym 29834 w_smi_data_input[4] +.sym 29838 w_smi_data_input[3] +.sym 29846 w_smi_data_input[2] +.sym 29850 lvds_tx_inst.r_fifo_data[12] +.sym 29851 lvds_tx_inst.r_fifo_data[8] +.sym 29852 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 29853 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 29854 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 29855 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 29856 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 29857 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 29859 tx_fifo.rd_addr[0] +.sym 29864 tx_fifo.rd_addr[1] +.sym 29865 tx_fifo.rd_addr[0] +.sym 29868 tx_fifo.rd_addr[2] +.sym 29869 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[2] +.sym 29872 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 29873 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[3] +.sym 29876 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 29877 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[4] +.sym 29880 tx_fifo.rd_addr[5] +.sym 29881 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[5] +.sym 29884 tx_fifo.rd_addr[6] +.sym 29885 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[6] +.sym 29888 tx_fifo.rd_addr[7] +.sym 29889 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[7] +.sym 29892 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 29893 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[8] +.sym 29896 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 29897 tx_fifo.rd_addr_gray_SB_LUT4_I2_I3[9] +.sym 29898 tx_fifo.wr_addr_gray[4] +.sym 29902 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 29903 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 29904 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 29905 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 29906 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[0] +.sym 29907 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[1] +.sym 29908 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_I0[2] +.sym 29909 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 29910 tx_fifo.wr_addr_gray_rd[4] +.sym 29915 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[0] +.sym 29916 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 29917 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 29918 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[0] +.sym 29919 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[1] +.sym 29920 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[2] +.sym 29921 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I0_O[3] +.sym 29924 tx_fifo.rd_addr[6] +.sym 29925 tx_fifo.rd_addr[7] +.sym 29930 tx_fifo.empty_o_SB_LUT4_I3_I1[0] +.sym 29931 tx_fifo.empty_o_SB_LUT4_I3_I1[1] +.sym 29932 tx_fifo.empty_o_SB_LUT4_I3_I1[2] +.sym 29933 w_tx_fifo_empty +.sym 29934 tx_fifo.wr_addr_gray_rd[8] +.sym 29938 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 29939 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 29940 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 29941 tx_fifo.wr_addr_gray_rd_r[9] +.sym 29944 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1] +.sym 29945 tx_fifo.rd_addr[7] +.sym 29946 tx_fifo.wr_addr_gray[1] +.sym 29950 tx_fifo.wr_addr_gray_rd[1] +.sym 29954 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[0] +.sym 29955 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 29956 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 29957 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 29958 tx_fifo.rd_addr_gray[7] +.sym 29964 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 29965 i_rst_b$SB_IO_IN +.sym 29967 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 29968 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[1] +.sym 29969 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 29970 tx_fifo.rd_addr_gray_wr[8] +.sym 29974 tx_fifo.rd_addr_gray_wr[7] +.sym 29982 tx_fifo.rd_addr_gray[8] +.sym 29987 lvds_rx_24_inst.r_phase_count[0] +.sym 29991 lvds_rx_24_inst.r_phase_count[1] +.sym 29992 $PACKER_VCC_NET +.sym 29993 lvds_rx_24_inst.r_phase_count[0] +.sym 29994 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 29996 $PACKER_VCC_NET +.sym 29997 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q_SB_LUT4_O_I3[2] +.sym 29998 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 30007 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 30008 i_rst_b$SB_IO_IN +.sym 30009 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I0_O[2] +.sym 30012 i_ss$SB_IO_IN +.sym 30013 spi_if_ins.r_tx_data_valid +.sym 30014 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 30015 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 30016 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 30017 i_rst_b$SB_IO_IN +.sym 30020 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[5] +.sym 30021 rx_fifo.rd_addr_gray_SB_LUT4_I2_O[6] +.sym 30022 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 30023 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 30024 spi_if_ins.state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[2] +.sym 30025 i_rst_b$SB_IO_IN +.sym 30026 rx_fifo.rd_addr_gray[3] +.sym 30030 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30031 spi_if_ins.state_if[0] +.sym 30032 spi_if_ins.state_if[1] +.sym 30033 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 30035 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 30036 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 30037 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 30039 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 30040 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[1] +.sym 30041 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 30043 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 30044 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30045 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30046 rx_fifo.rd_addr_gray_wr[3] +.sym 30052 spi_if_ins.state_if[0] +.sym 30053 spi_if_ins.state_if[1] +.sym 30055 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[2] +.sym 30056 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 30057 i_rst_b$SB_IO_IN +.sym 30062 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30063 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30064 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 30065 i_rst_b$SB_IO_IN +.sym 30071 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30072 spi_if_ins.state_if[0] +.sym 30073 spi_if_ins.state_if[1] +.sym 30074 spi_if_ins.r_tx_byte[0] +.sym 30080 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30081 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30082 w_cs[3] +.sym 30083 w_cs[2] +.sym 30084 w_cs[1] +.sym 30085 w_cs[0] +.sym 30092 i_button_SB_LUT4_I0_I1[0] +.sym 30093 smi_ctrl_ins.r_channel_SB_DFFE_Q_E_SB_LUT4_O_I3[1] +.sym 30098 w_tx_data_sys[0] +.sym 30099 spi_if_ins.o_cs_SB_LUT4_I0_3_O[1] +.sym 30100 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 30101 spi_if_ins.o_cs_SB_LUT4_I0_3_O[3] +.sym 30102 w_cs[3] +.sym 30103 w_cs[2] +.sym 30104 w_cs[1] +.sym 30105 w_cs[0] +.sym 30110 w_fetch +.sym 30111 w_cs[2] +.sym 30112 i_rst_b$SB_IO_IN +.sym 30113 w_load +.sym 30116 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30117 w_rx_24_fifo_data[27] +.sym 30120 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30121 w_rx_24_fifo_data[5] +.sym 30122 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[0] +.sym 30123 i_rst_b$SB_IO_IN +.sym 30124 w_cs[2] +.sym 30125 w_fetch +.sym 30132 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30133 w_rx_24_fifo_data[25] +.sym 30136 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30137 w_rx_24_fifo_data[2] +.sym 30140 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30141 w_rx_24_fifo_data[26] +.sym 30144 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30145 w_rx_24_fifo_data[6] +.sym 30148 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30149 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 30170 w_rx_fifo_full +.sym 30171 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30172 w_lvds_rx_24_d0_SB_LUT4_I2_O[3] +.sym 30173 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 30202 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 30229 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30256 w_smi_data_input[7] +.sym 30257 w_smi_data_input[6] +.sym 30260 w_smi_data_input[7] +.sym 30261 smi_ctrl_ins.tx_reg_state[3] +.sym 30265 $PACKER_VCC_NET +.sym 30268 i_rst_b$SB_IO_IN +.sym 30269 i_smi_swe_srw$SB_IO_IN +.sym 30274 w_smi_data_input[6] +.sym 30280 smi_ctrl_ins.tx_reg_state[0] +.sym 30281 smi_ctrl_ins.tx_reg_state[3] +.sym 30282 w_smi_data_input[4] +.sym 30287 smi_ctrl_ins.tx_reg_state[1] +.sym 30288 smi_ctrl_ins.tx_reg_state[2] +.sym 30289 smi_ctrl_ins.tx_reg_state[3] +.sym 30292 smi_ctrl_ins.tx_reg_state[0] +.sym 30293 i_rst_b$SB_IO_IN +.sym 30294 smi_ctrl_ins.modem_tx_ctrl +.sym 30299 w_smi_data_input[7] +.sym 30300 smi_ctrl_ins.tx_reg_state[1] +.sym 30301 i_rst_b$SB_IO_IN +.sym 30302 w_smi_data_input[5] +.sym 30306 w_smi_data_input[6] +.sym 30310 w_smi_data_input[5] +.sym 30316 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 30317 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 30318 w_smi_data_input[1] +.sym 30323 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 30324 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5] +.sym 30325 tx_fifo.rd_addr_gray_wr_r[4] +.sym 30326 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[0] +.sym 30327 tx_fifo.rd_addr_gray_wr_r[6] +.sym 30328 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 30329 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 30335 w_smi_data_input[7] +.sym 30336 smi_ctrl_ins.tx_reg_state[2] +.sym 30337 i_rst_b$SB_IO_IN +.sym 30340 i_smi_a2$SB_IO_IN +.sym 30341 w_tx_fifo_pulled_data[30] +.sym 30344 i_smi_a2$SB_IO_IN +.sym 30345 w_tx_fifo_pulled_data[13] +.sym 30346 lvds_tx_inst.r_fifo_data[13] +.sym 30347 lvds_tx_inst.r_fifo_data[9] +.sym 30348 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 30349 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 30352 i_smi_a2$SB_IO_IN +.sym 30353 w_tx_fifo_pulled_data[12] +.sym 30356 i_smi_a2$SB_IO_IN +.sym 30357 w_tx_fifo_pulled_data[9] +.sym 30360 i_smi_a2$SB_IO_IN +.sym 30361 w_tx_fifo_pulled_data[10] +.sym 30364 i_smi_a2$SB_IO_IN +.sym 30365 w_tx_fifo_pulled_data[8] +.sym 30368 i_smi_a2$SB_IO_IN +.sym 30369 w_tx_fifo_pulled_data[22] +.sym 30372 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 30373 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 30376 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 30377 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 30380 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 30381 tx_fifo.rd_addr_SB_DFFESR_Q_D[4] +.sym 30382 tx_fifo.wr_addr_gray_rd[5] +.sym 30386 tx_fifo.wr_addr_gray[5] +.sym 30392 tx_fifo.rd_addr_SB_DFFESR_Q_D[5] +.sym 30393 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 30394 lvds_tx_inst.r_fifo_data[30] +.sym 30395 lvds_tx_inst.r_fifo_data[28] +.sym 30396 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 30397 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 30398 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[0] +.sym 30399 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 30400 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 30401 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[3] +.sym 30404 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 30405 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 30406 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 30412 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 30413 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 30416 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 30417 tx_fifo.rd_addr_SB_DFFESR_Q_D[8] +.sym 30418 tx_fifo.rd_addr_SB_DFFESR_Q_D[7] +.sym 30423 tx_fifo.wr_addr_gray_rd_r[9] +.sym 30424 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 30425 w_tx_fifo_pull +.sym 30426 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[0] +.sym 30427 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 30428 tx_fifo.empty_o_SB_LUT4_I3_I1[0] +.sym 30429 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[3] +.sym 30432 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[1] +.sym 30433 tx_fifo.rd_addr_SB_DFFESR_Q_D[3] +.sym 30434 tx_fifo.wr_addr_gray_rd[0] +.sym 30438 tx_fifo.wr_addr_gray_rd[6] +.sym 30442 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 30443 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1] +.sym 30444 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30445 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 30446 tx_fifo.wr_addr_gray[8] +.sym 30450 tx_fifo.wr_addr_gray_rd[9] +.sym 30454 tx_fifo.wr_addr_gray[7] +.sym 30458 tx_fifo.wr_addr_gray_rd[7] +.sym 30462 tx_fifo.wr_addr_gray[6] +.sym 30466 tx_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 30467 tx_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 30468 tx_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 30469 tx_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 30470 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[0] +.sym 30471 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1] +.sym 30472 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2] +.sym 30473 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3] +.sym 30474 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2] +.sym 30478 tx_fifo.rd_addr_SB_DFFESR_Q_D[9] +.sym 30482 tx_fifo.rd_addr_SB_DFFESR_Q_D[6] +.sym 30487 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[2] +.sym 30488 tx_fifo.rd_addr[5] +.sym 30489 tx_fifo.rd_addr[6] +.sym 30490 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 30497 i_rst_b$SB_IO_IN +.sym 30499 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 30503 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 30504 $PACKER_VCC_NET +.sym 30507 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30508 $PACKER_VCC_NET +.sym 30509 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 30511 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 30512 $PACKER_VCC_NET +.sym 30513 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 30514 spi_if_ins.spi.SCKr[2] +.sym 30515 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 30516 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30517 spi_if_ins.spi.SCKr[1] +.sym 30521 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 30523 spi_if_ins.spi.SCKr[2] +.sym 30524 spi_if_ins.spi.SCKr[1] +.sym 30525 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 30526 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] +.sym 30527 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] +.sym 30528 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 30529 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 30531 spi_if_ins.spi.r_tx_byte[0] +.sym 30532 spi_if_ins.spi.r_tx_byte[4] +.sym 30533 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30534 i_sck$SB_IO_IN +.sym 30538 spi_if_ins.spi.r_tx_byte[3] +.sym 30539 spi_if_ins.spi.r_tx_byte[7] +.sym 30540 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30541 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 30543 spi_if_ins.spi.r_tx_byte[1] +.sym 30544 spi_if_ins.spi.r_tx_byte[5] +.sym 30545 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30546 spi_if_ins.spi.SCKr[1] +.sym 30550 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 30551 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 30552 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 30553 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] +.sym 30554 spi_if_ins.spi.r_tx_byte[2] +.sym 30555 spi_if_ins.spi.r_tx_byte[6] +.sym 30556 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] +.sym 30557 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30558 spi_if_ins.spi.SCKr[0] +.sym 30562 spi_if_ins.r_tx_byte[3] +.sym 30566 spi_if_ins.r_tx_byte[4] +.sym 30570 spi_if_ins.r_tx_byte[7] +.sym 30577 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 30578 spi_if_ins.r_tx_byte[6] +.sym 30582 spi_if_ins.r_tx_byte[5] +.sym 30586 spi_if_ins.r_tx_byte[2] +.sym 30590 spi_if_ins.r_tx_byte[1] +.sym 30594 r_tx_data[3] +.sym 30598 r_tx_data[5] +.sym 30602 r_tx_data[1] +.sym 30608 spi_if_ins.o_cs_SB_LUT4_I0_2_O[0] +.sym 30609 i_rst_b$SB_IO_IN +.sym 30610 r_tx_data[6] +.sym 30614 r_tx_data[2] +.sym 30618 r_tx_data[7] +.sym 30622 r_tx_data[4] +.sym 30626 w_cs[2] +.sym 30627 w_cs[1] +.sym 30628 w_cs[0] +.sym 30629 w_cs[3] +.sym 30631 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 30632 w_cs[0] +.sym 30633 w_fetch +.sym 30636 w_ioc[1] +.sym 30637 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 30639 i_rst_b$SB_IO_IN +.sym 30640 w_cs[1] +.sym 30641 w_fetch +.sym 30645 w_tx_fifo_empty +.sym 30646 w_tx_data_smi[0] +.sym 30647 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 30648 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 30649 w_tx_data_io[0] +.sym 30650 w_tx_data_smi[2] +.sym 30651 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 30652 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 30653 w_tx_data_io[2] +.sym 30654 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[0] +.sym 30655 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 30656 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 30657 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 30663 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 30664 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[1] +.sym 30665 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 30679 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 30680 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 30681 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2] +.sym 30682 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 30683 w_fetch +.sym 30684 w_cs[1] +.sym 30685 w_load +.sym 30702 w_rx_data[2] +.sym 30718 io_ctrl_ins.o_pmod[2] +.sym 30719 o_shdn_tx_lna$SB_IO_OUT +.sym 30720 w_ioc[0] +.sym 30721 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 30725 i_rst_b$SB_IO_IN +.sym 30730 w_rx_data[2] +.sym 30755 smi_ctrl_ins.r_fifo_push_1 +.sym 30756 w_tx_fifo_full +.sym 30757 smi_ctrl_ins.r_fifo_push +.sym 30762 smi_ctrl_ins.r_fifo_push +.sym 30770 smi_ctrl_ins.w_fifo_push_trigger +.sym 30780 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 30781 i_rst_b$SB_IO_IN +.sym 30787 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 30792 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 30793 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 30796 tx_fifo.wr_addr[2] +.sym 30797 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2] +.sym 30800 tx_fifo.wr_addr[3] +.sym 30801 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3] +.sym 30804 tx_fifo.wr_addr[4] +.sym 30805 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4] +.sym 30808 tx_fifo.wr_addr[5] +.sym 30809 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5] +.sym 30812 tx_fifo.wr_addr[6] +.sym 30813 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6] +.sym 30816 tx_fifo.wr_addr[7] +.sym 30817 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7] +.sym 30820 tx_fifo.wr_addr[8] +.sym 30821 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[8] +.sym 30824 tx_fifo.wr_addr[9] +.sym 30825 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[9] +.sym 30827 tx_fifo.rd_addr_gray_wr_r[6] +.sym 30828 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 30829 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[6] +.sym 30833 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_21_E +.sym 30834 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 30840 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 30841 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 30842 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 30846 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 30850 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[0] +.sym 30851 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[1] +.sym 30852 smi_ctrl_ins.int_cnt_rx[3] +.sym 30853 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_5_I3[3] +.sym 30854 tx_fifo.rd_addr_gray_wr_r[7] +.sym 30855 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 30856 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 30857 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[3] +.sym 30858 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[0] +.sym 30859 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[1] +.sym 30860 smi_ctrl_ins.int_cnt_rx[3] +.sym 30861 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_1_I3[3] +.sym 30864 smi_ctrl_ins.int_cnt_rx[4] +.sym 30865 smi_ctrl_ins.int_cnt_rx[3] +.sym 30866 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[0] +.sym 30867 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[1] +.sym 30868 smi_ctrl_ins.int_cnt_rx[3] +.sym 30869 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_3_I3[3] +.sym 30870 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[0] +.sym 30871 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[1] +.sym 30872 smi_ctrl_ins.int_cnt_rx[3] +.sym 30873 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_4_I3[3] +.sym 30874 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[0] +.sym 30875 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[1] +.sym 30876 smi_ctrl_ins.int_cnt_rx[3] +.sym 30877 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_7_I3[3] +.sym 30878 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[0] +.sym 30879 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[1] +.sym 30880 smi_ctrl_ins.int_cnt_rx[3] +.sym 30881 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_6_I3[3] +.sym 30882 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[0] +.sym 30883 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 30884 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 30885 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 30886 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 30887 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 30888 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 30889 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 30891 tx_fifo.rd_addr_gray_wr_r[2] +.sym 30892 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 30893 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 30894 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 30895 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 30896 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] +.sym 30897 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 30901 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 30902 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 30903 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 30904 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[2] +.sym 30905 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[3] +.sym 30908 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[0] +.sym 30909 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2[1] +.sym 30910 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[0] +.sym 30911 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[1] +.sym 30912 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[2] +.sym 30913 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O[3] +.sym 30914 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3] +.sym 30920 tx_fifo.rd_addr[0] +.sym 30921 tx_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2[2] +.sym 30922 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D_SB_LUT4_I2_O[1] +.sym 30928 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 30929 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 30930 tx_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0] +.sym 30934 tx_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0] +.sym 30938 tx_fifo.rd_addr_gray_SB_DFFESR_Q_3_D[1] +.sym 30944 w_tx_fifo_push +.sym 30945 i_rst_b$SB_IO_IN +.sym 30952 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30953 w_rx_24_fifo_data[10] +.sym 30956 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30957 w_rx_24_fifo_data[20] +.sym 30960 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30961 w_rx_24_fifo_data[11] +.sym 30965 tx_fifo.wr_addr_gray[6] +.sym 30969 tx_fifo.wr_addr_gray[8] +.sym 30972 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30973 w_rx_24_fifo_data[28] +.sym 30976 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 30977 w_rx_24_fifo_data[19] +.sym 30978 tx_fifo.wr_addr_gray[3] +.sym 30982 tx_fifo.wr_addr_gray_rd[2] +.sym 30986 tx_fifo.wr_addr_gray[0] +.sym 30990 tx_fifo.wr_addr_gray_rd[3] +.sym 30996 tx_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2] +.sym 30997 tx_fifo.rd_addr[2] +.sym 30998 tx_fifo.wr_addr[9] +.sym 31002 tx_fifo.wr_addr_gray[2] +.sym 31008 w_tx_fifo_pull +.sym 31009 i_rst_b$SB_IO_IN +.sym 31012 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31013 w_rx_24_fifo_data[23] +.sym 31016 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31017 w_rx_24_fifo_data[8] +.sym 31020 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31021 w_rx_24_fifo_data[12] +.sym 31028 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31029 w_rx_24_fifo_data[24] +.sym 31033 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 31036 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31037 w_rx_24_fifo_data[0] +.sym 31040 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31041 w_rx_24_fifo_data[14] +.sym 31042 spi_if_ins.spi.r_rx_done +.sym 31046 tx_fifo.rd_addr_gray_wr[9] +.sym 31050 spi_if_ins.spi.r2_rx_done +.sym 31056 spi_if_ins.spi.r3_rx_done +.sym 31057 spi_if_ins.spi.r2_rx_done +.sym 31062 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 31070 tx_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[1] +.sym 31074 spi_if_ins.spi.r_rx_byte[3] +.sym 31078 spi_if_ins.spi.r_rx_byte[2] +.sym 31082 spi_if_ins.spi.r_rx_byte[1] +.sym 31086 spi_if_ins.spi.r_rx_byte[4] +.sym 31090 spi_if_ins.spi.r_rx_byte[5] +.sym 31094 spi_if_ins.spi.r_rx_byte[0] +.sym 31098 spi_if_ins.spi.r_rx_byte[6] +.sym 31102 spi_if_ins.spi.r_rx_byte[7] +.sym 31107 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 31108 w_tx_data_io[7] +.sym 31109 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 31112 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 31113 w_tx_data_io[6] +.sym 31116 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 31117 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1] +.sym 31118 w_tx_data_smi[1] +.sym 31119 spi_if_ins.o_cs_SB_LUT4_I0_O[1] +.sym 31120 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 31121 w_tx_data_io[1] +.sym 31124 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 31125 w_tx_data_io[4] +.sym 31126 w_cs[3] +.sym 31127 w_cs[2] +.sym 31128 w_cs[0] +.sym 31129 w_cs[1] +.sym 31131 spi_if_ins.o_cs_SB_LUT4_I0_1_O[0] +.sym 31132 w_tx_data_io[5] +.sym 31133 spi_if_ins.o_cs_SB_LUT4_I0_3_O[2] +.sym 31134 w_cs[3] +.sym 31135 w_cs[1] +.sym 31136 w_cs[0] +.sym 31137 w_cs[2] +.sym 31138 i_config[1]$SB_IO_IN +.sym 31139 i_button_SB_LUT4_I0_I1[0] +.sym 31140 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2] +.sym 31141 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3] +.sym 31146 w_fetch +.sym 31147 w_cs[1] +.sym 31148 i_button_SB_LUT4_I0_I1[0] +.sym 31149 w_load +.sym 31150 o_led1$SB_IO_OUT +.sym 31151 i_button_SB_LUT4_I0_I1[0] +.sym 31152 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2] +.sym 31153 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3] +.sym 31155 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 31156 w_ioc[1] +.sym 31157 w_ioc[0] +.sym 31158 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 31159 io_ctrl_ins.debug_mode[0] +.sym 31160 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 31161 io_ctrl_ins.pmod_dir_state[0] +.sym 31162 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1] +.sym 31163 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31164 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 31165 io_ctrl_ins.pmod_dir_state[3] +.sym 31167 w_ioc[1] +.sym 31168 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] 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tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 31308 tx_fifo.wr_addr[3] +.sym 31309 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[2] +.sym 31312 tx_fifo.wr_addr[4] +.sym 31313 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[3] +.sym 31316 tx_fifo.wr_addr[5] +.sym 31317 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[4] +.sym 31320 tx_fifo.wr_addr[6] +.sym 31321 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[5] +.sym 31324 tx_fifo.wr_addr[7] +.sym 31325 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[6] +.sym 31328 tx_fifo.wr_addr[8] +.sym 31329 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[7] +.sym 31332 tx_fifo.wr_addr[9] +.sym 31333 tx_fifo.wr_addr_gray_SB_LUT4_I2_I3[8] +.sym 31334 tx_fifo.rd_addr_gray_wr_r[8] +.sym 31335 tx_fifo.rd_addr_gray_wr_r[9] +.sym 31336 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[8] +.sym 31337 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[7] +.sym 31340 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 31341 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4] +.sym 31342 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 31343 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 31344 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 31345 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 31348 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 31349 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[3] +.sym 31351 tx_fifo.rd_addr_gray_wr_r[7] +.sym 31352 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[6] +.sym 31353 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_I2[7] +.sym 31354 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[0] +.sym 31355 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[1] +.sym 31356 smi_ctrl_ins.int_cnt_rx[3] +.sym 31357 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_2_I3[3] +.sym 31360 tx_fifo.rd_addr_gray_wr_r[4] +.sym 31361 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[2] +.sym 31362 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 31363 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 31364 tx_fifo.wr_addr_gray_SB_DFFESR_Q_6_D[2] +.sym 31365 w_tx_fifo_full +.sym 31366 tx_fifo.rd_addr_gray_wr_r[4] +.sym 31367 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 31368 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0] +.sym 31369 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 31370 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0] +.sym 31371 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1] +.sym 31372 w_tx_fifo_push +.sym 31373 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3] +.sym 31375 tx_fifo.rd_addr_gray_wr_r[2] +.sym 31376 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 31377 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 31378 tx_fifo.rd_addr_gray_wr_r[8] +.sym 31379 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 31380 tx_fifo.rd_addr_gray_wr_r[9] +.sym 31381 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 31382 smi_ctrl_ins.r_fifo_pushed_data[19] +.sym 31386 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 31387 tx_fifo.rd_addr_gray_wr_r[2] +.sym 31388 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 31389 tx_fifo.rd_addr_gray_wr_r[7] +.sym 31390 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[0] +.sym 31391 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[1] +.sym 31392 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[2] +.sym 31393 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_I0[3] +.sym 31394 tx_fifo.rd_addr_gray_wr[5] +.sym 31398 tx_fifo.rd_addr_gray_wr[1] +.sym 31402 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 31403 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[1] +.sym 31404 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[2] +.sym 31405 tx_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] +.sym 31406 tx_fifo.rd_addr_gray_wr[6] +.sym 31410 tx_fifo.rd_addr_gray[4] +.sym 31414 tx_fifo.rd_addr_gray_wr[0] +.sym 31418 tx_fifo.rd_addr_gray[6] +.sym 31422 tx_fifo.rd_addr_gray_wr[4] +.sym 31426 lvds_tx_inst.r_fifo_data[15] +.sym 31427 lvds_tx_inst.r_fifo_data[11] +.sym 31428 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31429 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q_SB_LUT4_O_I3[3] +.sym 31430 tx_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[0] +.sym 31434 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[1] +.sym 31440 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 31441 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 31444 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[2] +.sym 31445 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D_SB_LUT4_I1_O_SB_LUT4_O_I0[3] +.sym 31448 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 31449 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[8] +.sym 31450 tx_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1] +.sym 31454 tx_fifo.wr_addr_gray_SB_LUT4_I2_1_O[9] +.sym 31458 tx_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[3] +.sym 31462 lvds_tx_inst.r_fifo_data[18] +.sym 31463 lvds_tx_inst.r_fifo_data[16] +.sym 31464 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31465 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 31466 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[0] +.sym 31467 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[1] +.sym 31468 lvds_tx_inst.r_phase_count_SB_CARRY_CI_CO_SB_LUT4_I3_O_SB_DFFSR_D_Q[2] +.sym 31469 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 31473 i_ss$SB_IO_IN +.sym 31474 lvds_tx_inst.r_fifo_data[22] +.sym 31475 lvds_tx_inst.r_fifo_data[20] +.sym 31476 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 31477 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31478 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[0] +.sym 31479 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[1] +.sym 31480 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[2] +.sym 31481 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 31486 tx_fifo.wr_addr_gray_SB_DFFESR_Q_9_D[1] +.sym 31491 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31496 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31500 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31501 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 31502 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0] +.sym 31503 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[1] +.sym 31504 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[2] +.sym 31505 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0[3] +.sym 31508 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31509 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31510 lvds_tx_inst.r_fifo_data[23] +.sym 31511 lvds_tx_inst.r_fifo_data[21] +.sym 31512 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 31513 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31517 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31518 lvds_tx_inst.r_fifo_data[19] +.sym 31519 lvds_tx_inst.r_fifo_data[17] +.sym 31520 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31521 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 31530 i_ss$SB_IO_IN +.sym 31531 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31532 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31533 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31534 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 31539 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31540 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31541 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31549 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 31553 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 31554 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 31558 i_mosi$SB_IO_IN +.sym 31562 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 31566 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 31570 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 31574 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 31578 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 31584 i_ss$SB_IO_IN +.sym 31585 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 31586 i_mosi$SB_IO_IN +.sym 31590 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 31594 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 31598 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 31602 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 31606 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 31610 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 31614 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 31628 i_rst_b$SB_IO_IN +.sym 31629 i_smi_soe_se$SB_IO_IN +.sym 31650 w_rx_data[1] +.sym 31660 i_button_SB_LUT4_I0_I1[0] +.sym 31661 i_button_SB_LUT4_I0_I1[1] +.sym 31666 w_rx_data[0] +.sym 31679 w_ioc[0] +.sym 31680 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 31681 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 31682 w_rx_data[3] +.sym 31686 w_rx_data[0] +.sym 31694 w_rx_data[1] +.sym 31698 io_ctrl_ins.o_pmod[1] +.sym 31699 o_shdn_rx_lna$SB_IO_OUT +.sym 31700 w_ioc[0] +.sym 31701 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 31702 w_rx_data[4] +.sym 31710 io_ctrl_ins.o_pmod[4] +.sym 31711 o_tr_vc1_b$SB_IO_OUT +.sym 31712 w_ioc[0] +.sym 31713 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 31715 w_ioc[0] +.sym 31716 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 31717 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 31719 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31720 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 31721 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31722 w_rx_data[6] +.sym 31726 w_rx_data[5] +.sym 31731 io_ctrl_ins.debug_mode_SB_LUT4_I2_1_I1[0] +.sym 31732 io_ctrl_ins.debug_mode[1] +.sym 31733 i_rst_b$SB_IO_IN +.sym 31734 io_ctrl_ins.o_pmod[6] +.sym 31735 o_rx_h_tx_l_b$SB_IO_OUT +.sym 31736 w_ioc[0] +.sym 31737 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 31738 w_rx_data[7] +.sym 31744 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I3[0] +.sym 31745 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[1] +.sym 31759 i_config[3]$SB_IO_IN +.sym 31760 i_button_SB_LUT4_I0_I1[0] +.sym 31761 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[2] +.sym 31762 w_rx_data[7] +.sym 31766 w_rx_data[6] +.sym 31774 w_rx_data[5] +.sym 31801 w_smi_data_input[7] +.sym 31810 smi_ctrl_ins.tx_reg_state_SB_DFFN_Q_3_D_SB_LUT4_O_I0[0] +.sym 31811 smi_ctrl_ins.r_fifo_pushed_data_SB_DFFNESR_Q_E[0] +.sym 31812 w_smi_data_input[7] +.sym 31813 i_rst_b$SB_IO_IN +.sym 31819 w_smi_data_input[7] +.sym 31820 i_rst_b$SB_IO_IN +.sym 31821 smi_ctrl_ins.tx_reg_state[1] +.sym 31823 i_rst_b$SB_IO_IN +.sym 31824 smi_ctrl_ins.tx_reg_state[0] +.sym 31825 w_smi_data_input[7] +.sym 31839 w_smi_data_input[7] +.sym 31840 i_rst_b$SB_IO_IN +.sym 31841 smi_ctrl_ins.tx_reg_state[2] +.sym 31853 w_tx_fifo_pull +.sym 31880 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31881 w_rx_24_fifo_data[13] +.sym 31896 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31897 w_rx_24_fifo_data[7] +.sym 31904 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31905 w_rx_24_fifo_data[9] +.sym 31906 lvds_tx_inst.r_fifo_data[31] +.sym 31907 lvds_tx_inst.r_fifo_data[29] +.sym 31908 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 31909 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31912 i_smi_a2$SB_IO_IN +.sym 31913 w_tx_fifo_pulled_data[29] +.sym 31916 i_smi_a2$SB_IO_IN +.sym 31917 w_tx_fifo_pulled_data[15] +.sym 31920 i_smi_a2$SB_IO_IN +.sym 31921 w_tx_fifo_pulled_data[28] +.sym 31924 i_smi_a2$SB_IO_IN +.sym 31925 w_tx_fifo_pulled_data[11] +.sym 31928 i_smi_a2$SB_IO_IN +.sym 31929 w_tx_fifo_pulled_data[14] +.sym 31931 w_lvds_rx_24_d0_SB_LUT4_I2_O[2] +.sym 31932 w_lvds_rx_24_d0_SB_LUT4_I2_O[1] +.sym 31933 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 31936 i_smi_a2$SB_IO_IN +.sym 31937 w_tx_fifo_pulled_data[31] +.sym 31938 tx_fifo.rd_addr_gray[2] +.sym 31942 tx_fifo.rd_addr_gray[3] +.sym 31946 tx_fifo.rd_addr_gray[1] +.sym 31950 tx_fifo.rd_addr_gray[5] +.sym 31954 lvds_tx_inst.r_fifo_data[26] +.sym 31955 lvds_tx_inst.r_fifo_data[24] +.sym 31956 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31957 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 31958 tx_fifo.rd_addr_gray_wr[2] +.sym 31962 tx_fifo.rd_addr_gray_wr[3] +.sym 31966 tx_fifo.rd_addr_gray[0] +.sym 31970 lvds_tx_inst.r_fifo_data[27] +.sym 31971 lvds_tx_inst.r_fifo_data[25] +.sym 31972 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 31973 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 31976 i_smi_a2$SB_IO_IN +.sym 31977 w_tx_fifo_pulled_data[16] +.sym 31980 i_smi_a2$SB_IO_IN +.sym 31981 w_tx_fifo_pulled_data[20] +.sym 31984 i_smi_a2$SB_IO_IN +.sym 31985 w_tx_fifo_pulled_data[27] +.sym 31988 i_smi_a2$SB_IO_IN +.sym 31989 w_tx_fifo_pulled_data[18] +.sym 31992 i_smi_a2$SB_IO_IN +.sym 31993 w_tx_fifo_pulled_data[26] +.sym 31996 i_smi_a2$SB_IO_IN +.sym 31997 w_tx_fifo_pulled_data[5] +.sym 32000 i_smi_a2$SB_IO_IN +.sym 32001 w_tx_fifo_pulled_data[25] +.sym 32004 i_smi_a2$SB_IO_IN +.sym 32005 w_tx_fifo_pulled_data[1] +.sym 32008 i_smi_a2$SB_IO_IN +.sym 32009 w_tx_fifo_pulled_data[17] +.sym 32012 i_smi_a2$SB_IO_IN +.sym 32013 w_tx_fifo_pulled_data[23] +.sym 32016 i_smi_a2$SB_IO_IN +.sym 32017 w_tx_fifo_pulled_data[21] +.sym 32020 i_smi_a2$SB_IO_IN +.sym 32021 w_tx_fifo_pulled_data[19] +.sym 32022 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[0] +.sym 32023 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[1] +.sym 32024 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 32025 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[3] +.sym 32028 i_smi_a2$SB_IO_IN +.sym 32029 w_tx_fifo_pulled_data[3] +.sym 32030 lvds_tx_inst.r_fifo_data[5] +.sym 32031 lvds_tx_inst.r_fifo_data[1] +.sym 32032 w_lvds_tx_d1_SB_DFFE_Q_D_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3[2] +.sym 32033 lvds_tx_inst.o_fifo_pull_SB_DFFSR_Q_R_SB_LUT4_O_I2[2] +.sym 32039 spi_if_ins.r_tx_byte[7] +.sym 32040 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 32041 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 32045 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E +.sym 32053 i_rst_b$SB_IO_IN +.sym 32059 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFER_Q_E_SB_DFFER_E_1_Q[0] +.sym 32060 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3 +.sym 32061 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] +.sym 32065 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3 +.sym 32079 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 32080 spi_if_ins.state_if_SB_DFFESR_Q_E[1] +.sym 32081 i_rst_b$SB_IO_IN +.sym 32086 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 32091 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[0] +.sym 32092 i_rst_b$SB_IO_IN +.sym 32093 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0] +.sym 32098 spi_if_ins.w_rx_data[6] +.sym 32102 spi_if_ins.w_rx_data[1] +.sym 32106 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D[2] +.sym 32110 spi_if_ins.w_rx_data[0] +.sym 32114 spi_if_ins.w_rx_data[5] +.sym 32118 spi_if_ins.w_rx_data[4] +.sym 32122 spi_if_ins.w_rx_data[3] +.sym 32126 spi_if_ins.w_rx_data[2] +.sym 32138 spi_if_ins.w_rx_data[1] +.sym 32142 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 32146 spi_if_ins.w_rx_data[0] +.sym 32150 spi_if_ins.w_rx_data[4] +.sym 32154 spi_if_ins.w_rx_data[3] +.sym 32158 spi_if_ins.w_rx_data[2] +.sym 32162 w_ioc[1] +.sym 32163 w_ioc[4] +.sym 32164 w_ioc[3] +.sym 32165 w_ioc[2] +.sym 32167 w_ioc[0] +.sym 32168 w_ioc[1] +.sym 32169 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 32175 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 32176 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 32177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I2[1] +.sym 32178 o_led0$SB_IO_OUT +.sym 32179 i_button_SB_LUT4_I0_I1[0] +.sym 32180 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[2] +.sym 32181 io_ctrl_ins.mixer_en_state_SB_LUT4_I1_O[3] +.sym 32183 w_ioc[2] +.sym 32184 w_ioc[4] +.sym 32185 w_ioc[3] +.sym 32186 i_config[0]$SB_IO_IN +.sym 32187 i_button_SB_LUT4_I0_I1[0] +.sym 32188 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2] +.sym 32189 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3] +.sym 32190 w_ioc[1] +.sym 32191 w_ioc[0] +.sym 32192 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1] +.sym 32193 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I0[1] +.sym 32194 io_ctrl_ins.rf_pin_state[3] +.sym 32195 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 32196 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 32197 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 32198 io_ctrl_ins.rf_pin_state[0] +.sym 32199 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 32200 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 32201 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 32206 io_ctrl_ins.o_pmod[0] +.sym 32207 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