kopia lustrzana https://github.com/cariboulabs/cariboulite
fifo 9 bit length, for 900 and 2.4, half tested
rodzic
45f6076a30
commit
ed59e9996a
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@ -1,5 +1,5 @@
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module complex_fifo #(
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parameter ADDR_WIDTH = 8,
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parameter ADDR_WIDTH = 9,
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parameter DATA_WIDTH = 16
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)
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(
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@ -36,16 +36,27 @@ always @(posedge wr_clk_i) begin
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end
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end
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//reg [1:0] cnt;
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always @(posedge rd_clk_i) begin
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if (rd_rst_i) begin
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rd_addr <= 0;
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empty_o <= 1'b1;
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//cnt <= 2'b00;
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end else begin
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if (rd_en_i) begin
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rd_addr <= rd_addr + 1'b1;
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empty_o <= (rd_addr + 1) == wr_addr;
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rd_data_o[31:16] <= mem_i[rd_addr];
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rd_data_o[15:0] <= mem_q[rd_addr];
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// big endien to little endien the following is the regular read, and it is
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// followed by the converted form
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//rd_data_o[29:16] <= mem_i[rd_addr][13:0];
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//rd_data_o[15:0] <= mem_q[rd_addr];
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//rd_data_o[31:30] <= cnt;
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//cnt <= cnt + 1;
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rd_data_o[31:24] <= mem_q[rd_addr][7:0];
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rd_data_o[23:16] <= mem_q[rd_addr][15:8];
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rd_data_o[15:8] <= mem_i[rd_addr][7:0];
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rd_data_o[7:0] <= mem_i[rd_addr][15:8];
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end else begin
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empty_o <= empty_o & (rd_addr == wr_addr);
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end
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@ -56,70 +67,3 @@ reg [DATA_WIDTH-1:0] mem_i[(1<<ADDR_WIDTH)-1:0];
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reg [DATA_WIDTH-1:0] mem_q[(1<<ADDR_WIDTH)-1:0];
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endmodule
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// generate dual clocked memory
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/*SB_RAM40_4K #(
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.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.WRITE_MODE(0),
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.READ_MODE(0)
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) ram256x16_i_inst (
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.RDATA(rd_data_o[31:16]),
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.RADDR(rd_addr),
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.RCLK(rd_clk_i),
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.RCLKE(1), //<<
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.RE(rd_en_i),
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.WADDR(wr_addr),
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.WCLK (wr_clk_i),
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.WCLKE(wr_en_i), //<<
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.WDATA(wr_data_i[31:16]),
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.WE(wr_en_i),
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.MASK(16'h0000) );
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SB_RAM40_4K #(
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.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.WRITE_MODE(0),
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.READ_MODE(0)
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) ram256x16_q_inst (
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.RDATA(rd_data_o[15:0]),
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.RADDR(rd_addr),
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.RCLK(rd_clk_i),
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.RCLKE(1), //<<
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.RE(rd_en_i),
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.WADDR(wr_addr),
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.WCLK (wr_clk_i),
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.WCLKE(wr_en_i), //<<
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.WDATA(wr_data_i[15:0]),
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.WE(wr_en_i),
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.MASK(16'h0000) );
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endmodule*/
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@ -59,9 +59,6 @@ module lvds_rx
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state_idle: begin
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if (i_ddr_data == modem_i_sync ) begin
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r_state_if <= state_i_phase;
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//r_data <= 0;
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//r_data[0] <= !r_cnt;
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//r_cnt = !r_cnt;
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end
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r_phase_count <= 3'b111;
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@ -100,4 +97,4 @@ module lvds_rx
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end
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endmodule // smi_ctrl
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endmodule
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@ -87,7 +87,7 @@ module smi_ctrl
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end
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// Tell the RPI that data is pending in either of the two fifos
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assign o_smi_read_req = !i_fifo_09_empty || !i_fifo_24_empty || i_smi_test;
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assign o_smi_read_req = !i_fifo_09_empty || !i_fifo_24_empty /*|| i_smi_test*/;
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reg [4:0] int_cnt_09;
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reg [4:0] int_cnt_24;
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15858
firmware/top.asc
15858
firmware/top.asc
Plik diff jest za duży
Load Diff
BIN
firmware/top.bin
BIN
firmware/top.bin
Plik binarny nie jest wyświetlany.
18585
firmware/top.json
18585
firmware/top.json
Plik diff jest za duży
Load Diff
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@ -287,7 +287,7 @@ module top(
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.empty_o (w_rx_09_fifo_empty)
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);
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/*lvds_rx lvds_rx_24_inst
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lvds_rx lvds_rx_24_inst
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(
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.i_reset (w_soft_reset),
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.i_ddr_clk (lvds_clock_buf),
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@ -309,7 +309,7 @@ module top(
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.rd_data_o (w_rx_24_fifo_pulled_data),
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.full_o (w_rx_24_fifo_full),
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.empty_o (w_rx_24_fifo_empty)
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);*/
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);
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smi_ctrl smi_ctrl_ins
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(
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@ -362,12 +362,12 @@ module top(
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// Testing - output the clock signal (positive and negative) to the PMOD
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// assign io_pmod[0] = lvds_clock_buf;
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//assign io_pmod[1] = w_rx_09_fifo_data[30];
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//assign io_pmod[2] = w_rx_09_fifo_data[31];
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assign io_pmod[3] = w_rx_09_fifo_push;
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assign io_pmod[4] = w_rx_09_fifo_pull;
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assign io_pmod[5] = w_rx_09_fifo_empty;
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assign io_pmod[6] = w_rx_09_fifo_full;
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assign io_pmod[7] = i_smi_soe_se;
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//assign io_pmod[2] = w_smi_read_req;
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//assign io_pmod[3] = w_rx_09_fifo_push;
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//assign io_pmod[4] = w_rx_09_fifo_pull;
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//assign io_pmod[5] = w_rx_09_fifo_empty;
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//assign io_pmod[6] = w_rx_09_fifo_full;
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//assign io_pmod[7] = i_smi_soe_se;
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//assign io_pmod[7] = w_smi_addr[1];
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@ -409,7 +409,7 @@ static void caribou_smi_print_smi_settings(struct smi_settings *settings)
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static void caribou_smi_setup_settings (struct smi_settings *settings)
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{
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settings->read_setup_time = 0;
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settings->read_strobe_time = 5;
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settings->read_strobe_time = 4;
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settings->read_hold_time = 0;
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settings->read_pace_time = 0;
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settings->write_setup_time = 1;
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@ -39,7 +39,7 @@ void caribou_smi_data_event(void *ctx, caribou_smi_stream_type_en type, caribou_
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if ( byte_count > 0 )
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{
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printf("CHUNK %d> %02x %02x %02x %02x...\n", c, buffer[0],
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buffer[1],
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buffer[1],
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buffer[2],
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buffer[3]);
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/*
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@ -100,12 +100,12 @@ void print_iq(uint32_t* array, int len)
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for (int i=0; i<len; i++)
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{
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unsigned int v = array[i];
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uint8_t b[4];
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/*uint8_t b[4];
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b[0] = (uint8_t) (v >> 24u);
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b[1] = (uint8_t) (v >> 16u);
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b[2] = (uint8_t) (v >> 8u);
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b[3] = (uint8_t) (v >> 0u);
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v = *((uint32_t*)(b));
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v = *((uint32_t*)(b));*/
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//printf("%08x\n", v);
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int cnt = (v >> 30) & 0x3;
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@ -129,7 +129,7 @@ void print_iq(uint32_t* array, int len)
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int main()
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{
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int count = 4096;
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/*int count = 4096;
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uint32_t buffer[count];
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uint8_t* b8 = (uint8_t*)buffer;
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@ -137,14 +137,11 @@ int main()
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caribou_smi_timeout_read(&dev, caribou_smi_address_read_900, b8, count*sizeof(uint32_t), 1000);
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dump_hex(b8, count*sizeof(uint32_t));
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print_iq(buffer, count);
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caribou_smi_close (&dev);
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return 0;
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return 0;*/
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caribou_smi_init(&dev, caribou_smi_error_event, program_name);
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int stream_id = caribou_smi_setup_stream(&dev,
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caribou_smi_stream_type_read,
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caribou_smi_channel_900,
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