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fifo 9 bit length, for 900 and 2.4, half tested

pull/18/head
meexmachina 2021-09-05 00:08:57 +03:00
rodzic 45f6076a30
commit ed59e9996a
9 zmienionych plików z 22075 dodań i 12492 usunięć
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84
firmware/complex_fifo.v
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@ -1,5 +1,5 @@
module complex_fifo #(
parameter ADDR_WIDTH = 8,
parameter ADDR_WIDTH = 9,
parameter DATA_WIDTH = 16
)
(
@ -36,16 +36,27 @@ always @(posedge wr_clk_i) begin
end
end
//reg [1:0] cnt;
always @(posedge rd_clk_i) begin
if (rd_rst_i) begin
rd_addr <= 0;
empty_o <= 1'b1;
//cnt <= 2'b00;
end else begin
if (rd_en_i) begin
rd_addr <= rd_addr + 1'b1;
empty_o <= (rd_addr + 1) == wr_addr;
rd_data_o[31:16] <= mem_i[rd_addr];
rd_data_o[15:0] <= mem_q[rd_addr];
// big endien to little endien the following is the regular read, and it is
// followed by the converted form
//rd_data_o[29:16] <= mem_i[rd_addr][13:0];
//rd_data_o[15:0] <= mem_q[rd_addr];
//rd_data_o[31:30] <= cnt;
//cnt <= cnt + 1;
rd_data_o[31:24] <= mem_q[rd_addr][7:0];
rd_data_o[23:16] <= mem_q[rd_addr][15:8];
rd_data_o[15:8] <= mem_i[rd_addr][7:0];
rd_data_o[7:0] <= mem_i[rd_addr][15:8];
end else begin
empty_o <= empty_o & (rd_addr == wr_addr);
end
@ -56,70 +67,3 @@ reg [DATA_WIDTH-1:0] mem_i[(1<<ADDR_WIDTH)-1:0];
reg [DATA_WIDTH-1:0] mem_q[(1<<ADDR_WIDTH)-1:0];
endmodule
// generate dual clocked memory
/*SB_RAM40_4K #(
.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.WRITE_MODE(0),
.READ_MODE(0)
) ram256x16_i_inst (
.RDATA(rd_data_o[31:16]),
.RADDR(rd_addr),
.RCLK(rd_clk_i),
.RCLKE(1), //<<
.RE(rd_en_i),
.WADDR(wr_addr),
.WCLK (wr_clk_i),
.WCLKE(wr_en_i), //<<
.WDATA(wr_data_i[31:16]),
.WE(wr_en_i),
.MASK(16'h0000) );
SB_RAM40_4K #(
.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.WRITE_MODE(0),
.READ_MODE(0)
) ram256x16_q_inst (
.RDATA(rd_data_o[15:0]),
.RADDR(rd_addr),
.RCLK(rd_clk_i),
.RCLKE(1), //<<
.RE(rd_en_i),
.WADDR(wr_addr),
.WCLK (wr_clk_i),
.WCLKE(wr_en_i), //<<
.WDATA(wr_data_i[15:0]),
.WE(wr_en_i),
.MASK(16'h0000) );
endmodule*/

5
firmware/lvds_rx.v
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@ -59,9 +59,6 @@ module lvds_rx
state_idle: begin
if (i_ddr_data == modem_i_sync ) begin
r_state_if <= state_i_phase;
//r_data <= 0;
//r_data[0] <= !r_cnt;
//r_cnt = !r_cnt;
end
r_phase_count <= 3'b111;
@ -100,4 +97,4 @@ module lvds_rx
end
endmodule // smi_ctrl
endmodule

2
firmware/smi_ctrl.v
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@ -87,7 +87,7 @@ module smi_ctrl
end
// Tell the RPI that data is pending in either of the two fifos
assign o_smi_read_req = !i_fifo_09_empty || !i_fifo_24_empty || i_smi_test;
assign o_smi_read_req = !i_fifo_09_empty || !i_fifo_24_empty /*|| i_smi_test*/;
reg [4:0] int_cnt_09;
reg [4:0] int_cnt_24;

15858
firmware/top.asc
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Plik diff jest za duży Load Diff

BIN
firmware/top.bin
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Plik binarny nie jest wyświetlany.

18585
firmware/top.json
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Plik diff jest za duży Load Diff

16
firmware/top.v
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@ -287,7 +287,7 @@ module top(
.empty_o (w_rx_09_fifo_empty)
);
/*lvds_rx lvds_rx_24_inst
lvds_rx lvds_rx_24_inst
(
.i_reset (w_soft_reset),
.i_ddr_clk (lvds_clock_buf),
@ -309,7 +309,7 @@ module top(
.rd_data_o (w_rx_24_fifo_pulled_data),
.full_o (w_rx_24_fifo_full),
.empty_o (w_rx_24_fifo_empty)
);*/
);
smi_ctrl smi_ctrl_ins
(
@ -362,12 +362,12 @@ module top(
// Testing - output the clock signal (positive and negative) to the PMOD
// assign io_pmod[0] = lvds_clock_buf;
//assign io_pmod[1] = w_rx_09_fifo_data[30];
//assign io_pmod[2] = w_rx_09_fifo_data[31];
assign io_pmod[3] = w_rx_09_fifo_push;
assign io_pmod[4] = w_rx_09_fifo_pull;
assign io_pmod[5] = w_rx_09_fifo_empty;
assign io_pmod[6] = w_rx_09_fifo_full;
assign io_pmod[7] = i_smi_soe_se;
//assign io_pmod[2] = w_smi_read_req;
//assign io_pmod[3] = w_rx_09_fifo_push;
//assign io_pmod[4] = w_rx_09_fifo_pull;
//assign io_pmod[5] = w_rx_09_fifo_empty;
//assign io_pmod[6] = w_rx_09_fifo_full;
//assign io_pmod[7] = i_smi_soe_se;
//assign io_pmod[7] = w_smi_addr[1];

2
software/libcariboulite/src/caribou_smi/caribou_smi.c
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@ -409,7 +409,7 @@ static void caribou_smi_print_smi_settings(struct smi_settings *settings)
static void caribou_smi_setup_settings (struct smi_settings *settings)
{
settings->read_setup_time = 0;
settings->read_strobe_time = 5;
settings->read_strobe_time = 4;
settings->read_hold_time = 0;
settings->read_pace_time = 0;
settings->write_setup_time = 1;

15
software/libcariboulite/src/caribou_smi/test_caribou_smi.c
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@ -39,7 +39,7 @@ void caribou_smi_data_event(void *ctx, caribou_smi_stream_type_en type, caribou_
if ( byte_count > 0 )
{
printf("CHUNK %d> %02x %02x %02x %02x...\n", c, buffer[0],
buffer[1],
buffer[1],
buffer[2],
buffer[3]);
/*
@ -100,12 +100,12 @@ void print_iq(uint32_t* array, int len)
for (int i=0; i<len; i++)
{
unsigned int v = array[i];
uint8_t b[4];
/*uint8_t b[4];
b[0] = (uint8_t) (v >> 24u);
b[1] = (uint8_t) (v >> 16u);
b[2] = (uint8_t) (v >> 8u);
b[3] = (uint8_t) (v >> 0u);
v = *((uint32_t*)(b));
v = *((uint32_t*)(b));*/
//printf("%08x\n", v);
int cnt = (v >> 30) & 0x3;
@ -129,7 +129,7 @@ void print_iq(uint32_t* array, int len)
int main()
{
int count = 4096;
/*int count = 4096;
uint32_t buffer[count];
uint8_t* b8 = (uint8_t*)buffer;
@ -137,14 +137,11 @@ int main()
caribou_smi_timeout_read(&dev, caribou_smi_address_read_900, b8, count*sizeof(uint32_t), 1000);
dump_hex(b8, count*sizeof(uint32_t));
print_iq(buffer, count);
caribou_smi_close (&dev);
return 0;
return 0;*/
caribou_smi_init(&dev, caribou_smi_error_event, program_name);
int stream_id = caribou_smi_setup_stream(&dev,
caribou_smi_stream_type_read,
caribou_smi_channel_900,