kopia lustrzana https://github.com/cariboulabs/cariboulite
firmware: fixed short circuit during RX
rodzic
c30f2ef911
commit
bb3cd45dd2
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@ -493,6 +493,7 @@ module top (
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wire w_smi_read_req;
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wire w_smi_read_req;
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wire w_smi_write_req;
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wire w_smi_write_req;
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wire w_smi_data_direction;
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wire w_smi_data_direction;
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wire w_smi_data_output_enable;
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// the "Writing" flag indicates that the data[7:0] direction (inout)
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// the "Writing" flag indicates that the data[7:0] direction (inout)
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// from the FPGA's SMI module should be "output". This happens when the
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// from the FPGA's SMI module should be "output". This happens when the
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@ -501,78 +502,23 @@ module top (
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// the data is high-z, which is the more "recessive" mode
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// the data is high-z, which is the more "recessive" mode
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assign w_smi_data_direction = i_smi_a2;
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assign w_smi_data_direction = i_smi_a2;
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assign w_smi_data_output_enable = i_smi_a2 & !i_smi_soe_se;
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genvar k;
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generate
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for (k=0; k<8;k++) begin
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SB_IO #(
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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.PULLUP (1'b0)
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) smi_io0 (
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) smi_io0 (
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.PACKAGE_PIN(io_smi_data[0]),
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.PACKAGE_PIN(io_smi_data[k]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.OUTPUT_ENABLE(w_smi_data_output_enable),
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.D_OUT_0(w_smi_data_output[0]),
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.D_OUT_0(w_smi_data_output[k]),
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.D_IN_0(w_smi_data_input[0])
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.D_IN_0(w_smi_data_input[k])
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);
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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) smi_io1 (
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.PACKAGE_PIN(io_smi_data[1]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.D_OUT_0(w_smi_data_output[1]),
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.D_IN_0(w_smi_data_input[1])
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);
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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) smi_io2 (
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.PACKAGE_PIN(io_smi_data[2]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.D_OUT_0(w_smi_data_output[2]),
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.D_IN_0(w_smi_data_input[2])
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);
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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) smi_io3 (
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.PACKAGE_PIN(io_smi_data[3]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.D_OUT_0(w_smi_data_output[3]),
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.D_IN_0(w_smi_data_input[3])
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);
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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) smi_io4 (
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.PACKAGE_PIN(io_smi_data[4]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.D_OUT_0(w_smi_data_output[4]),
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.D_IN_0(w_smi_data_input[4])
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);
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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) smi_io5 (
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.PACKAGE_PIN(io_smi_data[5]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.D_OUT_0(w_smi_data_output[5]),
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.D_IN_0(w_smi_data_input[5])
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);
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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) smi_io6 (
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.PACKAGE_PIN(io_smi_data[6]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.D_OUT_0(w_smi_data_output[6]),
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.D_IN_0(w_smi_data_input[6])
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);
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SB_IO #(
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.PIN_TYPE(6'b1010_01),
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.PULLUP (1'b0)
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) smi_io7 (
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.PACKAGE_PIN(io_smi_data[7]),
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.OUTPUT_ENABLE(w_smi_data_direction),
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.D_OUT_0(w_smi_data_output[7]),
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.D_IN_0(w_smi_data_input[7])
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);
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);
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end
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endgenerate
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// We need the 'o_smi_write_req' to be 1 only when the direction is TX
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// We need the 'o_smi_write_req' to be 1 only when the direction is TX
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// (w_smi_data_direction == 0) and the write fifo is not full
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// (w_smi_data_direction == 0) and the write fifo is not full
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