kopia lustrzana https://github.com/cariboulabs/cariboulite
added kernel modules
meexmachina
rodzic
d9e774d0de
commit
b3f34b9f4e
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@ -0,0 +1,20 @@
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// Description: Overlay to enable character device interface for SMI.
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// Author: Luke Wren <luke@raspberrypi.org>
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/dts-v1/;
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/plugin/;
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/{
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compatible = "brcm,bcm2835";
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fragment@0 {
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target = <&soc>;
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__overlay__ {
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smi_dev {
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compatible = "brcm,bcm2835-smi-dev";
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smi_handle = <&smi>;
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status = "okay";
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};
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};
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};
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};
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@ -0,0 +1,37 @@
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// Description: Overlay to enable the secondary memory interface peripheral
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// Author: Luke Wren
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/dts-v1/;
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/plugin/;
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/{
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compatible = "brcm,bcm2835";
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fragment@0 {
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target = <&smi>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&smi_pins>;
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status = "okay";
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};
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};
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fragment@1 {
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target = <&gpio>;
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__overlay__ {
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smi_pins: smi_pins {
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/* Don't configure the top two address bits, as
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these are already used as ID_SD and ID_SC */
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brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23 24 25>;
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/* Alt 1: SMI */
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brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
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5 5 5 5 5 5 5 5 5>;
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/* /CS, /WE and /OE are pulled high, as they are
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generally active low signals */
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brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0>;
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};
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};
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};
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};
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@ -0,0 +1,391 @@
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/**
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* Declarations and definitions for Broadcom's Secondary Memory Interface
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*
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* Written by Luke Wren <luke@raspberrypi.org>
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* Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
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* Copyright (c) 2010-2012 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef BCM2835_SMI_H
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#define BCM2835_SMI_H
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#include <linux/ioctl.h>
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#ifndef __KERNEL__
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#include <stdint.h>
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#include <stdbool.h>
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#endif
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#define BCM2835_SMI_IOC_MAGIC 0x1
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#define BCM2835_SMI_INVALID_HANDLE (~0)
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/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
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#define BCM2835_SMI_IOC_GET_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 0)
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#define BCM2835_SMI_IOC_WRITE_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 1)
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#define BCM2835_SMI_IOC_ADDRESS _IO(BCM2835_SMI_IOC_MAGIC, 2)
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#define BCM2835_SMI_IOC_MAX 2
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#define SMI_WIDTH_8BIT 0
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#define SMI_WIDTH_16BIT 1
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#define SMI_WIDTH_9BIT 2
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#define SMI_WIDTH_18BIT 3
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/* max number of bytes where DMA will not be used */
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#define DMA_THRESHOLD_BYTES 128
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#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
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#define DMA_BOUNCE_BUFFER_COUNT 3
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struct smi_settings {
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int data_width;
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/* Whether or not to pack multiple SMI transfers into a
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single 32 bit FIFO word */
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bool pack_data;
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/* Timing for reads (writes the same but for WE)
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*
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* OE ----------+ +--------------------
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* | |
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* +----------+
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* SD -<==============================>-----------
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* SA -<=========================================>-
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* <-setup-> <-strobe -> <-hold -> <- pace ->
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*/
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int read_setup_time;
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int read_hold_time;
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int read_pace_time;
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int read_strobe_time;
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int write_setup_time;
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int write_hold_time;
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int write_pace_time;
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int write_strobe_time;
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bool dma_enable; /* DREQs */
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bool dma_passthrough_enable; /* External DREQs */
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int dma_read_thresh;
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int dma_write_thresh;
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int dma_panic_read_thresh;
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int dma_panic_write_thresh;
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};
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/****************************************************************************
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*
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* Declare exported SMI functions
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*
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***************************************************************************/
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#ifdef __KERNEL__
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#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
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#include <linux/of.h>
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#include <linux/semaphore.h>
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struct bcm2835_smi_instance;
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struct bcm2835_smi_bounce_info {
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struct semaphore callback_sem;
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void *buffer[DMA_BOUNCE_BUFFER_COUNT];
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dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
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struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
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};
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void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
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struct smi_settings *bcm2835_smi_get_settings_from_regs(
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struct bcm2835_smi_instance *inst);
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void bcm2835_smi_write_buf(
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struct bcm2835_smi_instance *inst,
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const void *buf,
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size_t n_bytes);
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void bcm2835_smi_read_buf(
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struct bcm2835_smi_instance *inst,
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void *buf,
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size_t n_bytes);
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void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
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unsigned int address);
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ssize_t bcm2835_smi_user_dma(
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struct bcm2835_smi_instance *inst,
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enum dma_transfer_direction dma_dir,
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char __user *user_ptr,
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size_t count,
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struct bcm2835_smi_bounce_info **bounce);
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struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
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#endif /* __KERNEL__ */
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/****************************************************************
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*
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* Implementation-only declarations
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*
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****************************************************************/
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#ifdef BCM2835_SMI_IMPLEMENTATION
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/* Clock manager registers for SMI clock: */
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#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
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/* Clock manager "password" to protect registers from spurious writes */
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#define CM_PWD (0x5a << 24)
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#define CM_SMI_CTL 0x00
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#define CM_SMI_DIV 0x04
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#define CM_SMI_CTL_FLIP (1 << 8)
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#define CM_SMI_CTL_BUSY (1 << 7)
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#define CM_SMI_CTL_KILL (1 << 5)
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#define CM_SMI_CTL_ENAB (1 << 4)
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#define CM_SMI_CTL_SRC_MASK (0xf)
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#define CM_SMI_CTL_SRC_OFFS (0)
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#define CM_SMI_DIV_DIVI_MASK (0xf << 12)
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#define CM_SMI_DIV_DIVI_OFFS (12)
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#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
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#define CM_SMI_DIV_DIVF_OFFS (4)
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/* SMI register mapping:*/
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#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
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#define SMICS 0x00 /* control + status register */
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#define SMIL 0x04 /* length/count (n external txfers) */
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#define SMIA 0x08 /* address register */
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#define SMID 0x0c /* data register */
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#define SMIDSR0 0x10 /* device 0 read settings */
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#define SMIDSW0 0x14 /* device 0 write settings */
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#define SMIDSR1 0x18 /* device 1 read settings */
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#define SMIDSW1 0x1c /* device 1 write settings */
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#define SMIDSR2 0x20 /* device 2 read settings */
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#define SMIDSW2 0x24 /* device 2 write settings */
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#define SMIDSR3 0x28 /* device 3 read settings */
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#define SMIDSW3 0x2c /* device 3 write settings */
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#define SMIDC 0x30 /* DMA control registers */
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#define SMIDCS 0x34 /* direct control/status register */
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#define SMIDA 0x38 /* direct address register */
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#define SMIDD 0x3c /* direct data registers */
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#define SMIFD 0x40 /* FIFO debug register */
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/* Control and Status register bits:
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* SMICS_RXF : RX fifo full: 1 when RX fifo is full
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* SMICS_TXE : TX fifo empty: 1 when empty.
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* SMICS_RXD : RX fifo contains data: 1 when there is data.
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* SMICS_TXD : TX fifo can accept data: 1 when true.
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* SMICS_RXR : RX fifo needs reading: 1 when fifo more than 3/4 full, or
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* when "DONE" and fifo not emptied.
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* SMICS_TXW : TX fifo needs writing: 1 when less than 1/4 full.
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* SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written
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* when full. Write 1 to clear.
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* SMICS_EDREQ : 1 when external DREQ received.
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* SMICS_PXLDAT : Pixel data: write 1 to enable pixel transfer modes.
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* SMICS_SETERR : 1 if there was an error writing to setup regs (e.g.
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* tx was in progress). Write 1 to clear.
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* SMICS_PVMODE : Set to 1 to enable pixel valve mode.
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* SMICS_INTR : Set to 1 to enable interrupt on RX.
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* SMICS_INTT : Set to 1 to enable interrupt on TX.
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* SMICS_INTD : Set to 1 to enable interrupt on DONE condition.
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* SMICS_TEEN : Tear effect mode enabled: Programmed transfers will wait
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* for a TE trigger before writing.
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* SMICS_PAD1 : Padding settings for external transfers. For writes: the
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* number of bytes initially written to the TX fifo that
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* SMICS_PAD0 : should be ignored. For reads: the number of bytes that will
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* be read before the data, and should be dropped.
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* SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read
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* SMICS_CLEAR : Write 1 to clear the FIFOs.
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* SMICS_START : Write 1 to start the programmed transfer.
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* SMICS_ACTIVE : Reads as 1 when a programmed transfer is underway.
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* SMICS_DONE : Reads as 1 when transfer finished. For RX, not set until
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* FIFO emptied.
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* SMICS_ENABLE : Set to 1 to enable the SMI peripheral, 0 to disable.
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*/
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#define SMICS_RXF (1 << 31)
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#define SMICS_TXE (1 << 30)
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#define SMICS_RXD (1 << 29)
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#define SMICS_TXD (1 << 28)
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#define SMICS_RXR (1 << 27)
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#define SMICS_TXW (1 << 26)
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#define SMICS_AFERR (1 << 25)
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#define SMICS_EDREQ (1 << 15)
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#define SMICS_PXLDAT (1 << 14)
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#define SMICS_SETERR (1 << 13)
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#define SMICS_PVMODE (1 << 12)
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#define SMICS_INTR (1 << 11)
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#define SMICS_INTT (1 << 10)
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#define SMICS_INTD (1 << 9)
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#define SMICS_TEEN (1 << 8)
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#define SMICS_PAD1 (1 << 7)
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#define SMICS_PAD0 (1 << 6)
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#define SMICS_WRITE (1 << 5)
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#define SMICS_CLEAR (1 << 4)
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#define SMICS_START (1 << 3)
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#define SMICS_ACTIVE (1 << 2)
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#define SMICS_DONE (1 << 1)
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#define SMICS_ENABLE (1 << 0)
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/* Address register bits: */
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#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
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#define SMIA_DEVICE_OFFS (8)
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#define SMIA_ADDR_MASK (0x3f) /* bits 5 -> 0 */
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#define SMIA_ADDR_OFFS (0)
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/* DMA control register bits:
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* SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued.
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* SMIDC_DMAP : DMA passthrough: when set to 0, top two data pins are used by
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* SMI as usual. When set to 1, the top two pins are used for
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* external DREQs: pin 16 read request, 17 write.
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* SMIDC_PANIC* : Threshold at which DMA will panic during read/write.
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* SMIDC_REQ* : Threshold at which DMA will generate a DREQ.
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*/
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#define SMIDC_DMAEN (1 << 28)
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#define SMIDC_DMAP (1 << 24)
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#define SMIDC_PANICR_MASK (0x3f << 18)
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#define SMIDC_PANICR_OFFS (18)
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#define SMIDC_PANICW_MASK (0x3f << 12)
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#define SMIDC_PANICW_OFFS (12)
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#define SMIDC_REQR_MASK (0x3f << 6)
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#define SMIDC_REQR_OFFS (6)
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#define SMIDC_REQW_MASK (0x3f)
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#define SMIDC_REQW_OFFS (0)
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/* Device settings register bits: same for all 4 (or 3?) device register sets.
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* Device read settings:
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* SMIDSR_RWIDTH : Read transfer width. 00 = 8bit, 01 = 16bit,
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* 10 = 18bit, 11 = 9bit.
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* SMIDSR_RSETUP : Read setup time: number of core cycles between chip
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* select/address and read strobe. Min 1, max 64.
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* SMIDSR_MODE68 : 1 for System 68 mode (i.e. enable + direction pins,
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* rather than OE + WE pin)
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* SMIDSR_FSETUP : If set to 1, setup time only applies to first
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* transfer after address change.
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* SMIDSR_RHOLD : Number of core cycles between read strobe going
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* inactive and CS/address going inactive. Min 1, max 64
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* SMIDSR_RPACEALL : When set to 1, this device's RPACE value will always
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* be used for the next transaction, even if it is not
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* to this device.
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* SMIDSR_RPACE : Number of core cycles spent waiting between CS
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* deassert and start of next transfer. Min 1, max 128
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* SMIDSR_RDREQ : 1 = use external DMA request on SD16 to pace reads
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* from device. Must also set DMAP in SMICS.
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* SMIDSR_RSTROBE : Number of cycles to assert the read strobe.
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* min 1, max 128.
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*/
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#define SMIDSR_RWIDTH_MASK ((1<<31)|(1<<30))
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#define SMIDSR_RWIDTH_OFFS (30)
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#define SMIDSR_RSETUP_MASK (0x3f << 24)
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#define SMIDSR_RSETUP_OFFS (24)
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#define SMIDSR_MODE68 (1 << 23)
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#define SMIDSR_FSETUP (1 << 22)
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#define SMIDSR_RHOLD_MASK (0x3f << 16)
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#define SMIDSR_RHOLD_OFFS (16)
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#define SMIDSR_RPACEALL (1 << 15)
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#define SMIDSR_RPACE_MASK (0x7f << 8)
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#define SMIDSR_RPACE_OFFS (8)
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#define SMIDSR_RDREQ (1 << 7)
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#define SMIDSR_RSTROBE_MASK (0x7f)
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#define SMIDSR_RSTROBE_OFFS (0)
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/* Device write settings:
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* SMIDSW_WWIDTH : Write transfer width. 00 = 8bit, 01 = 16bit,
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* 10= 18bit, 11 = 9bit.
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* SMIDSW_WSETUP : Number of cycles between CS assert and write strobe.
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* Min 1, max 64.
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* SMIDSW_WFORMAT : Pixel format of input. 0 = 16bit RGB 565,
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* 1 = 32bit RGBA 8888
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* SMIDSW_WSWAP : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
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* SMIDSW_WHOLD : Time between WE deassert and CS deassert. 1 to 64
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* SMIDSW_WPACEALL : 1: this device's WPACE will be used for the next
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* transfer, regardless of that transfer's device.
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* SMIDSW_WPACE : Cycles between CS deassert and next CS assert.
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* Min 1, max 128
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* SMIDSW_WDREQ : Use external DREQ on pin 17 to pace writes. DMAP must
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* be set in SMICS.
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* SMIDSW_WSTROBE : Number of cycles to assert the write strobe.
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* Min 1, max 128
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*/
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#define SMIDSW_WWIDTH_MASK ((1<<31)|(1<<30))
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#define SMIDSW_WWIDTH_OFFS (30)
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#define SMIDSW_WSETUP_MASK (0x3f << 24)
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#define SMIDSW_WSETUP_OFFS (24)
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#define SMIDSW_WFORMAT (1 << 23)
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#define SMIDSW_WSWAP (1 << 22)
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#define SMIDSW_WHOLD_MASK (0x3f << 16)
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#define SMIDSW_WHOLD_OFFS (16)
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#define SMIDSW_WPACEALL (1 << 15)
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#define SMIDSW_WPACE_MASK (0x7f << 8)
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#define SMIDSW_WPACE_OFFS (8)
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#define SMIDSW_WDREQ (1 << 7)
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#define SMIDSW_WSTROBE_MASK (0x7f)
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#define SMIDSW_WSTROBE_OFFS (0)
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|
||||
/* Direct transfer control + status register
|
||||
* SMIDCS_WRITE : Direction of transfer: 1 -> write, 0 -> read
|
||||
* SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear.
|
||||
* SMIDCS_START : Write 1 to start a transfer, if one is not already underway.
|
||||
* SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
|
||||
*/
|
||||
|
||||
#define SMIDCS_WRITE (1 << 3)
|
||||
#define SMIDCS_DONE (1 << 2)
|
||||
#define SMIDCS_START (1 << 1)
|
||||
#define SMIDCS_ENABLE (1 << 0)
|
||||
|
||||
/* Direct transfer address register
|
||||
* SMIDA_DEVICE : Indicates which of the device settings banks should be used.
|
||||
* SMIDA_ADDR : The value to be asserted on the address pins.
|
||||
*/
|
||||
|
||||
#define SMIDA_DEVICE_MASK ((1<<9)|(1<<8))
|
||||
#define SMIDA_DEVICE_OFFS (8)
|
||||
#define SMIDA_ADDR_MASK (0x3f)
|
||||
#define SMIDA_ADDR_OFFS (0)
|
||||
|
||||
/* FIFO debug register
|
||||
* SMIFD_FLVL : The high-tide mark of FIFO count during the most recent txfer
|
||||
* SMIFD_FCNT : The current FIFO count.
|
||||
*/
|
||||
#define SMIFD_FLVL_MASK (0x3f << 8)
|
||||
#define SMIFD_FLVL_OFFS (8)
|
||||
#define SMIFD_FCNT_MASK (0x3f)
|
||||
#define SMIFD_FCNT_OFFS (0)
|
||||
|
||||
#endif /* BCM2835_SMI_IMPLEMENTATION */
|
||||
|
||||
#endif /* BCM2835_SMI_H */
|
||||
|
|
@ -0,0 +1,402 @@
|
|||
/**
|
||||
* Character device driver for Broadcom Secondary Memory Interface
|
||||
*
|
||||
* Written by Luke Wren <luke@raspberrypi.org>
|
||||
* Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The names of the above-listed copyright holders may not be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") version 2, as published by the Free
|
||||
* Software Foundation.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/fs.h>
|
||||
|
||||
#include <linux/broadcom/bcm2835_smi.h>
|
||||
|
||||
#define DEVICE_NAME "bcm2835-smi-dev"
|
||||
#define DRIVER_NAME "smi-dev-bcm2835"
|
||||
#define DEVICE_MINOR 0
|
||||
|
||||
static struct cdev bcm2835_smi_cdev;
|
||||
static dev_t bcm2835_smi_devid;
|
||||
static struct class *bcm2835_smi_class;
|
||||
static struct device *bcm2835_smi_dev;
|
||||
|
||||
struct bcm2835_smi_dev_instance {
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
static struct bcm2835_smi_instance *smi_inst;
|
||||
static struct bcm2835_smi_dev_instance *inst;
|
||||
|
||||
static const char *const ioctl_names[] = {
|
||||
"READ_SETTINGS",
|
||||
"WRITE_SETTINGS",
|
||||
"ADDRESS"
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* SMI chardev file ops
|
||||
*
|
||||
***************************************************************************/
|
||||
static long
|
||||
bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
long ret = 0;
|
||||
|
||||
dev_info(inst->dev, "serving ioctl...");
|
||||
|
||||
switch (cmd) {
|
||||
case BCM2835_SMI_IOC_GET_SETTINGS:{
|
||||
struct smi_settings *settings;
|
||||
|
||||
dev_info(inst->dev, "Reading SMI settings to user.");
|
||||
settings = bcm2835_smi_get_settings_from_regs(smi_inst);
|
||||
if (copy_to_user((void *)arg, settings,
|
||||
sizeof(struct smi_settings)))
|
||||
dev_err(inst->dev, "settings copy failed.");
|
||||
break;
|
||||
}
|
||||
case BCM2835_SMI_IOC_WRITE_SETTINGS:{
|
||||
struct smi_settings *settings;
|
||||
|
||||
dev_info(inst->dev, "Setting user's SMI settings.");
|
||||
settings = bcm2835_smi_get_settings_from_regs(smi_inst);
|
||||
if (copy_from_user(settings, (void *)arg,
|
||||
sizeof(struct smi_settings)))
|
||||
dev_err(inst->dev, "settings copy failed.");
|
||||
else
|
||||
bcm2835_smi_set_regs_from_settings(smi_inst);
|
||||
break;
|
||||
}
|
||||
case BCM2835_SMI_IOC_ADDRESS:
|
||||
dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg);
|
||||
bcm2835_smi_set_address(smi_inst, arg);
|
||||
break;
|
||||
default:
|
||||
dev_err(inst->dev, "invalid ioctl cmd: %d", cmd);
|
||||
ret = -ENOTTY;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bcm2835_smi_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
int dev = iminor(inode);
|
||||
|
||||
dev_dbg(inst->dev, "SMI device opened.");
|
||||
|
||||
if (dev != DEVICE_MINOR) {
|
||||
dev_err(inst->dev,
|
||||
"bcm2835_smi_release: Unknown minor device: %d",
|
||||
dev);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_smi_release(struct inode *inode, struct file *file)
|
||||
{
|
||||
int dev = iminor(inode);
|
||||
|
||||
if (dev != DEVICE_MINOR) {
|
||||
dev_err(inst->dev,
|
||||
"bcm2835_smi_release: Unknown minor device %d", dev);
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t dma_bounce_user(
|
||||
enum dma_transfer_direction dma_dir,
|
||||
char __user *user_ptr,
|
||||
size_t count,
|
||||
struct bcm2835_smi_bounce_info *bounce)
|
||||
{
|
||||
int chunk_size;
|
||||
int chunk_no = 0;
|
||||
int count_left = count;
|
||||
|
||||
while (count_left) {
|
||||
int rv;
|
||||
void *buf;
|
||||
|
||||
/* Wait for current chunk to complete: */
|
||||
if (down_timeout(&bounce->callback_sem,
|
||||
msecs_to_jiffies(1000))) {
|
||||
dev_err(inst->dev, "DMA bounce timed out");
|
||||
count -= (count_left);
|
||||
break;
|
||||
}
|
||||
|
||||
if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)
|
||||
dev_err(inst->dev, "WARNING: Ring buffer overflow");
|
||||
chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
|
||||
DMA_BOUNCE_BUFFER_SIZE : count_left;
|
||||
buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
|
||||
if (dma_dir == DMA_DEV_TO_MEM)
|
||||
rv = copy_to_user(user_ptr, buf, chunk_size);
|
||||
else
|
||||
rv = copy_from_user(buf, user_ptr, chunk_size);
|
||||
if (rv)
|
||||
dev_err(inst->dev, "copy_*_user() failed!: %d", rv);
|
||||
user_ptr += chunk_size;
|
||||
count_left -= chunk_size;
|
||||
chunk_no++;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
bcm2835_read_file(struct file *f, char __user *user_ptr,
|
||||
size_t count, loff_t *offs)
|
||||
{
|
||||
int odd_bytes;
|
||||
|
||||
dev_dbg(inst->dev, "User reading %zu bytes from SMI.", count);
|
||||
/* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */
|
||||
if (count > DMA_THRESHOLD_BYTES)
|
||||
odd_bytes = count & 0x3;
|
||||
else
|
||||
odd_bytes = count;
|
||||
count -= odd_bytes;
|
||||
if (count) {
|
||||
struct bcm2835_smi_bounce_info *bounce;
|
||||
|
||||
count = bcm2835_smi_user_dma(smi_inst,
|
||||
DMA_DEV_TO_MEM, user_ptr, count,
|
||||
&bounce);
|
||||
if (count)
|
||||
count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,
|
||||
count, bounce);
|
||||
}
|
||||
if (odd_bytes) {
|
||||
/* Read from FIFO directly if not using DMA */
|
||||
uint8_t buf[DMA_THRESHOLD_BYTES];
|
||||
|
||||
bcm2835_smi_read_buf(smi_inst, buf, odd_bytes);
|
||||
if (copy_to_user(user_ptr, buf, odd_bytes))
|
||||
dev_err(inst->dev, "copy_to_user() failed.");
|
||||
count += odd_bytes;
|
||||
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t
|
||||
bcm2835_write_file(struct file *f, const char __user *user_ptr,
|
||||
size_t count, loff_t *offs)
|
||||
{
|
||||
int odd_bytes;
|
||||
|
||||
dev_dbg(inst->dev, "User writing %zu bytes to SMI.", count);
|
||||
if (count > DMA_THRESHOLD_BYTES)
|
||||
odd_bytes = count & 0x3;
|
||||
else
|
||||
odd_bytes = count;
|
||||
count -= odd_bytes;
|
||||
if (count) {
|
||||
struct bcm2835_smi_bounce_info *bounce;
|
||||
|
||||
count = bcm2835_smi_user_dma(smi_inst,
|
||||
DMA_MEM_TO_DEV, (char __user *)user_ptr, count,
|
||||
&bounce);
|
||||
if (count)
|
||||
count = dma_bounce_user(DMA_MEM_TO_DEV,
|
||||
(char __user *)user_ptr,
|
||||
count, bounce);
|
||||
}
|
||||
if (odd_bytes) {
|
||||
uint8_t buf[DMA_THRESHOLD_BYTES];
|
||||
|
||||
if (copy_from_user(buf, user_ptr, odd_bytes))
|
||||
dev_err(inst->dev, "copy_from_user() failed.");
|
||||
else
|
||||
bcm2835_smi_write_buf(smi_inst, buf, odd_bytes);
|
||||
count += odd_bytes;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static const struct file_operations
|
||||
bcm2835_smi_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.unlocked_ioctl = bcm2835_smi_ioctl,
|
||||
.open = bcm2835_smi_open,
|
||||
.release = bcm2835_smi_release,
|
||||
.read = bcm2835_read_file,
|
||||
.write = bcm2835_write_file,
|
||||
};
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* bcm2835_smi_probe - called when the driver is loaded.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
static int bcm2835_smi_dev_probe(struct platform_device *pdev)
|
||||
{
|
||||
int err;
|
||||
void *ptr_err;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->of_node, *smi_node;
|
||||
|
||||
if (!node) {
|
||||
dev_err(dev, "No device tree node supplied!");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
smi_node = of_parse_phandle(node, "smi_handle", 0);
|
||||
|
||||
if (!smi_node) {
|
||||
dev_err(dev, "No such property: smi_handle");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
smi_inst = bcm2835_smi_get(smi_node);
|
||||
|
||||
if (!smi_inst)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
/* Allocate buffers and instance data */
|
||||
|
||||
inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
|
||||
|
||||
if (!inst)
|
||||
return -ENOMEM;
|
||||
|
||||
inst->dev = dev;
|
||||
|
||||
/* Create character device entries */
|
||||
|
||||
err = alloc_chrdev_region(&bcm2835_smi_devid,
|
||||
DEVICE_MINOR, 1, DEVICE_NAME);
|
||||
if (err != 0) {
|
||||
dev_err(inst->dev, "unable to allocate device number");
|
||||
return -ENOMEM;
|
||||
}
|
||||
cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);
|
||||
bcm2835_smi_cdev.owner = THIS_MODULE;
|
||||
err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);
|
||||
if (err != 0) {
|
||||
dev_err(inst->dev, "unable to register device");
|
||||
err = -ENOMEM;
|
||||
goto failed_cdev_add;
|
||||
}
|
||||
|
||||
/* Create sysfs entries */
|
||||
|
||||
bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);
|
||||
ptr_err = bcm2835_smi_class;
|
||||
if (IS_ERR(ptr_err))
|
||||
goto failed_class_create;
|
||||
|
||||
bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,
|
||||
bcm2835_smi_devid, NULL,
|
||||
"smi");
|
||||
ptr_err = bcm2835_smi_dev;
|
||||
if (IS_ERR(ptr_err))
|
||||
goto failed_device_create;
|
||||
|
||||
dev_info(inst->dev, "initialised");
|
||||
|
||||
return 0;
|
||||
|
||||
failed_device_create:
|
||||
class_destroy(bcm2835_smi_class);
|
||||
failed_class_create:
|
||||
cdev_del(&bcm2835_smi_cdev);
|
||||
err = PTR_ERR(ptr_err);
|
||||
failed_cdev_add:
|
||||
unregister_chrdev_region(bcm2835_smi_devid, 1);
|
||||
dev_err(dev, "could not load bcm2835_smi_dev");
|
||||
return err;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* bcm2835_smi_remove - called when the driver is unloaded.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
static int bcm2835_smi_dev_remove(struct platform_device *pdev)
|
||||
{
|
||||
device_destroy(bcm2835_smi_class, bcm2835_smi_devid);
|
||||
class_destroy(bcm2835_smi_class);
|
||||
cdev_del(&bcm2835_smi_cdev);
|
||||
unregister_chrdev_region(bcm2835_smi_devid, 1);
|
||||
|
||||
dev_info(inst->dev, "SMI character dev removed - OK");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Register the driver with device tree
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
static const struct of_device_id bcm2835_smi_dev_of_match[] = {
|
||||
{.compatible = "brcm,bcm2835-smi-dev",},
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);
|
||||
|
||||
static struct platform_driver bcm2835_smi_dev_driver = {
|
||||
.probe = bcm2835_smi_dev_probe,
|
||||
.remove = bcm2835_smi_dev_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = bcm2835_smi_dev_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(bcm2835_smi_dev_driver);
|
||||
|
||||
MODULE_ALIAS("platform:smi-dev-bcm2835");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION(
|
||||
"Character device driver for BCM2835's secondary memory interface");
|
||||
MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
/**
|
||||
* NAND flash driver for Broadcom Secondary Memory Interface
|
||||
*
|
||||
* Written by Luke Wren <luke@raspberrypi.org>
|
||||
* Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The names of the above-listed copyright holders may not be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") version 2, as published by the Free
|
||||
* Software Foundation.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
|
||||
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
|
||||
#include <linux/broadcom/bcm2835_smi.h>
|
||||
|
||||
#define DEVICE_NAME "bcm2835-smi-nand"
|
||||
#define DRIVER_NAME "smi-nand-bcm2835"
|
||||
|
||||
struct bcm2835_smi_nand_host {
|
||||
struct bcm2835_smi_instance *smi_inst;
|
||||
struct nand_chip nand_chip;
|
||||
struct mtd_info mtd;
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* NAND functionality implementation
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#define SMI_NAND_CLE_PIN 0x01
|
||||
#define SMI_NAND_ALE_PIN 0x02
|
||||
|
||||
static inline void bcm2835_smi_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
|
||||
unsigned int ctrl)
|
||||
{
|
||||
uint32_t cmd32 = cmd;
|
||||
uint32_t addr = ~(SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN);
|
||||
struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
|
||||
struct bcm2835_smi_instance *inst = host->smi_inst;
|
||||
|
||||
if (ctrl & NAND_CLE)
|
||||
addr |= SMI_NAND_CLE_PIN;
|
||||
if (ctrl & NAND_ALE)
|
||||
addr |= SMI_NAND_ALE_PIN;
|
||||
/* Lower ALL the CS pins! */
|
||||
if (ctrl & NAND_NCE)
|
||||
addr &= (SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN);
|
||||
|
||||
bcm2835_smi_set_address(inst, addr);
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
bcm2835_smi_write_buf(inst, &cmd32, 1);
|
||||
}
|
||||
|
||||
static inline uint8_t bcm2835_smi_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
uint8_t byte;
|
||||
struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
|
||||
struct bcm2835_smi_instance *inst = host->smi_inst;
|
||||
|
||||
bcm2835_smi_read_buf(inst, &byte, 1);
|
||||
return byte;
|
||||
}
|
||||
|
||||
static inline void bcm2835_smi_nand_write_byte(struct mtd_info *mtd,
|
||||
uint8_t byte)
|
||||
{
|
||||
struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
|
||||
struct bcm2835_smi_instance *inst = host->smi_inst;
|
||||
|
||||
bcm2835_smi_write_buf(inst, &byte, 1);
|
||||
}
|
||||
|
||||
static inline void bcm2835_smi_nand_write_buf(struct mtd_info *mtd,
|
||||
const uint8_t *buf, int len)
|
||||
{
|
||||
struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
|
||||
struct bcm2835_smi_instance *inst = host->smi_inst;
|
||||
|
||||
bcm2835_smi_write_buf(inst, buf, len);
|
||||
}
|
||||
|
||||
static inline void bcm2835_smi_nand_read_buf(struct mtd_info *mtd,
|
||||
uint8_t *buf, int len)
|
||||
{
|
||||
struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent);
|
||||
struct bcm2835_smi_instance *inst = host->smi_inst;
|
||||
|
||||
bcm2835_smi_read_buf(inst, buf, len);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Probe and remove functions
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
static int bcm2835_smi_nand_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_smi_nand_host *host;
|
||||
struct nand_chip *this;
|
||||
struct mtd_info *mtd;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->of_node, *smi_node;
|
||||
struct mtd_part_parser_data ppdata;
|
||||
struct smi_settings *smi_settings;
|
||||
struct bcm2835_smi_instance *smi_inst;
|
||||
int ret = -ENXIO;
|
||||
|
||||
if (!node) {
|
||||
dev_err(dev, "No device tree node supplied!");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
smi_node = of_parse_phandle(node, "smi_handle", 0);
|
||||
|
||||
/* Request use of SMI peripheral: */
|
||||
smi_inst = bcm2835_smi_get(smi_node);
|
||||
|
||||
if (!smi_inst) {
|
||||
dev_err(dev, "Could not register with SMI.");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
/* Set SMI timing and bus width */
|
||||
|
||||
smi_settings = bcm2835_smi_get_settings_from_regs(smi_inst);
|
||||
|
||||
smi_settings->data_width = SMI_WIDTH_8BIT;
|
||||
smi_settings->read_setup_time = 2;
|
||||
smi_settings->read_hold_time = 1;
|
||||
smi_settings->read_pace_time = 1;
|
||||
smi_settings->read_strobe_time = 3;
|
||||
|
||||
smi_settings->write_setup_time = 2;
|
||||
smi_settings->write_hold_time = 1;
|
||||
smi_settings->write_pace_time = 1;
|
||||
smi_settings->write_strobe_time = 3;
|
||||
|
||||
bcm2835_smi_set_regs_from_settings(smi_inst);
|
||||
|
||||
host = devm_kzalloc(dev, sizeof(struct bcm2835_smi_nand_host),
|
||||
GFP_KERNEL);
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
host->dev = dev;
|
||||
host->smi_inst = smi_inst;
|
||||
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
/* Link the structures together */
|
||||
|
||||
this = &host->nand_chip;
|
||||
mtd = &host->mtd;
|
||||
mtd->priv = this;
|
||||
mtd->owner = THIS_MODULE;
|
||||
mtd->dev.parent = dev;
|
||||
mtd->name = DRIVER_NAME;
|
||||
ppdata.of_node = node;
|
||||
|
||||
/* 20 us command delay time... */
|
||||
this->chip_delay = 20;
|
||||
|
||||
this->priv = host;
|
||||
this->cmd_ctrl = bcm2835_smi_nand_cmd_ctrl;
|
||||
this->read_byte = bcm2835_smi_nand_read_byte;
|
||||
this->write_byte = bcm2835_smi_nand_write_byte;
|
||||
this->write_buf = bcm2835_smi_nand_write_buf;
|
||||
this->read_buf = bcm2835_smi_nand_read_buf;
|
||||
|
||||
this->ecc.mode = NAND_ECC_SOFT;
|
||||
|
||||
/* Should never be accessed directly: */
|
||||
|
||||
this->IO_ADDR_R = (void *)0xdeadbeef;
|
||||
this->IO_ADDR_W = (void *)0xdeadbeef;
|
||||
|
||||
/* First scan to find the device and get the page size */
|
||||
|
||||
if (nand_scan_ident(mtd, 1, NULL))
|
||||
return -ENXIO;
|
||||
|
||||
/* Second phase scan */
|
||||
|
||||
if (nand_scan_tail(mtd))
|
||||
return -ENXIO;
|
||||
|
||||
ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
|
||||
if (!ret)
|
||||
return 0;
|
||||
|
||||
nand_release(mtd);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int bcm2835_smi_nand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct bcm2835_smi_nand_host *host = platform_get_drvdata(pdev);
|
||||
|
||||
nand_release(&host->mtd);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Register the driver with device tree
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
static const struct of_device_id bcm2835_smi_nand_of_match[] = {
|
||||
{.compatible = "brcm,bcm2835-smi-nand",},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, bcm2835_smi_nand_of_match);
|
||||
|
||||
static struct platform_driver bcm2835_smi_nand_driver = {
|
||||
.probe = bcm2835_smi_nand_probe,
|
||||
.remove = bcm2835_smi_nand_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = bcm2835_smi_nand_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(bcm2835_smi_nand_driver);
|
||||
|
||||
MODULE_ALIAS("platform:smi-nand-bcm2835");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION
|
||||
("Driver for NAND chips using Broadcom Secondary Memory Interface");
|
||||
MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
|
||||
Ładowanie…
Reference in New Issue