diff --git a/examples/python/soapy_psd.py b/examples/python/soapy_psd.py index 57d6790..a4cd758 100644 --- a/examples/python/soapy_psd.py +++ b/examples/python/soapy_psd.py @@ -22,7 +22,7 @@ def setup_receiver(sdr, channel, freq_hz): sdr.setGainMode(SOAPY_SDR_RX, channel, use_agc) # Set the gain mode sdr.setGain(SOAPY_SDR_RX, channel, 0) # Set the gain sdr.setFrequency(SOAPY_SDR_RX, channel, freq_hz) # Tune the LO - sdr.setBandwidth(SOAPY_SDR_RX, channel, 2.5e6) + sdr.setBandwidth(SOAPY_SDR_RX, channel, 2500e5) rx_stream = sdr.setupStream(SOAPY_SDR_RX, SOAPY_SDR_CS16, [channel]) # Setup data stream return rx_stream @@ -77,4 +77,4 @@ plt.show() fig = plt.figure() plt.plot(s_real) plt.plot(s_imag) -plt.show() +plt.show() \ No newline at end of file diff --git a/firmware/h-files/cariboulite_fpga_firmware.h b/firmware/h-files/cariboulite_fpga_firmware.h index 1bf4849..7497543 100644 --- a/firmware/h-files/cariboulite_fpga_firmware.h +++ b/firmware/h-files/cariboulite_fpga_firmware.h @@ -17,16 +17,16 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2021-12-27 - * Time: 23:29:22 + * Date: 2022-01-03 + * Time: 16:23:23 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 22, - .tm_min = 29, - .tm_hour = 23, - .tm_mday = 27, - .tm_mon = 11, /* +1 */ - .tm_year = 121, /* +1900 */ + .tm_sec = 23, + .tm_min = 23, + .tm_hour = 16, + .tm_mday = 3, + .tm_mon = 0, /* +1 */ + .tm_year = 122, /* +1900 */ }; /* @@ -44,392 +44,392 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x05, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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+2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x99, 0xA5, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x74, 0x9B, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/firmware/lvds_rx.v b/firmware/lvds_rx.v index 155b5f3..78d298e 100644 --- a/firmware/lvds_rx.v +++ b/firmware/lvds_rx.v @@ -20,15 +20,13 @@ module lvds_rx localparam modem_i_sync = 3'b10, modem_q_sync = 3'b01; - // modem_i_sync = 3'b01, - // modem_q_sync = 3'b10; // Internal Registers reg [1:0] r_state_if; reg [2:0] r_phase_count; reg [31:0] r_data; reg r_push; - reg [1:0] r_cnt; + reg r_cnt; assign o_debug_state = r_state_if; @@ -64,39 +62,35 @@ module lvds_rx end r_phase_count <= 3'b111; + r_data <= 0; r_push <= 1'b0; - r_data[3:2] <= 2'b11; - r_data[1:0] <= r_cnt; end state_i_phase: begin if (r_phase_count == 3'b000) begin if (i_ddr_data == modem_q_sync ) begin - r_phase_count <= 3'b111; + r_phase_count <= 3'b110; r_state_if <= state_q_phase; end else begin r_state_if <= state_idle; end + end else begin r_phase_count <= r_phase_count - 1; - r_data <= {r_data[29:0], i_ddr_data}; end - //r_data <= {r_data[29:0], i_ddr_data}; + r_data <= {r_data[29:0], i_ddr_data}; end state_q_phase: begin if (r_phase_count == 3'b000) begin r_push <= ~i_fifo_full; r_state_if <= state_idle; - //o_fifo_data <= {r_data[29:0], i_ddr_data}; - o_fifo_data <= r_data; - r_cnt <= r_cnt + 1; + o_fifo_data <= {r_data[29:0], i_ddr_data}; end else begin r_phase_count <= r_phase_count - 1; - r_data <= {r_data[29:0], i_ddr_data}; end - //r_data <= {r_data[29:0], i_ddr_data}; + r_data <= {r_data[29:0], i_ddr_data}; end endcase end diff --git a/firmware/top.asc b/firmware/top.asc index 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rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 779 w_lvds_rx_09_d1 +.sym 803 w_lvds_rx_09_d0 +.sym 826 w_lvds_rx_09_d1 +.sym 827 w_lvds_rx_09_d0 +.sym 830 lvds_clock +.sym 856 lvds_clock +.sym 865 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 886 rx_24_fifo.rd_addr[1] .sym 893 w_lvds_rx_09_d1 -.sym 936 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 937 w_lvds_rx_09_d0 +.sym 917 w_lvds_rx_09_d0 .sym 940 w_lvds_rx_09_d1 .sym 941 w_lvds_rx_09_d0 -.sym 944 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O -.sym 959 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O -.sym 976 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 1007 w_lvds_rx_09_d1 -.sym 1031 w_lvds_rx_09_d0 -.sym 1054 w_lvds_rx_09_d1 -.sym 1055 w_lvds_rx_09_d0 -.sym 1056 i_smi_a2$SB_IO_IN -.sym 1168 lvds_clock +.sym 944 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 963 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 986 lvds_rx_24_inst.r_data[17] +.sym 1051 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i_smi_a2$SB_IO_IN -.sym 1624 lvds_clock -.sym 1880 w_rx_09_fifo_data[12] -.sym 1881 w_rx_09_fifo_data[13] -.sym 1885 w_rx_09_fifo_data[15] -.sym 1980 lvds_rx_09_inst.r_data[14] -.sym 2023 lvds_rx_09_inst.r_data[14] -.sym 2048 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 2049 lvds_clock_$glb_clk -.sym 2065 lvds_rx_09_inst.r_data[12] -.sym 2067 lvds_rx_09_inst.r_data[13] -.sym 2068 lvds_rx_09_inst.r_data[15] -.sym 2070 lvds_rx_09_inst.r_data[17] -.sym 2079 w_rx_09_fifo_pulled_data[21] -.sym 2080 rx_09_fifo.wr_addr[6] -.sym 2086 rx_09_fifo.wr_addr[3] -.sym 2103 w_rx_09_fifo_data[14] -.sym 2129 lvds_rx_09_inst.r_data[18] -.sym 2178 lvds_rx_09_inst.r_data[12] -.sym 2179 lvds_rx_09_inst.r_data[14] -.sym 2203 lvds_rx_09_inst.r_data[12] -.sym 2221 lvds_rx_09_inst.r_data[14] -.sym 2231 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2]_$glb_ce -.sym 2232 lvds_clock_$glb_clk -.sym 2233 w_soft_reset_$glb_sr -.sym 2236 w_rx_09_fifo_data[16] -.sym 2237 w_rx_09_fifo_data[5] -.sym 2238 w_rx_09_fifo_data[19] -.sym 2239 w_rx_09_fifo_data[23] -.sym 2241 w_rx_09_fifo_data[7] -.sym 2250 rx_09_fifo.rd_addr[9] -.sym 2256 rx_09_fifo.rd_addr[8] -.sym 2258 lvds_rx_09_inst.r_data[11] -.sym 2262 lvds_rx_09_inst.r_data[10] -.sym 2266 lvds_rx_09_inst.r_data[25] -.sym 2292 lvds_rx_09_inst.r_data[21] +.sym 1317 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 1318 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 1319 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 1320 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 1322 lvds_rx_09_inst.r_phase_count[1] +.sym 1323 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 1401 w_lvds_rx_24_d0 +.sym 1402 w_lvds_rx_24_d1 +.sym 1411 $PACKER_VCC_NET +.sym 1412 lvds_clock_$glb_clk +.sym 1427 $PACKER_VCC_NET +.sym 1430 w_lvds_rx_24_d1 +.sym 1431 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 1432 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 1434 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E +.sym 1435 lvds_rx_09_inst.o_debug_state[0] +.sym 1436 lvds_rx_09_inst.o_debug_state[1] +.sym 1438 w_lvds_rx_24_d0 +.sym 1450 w_lvds_rx_24_d1 +.sym 1488 w_lvds_rx_24_d0 +.sym 1490 w_lvds_rx_24_d1 +.sym 1499 w_lvds_rx_24_d1 +.sym 1506 lvds_rx_24_inst.r_data[4] +.sym 1544 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 1577 w_lvds_rx_24_d0 +.sym 1610 lvds_rx_24_inst.o_debug_state[0] +.sym 1620 lvds_rx_24_inst.o_debug_state[1] +.sym 1670 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 1696 lvds_rx_24_inst.o_debug_state[0] +.sym 1880 w_rx_09_fifo_data[28] +.sym 1881 w_rx_09_fifo_data[29] +.sym 1883 w_rx_09_fifo_data[30] +.sym 1884 w_rx_09_fifo_data[31] +.sym 2063 lvds_rx_09_inst.r_data[28] +.sym 2064 lvds_rx_09_inst.r_data[29] +.sym 2065 lvds_rx_09_inst.r_data[8] +.sym 2066 lvds_rx_09_inst.r_data[11] +.sym 2067 lvds_rx_09_inst.r_data[12] +.sym 2068 lvds_rx_09_inst.r_data[13] +.sym 2069 lvds_rx_09_inst.r_data[15] +.sym 2070 lvds_rx_09_inst.r_data[10] +.sym 2072 smi_ctrl_ins.soe_and_reset +.sym 2077 rx_09_fifo.wr_addr[9] +.sym 2081 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 2118 lvds_rx_09_inst.r_data[27] +.sym 2120 lvds_rx_09_inst.r_data[17] +.sym 2129 lvds_rx_09_inst.r_data[6] +.sym 2234 w_rx_09_fifo_data[11] +.sym 2235 w_rx_09_fifo_data[10] +.sym 2236 w_rx_09_fifo_data[9] +.sym 2239 w_rx_09_fifo_data[20] +.sym 2240 w_rx_09_fifo_data[8] +.sym 2241 w_rx_09_fifo_data[23] +.sym 2248 lvds_rx_09_inst.o_debug_state[0] +.sym 2250 w_rx_09_fifo_pulled_data[7] +.sym 2251 lvds_rx_09_inst.r_data[10] +.sym 2260 lvds_rx_09_inst.r_data[26] +.sym 2264 lvds_rx_09_inst.r_data[9] +.sym 2281 lvds_rx_09_inst.o_debug_state[0] .sym 2294 lvds_rx_09_inst.r_data[17] -.sym 2296 lvds_rx_09_inst.r_data[19] -.sym 2301 lvds_rx_09_inst.r_data[16] -.sym 2315 lvds_rx_09_inst.r_data[23] -.sym 2321 lvds_rx_09_inst.r_data[23] -.sym 2328 lvds_rx_09_inst.r_data[17] -.sym 2340 lvds_rx_09_inst.r_data[16] -.sym 2345 lvds_rx_09_inst.r_data[21] -.sym 2353 lvds_rx_09_inst.r_data[19] -.sym 2366 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2]_$glb_ce +.sym 2301 lvds_rx_09_inst.r_data[15] +.sym 2309 lvds_rx_09_inst.r_data[19] +.sym 2318 lvds_rx_09_inst.o_debug_state[0] +.sym 2339 lvds_rx_09_inst.o_debug_state[0] +.sym 2341 lvds_rx_09_inst.r_data[19] +.sym 2356 lvds_rx_09_inst.o_debug_state[0] +.sym 2359 lvds_rx_09_inst.r_data[17] +.sym 2364 lvds_rx_09_inst.r_data[15] +.sym 2365 lvds_rx_09_inst.o_debug_state[0] +.sym 2366 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce .sym 2367 lvds_clock_$glb_clk -.sym 2368 w_soft_reset_$glb_sr -.sym 2373 w_rx_09_fifo_data[4] -.sym 2375 w_rx_09_fifo_data[6] -.sym 2376 w_rx_09_fifo_data[2] -.sym 2377 i_smi_a2$SB_IO_IN -.sym 2380 i_smi_a2$SB_IO_IN -.sym 2381 lvds_rx_09_inst.r_data[25] -.sym 2383 w_rx_09_fifo_pulled_data[28] -.sym 2385 w_rx_09_fifo_pulled_data[29] -.sym 2386 lvds_rx_09_inst.r_data[7] -.sym 2387 rx_09_fifo.wr_addr[9] -.sym 2389 lvds_rx_09_inst.r_data[18] -.sym 2390 rx_09_fifo.wr_addr[6] -.sym 2395 w_rx_09_fifo_data[10] -.sym 2413 lvds_rx_09_inst.r_data[7] -.sym 2423 lvds_rx_09_inst.r_data[2] -.sym 2433 lvds_rx_09_inst.r_data[4] -.sym 2475 lvds_rx_09_inst.r_data[2] -.sym 2486 lvds_rx_09_inst.r_data[4] -.sym 2501 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2]_$glb_ce +.sym 2368 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 2369 lvds_rx_09_inst.r_data[27] +.sym 2370 lvds_rx_09_inst.r_data[9] +.sym 2371 lvds_rx_09_inst.r_data[20] +.sym 2372 lvds_rx_09_inst.r_data[24] +.sym 2373 lvds_rx_09_inst.r_data[7] +.sym 2374 lvds_rx_09_inst.r_data[6] +.sym 2375 lvds_rx_09_inst.r_data[22] +.sym 2376 lvds_rx_09_inst.r_data[26] +.sym 2385 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 2388 lvds_rx_09_inst.o_debug_state[1] +.sym 2391 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 2393 w_rx_09_fifo_data[6] +.sym 2398 w_rx_24_fifo_empty +.sym 2402 lvds_rx_09_inst.r_data[5] +.sym 2403 lvds_rx_09_inst.o_debug_state[0] +.sym 2404 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 2409 lvds_rx_09_inst.o_debug_state[1] +.sym 2433 lvds_rx_09_inst.r_data[21] +.sym 2448 lvds_rx_09_inst.o_debug_state[0] +.sym 2453 lvds_rx_09_inst.r_data[23] +.sym 2493 lvds_rx_09_inst.r_data[23] +.sym 2494 lvds_rx_09_inst.o_debug_state[0] +.sym 2497 lvds_rx_09_inst.o_debug_state[0] +.sym 2500 lvds_rx_09_inst.r_data[21] +.sym 2501 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce .sym 2502 lvds_clock_$glb_clk -.sym 2503 w_soft_reset_$glb_sr -.sym 2504 w_rx_09_fifo_data[11] -.sym 2506 w_rx_09_fifo_data[8] -.sym 2509 w_rx_09_fifo_data[9] -.sym 2511 w_rx_09_fifo_data[10] -.sym 2513 lvds_rx_09_inst.r_data[2] -.sym 2528 w_soft_reset -.sym 2566 lvds_rx_09_inst.r_data[8] -.sym 2570 lvds_rx_09_inst.r_data[6] -.sym 2574 lvds_rx_09_inst.r_data[7] -.sym 2580 lvds_rx_09_inst.r_data[9] -.sym 2593 lvds_rx_09_inst.r_data[9] -.sym 2597 lvds_rx_09_inst.r_data[6] -.sym 2602 lvds_rx_09_inst.r_data[8] -.sym 2632 lvds_rx_09_inst.r_data[7] -.sym 2636 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2]_$glb_ce +.sym 2503 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 2504 w_rx_09_fifo_data[7] +.sym 2505 w_rx_09_fifo_data[5] +.sym 2506 w_rx_09_fifo_data[4] +.sym 2507 w_rx_09_fifo_data[26] +.sym 2509 w_rx_09_fifo_data[24] +.sym 2510 w_rx_09_fifo_data[6] +.sym 2511 w_rx_09_fifo_data[27] +.sym 2519 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 2521 i_smi_a2_SB_LUT4_I1_O[1] +.sym 2524 rx_09_fifo.rd_addr[4] +.sym 2528 lvds_rx_09_inst.r_data[18] +.sym 2530 lvds_rx_09_inst.r_data[4] +.sym 2534 w_lvds_rx_09_d0 +.sym 2538 w_rx_09_fifo_push +.sym 2548 i_smi_a2_SB_LUT4_I1_O[1] +.sym 2572 lvds_rx_09_inst.r_data[23] +.sym 2614 lvds_rx_09_inst.r_data[23] +.sym 2636 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce .sym 2637 lvds_clock_$glb_clk -.sym 2638 w_soft_reset_$glb_sr -.sym 2639 lvds_rx_09_inst.r_cnt[1] -.sym 2640 lvds_rx_09_inst.r_cnt[0] -.sym 2641 lvds_rx_09_inst.r_cnt_SB_DFFESR_Q_E[2] -.sym 2644 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E -.sym 2652 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 2654 lvds_rx_09_inst.o_debug_state[1] -.sym 2655 w_rx_09_fifo_pulled_data[25] -.sym 2656 rx_09_fifo.wr_addr[3] -.sym 2658 lvds_rx_09_inst.o_debug_state[0] -.sym 2659 rx_09_fifo.wr_addr[8] -.sym 2662 rx_09_fifo.wr_addr[6] -.sym 2666 sys_ctrl_ins.reset_cmd -.sym 2668 w_soft_reset -.sym 2670 lvds_rx_09_inst.r_data[18] -.sym 2676 lvds_rx_09_inst.o_debug_state[0] -.sym 2682 lvds_rx_09_inst.o_debug_state[1] -.sym 2684 w_soft_reset -.sym 2775 w_rx_09_fifo_data[17] -.sym 2778 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E -.sym 2779 w_rx_09_fifo_data[18] -.sym 2792 lvds_rx_09_inst.o_debug_state[1] -.sym 2798 lvds_rx_09_inst.o_debug_state[0] -.sym 2804 lvds_rx_09_inst.o_debug_state[1] -.sym 2806 w_soft_reset -.sym 2820 lvds_rx_09_inst.o_debug_state[1] -.sym 2840 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 2845 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E -.sym 2848 $PACKER_GND_NET -.sym 2861 $PACKER_GND_NET -.sym 2906 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E -.sym 2907 r_counter_$glb_clk -.sym 2908 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 2921 w_soft_reset -.sym 2925 w_rx_09_fifo_pulled_data[9] -.sym 2928 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 2932 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E -.sym 2938 lvds_rx_09_inst.o_debug_state[0] -.sym 2962 lvds_rx_09_inst.o_debug_state[0] -.sym 2965 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 2970 w_soft_reset -.sym 2973 lvds_rx_09_inst.o_debug_state[1] -.sym 3001 w_soft_reset -.sym 3002 lvds_rx_09_inst.o_debug_state[0] -.sym 3003 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 3004 lvds_rx_09_inst.o_debug_state[1] -.sym 3060 w_rx_09_fifo_pulled_data[11] -.sym 3062 $PACKER_VCC_NET -.sym 3097 w_soft_reset -.sym 3099 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E -.sym 3105 lvds_rx_09_inst.o_debug_state[0] -.sym 3107 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 3108 lvds_rx_09_inst.o_debug_state[1] -.sym 3109 w_lvds_rx_09_d1 -.sym 3111 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 3113 lvds_rx_09_inst.o_debug_state[0] -.sym 3115 w_lvds_rx_09_d0 -.sym 3130 lvds_rx_09_inst.o_debug_state[1] -.sym 3131 w_lvds_rx_09_d1 -.sym 3132 w_lvds_rx_09_d0 -.sym 3133 lvds_rx_09_inst.o_debug_state[0] -.sym 3148 w_lvds_rx_09_d1 -.sym 3149 w_lvds_rx_09_d0 -.sym 3150 lvds_rx_09_inst.o_debug_state[0] -.sym 3151 lvds_rx_09_inst.o_debug_state[1] -.sym 3160 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 3161 w_soft_reset -.sym 3162 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 3163 lvds_rx_09_inst.o_debug_state[0] -.sym 3176 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E -.sym 3177 lvds_clock_$glb_clk -.sym 3178 w_soft_reset_$glb_sr -.sym 3193 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E -.sym 3199 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 3240 lvds_rx_09_inst.o_debug_state[0] -.sym 3243 lvds_rx_09_inst.o_debug_state[1] -.sym 3249 w_lvds_rx_09_d0 -.sym 3252 w_lvds_rx_09_d1 -.sym 3277 w_lvds_rx_09_d1 -.sym 3278 lvds_rx_09_inst.o_debug_state[0] -.sym 3279 lvds_rx_09_inst.o_debug_state[1] -.sym 3280 w_lvds_rx_09_d0 -.sym 3466 $PACKER_VCC_NET -.sym 4000 i_smi_a2$SB_IO_IN +.sym 2639 lvds_rx_09_inst.r_data[3] +.sym 2640 lvds_rx_09_inst.r_data[2] +.sym 2642 lvds_rx_09_inst.r_data[16] +.sym 2643 lvds_rx_09_inst.r_data[5] +.sym 2644 lvds_rx_09_inst.r_data[14] +.sym 2645 lvds_rx_09_inst.r_data[18] +.sym 2646 lvds_rx_09_inst.r_data[4] +.sym 2652 smi_ctrl_ins.int_cnt_09[4] +.sym 2660 w_rx_09_fifo_data[5] +.sym 2661 w_rx_09_fifo_data[25] +.sym 2667 lvds_rx_09_inst.r_data[17] +.sym 2668 w_rx_09_fifo_full +.sym 2670 lvds_rx_09_inst.r_data[0] +.sym 2674 lvds_rx_09_inst.r_data[1] +.sym 2698 smi_ctrl_ins.int_cnt_24[4] +.sym 2701 smi_ctrl_ins.soe_and_reset +.sym 2704 w_rx_24_fifo_empty +.sym 2714 smi_ctrl_ins.int_cnt_24[3] +.sym 2719 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 2761 smi_ctrl_ins.int_cnt_24[4] +.sym 2762 w_rx_24_fifo_empty +.sym 2763 smi_ctrl_ins.int_cnt_24[3] +.sym 2771 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 2772 smi_ctrl_ins.soe_and_reset +.sym 2774 w_rx_09_fifo_data[2] +.sym 2775 w_rx_09_fifo_data[3] +.sym 2778 w_rx_09_fifo_data[18] +.sym 2779 w_rx_09_fifo_data[0] +.sym 2780 w_rx_09_fifo_data[1] +.sym 2781 w_rx_09_fifo_data[19] +.sym 2794 smi_ctrl_ins.int_cnt_24[4] +.sym 2805 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 2807 smi_ctrl_ins.w_fifo_24_pull_trigger +.sym 2821 lvds_rx_09_inst.o_debug_state[0] +.sym 2834 lvds_rx_09_inst.r_push +.sym 2890 lvds_rx_09_inst.r_push +.sym 2907 lvds_clock_$glb_clk +.sym 2908 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 2912 lvds_rx_09_inst.r_data[0] +.sym 2914 lvds_rx_09_inst.r_data[1] +.sym 2917 i_smi_a2$SB_IO_IN +.sym 2920 i_smi_a2$SB_IO_IN +.sym 2923 w_rx_09_fifo_push +.sym 2924 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 2936 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] +.sym 2937 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 2940 i_smi_a2_SB_LUT4_I1_O[1] +.sym 2943 lvds_rx_09_inst.o_debug_state[0] +.sym 2944 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 2953 lvds_rx_09_inst.o_debug_state[1] +.sym 2963 i_smi_a2_SB_LUT4_I1_O[1] +.sym 2967 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 2974 w_rx_09_fifo_full +.sym 2980 lvds_rx_09_inst.o_debug_state[0] +.sym 2982 lvds_rx_09_inst.o_debug_state[1] +.sym 2989 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E +.sym 3013 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3014 lvds_rx_09_inst.o_debug_state[0] +.sym 3015 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3016 lvds_rx_09_inst.o_debug_state[1] +.sym 3038 lvds_rx_09_inst.o_debug_state[1] +.sym 3039 w_rx_09_fifo_full +.sym 3040 lvds_rx_09_inst.o_debug_state[0] +.sym 3041 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E +.sym 3042 lvds_clock_$glb_clk +.sym 3043 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 3060 w_rx_09_fifo_pulled_data[27] +.sym 3067 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 3072 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3081 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3086 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 3089 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3112 lvds_rx_09_inst.o_debug_state[0] +.sym 3114 lvds_rx_09_inst.o_debug_state[1] +.sym 3124 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3161 lvds_rx_09_inst.o_debug_state[0] +.sym 3162 lvds_rx_09_inst.o_debug_state[1] +.sym 3163 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3179 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] +.sym 3180 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] +.sym 3183 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 3184 lvds_rx_24_inst.r_data[10] +.sym 3186 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 3191 rx_24_fifo.wr_addr[3] +.sym 3201 rx_24_fifo.wr_addr[8] +.sym 3315 lvds_rx_24_inst.r_data[8] +.sym 3327 rx_24_fifo.rd_addr[0] +.sym 3328 i_smi_a2$SB_IO_IN +.sym 3332 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 3341 lvds_rx_24_inst.r_data[6] +.sym 3347 w_lvds_rx_24_d0 +.sym 3349 w_lvds_rx_24_d1 +.sym 3354 i_smi_a2$SB_IO_IN +.sym 3359 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E +.sym 3361 lvds_rx_09_inst.o_debug_state[0] +.sym 3449 w_rx_24_fifo_data[0] +.sym 3450 w_rx_24_fifo_data[2] +.sym 3451 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3452 w_rx_24_fifo_data[10] +.sym 3454 w_rx_24_fifo_data[1] +.sym 3455 w_rx_24_fifo_data[8] +.sym 3464 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 3470 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 3473 $PACKER_VCC_NET +.sym 3476 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3477 lvds_rx_24_inst.o_debug_state[0] +.sym 3479 $PACKER_VCC_NET +.sym 3483 lvds_rx_09_inst.o_debug_state[0] +.sym 3485 lvds_rx_09_inst.o_debug_state[1] +.sym 3486 w_lvds_rx_09_d0 +.sym 3496 w_lvds_rx_09_d1 +.sym 3502 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3504 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3505 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 3509 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3517 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 3518 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 3520 lvds_rx_09_inst.o_debug_state[0] +.sym 3522 w_lvds_rx_09_d1 +.sym 3527 w_lvds_rx_09_d0 +.sym 3530 lvds_rx_09_inst.o_debug_state[1] +.sym 3535 lvds_rx_09_inst.o_debug_state[0] +.sym 3536 lvds_rx_09_inst.o_debug_state[1] +.sym 3537 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 3538 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3553 lvds_rx_09_inst.o_debug_state[1] +.sym 3554 w_lvds_rx_09_d0 +.sym 3555 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3556 w_lvds_rx_09_d1 +.sym 3559 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 3560 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 3561 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3568 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 3581 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3582 lvds_clock_$glb_clk +.sym 3583 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 3584 lvds_rx_24_inst.r_data[2] +.sym 3585 lvds_rx_24_inst.r_data[6] +.sym 3587 lvds_rx_24_inst.r_data[0] +.sym 3591 lvds_rx_24_inst.r_data[4] +.sym 3600 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3608 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3639 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3641 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 3642 lvds_rx_09_inst.o_debug_state[0] +.sym 3643 lvds_rx_09_inst.o_debug_state[1] +.sym 3644 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3645 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 3646 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 3650 lvds_rx_09_inst.r_phase_count[0] +.sym 3655 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 3657 $PACKER_VCC_NET +.sym 3659 lvds_rx_09_inst.r_phase_count[1] +.sym 3663 $PACKER_VCC_NET +.sym 3664 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 3669 $nextpnr_ICESTORM_LC_11$O +.sym 3672 lvds_rx_09_inst.r_phase_count[0] +.sym 3675 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 3677 lvds_rx_09_inst.r_phase_count[1] +.sym 3678 $PACKER_VCC_NET +.sym 3679 lvds_rx_09_inst.r_phase_count[0] +.sym 3682 $PACKER_VCC_NET +.sym 3684 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 3685 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 3688 lvds_rx_09_inst.o_debug_state[0] +.sym 3689 lvds_rx_09_inst.o_debug_state[1] +.sym 3690 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3691 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 3694 lvds_rx_09_inst.o_debug_state[1] +.sym 3695 lvds_rx_09_inst.o_debug_state[0] +.sym 3696 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 3697 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3706 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 3712 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 3713 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 3714 lvds_rx_09_inst.o_debug_state[0] +.sym 3715 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 3716 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3717 lvds_clock_$glb_clk +.sym 3718 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 3719 w_lvds_rx_24_d1_SB_LUT4_I1_O[1] +.sym 3720 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E +.sym 3721 lvds_rx_24_inst.o_debug_state[1] +.sym 3722 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3736 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 3740 w_lvds_rx_24_d1 +.sym 3774 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E +.sym 3777 w_lvds_rx_09_d0 +.sym 3779 w_lvds_rx_09_d1 +.sym 3781 lvds_rx_24_inst.o_debug_state[0] +.sym 3783 lvds_rx_24_inst.o_debug_state[1] +.sym 3787 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3789 w_lvds_rx_24_d1 +.sym 3792 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3794 lvds_rx_09_inst.o_debug_state[1] +.sym 3798 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 3800 w_lvds_rx_24_d0 +.sym 3801 lvds_rx_09_inst.o_debug_state[0] +.sym 3808 w_lvds_rx_24_d1 +.sym 3811 w_lvds_rx_24_d0 +.sym 3812 lvds_rx_24_inst.o_debug_state[1] +.sym 3813 w_lvds_rx_24_d1 +.sym 3814 lvds_rx_24_inst.o_debug_state[0] +.sym 3817 lvds_rx_09_inst.o_debug_state[1] +.sym 3818 w_lvds_rx_09_d0 +.sym 3819 lvds_rx_09_inst.o_debug_state[0] +.sym 3820 w_lvds_rx_09_d1 +.sym 3829 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 3831 i_smi_a2_SB_LUT4_I1_O[1] +.sym 3832 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 3835 w_lvds_rx_09_d1 +.sym 3836 lvds_rx_09_inst.o_debug_state[1] +.sym 3837 w_lvds_rx_09_d0 +.sym 3838 lvds_rx_09_inst.o_debug_state[0] +.sym 3841 lvds_rx_09_inst.o_debug_state[0] +.sym 3842 w_lvds_rx_09_d0 +.sym 3843 lvds_rx_09_inst.o_debug_state[1] +.sym 3844 w_lvds_rx_09_d1 +.sym 3851 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E +.sym 3852 lvds_clock_$glb_clk +.sym 3853 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 3855 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 3856 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 3857 lvds_rx_24_inst.r_phase_count[0] +.sym 3858 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 3859 lvds_rx_24_inst.r_phase_count[1] +.sym 3860 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 3861 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 3870 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E +.sym 3874 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 3875 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 3898 i_smi_a2$SB_IO_IN +.sym 3909 lvds_rx_24_inst.o_debug_state[1] +.sym 3918 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3925 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 3926 lvds_rx_24_inst.o_debug_state[0] +.sym 3935 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 3940 lvds_rx_24_inst.o_debug_state[1] +.sym 3941 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 3942 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 3943 lvds_rx_24_inst.o_debug_state[0] +.sym 3986 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 3987 lvds_clock_$glb_clk +.sym 3988 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 4004 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 4009 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 4012 rx_24_fifo.wr_addr[2] .sym 4138 i_smi_a2$SB_IO_IN -.sym 4238 w_rx_09_fifo_pulled_data[20] -.sym 4242 w_rx_09_fifo_pulled_data[21] -.sym 4254 lvds_rx_09_inst.r_data[17] -.sym 4281 lvds_rx_09_inst.r_data[12] -.sym 4291 lvds_rx_09_inst.r_data[13] -.sym 4292 lvds_rx_09_inst.r_data[15] -.sym 4321 lvds_rx_09_inst.r_data[12] -.sym 4325 lvds_rx_09_inst.r_data[13] -.sym 4348 lvds_rx_09_inst.r_data[15] -.sym 4358 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce +.sym 4158 o_shdn_tx_lna$SB_IO_OUT +.sym 4238 w_rx_09_fifo_pulled_data[4] +.sym 4242 w_rx_09_fifo_pulled_data[5] +.sym 4248 lvds_rx_09_inst.r_data[12] +.sym 4279 lvds_rx_09_inst.r_data[28] +.sym 4282 lvds_rx_09_inst.r_data[26] +.sym 4288 lvds_rx_09_inst.r_data[29] +.sym 4300 lvds_rx_09_inst.r_data[27] +.sym 4320 lvds_rx_09_inst.r_data[26] +.sym 4325 lvds_rx_09_inst.r_data[27] +.sym 4336 lvds_rx_09_inst.r_data[28] +.sym 4343 lvds_rx_09_inst.r_data[29] +.sym 4358 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce .sym 4359 lvds_clock_$glb_clk -.sym 4366 w_rx_09_fifo_pulled_data[22] -.sym 4370 w_rx_09_fifo_pulled_data[23] -.sym 4378 rx_09_fifo.wr_addr[4] -.sym 4380 rx_09_fifo.wr_addr[5] -.sym 4382 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 4385 rx_09_fifo.wr_addr[7] -.sym 4388 rx_09_fifo.wr_addr[9] -.sym 4389 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 4399 w_rx_09_fifo_pulled_data[20] +.sym 4366 w_rx_09_fifo_pulled_data[6] +.sym 4370 w_rx_09_fifo_pulled_data[7] +.sym 4377 w_rx_09_fifo_data[15] +.sym 4379 rx_09_fifo.wr_addr[8] +.sym 4381 rx_09_fifo.wr_addr[5] +.sym 4382 lvds_rx_09_inst.r_data[26] +.sym 4385 rx_09_fifo.wr_addr[4] +.sym 4387 rx_09_fifo.wr_addr[6] +.sym 4393 $PACKER_VCC_NET +.sym 4406 lvds_rx_09_inst.r_data[15] .sym 4407 i_smi_a3$SB_IO_IN -.sym 4420 w_rx_09_fifo_data[13] -.sym 4422 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 4424 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 4425 rx_09_fifo.wr_addr[8] -.sym 4427 rx_09_fifo.wr_addr[3] -.sym 4431 rx_09_fifo.wr_addr[7] -.sym 4454 lvds_rx_09_inst.r_data[13] -.sym 4455 lvds_rx_09_inst.r_data[15] -.sym 4458 lvds_rx_09_inst.r_data[10] -.sym 4462 lvds_rx_09_inst.r_data[11] -.sym 4487 lvds_rx_09_inst.r_data[10] -.sym 4501 lvds_rx_09_inst.r_data[11] -.sym 4507 lvds_rx_09_inst.r_data[13] -.sym 4518 lvds_rx_09_inst.r_data[15] -.sym 4521 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2]_$glb_ce +.sym 4414 rx_09_fifo.rd_addr[1] +.sym 4420 w_rx_09_fifo_data[8] +.sym 4422 w_rx_09_fifo_data[23] +.sym 4452 lvds_rx_09_inst.r_data[8] +.sym 4457 lvds_rx_09_inst.o_debug_state[0] +.sym 4458 lvds_rx_09_inst.r_data[27] +.sym 4460 lvds_rx_09_inst.r_data[9] +.sym 4461 lvds_rx_09_inst.r_data[11] +.sym 4463 lvds_rx_09_inst.r_data[13] +.sym 4465 lvds_rx_09_inst.r_data[10] +.sym 4468 lvds_rx_09_inst.r_data[6] +.sym 4472 lvds_rx_09_inst.r_data[26] +.sym 4475 lvds_rx_09_inst.o_debug_state[0] +.sym 4478 lvds_rx_09_inst.r_data[26] +.sym 4482 lvds_rx_09_inst.r_data[27] +.sym 4484 lvds_rx_09_inst.o_debug_state[0] +.sym 4489 lvds_rx_09_inst.o_debug_state[0] +.sym 4490 lvds_rx_09_inst.r_data[6] +.sym 4494 lvds_rx_09_inst.o_debug_state[0] +.sym 4496 lvds_rx_09_inst.r_data[9] +.sym 4501 lvds_rx_09_inst.o_debug_state[0] +.sym 4502 lvds_rx_09_inst.r_data[10] +.sym 4505 lvds_rx_09_inst.r_data[11] +.sym 4506 lvds_rx_09_inst.o_debug_state[0] +.sym 4512 lvds_rx_09_inst.r_data[13] +.sym 4513 lvds_rx_09_inst.o_debug_state[0] +.sym 4517 lvds_rx_09_inst.r_data[8] +.sym 4520 lvds_rx_09_inst.o_debug_state[0] +.sym 4521 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce .sym 4522 lvds_clock_$glb_clk -.sym 4523 w_soft_reset_$glb_sr -.sym 4525 w_rx_09_fifo_pulled_data[28] -.sym 4529 w_rx_09_fifo_pulled_data[29] -.sym 4533 w_rx_09_fifo_pulled_data[23] -.sym 4537 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 4538 w_rx_09_fifo_data[14] -.sym 4540 rx_09_fifo.rd_addr[7] -.sym 4541 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 4545 w_rx_09_fifo_pulled_data[22] -.sym 4548 w_rx_09_fifo_data[19] -.sym 4549 rx_09_fifo.rd_addr[4] -.sym 4551 rx_09_fifo.rd_addr[5] -.sym 4553 rx_09_fifo.rd_addr[6] -.sym 4555 rx_09_fifo.rd_addr[4] -.sym 4556 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 4566 lvds_rx_09_inst.r_data[19] -.sym 4573 lvds_rx_09_inst.r_data[5] -.sym 4577 lvds_rx_09_inst.r_data[23] -.sym 4579 lvds_rx_09_inst.r_data[7] -.sym 4587 lvds_rx_09_inst.r_data[16] -.sym 4610 lvds_rx_09_inst.r_data[16] -.sym 4616 lvds_rx_09_inst.r_data[5] -.sym 4623 lvds_rx_09_inst.r_data[19] -.sym 4630 lvds_rx_09_inst.r_data[23] -.sym 4640 lvds_rx_09_inst.r_data[7] -.sym 4644 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce +.sym 4523 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 4525 w_rx_09_fifo_pulled_data[16] +.sym 4529 w_rx_09_fifo_pulled_data[17] +.sym 4536 rx_09_fifo.rd_addr[4] +.sym 4538 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 4540 rx_09_fifo.rd_addr[5] +.sym 4545 w_rx_09_fifo_pulled_data[6] +.sym 4548 rx_09_fifo.wr_addr[8] +.sym 4550 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 4551 lvds_rx_09_inst.r_data[11] +.sym 4553 lvds_rx_09_inst.r_data[12] +.sym 4555 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 4557 rx_09_fifo.rd_addr[0] +.sym 4566 lvds_rx_09_inst.r_data[9] +.sym 4569 lvds_rx_09_inst.r_data[7] +.sym 4570 lvds_rx_09_inst.r_data[6] +.sym 4575 lvds_rx_09_inst.r_data[8] +.sym 4576 lvds_rx_09_inst.r_data[21] +.sym 4579 lvds_rx_09_inst.r_data[18] +.sym 4599 lvds_rx_09_inst.r_data[9] +.sym 4604 lvds_rx_09_inst.r_data[8] +.sym 4610 lvds_rx_09_inst.r_data[7] +.sym 4628 lvds_rx_09_inst.r_data[18] +.sym 4635 lvds_rx_09_inst.r_data[6] +.sym 4641 lvds_rx_09_inst.r_data[21] +.sym 4644 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce .sym 4645 lvds_clock_$glb_clk -.sym 4648 w_rx_09_fifo_pulled_data[30] -.sym 4652 w_rx_09_fifo_pulled_data[31] -.sym 4659 lvds_rx_09_inst.r_data[5] -.sym 4660 w_soft_reset -.sym 4661 w_rx_09_fifo_data[23] -.sym 4664 rx_09_fifo.wr_addr[4] -.sym 4666 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 4667 lvds_rx_09_inst.r_data[24] -.sym 4674 rx_09_fifo.rd_addr[8] -.sym 4676 w_rx_09_fifo_data[11] -.sym 4677 w_rx_09_fifo_data[2] -.sym 4678 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 4680 rx_09_fifo.rd_addr[1] -.sym 4693 lvds_rx_09_inst.r_data[6] -.sym 4698 lvds_rx_09_inst.r_data[2] -.sym 4699 lvds_rx_09_inst.r_data[4] -.sym 4747 lvds_rx_09_inst.r_data[4] -.sym 4760 lvds_rx_09_inst.r_data[6] -.sym 4765 lvds_rx_09_inst.r_data[2] -.sym 4767 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce +.sym 4648 w_rx_09_fifo_pulled_data[18] +.sym 4652 w_rx_09_fifo_pulled_data[19] +.sym 4656 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 4661 w_rx_09_fifo_data[20] +.sym 4662 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 4665 w_rx_09_fifo_push +.sym 4667 lvds_rx_09_inst.r_data[18] +.sym 4671 $PACKER_VCC_NET +.sym 4672 w_rx_24_fifo_data[26] +.sym 4675 $PACKER_VCC_NET +.sym 4676 w_rx_09_fifo_data[7] +.sym 4677 rx_09_fifo.rd_addr[6] +.sym 4679 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 4680 $PACKER_VCC_NET +.sym 4681 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 4682 w_rx_09_fifo_data[26] +.sym 4691 lvds_rx_09_inst.r_data[24] +.sym 4692 lvds_rx_09_inst.r_data[7] +.sym 4694 lvds_rx_09_inst.r_data[25] +.sym 4698 lvds_rx_09_inst.r_data[20] +.sym 4702 lvds_rx_09_inst.r_data[22] +.sym 4707 lvds_rx_09_inst.o_debug_state[0] +.sym 4710 lvds_rx_09_inst.r_data[4] +.sym 4712 lvds_rx_09_inst.r_data[5] +.sym 4716 lvds_rx_09_inst.r_data[18] +.sym 4721 lvds_rx_09_inst.r_data[25] +.sym 4724 lvds_rx_09_inst.o_debug_state[0] +.sym 4727 lvds_rx_09_inst.o_debug_state[0] +.sym 4730 lvds_rx_09_inst.r_data[7] +.sym 4734 lvds_rx_09_inst.o_debug_state[0] +.sym 4736 lvds_rx_09_inst.r_data[18] +.sym 4739 lvds_rx_09_inst.r_data[22] +.sym 4741 lvds_rx_09_inst.o_debug_state[0] +.sym 4746 lvds_rx_09_inst.o_debug_state[0] +.sym 4748 lvds_rx_09_inst.r_data[5] +.sym 4753 lvds_rx_09_inst.o_debug_state[0] +.sym 4754 lvds_rx_09_inst.r_data[4] +.sym 4758 lvds_rx_09_inst.r_data[20] +.sym 4760 lvds_rx_09_inst.o_debug_state[0] +.sym 4763 lvds_rx_09_inst.o_debug_state[0] +.sym 4765 lvds_rx_09_inst.r_data[24] +.sym 4767 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce .sym 4768 lvds_clock_$glb_clk -.sym 4771 w_rx_09_fifo_pulled_data[24] -.sym 4775 w_rx_09_fifo_pulled_data[25] -.sym 4779 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 4783 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 4786 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 4787 rx_09_fifo.rd_addr[7] -.sym 4788 w_soft_reset -.sym 4790 rx_09_fifo.rd_addr[5] -.sym 4792 rx_09_fifo.rd_addr[1] -.sym 4799 $PACKER_VCC_NET -.sym 4801 w_rx_09_fifo_data[16] -.sym 4802 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E -.sym 4804 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] +.sym 4769 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 4771 w_rx_09_fifo_pulled_data[0] +.sym 4775 w_rx_09_fifo_pulled_data[1] +.sym 4782 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 4784 w_rx_09_fifo_full +.sym 4788 lvds_rx_09_inst.r_data[20] +.sym 4794 rx_09_fifo.rd_addr[9] +.sym 4795 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 4797 rx_09_fifo.rd_addr[1] +.sym 4798 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 4799 rx_09_fifo.wr_addr[9] +.sym 4800 rx_09_fifo.rd_addr[9] +.sym 4801 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 4804 w_rx_09_fifo_data[0] .sym 4805 i_smi_a3$SB_IO_IN -.sym 4819 lvds_rx_09_inst.r_data[11] -.sym 4820 lvds_rx_09_inst.r_data[8] -.sym 4821 lvds_rx_09_inst.r_data[10] -.sym 4826 lvds_rx_09_inst.r_data[9] -.sym 4847 lvds_rx_09_inst.r_data[11] -.sym 4856 lvds_rx_09_inst.r_data[8] -.sym 4877 lvds_rx_09_inst.r_data[9] -.sym 4886 lvds_rx_09_inst.r_data[10] -.sym 4890 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce +.sym 4812 lvds_rx_09_inst.r_data[2] +.sym 4815 lvds_rx_09_inst.r_data[5] +.sym 4819 lvds_rx_09_inst.r_data[3] +.sym 4822 lvds_rx_09_inst.r_data[24] +.sym 4825 lvds_rx_09_inst.r_data[22] +.sym 4826 lvds_rx_09_inst.r_data[4] +.sym 4841 lvds_rx_09_inst.r_data[25] +.sym 4844 lvds_rx_09_inst.r_data[5] +.sym 4850 lvds_rx_09_inst.r_data[3] +.sym 4857 lvds_rx_09_inst.r_data[2] +.sym 4863 lvds_rx_09_inst.r_data[24] +.sym 4876 lvds_rx_09_inst.r_data[22] +.sym 4882 lvds_rx_09_inst.r_data[4] +.sym 4888 lvds_rx_09_inst.r_data[25] +.sym 4890 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce .sym 4891 lvds_clock_$glb_clk -.sym 4894 w_rx_09_fifo_pulled_data[26] -.sym 4898 w_rx_09_fifo_pulled_data[27] -.sym 4905 lvds_rx_09_inst.o_debug_state[1] -.sym 4906 rx_09_fifo.wr_addr[5] -.sym 4907 w_rx_09_fifo_data[9] -.sym 4908 rx_09_fifo.wr_addr[7] -.sym 4909 w_soft_reset -.sym 4911 w_rx_09_fifo_data[8] -.sym 4913 lvds_rx_09_inst.o_debug_state[0] -.sym 4916 lvds_rx_09_inst.r_data[25] -.sym 4918 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 4920 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 4922 rx_09_fifo.wr_addr[7] -.sym 4926 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 4927 lvds_rx_09_inst.r_cnt[0] -.sym 4936 lvds_rx_09_inst.r_cnt_SB_DFFESR_Q_E[2] -.sym 4943 lvds_rx_09_inst.r_cnt[0] -.sym 4944 lvds_rx_09_inst.r_cnt_SB_DFFESR_Q_E[2] -.sym 4950 w_soft_reset -.sym 4952 lvds_rx_09_inst.o_debug_state[1] -.sym 4958 lvds_rx_09_inst.r_cnt[1] -.sym 4962 lvds_rx_09_inst.o_debug_state[0] -.sym 4964 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 4968 lvds_rx_09_inst.r_cnt[1] -.sym 4969 lvds_rx_09_inst.r_cnt[0] -.sym 4976 lvds_rx_09_inst.r_cnt[0] -.sym 4979 w_soft_reset -.sym 4980 lvds_rx_09_inst.o_debug_state[0] -.sym 4981 lvds_rx_09_inst.o_debug_state[1] -.sym 4982 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 4997 lvds_rx_09_inst.r_cnt_SB_DFFESR_Q_E[2] -.sym 4999 lvds_rx_09_inst.o_debug_state[0] -.sym 5000 lvds_rx_09_inst.o_debug_state[1] -.sym 5013 lvds_rx_09_inst.r_cnt_SB_DFFESR_Q_E[2] +.sym 4894 w_rx_09_fifo_pulled_data[2] +.sym 4898 w_rx_09_fifo_pulled_data[3] +.sym 4901 rx_09_fifo.wr_addr[4] +.sym 4905 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 4908 rx_09_fifo.wr_addr[6] +.sym 4909 smi_ctrl_ins.int_cnt_09[3] +.sym 4911 w_rx_09_fifo_data[4] +.sym 4914 rx_09_fifo.wr_addr[5] +.sym 4915 smi_ctrl_ins.w_fifo_24_pull_trigger +.sym 4916 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 4920 w_rx_09_fifo_data[19] +.sym 4934 lvds_rx_09_inst.r_data[3] +.sym 4939 lvds_rx_09_inst.r_data[14] +.sym 4943 lvds_rx_09_inst.r_data[2] +.sym 4945 lvds_rx_09_inst.o_debug_state[0] +.sym 4950 lvds_rx_09_inst.r_data[12] +.sym 4953 lvds_rx_09_inst.r_data[16] +.sym 4956 lvds_rx_09_inst.r_data[0] +.sym 4960 lvds_rx_09_inst.r_data[1] +.sym 4968 lvds_rx_09_inst.r_data[1] +.sym 4969 lvds_rx_09_inst.o_debug_state[0] +.sym 4974 lvds_rx_09_inst.o_debug_state[0] +.sym 4976 lvds_rx_09_inst.r_data[0] +.sym 4987 lvds_rx_09_inst.r_data[14] +.sym 4988 lvds_rx_09_inst.o_debug_state[0] +.sym 4991 lvds_rx_09_inst.r_data[3] +.sym 4993 lvds_rx_09_inst.o_debug_state[0] +.sym 4998 lvds_rx_09_inst.o_debug_state[0] +.sym 5000 lvds_rx_09_inst.r_data[12] +.sym 5004 lvds_rx_09_inst.r_data[16] +.sym 5005 lvds_rx_09_inst.o_debug_state[0] +.sym 5010 lvds_rx_09_inst.o_debug_state[0] +.sym 5012 lvds_rx_09_inst.r_data[2] +.sym 5013 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce .sym 5014 lvds_clock_$glb_clk -.sym 5015 w_soft_reset_$glb_sr -.sym 5017 w_rx_09_fifo_pulled_data[8] -.sym 5021 w_rx_09_fifo_pulled_data[9] -.sym 5028 lvds_rx_09_inst.r_cnt[1] -.sym 5029 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 5030 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E -.sym 5031 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 5033 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 5034 lvds_rx_09_inst.o_debug_state[0] -.sym 5036 rx_09_fifo.rd_addr[9] -.sym 5037 rx_09_fifo.rd_addr[7] -.sym 5039 w_rx_09_fifo_data[10] -.sym 5041 rx_09_fifo.rd_addr[6] -.sym 5042 rx_09_fifo.rd_addr[4] -.sym 5043 rx_09_fifo.wr_addr[4] -.sym 5045 rx_09_fifo.wr_addr[9] -.sym 5047 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 5048 w_rx_09_fifo_data[19] -.sym 5060 lvds_rx_09_inst.r_data[18] -.sym 5072 sys_ctrl_ins.reset_cmd -.sym 5086 lvds_rx_09_inst.r_data[17] -.sym 5099 lvds_rx_09_inst.r_data[17] -.sym 5114 sys_ctrl_ins.reset_cmd -.sym 5120 lvds_rx_09_inst.r_data[18] -.sym 5136 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce +.sym 5015 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 5017 w_rx_09_fifo_pulled_data[24] +.sym 5021 w_rx_09_fifo_pulled_data[25] +.sym 5028 w_cs[1] +.sym 5030 lvds_rx_09_inst.r_data[14] +.sym 5031 lvds_rx_09_inst.o_debug_state[0] +.sym 5032 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] +.sym 5034 w_rx_24_fifo_empty +.sym 5035 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 5036 i_smi_a2_SB_LUT4_I1_O[1] +.sym 5037 w_rx_09_fifo_data[6] +.sym 5038 smi_ctrl_ins.int_cnt_24[3] +.sym 5046 rx_09_fifo.wr_addr[8] +.sym 5047 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 5048 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 5049 rx_09_fifo.rd_addr[0] +.sym 5050 rx_09_fifo.wr_addr[6] +.sym 5057 lvds_rx_09_inst.r_data[17] +.sym 5060 lvds_rx_09_inst.r_data[16] +.sym 5064 w_lvds_rx_09_d0 +.sym 5068 lvds_rx_09_inst.r_data[0] +.sym 5070 lvds_rx_09_inst.r_data[1] +.sym 5074 w_lvds_rx_09_d1 +.sym 5090 lvds_rx_09_inst.r_data[0] +.sym 5099 lvds_rx_09_inst.r_data[1] +.sym 5115 lvds_rx_09_inst.r_data[16] +.sym 5120 w_lvds_rx_09_d0 +.sym 5129 w_lvds_rx_09_d1 +.sym 5133 lvds_rx_09_inst.r_data[17] +.sym 5136 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce .sym 5137 lvds_clock_$glb_clk -.sym 5140 w_rx_09_fifo_pulled_data[10] -.sym 5144 w_rx_09_fifo_pulled_data[11] -.sym 5152 w_soft_reset -.sym 5153 rx_09_fifo.wr_addr[3] -.sym 5157 $PACKER_GND_NET -.sym 5158 rx_09_fifo.wr_addr[6] -.sym 5161 rx_09_fifo.wr_addr[8] -.sym 5162 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 5166 rx_09_fifo.rd_addr[8] -.sym 5274 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 5276 w_soft_reset -.sym 5277 rx_09_fifo.rd_addr[1] -.sym 5278 sys_ctrl_ins.reset_cmd -.sym 5280 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 5281 rx_09_fifo.rd_addr[4] -.sym 5282 rx_09_fifo.rd_addr[7] -.sym 5283 rx_09_fifo.rd_addr[9] -.sym 5285 rx_09_fifo.rd_addr[5] -.sym 5291 $PACKER_VCC_NET -.sym 5520 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 5529 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 5652 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 5889 w_tx_data_io[2] -.sym 5898 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O +.sym 5140 w_rx_09_fifo_pulled_data[26] +.sym 5144 w_rx_09_fifo_pulled_data[27] +.sym 5151 rx_24_fifo.rd_addr[4] +.sym 5154 i_smi_a2_SB_LUT4_I1_O[1] +.sym 5155 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 5156 rx_09_fifo.wr_addr[5] +.sym 5159 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 5161 w_rx_09_fifo_data[18] +.sym 5163 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] +.sym 5164 w_rx_24_fifo_data[26] +.sym 5167 w_rx_24_fifo_pulled_data[3] +.sym 5170 w_rx_24_fifo_pulled_data[19] +.sym 5191 w_lvds_rx_09_d0 +.sym 5199 lvds_rx_09_inst.o_debug_state[0] +.sym 5205 w_lvds_rx_09_d1 +.sym 5233 lvds_rx_09_inst.o_debug_state[0] +.sym 5234 w_lvds_rx_09_d0 +.sym 5243 lvds_rx_09_inst.o_debug_state[0] +.sym 5244 w_lvds_rx_09_d1 +.sym 5259 w_lvds_rx_09_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 5260 lvds_clock_$glb_clk +.sym 5261 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 5263 w_rx_24_fifo_pulled_data[8] +.sym 5267 w_rx_24_fifo_pulled_data[9] +.sym 5274 rx_24_fifo.rd_addr[0] +.sym 5279 w_lvds_rx_09_d0 +.sym 5283 w_rx_09_fifo_pulled_data[26] +.sym 5289 lvds_rx_24_inst.o_debug_state[0] +.sym 5290 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 5291 rx_09_fifo.rd_addr[9] +.sym 5292 rx_24_fifo.rd_addr[6] +.sym 5294 $PACKER_VCC_NET +.sym 5296 w_rx_24_fifo_pulled_data[1] +.sym 5386 w_rx_24_fifo_pulled_data[10] +.sym 5390 w_rx_24_fifo_pulled_data[11] +.sym 5401 rx_24_fifo.wr_addr[4] +.sym 5405 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 5407 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 5409 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 5411 rx_24_fifo.rd_addr[1] +.sym 5414 rx_24_fifo.wr_addr[2] +.sym 5415 rx_24_fifo.wr_addr[5] +.sym 5416 rx_24_fifo.wr_addr[4] +.sym 5417 rx_24_fifo.rd_addr[1] +.sym 5419 rx_24_fifo.rd_addr[8] +.sym 5420 w_rx_24_fifo_pulled_data[27] +.sym 5426 smi_ctrl_ins.int_cnt_24[3] +.sym 5427 w_rx_24_fifo_pulled_data[27] +.sym 5431 w_rx_24_fifo_pulled_data[9] +.sym 5433 smi_ctrl_ins.int_cnt_24[3] +.sym 5435 lvds_rx_24_inst.r_data[8] +.sym 5437 smi_ctrl_ins.int_cnt_24[4] +.sym 5439 w_rx_24_fifo_pulled_data[3] +.sym 5440 w_rx_24_fifo_pulled_data[19] +.sym 5441 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 5446 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 5447 w_rx_24_fifo_pulled_data[11] +.sym 5449 lvds_rx_24_inst.o_debug_state[0] +.sym 5455 w_rx_24_fifo_pulled_data[25] +.sym 5456 w_rx_24_fifo_pulled_data[1] +.sym 5457 w_rx_24_fifo_pulled_data[17] +.sym 5459 w_rx_24_fifo_pulled_data[3] +.sym 5460 w_rx_24_fifo_pulled_data[19] +.sym 5461 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 5462 smi_ctrl_ins.int_cnt_24[3] +.sym 5465 smi_ctrl_ins.int_cnt_24[3] +.sym 5466 w_rx_24_fifo_pulled_data[17] +.sym 5467 w_rx_24_fifo_pulled_data[1] +.sym 5468 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 5483 w_rx_24_fifo_pulled_data[25] +.sym 5484 smi_ctrl_ins.int_cnt_24[3] +.sym 5485 smi_ctrl_ins.int_cnt_24[4] +.sym 5486 w_rx_24_fifo_pulled_data[9] +.sym 5491 lvds_rx_24_inst.o_debug_state[0] +.sym 5492 lvds_rx_24_inst.r_data[8] +.sym 5501 w_rx_24_fifo_pulled_data[27] +.sym 5502 smi_ctrl_ins.int_cnt_24[3] +.sym 5503 w_rx_24_fifo_pulled_data[11] +.sym 5504 smi_ctrl_ins.int_cnt_24[4] +.sym 5505 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 5506 lvds_clock_$glb_clk +.sym 5507 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 5509 w_rx_24_fifo_pulled_data[24] +.sym 5513 w_rx_24_fifo_pulled_data[25] +.sym 5517 smi_ctrl_ins.int_cnt_24[4] +.sym 5520 smi_ctrl_ins.int_cnt_24[3] +.sym 5522 lvds_rx_24_inst.r_data[10] +.sym 5525 smi_ctrl_ins.int_cnt_24[4] +.sym 5529 $PACKER_VCC_NET +.sym 5537 i_smi_a3$SB_IO_IN +.sym 5539 lvds_rx_24_inst.r_data[10] +.sym 5543 w_rx_24_fifo_pulled_data[17] +.sym 5559 lvds_rx_24_inst.o_debug_state[0] +.sym 5567 lvds_rx_24_inst.r_data[6] +.sym 5588 lvds_rx_24_inst.o_debug_state[0] +.sym 5589 lvds_rx_24_inst.r_data[6] +.sym 5628 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 5629 lvds_clock_$glb_clk +.sym 5630 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 5632 w_rx_24_fifo_pulled_data[26] +.sym 5636 w_rx_24_fifo_pulled_data[27] +.sym 5647 rx_24_fifo.wr_addr[7] +.sym 5657 w_rx_24_fifo_data[26] +.sym 5658 w_rx_24_fifo_pulled_data[3] +.sym 5661 w_rx_24_fifo_pulled_data[16] +.sym 5662 w_rx_24_fifo_pulled_data[2] +.sym 5666 w_rx_24_fifo_pulled_data[19] +.sym 5673 lvds_rx_24_inst.r_data[6] +.sym 5675 lvds_rx_24_inst.r_data[0] +.sym 5676 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 5677 w_lvds_rx_24_d0 +.sym 5679 w_lvds_rx_24_d1 +.sym 5681 lvds_rx_24_inst.r_data[8] +.sym 5708 w_lvds_rx_24_d0 +.sym 5711 lvds_rx_24_inst.r_data[0] +.sym 5717 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 5724 lvds_rx_24_inst.r_data[8] +.sym 5735 w_lvds_rx_24_d1 +.sym 5742 lvds_rx_24_inst.r_data[6] +.sym 5751 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 5752 lvds_clock_$glb_clk +.sym 5755 w_rx_24_fifo_pulled_data[16] +.sym 5759 w_rx_24_fifo_pulled_data[17] +.sym 5767 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 5768 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 5775 rx_24_fifo.wr_addr[5] +.sym 5778 $PACKER_VCC_NET +.sym 5779 lvds_rx_24_inst.o_debug_state[0] +.sym 5780 rx_24_fifo.rd_addr[6] +.sym 5781 w_rx_24_fifo_data[10] +.sym 5782 lvds_rx_24_inst.o_debug_state[0] +.sym 5784 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 5795 lvds_rx_24_inst.r_data[2] +.sym 5799 w_lvds_rx_24_d0 +.sym 5802 lvds_rx_24_inst.r_data[4] +.sym 5803 lvds_rx_24_inst.o_debug_state[0] +.sym 5822 lvds_rx_24_inst.r_data[0] +.sym 5828 lvds_rx_24_inst.r_data[0] +.sym 5831 lvds_rx_24_inst.o_debug_state[0] +.sym 5834 lvds_rx_24_inst.o_debug_state[0] +.sym 5836 lvds_rx_24_inst.r_data[4] +.sym 5846 lvds_rx_24_inst.o_debug_state[0] +.sym 5847 w_lvds_rx_24_d0 +.sym 5870 lvds_rx_24_inst.o_debug_state[0] +.sym 5871 lvds_rx_24_inst.r_data[2] +.sym 5874 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 5875 lvds_clock_$glb_clk +.sym 5876 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 5878 w_rx_24_fifo_pulled_data[18] +.sym 5882 w_rx_24_fifo_pulled_data[19] +.sym 5889 lvds_rx_24_inst.r_data[2] +.sym 5896 rx_24_fifo.wr_addr[2] +.sym 5898 rx_24_fifo.wr_addr[4] +.sym 5899 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 5901 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 5903 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 5906 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 5907 rx_24_fifo.wr_addr[3] +.sym 5909 rx_24_fifo.wr_addr[8] +.sym 5910 rx_24_fifo.wr_addr[5] +.sym 5911 rx_24_fifo.rd_addr[1] +.sym 5919 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 5922 i_smi_a2_SB_LUT4_I1_O[1] +.sym 5926 w_lvds_rx_24_d1 +.sym 5927 lvds_rx_24_inst.o_debug_state[1] +.sym 5929 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 5930 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 5942 w_lvds_rx_24_d1_SB_LUT4_I1_O[1] +.sym 5943 w_lvds_rx_24_d0 +.sym 5951 w_lvds_rx_24_d0 +.sym 5952 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 5953 lvds_rx_24_inst.o_debug_state[1] +.sym 5954 w_lvds_rx_24_d1 +.sym 5957 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 5959 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 5960 i_smi_a2_SB_LUT4_I1_O[1] +.sym 5965 lvds_rx_24_inst.o_debug_state[1] +.sym 5970 i_smi_a2_SB_LUT4_I1_O[1] +.sym 5971 w_lvds_rx_24_d1_SB_LUT4_I1_O[1] +.sym 5972 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 6001 w_rx_24_fifo_pulled_data[0] +.sym 6005 w_rx_24_fifo_pulled_data[1] +.sym 6009 lvds_rx_24_inst.o_debug_state[1] +.sym 6012 lvds_rx_24_inst.o_debug_state[0] +.sym 6016 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E +.sym 6033 i_smi_a3$SB_IO_IN +.sym 6041 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 6043 lvds_rx_24_inst.o_debug_state[1] +.sym 6046 lvds_rx_24_inst.r_phase_count[1] +.sym 6047 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 6048 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 6049 lvds_rx_24_inst.o_debug_state[0] +.sym 6050 $PACKER_VCC_NET +.sym 6051 lvds_rx_24_inst.o_debug_state[1] +.sym 6052 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 6053 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 6054 lvds_rx_24_inst.o_debug_state[0] +.sym 6066 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 6068 lvds_rx_24_inst.r_phase_count[0] +.sym 6072 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 6073 $nextpnr_ICESTORM_LC_3$O +.sym 6076 lvds_rx_24_inst.r_phase_count[0] +.sym 6079 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 6081 $PACKER_VCC_NET +.sym 6082 lvds_rx_24_inst.r_phase_count[1] +.sym 6083 lvds_rx_24_inst.r_phase_count[0] +.sym 6086 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 6088 $PACKER_VCC_NET +.sym 6089 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 6092 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 6098 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 6099 lvds_rx_24_inst.o_debug_state[0] +.sym 6100 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 6101 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 6107 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 6110 lvds_rx_24_inst.o_debug_state[0] +.sym 6111 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 6112 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 6113 lvds_rx_24_inst.o_debug_state[1] +.sym 6116 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 6117 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 6118 lvds_rx_24_inst.o_debug_state[0] +.sym 6119 lvds_rx_24_inst.o_debug_state[1] +.sym 6120 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 6121 lvds_clock_$glb_clk +.sym 6122 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 6124 w_rx_24_fifo_pulled_data[2] +.sym 6128 w_rx_24_fifo_pulled_data[3] +.sym 6142 w_rx_24_fifo_data[25] +.sym 6145 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 6146 o_shdn_tx_lna$SB_IO_OUT +.sym 6150 w_rx_24_fifo_pulled_data[3] +.sym 6154 w_rx_24_fifo_data[26] +.sym 6158 w_rx_24_fifo_pulled_data[2] .sym 6246 i_smi_a3$SB_IO_IN +.sym 6266 $PACKER_VCC_NET .sym 6294 o_shdn_tx_lna$SB_IO_OUT -.sym 6308 o_shdn_tx_lna$SB_IO_OUT -.sym 6316 o_shdn_tx_lna$SB_IO_OUT +.sym 6303 o_shdn_tx_lna$SB_IO_OUT +.sym 6350 w_rx_09_fifo_data[15] .sym 6378 i_smi_a3$SB_IO_IN -.sym 6386 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6388 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 6387 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 6388 w_rx_09_fifo_data[29] .sym 6389 rx_09_fifo.wr_addr[7] -.sym 6390 rx_09_fifo.wr_addr[4] -.sym 6395 w_rx_09_fifo_data[12] -.sym 6398 rx_09_fifo.wr_addr[9] -.sym 6399 $PACKER_VCC_NET -.sym 6400 rx_09_fifo.wr_addr[5] -.sym 6403 rx_09_fifo.wr_addr[3] -.sym 6410 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 6411 rx_09_fifo.wr_addr[8] -.sym 6413 rx_09_fifo.wr_addr[6] -.sym 6415 w_rx_09_fifo_data[13] -.sym 6417 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 6423 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 6424 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 6425 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 6426 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] -.sym 6427 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 6428 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 6429 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 6438 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6439 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 6441 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 6442 rx_09_fifo.wr_addr[3] +.sym 6390 $PACKER_VCC_NET +.sym 6393 rx_09_fifo.wr_addr[5] +.sym 6395 w_rx_09_fifo_data[28] +.sym 6396 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6397 rx_09_fifo.wr_addr[4] +.sym 6399 rx_09_fifo.wr_addr[6] +.sym 6401 rx_09_fifo.wr_addr[8] +.sym 6402 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6406 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 6412 rx_09_fifo.wr_addr[9] +.sym 6413 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 6424 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6425 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 6426 rx_09_fifo.rd_addr[4] +.sym 6427 rx_09_fifo.rd_addr[5] +.sym 6428 rx_09_fifo.rd_addr[6] +.sym 6429 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6438 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 6439 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6441 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6442 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 6443 rx_09_fifo.wr_addr[4] .sym 6444 rx_09_fifo.wr_addr[5] .sym 6445 rx_09_fifo.wr_addr[6] @@ -5075,90 +5680,99 @@ .sym 6448 rx_09_fifo.wr_addr[9] .sym 6449 lvds_clock_$glb_clk .sym 6450 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6452 w_rx_09_fifo_data[12] -.sym 6456 w_rx_09_fifo_data[13] +.sym 6452 w_rx_09_fifo_data[28] +.sym 6456 w_rx_09_fifo_data[29] .sym 6459 $PACKER_VCC_NET -.sym 6464 rx_09_fifo.rd_addr[4] -.sym 6468 rx_09_fifo.rd_addr[5] -.sym 6470 rx_09_fifo.rd_addr[6] -.sym 6498 $PACKER_VCC_NET -.sym 6503 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6506 lvds_rx_09_inst.r_data[3] -.sym 6511 $PACKER_VCC_NET -.sym 6520 w_smi_data_output[6] -.sym 6528 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 6530 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 6532 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6535 rx_09_fifo.rd_addr[7] +.sym 6465 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 6466 w_rx_09_fifo_pulled_data[5] +.sym 6467 rx_09_fifo.wr_addr[7] +.sym 6468 w_rx_09_fifo_pulled_data[4] +.sym 6473 lvds_rx_09_inst.r_data[11] +.sym 6475 lvds_rx_09_inst.r_data[12] +.sym 6478 w_smi_data_output[6] +.sym 6482 rx_09_fifo.rd_addr[0] +.sym 6487 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 6490 lvds_rx_09_inst.r_data[13] +.sym 6495 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6501 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 6502 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6509 rx_09_fifo.rd_addr[5] +.sym 6511 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 6512 rx_09_fifo.rd_addr[6] +.sym 6513 rx_09_fifo.rd_addr[9] +.sym 6514 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6532 $PACKER_VCC_NET .sym 6538 rx_09_fifo.rd_addr[1] -.sym 6541 $PACKER_VCC_NET -.sym 6542 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 6543 w_rx_09_fifo_data[14] -.sym 6544 rx_09_fifo.rd_addr[8] -.sym 6550 w_rx_09_fifo_data[15] -.sym 6551 rx_09_fifo.rd_addr[5] -.sym 6553 rx_09_fifo.rd_addr[6] -.sym 6554 rx_09_fifo.rd_addr[9] -.sym 6555 rx_09_fifo.rd_addr[4] -.sym 6560 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 6561 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 6562 lvds_rx_09_inst.r_data[27] -.sym 6563 lvds_rx_09_inst.r_data[7] -.sym 6564 lvds_rx_09_inst.r_data[5] -.sym 6565 lvds_rx_09_inst.r_data[22] -.sym 6566 lvds_rx_09_inst.r_data[20] -.sym 6567 lvds_rx_09_inst.r_data[24] -.sym 6576 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 6539 rx_09_fifo.rd_addr[0] +.sym 6541 rx_09_fifo.rd_addr[4] +.sym 6544 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 6545 rx_09_fifo.rd_addr[9] +.sym 6546 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6547 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 6548 w_rx_09_fifo_data[30] +.sym 6549 rx_09_fifo.rd_addr[5] +.sym 6550 rx_09_fifo.rd_addr[6] +.sym 6551 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6555 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 6557 w_rx_09_fifo_data[31] +.sym 6560 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 6561 rx_09_fifo.rd_addr[9] +.sym 6565 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 6576 rx_09_fifo.rd_addr[0] .sym 6577 rx_09_fifo.rd_addr[1] -.sym 6579 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6580 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 6579 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6580 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 6581 rx_09_fifo.rd_addr[4] .sym 6582 rx_09_fifo.rd_addr[5] .sym 6583 rx_09_fifo.rd_addr[6] -.sym 6584 rx_09_fifo.rd_addr[7] -.sym 6585 rx_09_fifo.rd_addr[8] +.sym 6584 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6585 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 6586 rx_09_fifo.rd_addr[9] .sym 6587 r_counter_$glb_clk -.sym 6588 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 6588 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 6589 $PACKER_VCC_NET -.sym 6593 w_rx_09_fifo_data[15] -.sym 6597 w_rx_09_fifo_data[14] -.sym 6602 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 6603 w_rx_09_fifo_pulled_data[20] -.sym 6604 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 6606 rx_09_fifo.rd_addr[1] -.sym 6607 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 6612 rx_09_fifo.rd_addr[8] -.sym 6616 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6617 rx_09_fifo.wr_addr[5] -.sym 6618 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 6622 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6624 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 6630 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6632 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6633 rx_09_fifo.wr_addr[3] -.sym 6636 rx_09_fifo.wr_addr[4] -.sym 6637 rx_09_fifo.wr_addr[7] -.sym 6638 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 6639 rx_09_fifo.wr_addr[8] -.sym 6640 rx_09_fifo.wr_addr[5] -.sym 6641 w_rx_09_fifo_data[5] -.sym 6643 $PACKER_VCC_NET -.sym 6645 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 6650 w_rx_09_fifo_data[4] -.sym 6658 rx_09_fifo.wr_addr[9] -.sym 6661 rx_09_fifo.wr_addr[6] -.sym 6663 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] -.sym 6664 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2] -.sym 6665 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] -.sym 6666 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4] -.sym 6667 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5] -.sym 6668 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] -.sym 6669 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7] -.sym 6678 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6679 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 6681 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 6682 rx_09_fifo.wr_addr[3] +.sym 6593 w_rx_09_fifo_data[31] +.sym 6597 w_rx_09_fifo_data[30] +.sym 6599 rx_09_fifo.rd_addr[5] +.sym 6602 w_rx_24_fifo_data[26] +.sym 6603 rx_09_fifo.rd_addr[6] +.sym 6605 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 6607 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6608 $PACKER_VCC_NET +.sym 6610 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 6612 $PACKER_VCC_NET +.sym 6613 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6614 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6615 smi_ctrl_ins.soe_and_reset +.sym 6616 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 6618 rx_09_fifo.rd_addr[4] +.sym 6624 w_rx_09_fifo_pulled_data[16] +.sym 6631 rx_09_fifo.wr_addr[7] +.sym 6632 w_rx_09_fifo_data[9] +.sym 6633 rx_09_fifo.wr_addr[5] +.sym 6636 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6639 rx_09_fifo.wr_addr[6] +.sym 6640 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6641 rx_09_fifo.wr_addr[4] +.sym 6642 rx_09_fifo.wr_addr[9] +.sym 6643 w_rx_09_fifo_data[8] +.sym 6645 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 6648 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 6649 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 6655 rx_09_fifo.wr_addr[8] +.sym 6659 $PACKER_VCC_NET +.sym 6662 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 6663 w_rx_09_fifo_full +.sym 6664 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 6665 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 6666 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 6667 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] +.sym 6668 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 6669 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 6678 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 6679 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6681 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6682 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 6683 rx_09_fifo.wr_addr[4] .sym 6684 rx_09_fifo.wr_addr[5] .sym 6685 rx_09_fifo.wr_addr[6] @@ -5167,86 +5781,90 @@ .sym 6688 rx_09_fifo.wr_addr[9] .sym 6689 lvds_clock_$glb_clk .sym 6690 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6692 w_rx_09_fifo_data[4] -.sym 6696 w_rx_09_fifo_data[5] +.sym 6692 w_rx_09_fifo_data[8] +.sym 6696 w_rx_09_fifo_data[9] .sym 6699 $PACKER_VCC_NET -.sym 6706 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 6709 i_smi_a3$SB_IO_IN -.sym 6716 rx_09_fifo.rd_addr[9] -.sym 6718 w_rx_09_fifo_pulled_data[31] -.sym 6721 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] -.sym 6723 w_rx_09_fifo_push -.sym 6726 w_rx_09_fifo_pulled_data[30] +.sym 6704 lvds_rx_09_inst.r_data[15] +.sym 6705 rx_09_fifo.wr_addr[6] +.sym 6707 rx_09_fifo.wr_addr[5] +.sym 6708 rx_09_fifo.rd_addr[1] +.sym 6709 rx_09_fifo.wr_addr[4] +.sym 6710 rx_09_fifo.wr_addr[9] +.sym 6711 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 6712 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6713 rx_09_fifo.rd_addr[9] +.sym 6715 rx_09_fifo.wr_addr[7] +.sym 6718 rx_09_fifo.rd_addr[0] +.sym 6720 i_smi_a2_SB_LUT4_I1_O[0] +.sym 6721 rx_09_fifo.rd_addr[5] +.sym 6723 w_rx_09_fifo_pulled_data[17] +.sym 6725 rx_09_fifo.rd_addr[4] +.sym 6726 smi_ctrl_ins.soe_and_reset +.sym 6727 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6732 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 6733 rx_09_fifo.rd_addr[9] -.sym 6734 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 6735 rx_09_fifo.rd_addr[5] -.sym 6736 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 6737 rx_09_fifo.rd_addr[1] -.sym 6738 w_rx_09_fifo_data[6] -.sym 6739 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 6741 rx_09_fifo.rd_addr[6] -.sym 6743 rx_09_fifo.rd_addr[4] -.sym 6745 $PACKER_VCC_NET -.sym 6746 rx_09_fifo.rd_addr[7] -.sym 6750 rx_09_fifo.rd_addr[8] -.sym 6754 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6763 w_rx_09_fifo_data[7] -.sym 6764 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] -.sym 6765 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] -.sym 6766 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] -.sym 6767 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] -.sym 6768 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[2] -.sym 6769 w_rx_09_fifo_data[3] -.sym 6770 w_rx_09_fifo_data[25] -.sym 6771 w_rx_09_fifo_data[1] -.sym 6780 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 6739 rx_09_fifo.rd_addr[1] +.sym 6742 rx_09_fifo.rd_addr[5] +.sym 6745 rx_09_fifo.rd_addr[0] +.sym 6746 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6748 w_rx_09_fifo_data[11] +.sym 6751 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 6752 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6754 rx_09_fifo.rd_addr[4] +.sym 6757 w_rx_09_fifo_data[10] +.sym 6759 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 6761 $PACKER_VCC_NET +.sym 6763 rx_09_fifo.rd_addr[6] +.sym 6764 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] +.sym 6765 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] +.sym 6766 smi_ctrl_ins.int_cnt_09[4] +.sym 6767 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] +.sym 6768 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] +.sym 6769 smi_ctrl_ins.int_cnt_09[3] +.sym 6771 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E +.sym 6780 rx_09_fifo.rd_addr[0] .sym 6781 rx_09_fifo.rd_addr[1] -.sym 6783 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6784 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 6783 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6784 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 6785 rx_09_fifo.rd_addr[4] .sym 6786 rx_09_fifo.rd_addr[5] .sym 6787 rx_09_fifo.rd_addr[6] -.sym 6788 rx_09_fifo.rd_addr[7] -.sym 6789 rx_09_fifo.rd_addr[8] +.sym 6788 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6789 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 6790 rx_09_fifo.rd_addr[9] .sym 6791 r_counter_$glb_clk -.sym 6792 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 6792 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 6793 $PACKER_VCC_NET -.sym 6797 w_rx_09_fifo_data[7] -.sym 6801 w_rx_09_fifo_data[6] -.sym 6806 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 6808 rx_09_fifo.wr_addr[7] -.sym 6809 lvds_rx_09_inst.r_cnt[0] -.sym 6810 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 6812 rx_09_fifo.wr_addr[8] -.sym 6814 rx_09_fifo.wr_addr[3] -.sym 6818 $PACKER_VCC_NET -.sym 6820 w_rx_09_fifo_data[0] -.sym 6821 $PACKER_VCC_NET +.sym 6797 w_rx_09_fifo_data[11] +.sym 6801 w_rx_09_fifo_data[10] +.sym 6808 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 6810 w_rx_09_fifo_data[23] +.sym 6815 rx_09_fifo.rd_addr[1] +.sym 6820 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6821 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6824 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] .sym 6826 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6834 rx_09_fifo.wr_addr[4] -.sym 6838 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6844 rx_09_fifo.wr_addr[9] -.sym 6845 w_rx_09_fifo_data[0] -.sym 6846 rx_09_fifo.wr_addr[5] -.sym 6848 rx_09_fifo.wr_addr[7] +.sym 6837 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6838 $PACKER_VCC_NET +.sym 6840 rx_09_fifo.wr_addr[6] +.sym 6841 rx_09_fifo.wr_addr[7] +.sym 6843 rx_09_fifo.wr_addr[8] +.sym 6844 rx_09_fifo.wr_addr[5] +.sym 6845 rx_09_fifo.wr_addr[4] +.sym 6846 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 6847 w_rx_09_fifo_data[24] +.sym 6849 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 6850 w_rx_09_fifo_data[25] .sym 6852 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6853 rx_09_fifo.wr_addr[3] -.sym 6854 $PACKER_VCC_NET -.sym 6855 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 6856 rx_09_fifo.wr_addr[8] -.sym 6859 rx_09_fifo.wr_addr[6] -.sym 6863 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 6865 w_rx_09_fifo_data[1] -.sym 6866 lvds_rx_09_inst.r_push -.sym 6867 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 6856 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6862 rx_09_fifo.wr_addr[9] .sym 6868 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6870 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6871 rx_09_fifo.wr_addr[5] -.sym 6882 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6883 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 6885 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 6886 rx_09_fifo.wr_addr[3] +.sym 6870 w_cs[1] +.sym 6872 w_cs[2] +.sym 6882 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 6883 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 6885 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 6886 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 6887 rx_09_fifo.wr_addr[4] .sym 6888 rx_09_fifo.wr_addr[5] .sym 6889 rx_09_fifo.wr_addr[6] @@ -5255,86 +5873,98 @@ .sym 6892 rx_09_fifo.wr_addr[9] .sym 6893 lvds_clock_$glb_clk .sym 6894 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 6896 w_rx_09_fifo_data[0] -.sym 6900 w_rx_09_fifo_data[1] +.sym 6896 w_rx_09_fifo_data[24] +.sym 6900 w_rx_09_fifo_data[25] .sym 6903 $PACKER_VCC_NET .sym 6907 i_smi_a3$SB_IO_IN -.sym 6908 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 6910 rx_09_fifo.wr_addr[9] -.sym 6912 w_rx_09_fifo_pulled_data[24] -.sym 6913 i_smi_a2$SB_IO_IN -.sym 6914 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 6915 lvds_rx_09_inst.r_data[1] -.sym 6918 rx_09_fifo.wr_addr[4] -.sym 6919 lvds_rx_09_inst.r_data[3] -.sym 6920 w_lvds_rx_09_d0 -.sym 6922 w_rx_09_fifo_pulled_data[27] -.sym 6923 $PACKER_VCC_NET -.sym 6926 w_lvds_rx_09_d1 -.sym 6930 w_rx_09_fifo_pulled_data[26] -.sym 6938 rx_09_fifo.rd_addr[8] -.sym 6939 rx_09_fifo.rd_addr[9] -.sym 6940 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6941 rx_09_fifo.rd_addr[5] -.sym 6942 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 6944 rx_09_fifo.rd_addr[1] -.sym 6946 rx_09_fifo.rd_addr[7] -.sym 6947 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 6949 w_rx_09_fifo_data[3] -.sym 6950 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 6951 w_rx_09_fifo_data[2] -.sym 6956 $PACKER_VCC_NET -.sym 6958 rx_09_fifo.rd_addr[4] -.sym 6965 rx_09_fifo.rd_addr[6] -.sym 6970 sys_ctrl_ins.reset_count[2] -.sym 6971 sys_ctrl_ins.reset_count[3] -.sym 6972 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 6973 sys_ctrl_ins.reset_count[0] -.sym 6974 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E -.sym 6975 sys_ctrl_ins.reset_count[1] -.sym 6984 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 6908 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 6909 rx_09_fifo.wr_addr[8] +.sym 6912 i_smi_a2_SB_LUT4_I1_O[1] +.sym 6913 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 6915 rx_09_fifo.wr_addr[6] +.sym 6917 rx_09_fifo.wr_addr[7] +.sym 6918 rx_09_fifo.rd_addr[0] +.sym 6920 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 6921 w_cs[1] +.sym 6923 rx_09_fifo.rd_addr[5] +.sym 6925 w_cs[2] +.sym 6926 rx_09_fifo.rd_addr[6] +.sym 6927 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6928 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 6930 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 6936 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 6937 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6938 w_rx_09_fifo_data[26] +.sym 6939 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 6943 rx_09_fifo.rd_addr[1] +.sym 6946 rx_09_fifo.rd_addr[9] +.sym 6947 rx_09_fifo.rd_addr[0] +.sym 6948 rx_09_fifo.rd_addr[5] +.sym 6949 $PACKER_VCC_NET +.sym 6951 rx_09_fifo.rd_addr[6] +.sym 6952 rx_09_fifo.rd_addr[4] +.sym 6954 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6963 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 6967 w_rx_09_fifo_data[27] +.sym 6970 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 6971 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 6972 rx_24_fifo.rd_addr[4] +.sym 6973 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 6974 rx_24_fifo.rd_addr[6] +.sym 6975 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 6984 rx_09_fifo.rd_addr[0] .sym 6985 rx_09_fifo.rd_addr[1] -.sym 6987 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 6988 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 6987 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 6988 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 6989 rx_09_fifo.rd_addr[4] .sym 6990 rx_09_fifo.rd_addr[5] .sym 6991 rx_09_fifo.rd_addr[6] -.sym 6992 rx_09_fifo.rd_addr[7] -.sym 6993 rx_09_fifo.rd_addr[8] +.sym 6992 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 6993 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 6994 rx_09_fifo.rd_addr[9] .sym 6995 r_counter_$glb_clk -.sym 6996 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 6996 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 6997 $PACKER_VCC_NET -.sym 7001 w_rx_09_fifo_data[3] -.sym 7005 w_rx_09_fifo_data[2] -.sym 7015 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 7016 w_rx_09_fifo_data[11] -.sym 7021 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 7022 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 7024 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 7025 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 7028 w_lvds_rx_09_d1 -.sym 7029 w_rx_09_fifo_pulled_data[10] -.sym 7038 rx_09_fifo.wr_addr[6] -.sym 7039 rx_09_fifo.wr_addr[7] +.sym 7001 w_rx_09_fifo_data[27] +.sym 7005 w_rx_09_fifo_data[26] +.sym 7010 $PACKER_VCC_NET +.sym 7011 w_cs[2] +.sym 7012 w_rx_09_fifo_data[7] +.sym 7015 $PACKER_VCC_NET +.sym 7018 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] +.sym 7019 i_smi_a2_SB_LUT4_I1_O[1] +.sym 7020 $PACKER_VCC_NET +.sym 7022 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 7023 rx_24_fifo.rd_addr[4] +.sym 7026 rx_09_fifo.rd_addr[1] +.sym 7028 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 7029 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 7030 rx_24_fifo.rd_addr[1] +.sym 7031 rx_09_fifo.rd_addr[4] +.sym 7032 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 7038 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] .sym 7040 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 7042 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 7043 rx_09_fifo.wr_addr[5] -.sym 7044 w_rx_09_fifo_data[16] -.sym 7045 rx_09_fifo.wr_addr[3] -.sym 7047 w_rx_09_fifo_data[17] -.sym 7050 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 7051 rx_09_fifo.wr_addr[8] -.sym 7053 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 7056 rx_09_fifo.wr_addr[4] -.sym 7066 rx_09_fifo.wr_addr[9] -.sym 7067 $PACKER_VCC_NET -.sym 7075 sys_ctrl_ins.reset_cmd -.sym 7076 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R -.sym 7086 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 7087 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 7089 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 7090 rx_09_fifo.wr_addr[3] +.sym 7041 rx_09_fifo.wr_addr[7] +.sym 7044 w_rx_09_fifo_data[1] +.sym 7047 rx_09_fifo.wr_addr[4] +.sym 7048 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 7049 w_rx_09_fifo_data[0] +.sym 7050 rx_09_fifo.wr_addr[9] +.sym 7051 $PACKER_VCC_NET +.sym 7052 rx_09_fifo.wr_addr[5] +.sym 7053 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 7055 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 7065 rx_09_fifo.wr_addr[6] +.sym 7069 rx_09_fifo.wr_addr[8] +.sym 7070 rx_24_fifo.rd_addr[8] +.sym 7071 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 7072 rx_24_fifo.rd_addr[1] +.sym 7074 rx_24_fifo.rd_addr[0] +.sym 7076 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 7086 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 7087 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 7089 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 7090 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 7091 rx_09_fifo.wr_addr[4] .sym 7092 rx_09_fifo.wr_addr[5] .sym 7093 rx_09_fifo.wr_addr[6] @@ -5343,2903 +5973,4513 @@ .sym 7096 rx_09_fifo.wr_addr[9] .sym 7097 lvds_clock_$glb_clk .sym 7098 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 7100 w_rx_09_fifo_data[16] -.sym 7104 w_rx_09_fifo_data[17] +.sym 7100 w_rx_09_fifo_data[0] +.sym 7104 w_rx_09_fifo_data[1] .sym 7107 $PACKER_VCC_NET -.sym 7114 i_smi_a3$SB_IO_IN -.sym 7115 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 7116 w_rx_09_fifo_pulled_data[8] -.sym 7125 w_cs[0] -.sym 7140 rx_09_fifo.rd_addr[4] -.sym 7143 rx_09_fifo.rd_addr[7] -.sym 7144 w_rx_09_fifo_data[19] -.sym 7149 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 7150 rx_09_fifo.rd_addr[9] -.sym 7151 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 7152 rx_09_fifo.rd_addr[5] -.sym 7153 rx_09_fifo.rd_addr[6] -.sym 7154 rx_09_fifo.rd_addr[1] -.sym 7158 rx_09_fifo.rd_addr[8] -.sym 7160 $PACKER_VCC_NET -.sym 7162 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 7163 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 7169 w_rx_09_fifo_data[18] -.sym 7188 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 7113 rx_24_fifo.rd_addr[6] +.sym 7114 w_rx_09_fifo_pulled_data[25] +.sym 7115 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 7116 w_rx_09_fifo_pulled_data[24] +.sym 7117 rx_09_fifo.wr_addr[7] +.sym 7119 $PACKER_VCC_NET +.sym 7123 rx_09_fifo.wr_addr[4] +.sym 7124 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 7126 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 7128 rx_24_fifo.rd_addr[4] +.sym 7129 $PACKER_VCC_NET +.sym 7130 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 7132 rx_24_fifo.rd_addr[6] +.sym 7133 rx_24_fifo.rd_addr[8] +.sym 7134 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 7135 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 7144 $PACKER_VCC_NET +.sym 7149 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 7150 rx_09_fifo.rd_addr[5] +.sym 7151 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 7153 rx_09_fifo.rd_addr[0] +.sym 7154 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 7155 rx_09_fifo.rd_addr[6] +.sym 7156 w_rx_09_fifo_data[2] +.sym 7157 rx_09_fifo.rd_addr[9] +.sym 7160 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 7164 rx_09_fifo.rd_addr[1] +.sym 7165 w_rx_09_fifo_data[3] +.sym 7169 rx_09_fifo.rd_addr[4] +.sym 7170 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 7172 w_rx_24_fifo_data[12] +.sym 7174 w_rx_24_fifo_data[27] +.sym 7175 w_rx_24_fifo_data[19] +.sym 7178 w_rx_24_fifo_data[16] +.sym 7179 w_rx_24_fifo_data[18] +.sym 7188 rx_09_fifo.rd_addr[0] .sym 7189 rx_09_fifo.rd_addr[1] -.sym 7191 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 7192 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 7191 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 7192 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 7193 rx_09_fifo.rd_addr[4] .sym 7194 rx_09_fifo.rd_addr[5] .sym 7195 rx_09_fifo.rd_addr[6] -.sym 7196 rx_09_fifo.rd_addr[7] -.sym 7197 rx_09_fifo.rd_addr[8] +.sym 7196 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 7197 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 7198 rx_09_fifo.rd_addr[9] .sym 7199 r_counter_$glb_clk -.sym 7200 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 7200 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 7201 $PACKER_VCC_NET -.sym 7205 w_rx_09_fifo_data[19] -.sym 7209 w_rx_09_fifo_data[18] -.sym 7215 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R -.sym 7233 $PACKER_VCC_NET -.sym 7274 w_cs[0] -.sym 7338 $PACKER_VCC_NET -.sym 7376 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 7377 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 7379 $PACKER_VCC_NET -.sym 7381 w_tx_data_sys[0] -.sym 7426 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 7481 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 7523 $PACKER_VCC_NET -.sym 7524 w_fetch -.sym 7527 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 7529 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 7583 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 7584 w_tx_data_io[2] -.sym 7585 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 7829 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 7949 o_shdn_rx_lna$SB_IO_OUT -.sym 8088 lvds_clock +.sym 7205 w_rx_09_fifo_data[3] +.sym 7209 w_rx_09_fifo_data[2] +.sym 7212 w_rx_24_fifo_pulled_data[1] +.sym 7218 w_rx_09_fifo_data[19] +.sym 7221 rx_24_fifo.rd_addr[8] +.sym 7223 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 7225 rx_24_fifo.rd_addr[1] +.sym 7226 rx_24_fifo.rd_addr[1] +.sym 7229 w_rx_24_fifo_data[17] +.sym 7230 rx_24_fifo.rd_addr[0] +.sym 7231 rx_24_fifo.wr_addr[0] +.sym 7233 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E +.sym 7234 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 7237 rx_24_fifo.wr_addr[7] +.sym 7243 rx_24_fifo.wr_addr[7] +.sym 7244 w_rx_24_fifo_data[17] +.sym 7246 rx_24_fifo.wr_addr[0] +.sym 7247 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 7253 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 7255 $PACKER_VCC_NET +.sym 7257 rx_24_fifo.wr_addr[4] +.sym 7258 rx_24_fifo.wr_addr[8] +.sym 7264 w_rx_24_fifo_data[16] +.sym 7265 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 7266 rx_24_fifo.wr_addr[3] +.sym 7267 rx_24_fifo.wr_addr[2] +.sym 7268 rx_24_fifo.wr_addr[5] +.sym 7269 rx_24_fifo.wr_addr[6] +.sym 7275 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] +.sym 7276 sys_ctrl_ins.reset_cmd +.sym 7277 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 7278 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] +.sym 7279 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 7280 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 7290 rx_24_fifo.wr_addr[0] +.sym 7291 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 7293 rx_24_fifo.wr_addr[2] +.sym 7294 rx_24_fifo.wr_addr[3] +.sym 7295 rx_24_fifo.wr_addr[4] +.sym 7296 rx_24_fifo.wr_addr[5] +.sym 7297 rx_24_fifo.wr_addr[6] +.sym 7298 rx_24_fifo.wr_addr[7] +.sym 7299 rx_24_fifo.wr_addr[8] +.sym 7300 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 7301 lvds_clock_$glb_clk +.sym 7302 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 7304 w_rx_24_fifo_data[16] +.sym 7308 w_rx_24_fifo_data[17] +.sym 7311 $PACKER_VCC_NET +.sym 7319 lvds_rx_24_inst.r_data[10] +.sym 7323 $PACKER_VCC_NET +.sym 7327 i_smi_a3$SB_IO_IN +.sym 7328 w_rx_24_fifo_data[27] +.sym 7329 rx_24_fifo.rd_addr[8] +.sym 7330 w_rx_24_fifo_pulled_data[26] +.sym 7331 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 7335 rx_24_fifo.wr_addr[6] +.sym 7336 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 7337 rx_24_fifo.rd_addr[0] +.sym 7338 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 7346 rx_24_fifo.rd_addr[6] +.sym 7348 $PACKER_VCC_NET +.sym 7352 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 7353 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 7355 w_rx_24_fifo_data[19] +.sym 7357 rx_24_fifo.rd_addr[4] +.sym 7359 w_rx_24_fifo_data[18] +.sym 7360 rx_24_fifo.rd_addr[8] +.sym 7361 rx_24_fifo.rd_addr[1] +.sym 7363 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 7365 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 7369 rx_24_fifo.rd_addr[0] +.sym 7371 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 7372 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 7376 rx_24_fifo.empty_o_SB_LUT4_I0_I1[1] +.sym 7377 rx_24_fifo.empty_o_SB_LUT4_I0_I1[2] +.sym 7378 rx_24_fifo.wr_addr[0] +.sym 7379 rx_24_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 7380 rx_24_fifo.empty_o_SB_LUT4_I0_I1[3] +.sym 7381 rx_24_fifo.wr_addr[7] +.sym 7392 rx_24_fifo.rd_addr[0] +.sym 7393 rx_24_fifo.rd_addr[1] +.sym 7395 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 7396 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 7397 rx_24_fifo.rd_addr[4] +.sym 7398 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 7399 rx_24_fifo.rd_addr[6] +.sym 7400 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 7401 rx_24_fifo.rd_addr[8] +.sym 7402 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 7403 r_counter_$glb_clk +.sym 7404 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 7405 $PACKER_VCC_NET +.sym 7409 w_rx_24_fifo_data[19] +.sym 7413 w_rx_24_fifo_data[18] +.sym 7418 smi_ctrl_ins.int_cnt_24[3] +.sym 7421 w_rx_24_fifo_pulled_data[2] +.sym 7424 smi_ctrl_ins.int_cnt_24[3] +.sym 7427 w_rx_24_fifo_pulled_data[16] +.sym 7429 sys_ctrl_ins.reset_cmd +.sym 7432 rx_24_fifo.rd_addr[4] +.sym 7433 rx_24_fifo.wr_addr[7] +.sym 7434 rx_24_fifo.rd_addr[1] +.sym 7436 w_rx_24_fifo_pulled_data[0] +.sym 7437 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 7438 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 7439 rx_24_fifo.rd_addr[4] +.sym 7440 rx_24_fifo.wr_addr[6] +.sym 7446 rx_24_fifo.wr_addr[6] +.sym 7450 $PACKER_VCC_NET +.sym 7455 rx_24_fifo.wr_addr[2] +.sym 7456 rx_24_fifo.wr_addr[5] +.sym 7457 rx_24_fifo.wr_addr[4] +.sym 7462 w_rx_24_fifo_data[0] +.sym 7463 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 7464 rx_24_fifo.wr_addr[0] +.sym 7467 rx_24_fifo.wr_addr[7] +.sym 7469 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 7473 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 7475 w_rx_24_fifo_data[1] +.sym 7476 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+.sym 7854 w_rx_24_fifo_data[25] +.sym 7856 w_rx_24_fifo_data[24] +.sym 7858 rx_24_fifo.wr_addr[8] +.sym 7859 rx_24_fifo.wr_addr[5] +.sym 7864 rx_24_fifo.wr_addr[3] +.sym 7865 rx_24_fifo.wr_addr[6] +.sym 7866 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 7867 $PACKER_VCC_NET +.sym 7868 rx_24_fifo.wr_addr[7] +.sym 7872 rx_24_fifo.wr_addr[0] +.sym 7876 rx_24_fifo.wr_addr[4] +.sym 7879 rx_24_fifo.wr_addr[2] +.sym 7881 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 7884 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 7902 rx_24_fifo.wr_addr[0] +.sym 7903 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 7905 rx_24_fifo.wr_addr[2] +.sym 7906 rx_24_fifo.wr_addr[3] +.sym 7907 rx_24_fifo.wr_addr[4] +.sym 7908 rx_24_fifo.wr_addr[5] +.sym 7909 rx_24_fifo.wr_addr[6] +.sym 7910 rx_24_fifo.wr_addr[7] +.sym 7911 rx_24_fifo.wr_addr[8] +.sym 7912 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 7913 lvds_clock_$glb_clk +.sym 7914 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 7916 w_rx_24_fifo_data[24] +.sym 7920 w_rx_24_fifo_data[25] +.sym 7923 $PACKER_VCC_NET +.sym 7928 lvds_rx_24_inst.o_debug_state[0] +.sym 7930 w_rx_24_fifo_data[24] +.sym 7935 $PACKER_VCC_NET +.sym 7941 rx_24_fifo.rd_addr[6] +.sym 7944 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 7945 rx_24_fifo.rd_addr[4] +.sym 7951 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 7956 rx_24_fifo.rd_addr[6] +.sym 7957 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 7959 rx_24_fifo.rd_addr[1] +.sym 7960 rx_24_fifo.rd_addr[4] +.sym 7961 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 7965 w_rx_24_fifo_data[27] +.sym 7966 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 7967 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 7968 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 7969 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 7972 rx_24_fifo.rd_addr[8] +.sym 7976 $PACKER_VCC_NET +.sym 7978 w_rx_24_fifo_data[26] +.sym 7985 rx_24_fifo.rd_addr[0] +.sym 8000 rx_24_fifo.rd_addr[0] +.sym 8001 rx_24_fifo.rd_addr[1] +.sym 8003 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 8004 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 8005 rx_24_fifo.rd_addr[4] +.sym 8006 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 8007 rx_24_fifo.rd_addr[6] +.sym 8008 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 8009 rx_24_fifo.rd_addr[8] +.sym 8010 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 8011 r_counter_$glb_clk +.sym 8012 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 8013 $PACKER_VCC_NET +.sym 8017 w_rx_24_fifo_data[27] +.sym 8021 w_rx_24_fifo_data[26] +.sym 8044 o_shdn_rx_lna$SB_IO_OUT +.sym 8047 rx_24_fifo.rd_addr[0] +.sym 8088 i_smi_a3$SB_IO_IN .sym 8093 w_smi_data_output[6] .sym 8095 i_smi_a3$SB_IO_IN -.sym 8108 w_smi_data_output[6] +.sym 8104 w_smi_data_output[6] .sym 8114 i_smi_a3$SB_IO_IN -.sym 8120 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 8121 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 8122 rx_09_fifo.rd_addr[4] -.sym 8123 rx_09_fifo.rd_addr[5] -.sym 8124 rx_09_fifo.rd_addr[6] -.sym 8125 rx_09_fifo.rd_addr[7] -.sym 8150 w_smi_data_output[7] -.sym 8246 rx_09_fifo.rd_addr[8] -.sym 8247 rx_09_fifo.rd_addr[9] -.sym 8248 rx_09_fifo.full_o_SB_LUT4_I3_O[2] -.sym 8250 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 8251 rx_09_fifo.rd_addr[1] -.sym 8252 rx_09_fifo.full_o_SB_LUT4_I3_O[1] -.sym 8253 rx_09_fifo.full_o_SB_LUT4_I3_O[3] -.sym 8259 w_smi_data_output[6] -.sym 8261 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 8267 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 8269 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 8274 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8278 rx_09_fifo.wr_addr[5] -.sym 8281 w_smi_data_output[2] -.sym 8284 rx_09_fifo.wr_addr[4] -.sym 8287 rx_09_fifo.rd_addr[4] -.sym 8288 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 8294 rx_09_fifo.rd_addr[7] -.sym 8300 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 8303 rx_09_fifo.wr_addr[7] -.sym 8305 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 8306 rx_09_fifo.wr_addr[6] -.sym 8307 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 8310 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8311 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 8312 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 8326 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8332 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8333 rx_09_fifo.wr_addr[7] -.sym 8335 rx_09_fifo.wr_addr[6] -.sym 8336 rx_09_fifo.wr_addr[5] -.sym 8339 rx_09_fifo.wr_addr[4] -.sym 8341 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 8345 rx_09_fifo.wr_addr[3] -.sym 8355 $nextpnr_ICESTORM_LC_0$O -.sym 8358 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8361 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[2] -.sym 8364 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8365 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8367 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[3] -.sym 8370 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 8371 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[2] -.sym 8373 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[4] -.sym 8375 rx_09_fifo.wr_addr[3] -.sym 8377 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[3] -.sym 8379 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[5] -.sym 8382 rx_09_fifo.wr_addr[4] -.sym 8383 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[4] -.sym 8385 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[6] -.sym 8387 rx_09_fifo.wr_addr[5] -.sym 8389 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[5] -.sym 8391 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[7] -.sym 8393 rx_09_fifo.wr_addr[6] -.sym 8395 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[6] -.sym 8397 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[8] -.sym 8400 rx_09_fifo.wr_addr[7] -.sym 8401 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[7] -.sym 8405 w_rx_09_fifo_data[22] -.sym 8406 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 8407 w_rx_09_fifo_data[0] -.sym 8408 w_rx_09_fifo_data[20] -.sym 8410 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 8411 rx_09_fifo.full_o_SB_LUT4_I3_O[0] -.sym 8412 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 8414 $PACKER_VCC_NET -.sym 8415 $PACKER_VCC_NET -.sym 8420 w_rx_09_fifo_pulled_data[30] -.sym 8426 rx_09_fifo.rd_addr[9] -.sym 8427 w_rx_09_fifo_pulled_data[31] -.sym 8429 rx_09_fifo.wr_addr[8] -.sym 8430 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 8431 rx_09_fifo.wr_addr[3] -.sym 8432 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 8434 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] -.sym 8435 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 8436 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 8437 rx_09_fifo.wr_addr[6] -.sym 8438 rx_09_fifo.rd_addr[4] -.sym 8439 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 8440 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 8441 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[8] -.sym 8450 lvds_rx_09_inst.r_data[3] -.sym 8451 lvds_rx_09_inst.r_data[22] -.sym 8466 lvds_rx_09_inst.r_data[5] -.sym 8467 lvds_rx_09_inst.r_data[25] -.sym 8468 rx_09_fifo.wr_addr[8] -.sym 8472 rx_09_fifo.wr_addr[9] -.sym 8473 lvds_rx_09_inst.r_data[18] -.sym 8476 lvds_rx_09_inst.r_data[20] -.sym 8478 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[9] -.sym 8481 rx_09_fifo.wr_addr[8] -.sym 8482 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[8] -.sym 8487 rx_09_fifo.wr_addr[9] -.sym 8488 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[9] -.sym 8494 lvds_rx_09_inst.r_data[25] -.sym 8500 lvds_rx_09_inst.r_data[5] -.sym 8505 lvds_rx_09_inst.r_data[3] -.sym 8511 lvds_rx_09_inst.r_data[20] -.sym 8517 lvds_rx_09_inst.r_data[18] -.sym 8523 lvds_rx_09_inst.r_data[22] -.sym 8525 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2]_$glb_ce -.sym 8526 lvds_clock_$glb_clk -.sym 8527 w_soft_reset_$glb_sr -.sym 8528 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] -.sym 8529 rx_09_fifo.wr_addr[7] -.sym 8530 rx_09_fifo.wr_addr[6] -.sym 8531 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 8532 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8533 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 8534 rx_09_fifo.wr_addr[8] -.sym 8535 rx_09_fifo.wr_addr[3] -.sym 8544 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 8546 lvds_rx_09_inst.r_data[27] -.sym 8551 w_rx_09_fifo_data[0] -.sym 8552 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8556 rx_09_fifo.wr_addr[4] -.sym 8558 rx_09_fifo.wr_addr[9] -.sym 8559 rx_09_fifo.rd_addr[8] -.sym 8560 rx_09_fifo.wr_addr[5] -.sym 8563 lvds_rx_09_inst.r_data[24] -.sym 8585 rx_09_fifo.wr_addr[4] -.sym 8586 rx_09_fifo.wr_addr[7] -.sym 8587 rx_09_fifo.wr_addr[6] -.sym 8589 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8591 rx_09_fifo.wr_addr[8] -.sym 8595 rx_09_fifo.wr_addr[5] -.sym 8597 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8598 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 8600 rx_09_fifo.wr_addr[3] -.sym 8601 $nextpnr_ICESTORM_LC_8$O -.sym 8603 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8607 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2] -.sym 8609 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 8611 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 8613 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3] -.sym 8616 rx_09_fifo.wr_addr[3] -.sym 8617 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2] -.sym 8619 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4] -.sym 8621 rx_09_fifo.wr_addr[4] -.sym 8623 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3] -.sym 8625 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5] -.sym 8627 rx_09_fifo.wr_addr[5] -.sym 8629 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4] -.sym 8631 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] -.sym 8633 rx_09_fifo.wr_addr[6] -.sym 8635 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5] -.sym 8637 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7] -.sym 8639 rx_09_fifo.wr_addr[7] -.sym 8641 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] -.sym 8643 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] -.sym 8645 rx_09_fifo.wr_addr[8] -.sym 8647 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7] -.sym 8651 rx_09_fifo.wr_addr[4] -.sym 8652 rx_09_fifo.wr_addr[9] -.sym 8653 rx_09_fifo.wr_addr[5] -.sym 8654 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[3] -.sym 8655 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 8656 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[0] -.sym 8657 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8658 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 8666 w_rx_09_fifo_pulled_data[26] -.sym 8667 $PACKER_VCC_NET -.sym 8668 w_rx_09_fifo_pulled_data[27] -.sym 8671 w_lvds_rx_09_d0 -.sym 8672 w_lvds_rx_09_d1 -.sym 8673 lvds_rx_09_inst.r_data[3] -.sym 8674 smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_E -.sym 8675 rx_09_fifo.wr_addr[6] -.sym 8676 w_soft_reset -.sym 8677 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E -.sym 8678 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] -.sym 8679 w_rx_09_fifo_data[25] -.sym 8681 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 8682 rx_09_fifo.rd_addr[7] -.sym 8684 rx_09_fifo.rd_addr[4] -.sym 8686 rx_09_fifo.wr_addr[9] -.sym 8687 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] -.sym 8692 lvds_rx_09_inst.r_data[1] -.sym 8695 w_rx_09_fifo_push -.sym 8696 rx_09_fifo.rd_addr[9] -.sym 8697 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 8699 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7] -.sym 8700 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] -.sym 8701 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] -.sym 8702 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2] -.sym 8703 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 8704 lvds_rx_09_inst.r_data[3] -.sym 8707 rx_09_fifo.wr_addr[3] -.sym 8708 rx_09_fifo.rd_addr[4] -.sym 8709 rx_09_fifo.wr_addr[9] -.sym 8716 rx_09_fifo.wr_addr[4] -.sym 8717 lvds_rx_09_inst.r_data[25] -.sym 8719 rx_09_fifo.rd_addr[8] -.sym 8724 $nextpnr_ICESTORM_LC_9$I3 -.sym 8726 rx_09_fifo.wr_addr[9] -.sym 8728 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] -.sym 8734 $nextpnr_ICESTORM_LC_9$I3 -.sym 8737 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] -.sym 8738 w_rx_09_fifo_push -.sym 8739 rx_09_fifo.rd_addr[8] -.sym 8740 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7] -.sym 8743 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] -.sym 8744 rx_09_fifo.rd_addr[9] -.sym 8745 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2] -.sym 8746 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 8749 rx_09_fifo.wr_addr[3] -.sym 8750 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 8751 rx_09_fifo.rd_addr[4] -.sym 8752 rx_09_fifo.wr_addr[4] -.sym 8757 lvds_rx_09_inst.r_data[3] -.sym 8763 lvds_rx_09_inst.r_data[25] -.sym 8768 lvds_rx_09_inst.r_data[1] -.sym 8771 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 8772 lvds_clock_$glb_clk -.sym 8780 spi_if_ins.state_if[0] -.sym 8781 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 8787 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8792 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] -.sym 8794 w_rx_09_fifo_pulled_data[10] -.sym 8795 w_lvds_rx_09_d1 -.sym 8797 rx_09_fifo.wr_addr[5] -.sym 8805 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 8807 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 8817 rx_09_fifo.wr_addr[5] -.sym 8821 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8825 w_rx_09_fifo_full -.sym 8827 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] -.sym 8829 w_rx_09_fifo_push -.sym 8833 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E -.sym 8835 lvds_rx_09_inst.o_debug_state[0] -.sym 8836 w_soft_reset -.sym 8838 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] -.sym 8840 lvds_rx_09_inst.o_debug_state[1] -.sym 8842 rx_09_fifo.rd_addr[7] -.sym 8844 rx_09_fifo.rd_addr[4] -.sym 8848 lvds_rx_09_inst.o_debug_state[1] -.sym 8849 w_rx_09_fifo_full -.sym 8850 lvds_rx_09_inst.o_debug_state[0] -.sym 8854 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] -.sym 8855 rx_09_fifo.rd_addr[4] -.sym 8856 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] -.sym 8857 rx_09_fifo.rd_addr[7] -.sym 8861 w_rx_09_fifo_push -.sym 8863 w_soft_reset -.sym 8872 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 8881 rx_09_fifo.wr_addr[5] -.sym 8894 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E -.sym 8895 lvds_clock_$glb_clk -.sym 8896 w_soft_reset_$glb_sr -.sym 8897 spi_if_ins.state_if_SB_DFFESR_Q_D[0] -.sym 8901 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 8903 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 8904 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 8909 lvds_rx_09_inst.r_push -.sym 8913 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 8917 w_rx_09_fifo_push -.sym 8928 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 8929 w_rx_09_fifo_empty -.sym 8940 sys_ctrl_ins.reset_count[2] -.sym 8943 sys_ctrl_ins.reset_cmd -.sym 8945 sys_ctrl_ins.reset_count[1] -.sym 8949 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E -.sym 8951 sys_ctrl_ins.reset_cmd -.sym 8957 sys_ctrl_ins.reset_count[3] -.sym 8958 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 8959 sys_ctrl_ins.reset_count[0] -.sym 8965 sys_ctrl_ins.reset_count[3] -.sym 8966 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 8970 $nextpnr_ICESTORM_LC_1$O -.sym 8972 sys_ctrl_ins.reset_count[0] -.sym 8976 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 8979 sys_ctrl_ins.reset_count[1] -.sym 8982 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] -.sym 8983 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 8985 sys_ctrl_ins.reset_count[2] -.sym 8986 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 8990 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 8991 sys_ctrl_ins.reset_count[3] -.sym 8992 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] -.sym 8995 sys_ctrl_ins.reset_count[2] -.sym 8996 sys_ctrl_ins.reset_count[1] -.sym 8997 sys_ctrl_ins.reset_count[3] -.sym 8998 sys_ctrl_ins.reset_count[0] -.sym 9003 sys_ctrl_ins.reset_count[0] -.sym 9008 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 9010 sys_ctrl_ins.reset_cmd -.sym 9013 sys_ctrl_ins.reset_count[1] -.sym 9015 sys_ctrl_ins.reset_count[0] -.sym 9016 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 9017 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E +.sym 8121 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 8124 w_rx_09_fifo_data[12] +.sym 8133 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 8139 rx_24_fifo.rd_addr[4] +.sym 8141 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 8153 w_smi_data_output[7] +.sym 8173 lvds_rx_09_inst.r_data[13] +.sym 8219 lvds_rx_09_inst.r_data[13] +.sym 8239 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 8240 lvds_clock_$glb_clk +.sym 8247 rx_09_fifo.full_o_SB_LUT4_I3_O[0] +.sym 8250 w_rx_24_fifo_data[26] +.sym 8253 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 8257 rx_24_fifo.rd_addr[6] +.sym 8259 w_rx_09_fifo_data[12] +.sym 8260 w_smi_data_output[6] +.sym 8263 w_rx_09_fifo_data[13] +.sym 8266 smi_ctrl_ins.soe_and_reset +.sym 8276 lvds_rx_09_inst.r_data[10] +.sym 8280 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8287 rx_09_fifo.rd_addr[6] +.sym 8290 rx_09_fifo.rd_addr[1] +.sym 8296 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 8298 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8299 lvds_rx_09_inst.o_debug_state[1] +.sym 8300 rx_09_fifo.rd_addr[4] +.sym 8301 w_smi_data_output[1] +.sym 8302 rx_09_fifo.rd_addr[5] +.sym 8305 rx_09_fifo.rd_addr[6] +.sym 8306 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 8307 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 8308 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 8310 i_smi_a2_SB_LUT4_I1_O[1] +.sym 8311 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 8326 rx_09_fifo.rd_addr[0] +.sym 8327 rx_09_fifo.rd_addr[4] +.sym 8329 rx_09_fifo.rd_addr[6] +.sym 8334 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 8338 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 8341 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 8342 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8345 rx_09_fifo.rd_addr[1] +.sym 8352 rx_09_fifo.rd_addr[5] +.sym 8355 $nextpnr_ICESTORM_LC_10$O +.sym 8357 rx_09_fifo.rd_addr[0] +.sym 8361 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 8363 rx_09_fifo.rd_addr[1] +.sym 8367 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 8370 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 8371 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 8373 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 8376 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8377 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 8379 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 8382 rx_09_fifo.rd_addr[4] +.sym 8383 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 8385 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 8387 rx_09_fifo.rd_addr[5] +.sym 8389 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 8391 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 8394 rx_09_fifo.rd_addr[6] +.sym 8395 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 8397 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 8399 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 8401 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 8402 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 8403 r_counter_$glb_clk +.sym 8404 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 8405 rx_09_fifo.full_o_SB_LUT4_I3_O[3] +.sym 8406 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 8407 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 8408 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 8409 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 8410 rx_09_fifo.full_o_SB_LUT4_I3_O[2] +.sym 8411 rx_09_fifo.wr_addr[9] +.sym 8412 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 8419 rx_09_fifo.rd_addr[5] +.sym 8420 smi_ctrl_ins.soe_and_reset +.sym 8422 rx_09_fifo.rd_addr[0] +.sym 8423 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 8425 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8427 rx_09_fifo.rd_addr[4] +.sym 8433 smi_ctrl_ins.int_cnt_09[4] +.sym 8434 rx_09_fifo.wr_addr[9] +.sym 8436 rx_09_fifo.rd_addr[5] +.sym 8439 smi_ctrl_ins.int_cnt_09[3] +.sym 8440 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 8441 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 8447 rx_09_fifo.rd_addr[9] +.sym 8450 rx_09_fifo.rd_addr[4] +.sym 8451 rx_09_fifo.rd_addr[5] +.sym 8462 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 8465 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3] +.sym 8466 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4] +.sym 8473 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 8478 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 8481 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 8482 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 8487 rx_09_fifo.rd_addr[9] +.sym 8488 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 8509 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3] +.sym 8510 rx_09_fifo.rd_addr[4] +.sym 8511 rx_09_fifo.rd_addr[5] +.sym 8512 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4] +.sym 8525 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 8526 r_counter_$glb_clk +.sym 8527 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 8529 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 8530 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2] +.sym 8531 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3] +.sym 8532 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4] +.sym 8533 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 8534 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 8535 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7] +.sym 8544 rx_09_fifo.rd_addr[9] +.sym 8545 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 8546 lvds_rx_09_inst.r_data[19] +.sym 8548 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 8549 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 8551 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 8552 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 8554 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 8556 spi_if_ins.w_rx_data[5] +.sym 8558 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8561 smi_ctrl_ins.int_cnt_09[4] +.sym 8569 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 8570 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 8572 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 8573 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 8574 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 8575 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 8576 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 8578 rx_09_fifo.rd_addr[9] +.sym 8580 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 8581 rx_09_fifo.rd_addr[6] +.sym 8582 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] +.sym 8583 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8584 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 8585 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] +.sym 8586 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] +.sym 8587 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2] +.sym 8588 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 8589 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 8590 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 8591 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 8592 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7] +.sym 8593 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 8595 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 8596 rx_09_fifo.rd_addr[0] +.sym 8597 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 8598 rx_09_fifo.empty_o_SB_LUT4_I3_I2[2] +.sym 8599 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 8600 w_rx_09_fifo_push +.sym 8602 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 8603 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 8604 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 8605 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 8608 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 8609 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 8610 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 8611 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 8614 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2] +.sym 8615 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 8616 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 8617 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 8620 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 8621 w_rx_09_fifo_push +.sym 8622 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] +.sym 8623 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 8627 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 8628 rx_09_fifo.rd_addr[0] +.sym 8632 rx_09_fifo.rd_addr[6] +.sym 8633 rx_09_fifo.rd_addr[9] +.sym 8634 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 8635 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] +.sym 8638 rx_09_fifo.empty_o_SB_LUT4_I3_I2[2] +.sym 8639 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7] +.sym 8640 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 8641 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 8644 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 8645 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 8646 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 8647 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] +.sym 8649 lvds_clock_$glb_clk +.sym 8650 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 8651 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] +.sym 8652 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] +.sym 8654 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E +.sym 8655 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 8656 rx_09_fifo.empty_o_SB_LUT4_I3_I2[2] +.sym 8657 smi_ctrl_ins.r_fifo_24_pull +.sym 8658 w_rx_09_fifo_empty +.sym 8661 rx_24_fifo.wr_addr[7] +.sym 8662 rx_24_fifo.rd_addr[8] +.sym 8664 rx_09_fifo.rd_addr[9] +.sym 8665 $PACKER_GND_NET +.sym 8667 w_rx_09_fifo_full +.sym 8673 rx_09_fifo.rd_addr[5] +.sym 8675 spi_if_ins.w_rx_data[6] +.sym 8677 smi_ctrl_ins.int_cnt_09[3] +.sym 8680 sys_ctrl_ins.reset_cmd +.sym 8682 w_rx_09_fifo_empty +.sym 8683 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] +.sym 8684 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 8685 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 8686 w_rx_09_fifo_push +.sym 8692 smi_ctrl_ins.soe_and_reset +.sym 8693 w_rx_09_fifo_pulled_data[0] +.sym 8695 w_rx_09_fifo_pulled_data[16] +.sym 8697 w_rx_09_fifo_pulled_data[1] +.sym 8699 i_smi_a2_SB_LUT4_I1_O[1] +.sym 8700 i_smi_a2_SB_LUT4_I1_O[0] +.sym 8703 w_rx_09_fifo_pulled_data[17] +.sym 8705 smi_ctrl_ins.int_cnt_09[3] +.sym 8709 w_rx_09_fifo_pulled_data[2] +.sym 8710 smi_ctrl_ins.int_cnt_09[4] +.sym 8713 w_rx_09_fifo_pulled_data[19] +.sym 8717 w_rx_09_fifo_pulled_data[18] +.sym 8718 smi_ctrl_ins.int_cnt_09[4] +.sym 8719 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E +.sym 8721 w_rx_09_fifo_pulled_data[3] +.sym 8725 smi_ctrl_ins.int_cnt_09[4] +.sym 8726 w_rx_09_fifo_pulled_data[0] +.sym 8727 smi_ctrl_ins.int_cnt_09[3] +.sym 8728 w_rx_09_fifo_pulled_data[16] +.sym 8731 w_rx_09_fifo_pulled_data[2] +.sym 8732 smi_ctrl_ins.int_cnt_09[3] +.sym 8733 smi_ctrl_ins.int_cnt_09[4] +.sym 8734 w_rx_09_fifo_pulled_data[18] +.sym 8739 smi_ctrl_ins.int_cnt_09[3] +.sym 8740 smi_ctrl_ins.int_cnt_09[4] +.sym 8743 smi_ctrl_ins.int_cnt_09[4] +.sym 8744 smi_ctrl_ins.int_cnt_09[3] +.sym 8745 w_rx_09_fifo_pulled_data[1] +.sym 8746 w_rx_09_fifo_pulled_data[17] +.sym 8749 smi_ctrl_ins.int_cnt_09[3] +.sym 8750 smi_ctrl_ins.int_cnt_09[4] +.sym 8751 w_rx_09_fifo_pulled_data[3] +.sym 8752 w_rx_09_fifo_pulled_data[19] +.sym 8756 smi_ctrl_ins.int_cnt_09[3] +.sym 8767 i_smi_a2_SB_LUT4_I1_O[1] +.sym 8769 i_smi_a2_SB_LUT4_I1_O[0] +.sym 8771 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E +.sym 8772 smi_ctrl_ins.soe_and_reset +.sym 8773 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 8774 w_smi_data_output[3] +.sym 8776 rx_09_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 8777 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 8778 w_smi_data_output[2] +.sym 8780 w_smi_data_output[1] +.sym 8781 w_smi_data_output[0] +.sym 8784 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 8786 rx_09_fifo.wr_addr[6] +.sym 8789 rx_09_fifo.rd_addr[1] +.sym 8791 w_rx_09_fifo_empty +.sym 8792 smi_ctrl_ins.int_cnt_09[4] +.sym 8794 i_smi_a1_SB_LUT4_I1_O +.sym 8799 smi_ctrl_ins.int_cnt_09[4] +.sym 8800 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 8801 w_rx_09_fifo_pulled_data[27] +.sym 8802 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 8803 w_smi_data_output[1] +.sym 8804 w_rx_09_fifo_pulled_data[10] +.sym 8805 smi_ctrl_ins.int_cnt_09[3] +.sym 8806 i_smi_a2_SB_LUT4_I1_O[1] +.sym 8807 smi_ctrl_ins.soe_and_reset +.sym 8809 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 8817 i_smi_a2_SB_LUT4_I1_O[1] +.sym 8828 spi_if_ins.w_rx_data[5] +.sym 8833 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 8835 spi_if_ins.w_rx_data[6] +.sym 8844 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 8846 w_rx_09_fifo_push +.sym 8860 i_smi_a2_SB_LUT4_I1_O[1] +.sym 8862 w_rx_09_fifo_push +.sym 8872 spi_if_ins.w_rx_data[6] +.sym 8874 spi_if_ins.w_rx_data[5] +.sym 8884 spi_if_ins.w_rx_data[6] +.sym 8886 spi_if_ins.w_rx_data[5] +.sym 8894 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 8895 r_counter_$glb_clk +.sym 8896 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 8898 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] +.sym 8899 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 8900 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] +.sym 8901 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] +.sym 8902 w_rx_09_fifo_data[16] +.sym 8903 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] +.sym 8910 i_smi_a1_SB_LUT4_I1_O +.sym 8915 lvds_rx_24_inst.r_data[11] +.sym 8916 i_smi_a2_SB_LUT4_I1_O[0] +.sym 8918 i_smi_a1_SB_LUT4_I1_O +.sym 8919 w_cs[1] +.sym 8921 w_rx_24_fifo_data[12] +.sym 8926 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] +.sym 8927 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 8928 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 8930 smi_ctrl_ins.r_fifo_09_pull_1 +.sym 8940 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 8942 rx_24_fifo.rd_addr[4] +.sym 8944 rx_24_fifo.rd_addr[6] +.sym 8945 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 8948 rx_24_fifo.rd_addr[1] +.sym 8950 rx_24_fifo.rd_addr[0] +.sym 8951 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 8956 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 8965 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 8970 $nextpnr_ICESTORM_LC_16$O +.sym 8972 rx_24_fifo.rd_addr[0] +.sym 8976 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 8979 rx_24_fifo.rd_addr[1] +.sym 8982 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 8985 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 8986 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 8988 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 8990 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 8992 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 8994 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 8997 rx_24_fifo.rd_addr[4] +.sym 8998 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 9000 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 9002 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 9004 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 9006 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 9009 rx_24_fifo.rd_addr[6] +.sym 9010 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 9012 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 9015 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 9016 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 9017 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O .sym 9018 r_counter_$glb_clk -.sym 9019 sys_ctrl_ins.reset_cmd -.sym 9022 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E -.sym 9023 w_load -.sym 9032 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O +.sym 9019 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 9021 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[1] +.sym 9022 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[2] +.sym 9023 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[3] +.sym 9024 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[4] +.sym 9025 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[5] +.sym 9026 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[6] +.sym 9027 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[7] +.sym 9029 w_rx_09_fifo_data[16] +.sym 9036 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O .sym 9037 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 9042 $PACKER_VCC_NET -.sym 9044 w_cs[0] -.sym 9065 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R -.sym 9077 w_cs[0] -.sym 9079 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E -.sym 9088 $PACKER_VCC_NET -.sym 9125 $PACKER_VCC_NET -.sym 9132 w_cs[0] -.sym 9140 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E +.sym 9039 w_rx_09_fifo_pulled_data[9] +.sym 9042 w_rx_24_fifo_data[17] +.sym 9044 rx_24_fifo.rd_addr[0] +.sym 9045 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 9047 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 9049 rx_24_fifo.rd_addr[4] +.sym 9051 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 9052 rx_24_fifo.rd_addr[8] +.sym 9053 rx_24_fifo.rd_addr[6] +.sym 9054 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9055 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 9056 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 9063 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 9065 rx_24_fifo.rd_addr[0] +.sym 9070 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9072 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O +.sym 9077 rx_24_fifo.rd_addr[8] +.sym 9078 i_smi_a2_SB_LUT4_I1_O[1] +.sym 9087 rx_24_fifo.rd_addr[1] +.sym 9093 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 9096 rx_24_fifo.rd_addr[8] +.sym 9097 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 9101 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9103 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 9107 rx_24_fifo.rd_addr[1] +.sym 9108 rx_24_fifo.rd_addr[0] +.sym 9118 rx_24_fifo.rd_addr[0] +.sym 9131 i_smi_a2_SB_LUT4_I1_O[1] +.sym 9132 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 9140 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O .sym 9141 r_counter_$glb_clk -.sym 9142 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R -.sym 9144 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 9145 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 9146 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 9148 w_tx_data_smi[1] -.sym 9150 w_tx_data_smi[0] -.sym 9160 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 9167 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 9168 w_soft_reset -.sym 9171 w_soft_reset -.sym 9173 $PACKER_VCC_NET -.sym 9176 spi_if_ins.w_rx_data[5] -.sym 9266 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 9267 w_cs[3] -.sym 9269 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 9270 w_cs[1] -.sym 9271 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 9272 w_cs[2] -.sym 9273 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 9288 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 9289 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 9290 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 9301 $PACKER_VCC_NET -.sym 9318 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 9334 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 9340 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 9386 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] +.sym 9142 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 9143 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[8] +.sym 9144 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[9] +.sym 9145 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[10] +.sym 9146 w_rx_24_fifo_empty +.sym 9147 smi_ctrl_ins.r_fifo_09_pull_1 +.sym 9148 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 9149 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] +.sym 9150 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 9155 rx_24_fifo.rd_addr[8] +.sym 9157 w_cs[2] +.sym 9159 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 9163 w_cs[1] +.sym 9165 rx_24_fifo.rd_addr[0] +.sym 9172 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 9174 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] +.sym 9176 sys_ctrl_ins.reset_cmd +.sym 9177 rx_24_fifo.wr_addr[7] +.sym 9186 lvds_rx_24_inst.r_data[16] +.sym 9194 lvds_rx_24_inst.r_data[14] +.sym 9196 lvds_rx_24_inst.r_data[17] +.sym 9198 lvds_rx_24_inst.r_data[10] +.sym 9207 lvds_rx_24_inst.r_data[25] +.sym 9218 lvds_rx_24_inst.r_data[10] +.sym 9232 lvds_rx_24_inst.r_data[25] +.sym 9237 lvds_rx_24_inst.r_data[17] +.sym 9256 lvds_rx_24_inst.r_data[14] +.sym 9262 lvds_rx_24_inst.r_data[16] +.sym 9263 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 9264 lvds_clock_$glb_clk +.sym 9266 lvds_rx_24_inst.r_data[21] +.sym 9267 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 9268 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[2] +.sym 9269 rx_24_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 9270 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[3] +.sym 9271 rx_24_fifo.full_o_SB_LUT4_I3_O[0] +.sym 9272 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 9273 lvds_rx_24_inst.r_data[25] +.sym 9278 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 9280 lvds_rx_24_inst.r_data[16] +.sym 9281 rx_24_fifo.wr_addr[6] +.sym 9282 lvds_rx_24_inst.r_data[14] +.sym 9284 $PACKER_VCC_NET +.sym 9286 lvds_rx_24_inst.r_data[12] +.sym 9287 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 9289 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 9290 rx_24_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 9292 w_rx_24_fifo_empty +.sym 9294 i_smi_a2_SB_LUT4_I1_O[1] +.sym 9295 smi_ctrl_ins.r_fifo_09_pull +.sym 9296 rx_24_fifo.wr_addr[6] +.sym 9297 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 9301 rx_24_fifo.wr_addr[5] +.sym 9308 smi_ctrl_ins.int_cnt_24[3] +.sym 9309 w_rx_24_fifo_pulled_data[16] +.sym 9310 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 9311 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R +.sym 9312 smi_ctrl_ins.int_cnt_24[4] +.sym 9313 w_rx_24_fifo_pulled_data[2] +.sym 9315 w_rx_24_fifo_pulled_data[18] +.sym 9316 w_rx_24_fifo_pulled_data[10] +.sym 9317 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 9318 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E +.sym 9320 smi_ctrl_ins.int_cnt_24[3] +.sym 9321 $PACKER_VCC_NET +.sym 9324 w_rx_24_fifo_pulled_data[8] +.sym 9325 w_rx_24_fifo_pulled_data[0] +.sym 9326 w_rx_24_fifo_pulled_data[26] +.sym 9332 w_rx_24_fifo_pulled_data[24] +.sym 9334 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 9337 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 9346 w_rx_24_fifo_pulled_data[18] +.sym 9347 w_rx_24_fifo_pulled_data[2] +.sym 9348 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 9349 smi_ctrl_ins.int_cnt_24[3] +.sym 9353 $PACKER_VCC_NET +.sym 9358 w_rx_24_fifo_pulled_data[26] +.sym 9359 w_rx_24_fifo_pulled_data[10] +.sym 9360 smi_ctrl_ins.int_cnt_24[4] +.sym 9361 smi_ctrl_ins.int_cnt_24[3] +.sym 9364 w_rx_24_fifo_pulled_data[0] +.sym 9365 smi_ctrl_ins.int_cnt_24[3] +.sym 9366 w_rx_24_fifo_pulled_data[16] +.sym 9367 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 9370 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 9373 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 9376 smi_ctrl_ins.int_cnt_24[3] +.sym 9377 w_rx_24_fifo_pulled_data[8] +.sym 9378 w_rx_24_fifo_pulled_data[24] +.sym 9379 smi_ctrl_ins.int_cnt_24[4] +.sym 9386 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E .sym 9387 r_counter_$glb_clk -.sym 9389 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 9390 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 9391 w_ioc[0] -.sym 9392 w_ioc[2] -.sym 9393 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 9394 w_ioc[3] -.sym 9395 w_ioc[1] -.sym 9396 w_ioc[4] -.sym 9405 spi_if_ins.w_rx_data[6] -.sym 9417 o_tr_vc1$SB_IO_OUT -.sym 9418 w_tx_data_io[0] -.sym 9424 i_config[2]$SB_IO_IN -.sym 9430 w_cs[0] -.sym 9432 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 9445 w_fetch -.sym 9452 w_ioc[1] -.sym 9453 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 9458 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 9465 w_ioc[1] -.sym 9466 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 9469 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 9470 w_cs[0] -.sym 9472 w_fetch -.sym 9495 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 9509 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E -.sym 9510 r_counter_$glb_clk -.sym 9512 w_tx_data_io[5] -.sym 9513 w_tx_data_io[7] -.sym 9515 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2] -.sym 9516 w_tx_data_io[6] -.sym 9517 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 9518 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 9519 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 9524 spi_if_ins.w_rx_data[2] -.sym 9525 spi_if_ins.w_rx_data[4] -.sym 9526 w_tx_data_sys[0] -.sym 9536 w_ioc[0] -.sym 9539 io_ctrl_ins.pmod_dir_state[0] -.sym 9542 w_tx_data_io[3] -.sym 9544 w_tx_data_io[4] -.sym 9553 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 9562 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 9583 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 9605 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 9606 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 9607 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 9635 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[2] -.sym 9636 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 9637 w_tx_data_io[0] -.sym 9638 w_tx_data_io[1] -.sym 9640 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[3] -.sym 9641 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 9642 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 9643 io_ctrl_ins.led1_state_SB_DFFESR_Q_E -.sym 9650 i_button_SB_LUT4_I1_O[0] -.sym 9652 i_button_SB_LUT4_I1_O[1] -.sym 9654 $PACKER_VCC_NET -.sym 9664 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 9680 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 9681 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 9683 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 9687 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 9697 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 9701 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 9727 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 9734 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 9736 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 9742 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 9755 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E -.sym 9756 r_counter_$glb_clk -.sym 9757 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R -.sym 9759 io_ctrl_ins.pmod_dir_state[0] -.sym 9762 io_ctrl_ins.pmod_dir_state[2] -.sym 9763 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 9772 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 9774 i_config[3]$SB_IO_IN -.sym 9777 io_ctrl_ins.pmod_dir_state[1] -.sym 9778 io_ctrl_ins.debug_mode[0] -.sym 9779 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 9896 w_rx_data[0] -.sym 9897 o_shdn_rx_lna$SB_IO_OUT +.sym 9388 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R +.sym 9390 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 9391 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[2] +.sym 9392 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 9393 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 9394 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1] +.sym 9395 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 9396 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 9404 $PACKER_VCC_NET +.sym 9405 lvds_rx_24_inst.o_debug_state[0] +.sym 9406 lvds_rx_24_inst.r_data[25] +.sym 9409 $PACKER_VCC_NET +.sym 9411 w_rx_24_fifo_pulled_data[18] +.sym 9413 rx_24_fifo.wr_addr[2] +.sym 9414 rx_24_fifo.wr_addr[3] +.sym 9415 rx_24_fifo.wr_addr[4] +.sym 9416 rx_24_fifo.wr_addr[8] +.sym 9418 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] +.sym 9420 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 9421 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9424 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 9431 rx_24_fifo.empty_o_SB_LUT4_I0_I1[2] +.sym 9432 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 9434 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 9436 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 9437 rx_24_fifo.wr_addr[8] +.sym 9440 rx_24_fifo.wr_addr[0] +.sym 9442 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 9443 rx_24_fifo.rd_addr[8] +.sym 9444 rx_24_fifo.wr_addr[3] +.sym 9446 rx_24_fifo.rd_addr[4] +.sym 9448 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 9450 rx_24_fifo.empty_o_SB_LUT4_I0_I1[3] +.sym 9451 rx_24_fifo.wr_addr[5] +.sym 9452 w_rx_24_fifo_empty +.sym 9453 rx_24_fifo.wr_addr[4] +.sym 9454 rx_24_fifo.empty_o_SB_LUT4_I0_I1[1] +.sym 9459 rx_24_fifo.wr_addr[7] +.sym 9460 rx_24_fifo.wr_addr[2] +.sym 9461 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 9463 rx_24_fifo.wr_addr[7] +.sym 9464 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 9465 rx_24_fifo.rd_addr[8] +.sym 9466 rx_24_fifo.wr_addr[8] +.sym 9469 rx_24_fifo.wr_addr[2] +.sym 9470 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 9471 rx_24_fifo.wr_addr[3] +.sym 9472 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 9476 rx_24_fifo.wr_addr[0] +.sym 9481 rx_24_fifo.empty_o_SB_LUT4_I0_I1[2] +.sym 9482 rx_24_fifo.empty_o_SB_LUT4_I0_I1[3] +.sym 9483 rx_24_fifo.empty_o_SB_LUT4_I0_I1[1] +.sym 9484 w_rx_24_fifo_empty +.sym 9487 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 9488 rx_24_fifo.wr_addr[4] +.sym 9489 rx_24_fifo.rd_addr[4] +.sym 9490 rx_24_fifo.wr_addr[5] +.sym 9494 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 9509 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 9510 lvds_clock_$glb_clk +.sym 9511 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 9512 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 9513 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 9514 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9515 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[3] +.sym 9516 rx_24_fifo.full_o_SB_LUT4_I3_O[2] +.sym 9517 rx_24_fifo.wr_addr[5] +.sym 9518 rx_24_fifo.wr_addr[2] +.sym 9519 rx_24_fifo.wr_addr[4] +.sym 9525 w_fetch +.sym 9526 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E +.sym 9530 rx_24_fifo.wr_addr[0] +.sym 9534 lvds_rx_24_inst.r_data[7] +.sym 9537 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 9539 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 9540 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 9541 rx_24_fifo.rd_addr[6] +.sym 9542 rx_24_fifo.rd_addr[4] +.sym 9543 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 9546 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 9555 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 9561 rx_24_fifo.rd_addr[1] +.sym 9564 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 9566 i_smi_a2_SB_LUT4_I1_O[1] +.sym 9567 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 9569 rx_24_fifo.rd_addr[8] +.sym 9570 w_rx_24_fifo_push +.sym 9571 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9572 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[3] +.sym 9577 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 9578 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 9580 rx_24_fifo.rd_addr[6] +.sym 9581 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9582 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[2] +.sym 9586 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9589 rx_24_fifo.rd_addr[1] +.sym 9595 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 9598 i_smi_a2_SB_LUT4_I1_O[1] +.sym 9601 w_rx_24_fifo_push +.sym 9604 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 9610 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 9611 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9612 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[2] +.sym 9613 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[3] +.sym 9616 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 9617 rx_24_fifo.rd_addr[6] +.sym 9618 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 9619 rx_24_fifo.rd_addr[8] +.sym 9622 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 9630 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 9632 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 9633 lvds_clock_$glb_clk +.sym 9634 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 9635 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0] +.sym 9636 w_rx_24_fifo_full +.sym 9637 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[2] +.sym 9638 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[3] +.sym 9639 rx_24_fifo.full_o_SB_LUT4_I3_O[3] +.sym 9640 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 9641 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1] +.sym 9642 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 9644 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 9652 rx_24_fifo.wr_addr[4] +.sym 9657 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 9658 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 9659 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9662 rx_24_fifo.wr_addr[6] +.sym 9663 w_rx_24_fifo_push +.sym 9665 rx_24_fifo.wr_addr[5] +.sym 9667 rx_24_fifo.wr_addr[2] +.sym 9668 rx_24_fifo.wr_addr[3] +.sym 9669 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 9670 rx_24_fifo.wr_addr[8] +.sym 9678 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9679 rx_24_fifo.wr_addr[6] +.sym 9682 rx_24_fifo.wr_addr[3] +.sym 9683 rx_24_fifo.wr_addr[4] +.sym 9686 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9689 rx_24_fifo.wr_addr[5] +.sym 9690 rx_24_fifo.wr_addr[2] +.sym 9691 rx_24_fifo.wr_addr[8] +.sym 9699 rx_24_fifo.rd_addr[8] +.sym 9706 rx_24_fifo.wr_addr[7] +.sym 9708 $nextpnr_ICESTORM_LC_1$O +.sym 9710 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9714 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2] +.sym 9717 rx_24_fifo.wr_addr[2] +.sym 9718 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 9720 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3] +.sym 9723 rx_24_fifo.wr_addr[3] +.sym 9724 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2] +.sym 9726 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[4] +.sym 9729 rx_24_fifo.wr_addr[4] +.sym 9730 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3] +.sym 9732 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[5] +.sym 9735 rx_24_fifo.wr_addr[5] +.sym 9736 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[4] +.sym 9738 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[6] +.sym 9741 rx_24_fifo.wr_addr[6] +.sym 9742 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[5] +.sym 9744 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7] +.sym 9746 rx_24_fifo.wr_addr[7] +.sym 9748 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[6] +.sym 9750 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 9751 rx_24_fifo.rd_addr[8] +.sym 9752 rx_24_fifo.wr_addr[8] +.sym 9754 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7] +.sym 9758 lvds_rx_24_inst.r_data[18] +.sym 9759 lvds_rx_24_inst.r_data[22] +.sym 9760 lvds_rx_24_inst.r_data[3] +.sym 9761 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 9763 lvds_rx_24_inst.r_data[20] +.sym 9764 lvds_rx_24_inst.r_data[23] +.sym 9765 lvds_rx_24_inst.r_data[1] +.sym 9773 rx_24_fifo.wr_addr[6] +.sym 9774 rx_24_fifo.rd_addr[4] +.sym 9779 w_rx_24_fifo_full +.sym 9781 lvds_rx_24_inst.r_data[4] +.sym 9784 w_rx_24_fifo_data[22] +.sym 9790 w_rx_24_fifo_data[23] +.sym 9794 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 9806 lvds_rx_24_inst.r_data[7] +.sym 9818 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 9821 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9830 lvds_rx_24_inst.r_data[1] +.sym 9831 $nextpnr_ICESTORM_LC_2$I3 +.sym 9832 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 9833 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 9835 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 9841 $nextpnr_ICESTORM_LC_2$I3 +.sym 9844 lvds_rx_24_inst.r_data[1] +.sym 9864 lvds_rx_24_inst.r_data[7] +.sym 9878 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 9879 lvds_clock_$glb_clk +.sym 9882 w_rx_24_fifo_data[24] +.sym 9883 w_rx_24_fifo_data[23] +.sym 9885 w_rx_24_fifo_data[25] +.sym 9888 w_rx_24_fifo_data[22] +.sym 9894 lvds_rx_24_inst.o_debug_state[0] +.sym 9898 lvds_rx_24_inst.o_debug_state[1] +.sym 9902 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] +.sym 9904 lvds_rx_24_inst.r_data[3] +.sym 9906 w_lvds_rx_24_d1 +.sym 9907 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 9947 lvds_rx_24_inst.r_push +.sym 9969 lvds_rx_24_inst.r_push +.sym 10002 lvds_clock_$glb_clk +.sym 10003 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 10005 lvds_rx_24_inst.r_push +.sym 10007 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E +.sym 10011 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E +.sym 10025 o_shdn_rx_lna$SB_IO_OUT +.sym 10131 rx_24_fifo.rd_addr[8] +.sym 10138 lvds_rx_24_inst.o_debug_state[1] .sym 10172 o_shdn_rx_lna$SB_IO_OUT -.sym 10194 o_shdn_rx_lna$SB_IO_OUT +.sym 10196 o_shdn_rx_lna$SB_IO_OUT .sym 10201 w_smi_data_output[2] .sym 10203 i_smi_a3$SB_IO_IN .sym 10204 w_smi_data_output[1] .sym 10206 i_smi_a3$SB_IO_IN .sym 10210 i_smi_a3$SB_IO_IN -.sym 10213 w_smi_data_output[1] +.sym 10215 w_smi_data_output[1] .sym 10218 i_smi_a3$SB_IO_IN .sym 10221 w_smi_data_output[2] -.sym 10236 rx_09_fifo.rd_addr[5] -.sym 10238 rx_09_fifo.rd_addr[6] -.sym 10254 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10261 w_smi_data_output[1] -.sym 10270 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 10271 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10272 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10273 rx_09_fifo.rd_addr[1] -.sym 10282 rx_09_fifo.rd_addr[6] -.sym 10288 rx_09_fifo.rd_addr[4] -.sym 10289 rx_09_fifo.rd_addr[5] -.sym 10294 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10299 rx_09_fifo.rd_addr[7] -.sym 10300 $nextpnr_ICESTORM_LC_3$O -.sym 10303 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10306 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 10309 rx_09_fifo.rd_addr[1] -.sym 10312 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] -.sym 10314 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10316 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 10318 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] -.sym 10321 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10322 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] -.sym 10324 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] -.sym 10327 rx_09_fifo.rd_addr[4] -.sym 10328 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] -.sym 10330 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] -.sym 10333 rx_09_fifo.rd_addr[5] -.sym 10334 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] -.sym 10336 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] -.sym 10338 rx_09_fifo.rd_addr[6] -.sym 10340 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] -.sym 10342 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] -.sym 10344 rx_09_fifo.rd_addr[7] -.sym 10346 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] -.sym 10347 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 10348 r_counter_$glb_clk -.sym 10349 w_soft_reset_$glb_sr -.sym 10356 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[2] -.sym 10357 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[3] -.sym 10358 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 10359 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 10360 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[6] -.sym 10361 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[7] -.sym 10365 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 10368 w_rx_09_fifo_pulled_data[21] -.sym 10370 rx_09_fifo.wr_addr[6] -.sym 10371 rx_09_fifo.wr_addr[3] -.sym 10376 rx_09_fifo.rd_addr[4] -.sym 10381 rx_09_fifo.rd_addr[5] -.sym 10382 rx_09_fifo.rd_addr[8] -.sym 10383 rx_09_fifo.rd_addr[6] -.sym 10384 rx_09_fifo.rd_addr[9] -.sym 10385 rx_09_fifo.rd_addr[7] -.sym 10392 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10394 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10396 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] -.sym 10397 w_rx_09_fifo_full -.sym 10398 w_rx_09_fifo_push -.sym 10408 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10409 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 10410 rx_09_fifo.rd_addr[1] -.sym 10411 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10414 rx_09_fifo.rd_addr[4] -.sym 10416 rx_09_fifo.rd_addr[5] -.sym 10417 rx_09_fifo.rd_addr[8] -.sym 10418 rx_09_fifo.rd_addr[6] -.sym 10419 rx_09_fifo.rd_addr[9] -.sym 10420 rx_09_fifo.rd_addr[7] -.sym 10426 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] -.sym 10431 rx_09_fifo.rd_addr[8] -.sym 10432 rx_09_fifo.rd_addr[9] -.sym 10435 rx_09_fifo.rd_addr[4] -.sym 10436 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 10438 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 10443 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] +.sym 10226 lvds_rx_24_inst.r_data[17] +.sym 10245 w_smi_data_output[2] +.sym 10282 lvds_rx_09_inst.r_data[10] +.sym 10291 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10293 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 10295 lvds_rx_09_inst.o_debug_state[1] +.sym 10320 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 10321 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10322 lvds_rx_09_inst.o_debug_state[1] +.sym 10340 lvds_rx_09_inst.r_data[10] +.sym 10347 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 10348 lvds_clock_$glb_clk +.sym 10355 rx_09_fifo.full_o_SB_LUT4_I3_I2[1] +.sym 10356 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 10357 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 10358 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 10359 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 10360 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 10361 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 10368 smi_ctrl_ins.int_cnt_09[4] +.sym 10371 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 10372 smi_ctrl_ins.int_cnt_09[3] +.sym 10374 lvds_rx_24_inst.r_data[15] +.sym 10377 rx_09_fifo.wr_addr[9] +.sym 10385 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10387 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 10389 lvds_rx_24_inst.r_data[24] +.sym 10396 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 10398 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 10400 w_smi_data_output[0] +.sym 10403 w_smi_data_output[3] +.sym 10414 lvds_rx_09_inst.r_data[20] +.sym 10418 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 10420 w_rx_09_fifo_full +.sym 10423 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 10437 rx_09_fifo.rd_addr[6] .sym 10444 rx_09_fifo.rd_addr[5] -.sym 10446 rx_09_fifo.rd_addr[7] -.sym 10448 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 10453 w_rx_09_fifo_push -.sym 10454 w_rx_09_fifo_full -.sym 10456 rx_09_fifo.rd_addr[9] -.sym 10458 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 10459 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10460 rx_09_fifo.rd_addr[1] -.sym 10463 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] -.sym 10466 rx_09_fifo.rd_addr[8] -.sym 10467 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] -.sym 10472 rx_09_fifo.rd_addr[9] -.sym 10473 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] -.sym 10476 rx_09_fifo.rd_addr[5] -.sym 10477 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 10478 rx_09_fifo.rd_addr[4] -.sym 10479 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] -.sym 10491 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10494 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10495 rx_09_fifo.rd_addr[1] -.sym 10500 rx_09_fifo.rd_addr[7] -.sym 10501 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 10502 w_rx_09_fifo_push -.sym 10503 w_rx_09_fifo_full -.sym 10506 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 10507 rx_09_fifo.rd_addr[9] -.sym 10508 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 10509 rx_09_fifo.rd_addr[7] -.sym 10510 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 10511 r_counter_$glb_clk -.sym 10512 w_soft_reset_$glb_sr -.sym 10513 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 10514 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[9] -.sym 10515 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[10] -.sym 10516 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[1] -.sym 10517 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 10518 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10519 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 10525 rx_09_fifo.rd_addr[8] -.sym 10526 w_smi_data_output[2] -.sym 10527 rx_09_fifo.rd_addr[1] -.sym 10529 rx_09_fifo.rd_addr[9] -.sym 10530 lvds_rx_09_inst.r_data[24] -.sym 10535 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10537 rx_09_fifo.wr_addr[4] -.sym 10538 lvds_rx_09_inst.o_debug_state[0] -.sym 10539 rx_09_fifo.wr_addr[9] -.sym 10540 w_soft_reset -.sym 10541 rx_09_fifo.wr_addr[5] -.sym 10542 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10543 rx_09_fifo.rd_addr[5] -.sym 10544 rx_09_fifo.wr_addr[7] -.sym 10545 w_rx_09_fifo_data[22] -.sym 10546 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10555 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 10559 lvds_rx_09_inst.r_data[22] -.sym 10560 rx_09_fifo.full_o_SB_LUT4_I3_O[1] -.sym 10562 rx_09_fifo.rd_addr[8] -.sym 10564 rx_09_fifo.full_o_SB_LUT4_I3_O[2] -.sym 10566 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10567 rx_09_fifo.rd_addr[1] -.sym 10568 lvds_rx_09_inst.r_data[20] -.sym 10569 rx_09_fifo.full_o_SB_LUT4_I3_O[3] -.sym 10572 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10573 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 10575 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 10576 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 10577 lvds_rx_09_inst.r_data[0] -.sym 10579 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 10580 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 10583 rx_09_fifo.rd_addr[6] -.sym 10584 rx_09_fifo.full_o_SB_LUT4_I3_O[0] -.sym 10585 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 10588 lvds_rx_09_inst.r_data[22] -.sym 10593 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 10594 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 10595 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 10596 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10600 lvds_rx_09_inst.r_data[0] -.sym 10605 lvds_rx_09_inst.r_data[20] -.sym 10617 rx_09_fifo.rd_addr[8] -.sym 10618 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 10619 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 10620 rx_09_fifo.rd_addr[6] -.sym 10623 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 10624 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10625 rx_09_fifo.rd_addr[1] -.sym 10626 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 10629 rx_09_fifo.full_o_SB_LUT4_I3_O[0] -.sym 10630 rx_09_fifo.full_o_SB_LUT4_I3_O[1] -.sym 10631 rx_09_fifo.full_o_SB_LUT4_I3_O[2] -.sym 10632 rx_09_fifo.full_o_SB_LUT4_I3_O[3] -.sym 10633 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce +.sym 10445 lvds_rx_24_inst.r_data[24] +.sym 10447 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10451 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 10452 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 10461 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 10470 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 10471 rx_09_fifo.rd_addr[6] +.sym 10472 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 10473 rx_09_fifo.rd_addr[5] +.sym 10489 lvds_rx_24_inst.r_data[24] +.sym 10507 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10509 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 10510 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 10511 lvds_clock_$glb_clk +.sym 10513 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 10514 rx_09_fifo.full_o_SB_LUT4_I3_I2[9] +.sym 10515 rx_09_fifo.full_o_SB_LUT4_I3_O[1] +.sym 10516 w_rx_09_fifo_data[22] +.sym 10517 w_rx_09_fifo_data[21] +.sym 10519 w_rx_09_fifo_data[17] +.sym 10520 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 10527 w_rx_09_fifo_pulled_data[7] +.sym 10535 smi_ctrl_ins.int_cnt_09[4] +.sym 10536 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 10538 rx_09_fifo.wr_addr[4] +.sym 10539 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 10540 rx_09_fifo.wr_addr[5] +.sym 10541 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 10542 rx_09_fifo.wr_addr[8] +.sym 10543 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 10544 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 10545 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 10546 rx_09_fifo.wr_addr[6] +.sym 10547 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 10555 rx_09_fifo.full_o_SB_LUT4_I3_I2[1] +.sym 10556 rx_09_fifo.rd_addr[1] +.sym 10557 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 10561 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 10562 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10563 rx_09_fifo.full_o_SB_LUT4_I3_O[0] +.sym 10564 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 10565 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 10569 rx_09_fifo.rd_addr[9] +.sym 10570 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 10571 rx_09_fifo.full_o_SB_LUT4_I3_I2[9] +.sym 10572 rx_09_fifo.full_o_SB_LUT4_I3_O[1] +.sym 10575 rx_09_fifo.full_o_SB_LUT4_I3_O[2] +.sym 10578 rx_09_fifo.full_o_SB_LUT4_I3_O[3] +.sym 10579 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 10581 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 10582 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 10585 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 10587 rx_09_fifo.rd_addr[9] +.sym 10588 rx_09_fifo.full_o_SB_LUT4_I3_I2[9] +.sym 10589 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 10590 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10596 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 10600 rx_09_fifo.full_o_SB_LUT4_I3_I2[1] +.sym 10605 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 10606 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 10607 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 10611 rx_09_fifo.full_o_SB_LUT4_I3_O[1] +.sym 10612 rx_09_fifo.full_o_SB_LUT4_I3_O[2] +.sym 10613 rx_09_fifo.full_o_SB_LUT4_I3_O[0] +.sym 10614 rx_09_fifo.full_o_SB_LUT4_I3_O[3] +.sym 10617 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 10618 rx_09_fifo.rd_addr[1] +.sym 10619 rx_09_fifo.full_o_SB_LUT4_I3_I2[1] +.sym 10620 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 10624 rx_09_fifo.full_o_SB_LUT4_I3_I2[9] +.sym 10629 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 10633 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O .sym 10634 lvds_clock_$glb_clk -.sym 10636 lvds_rx_09_inst.r_data[3] -.sym 10637 lvds_rx_09_inst.r_data[2] -.sym 10638 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[1] -.sym 10639 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[3] -.sym 10640 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[2] -.sym 10641 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 10642 lvds_rx_09_inst.r_data[1] -.sym 10643 lvds_rx_09_inst.r_data[0] -.sym 10650 w_rx_09_fifo_pulled_data[28] -.sym 10653 rx_09_fifo.wr_addr[9] -.sym 10655 w_rx_09_fifo_pulled_data[29] -.sym 10656 w_rx_09_fifo_data[20] -.sym 10660 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 10661 lvds_rx_09_inst.r_cnt[1] -.sym 10663 rx_09_fifo.rd_addr[7] -.sym 10664 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 10665 rx_09_fifo.rd_addr[8] -.sym 10667 rx_09_fifo.rd_addr[9] -.sym 10669 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10670 rx_09_fifo.wr_addr[7] -.sym 10671 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 10679 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 10680 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 10681 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4] -.sym 10682 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5] -.sym 10684 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 10688 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 10690 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 10691 rx_09_fifo.rd_addr[5] -.sym 10692 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 10693 rx_09_fifo.rd_addr[6] -.sym 10701 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 10707 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 10710 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4] -.sym 10711 rx_09_fifo.rd_addr[5] -.sym 10712 rx_09_fifo.rd_addr[6] -.sym 10713 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5] -.sym 10717 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 10722 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 10728 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 10737 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 10741 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 10747 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 10752 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 10756 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 10757 lvds_clock_$glb_clk -.sym 10758 w_soft_reset_$glb_sr -.sym 10759 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 10760 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[1] -.sym 10761 w_rx_09_fifo_empty -.sym 10762 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 10763 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] -.sym 10764 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[2] -.sym 10765 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 10766 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[3] -.sym 10773 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 10774 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 10780 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10783 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] -.sym 10784 rx_09_fifo.wr_addr[6] -.sym 10785 w_rx_09_fifo_push -.sym 10787 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 10788 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 10789 w_soft_reset -.sym 10790 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 10791 rx_09_fifo.wr_addr[4] -.sym 10792 rx_09_fifo.wr_addr[8] -.sym 10793 w_rx_09_fifo_full -.sym 10794 rx_09_fifo.wr_addr[3] -.sym 10801 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] -.sym 10802 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 10803 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 10804 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] -.sym 10806 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 10808 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] -.sym 10810 rx_09_fifo.wr_addr[6] -.sym 10811 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] -.sym 10812 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[2] -.sym 10813 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 10814 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 10815 rx_09_fifo.rd_addr[5] -.sym 10817 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] -.sym 10818 rx_09_fifo.wr_addr[5] -.sym 10819 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[3] -.sym 10820 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] -.sym 10828 rx_09_fifo.rd_addr[6] -.sym 10829 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10831 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 10833 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] -.sym 10839 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 10848 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 10851 rx_09_fifo.wr_addr[6] -.sym 10852 rx_09_fifo.rd_addr[5] -.sym 10853 rx_09_fifo.rd_addr[6] -.sym 10854 rx_09_fifo.wr_addr[5] -.sym 10857 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10859 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 10860 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] -.sym 10863 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[2] -.sym 10864 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 10865 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[3] -.sym 10866 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 10871 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 10875 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] -.sym 10876 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] -.sym 10877 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] -.sym 10878 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] -.sym 10879 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 10880 lvds_clock_$glb_clk -.sym 10881 w_soft_reset_$glb_sr -.sym 10885 w_rx_09_fifo_full -.sym 10888 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] -.sym 10889 w_rx_09_fifo_push -.sym 10894 rx_09_fifo.wr_addr[4] -.sym 10895 lvds_rx_09_inst.o_debug_state[0] -.sym 10896 w_rx_09_fifo_pulled_data[25] -.sym 10898 i_smi_a1_SB_LUT4_I1_O -.sym 10899 rx_09_fifo.wr_addr[6] -.sym 10900 rx_09_fifo.wr_addr[5] -.sym 10901 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O -.sym 10902 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 10903 lvds_rx_09_inst.o_debug_state[1] -.sym 10904 lvds_rx_09_inst.o_debug_state[0] -.sym 10905 w_rx_09_fifo_empty -.sym 10906 rx_09_fifo.rd_addr[7] -.sym 10907 rx_09_fifo.rd_addr[4] -.sym 10909 rx_09_fifo.rd_addr[9] -.sym 10911 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 10912 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 10914 rx_09_fifo.rd_addr[5] -.sym 10915 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 10916 rx_09_fifo.rd_addr[1] -.sym 10923 spi_if_ins.state_if_SB_DFFESR_Q_D[0] -.sym 10925 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 10936 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 10939 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 10994 spi_if_ins.state_if_SB_DFFESR_Q_D[0] -.sym 11001 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 11002 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 11003 r_counter_$glb_clk -.sym 11004 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 11005 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 11006 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 11008 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 11009 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 11011 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 11012 spi_if_ins.state_if[1] -.sym 11031 w_rx_09_fifo_full -.sym 11040 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 11050 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 11059 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 11060 spi_if_ins.state_if[0] -.sym 11064 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 11069 spi_if_ins.state_if[1] -.sym 11073 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 11079 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 11080 spi_if_ins.state_if[1] -.sym 11082 spi_if_ins.state_if[0] -.sym 11103 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 11115 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 11116 spi_if_ins.state_if[0] -.sym 11117 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 11118 spi_if_ins.state_if[1] -.sym 11121 spi_if_ins.state_if[0] -.sym 11123 spi_if_ins.state_if[1] -.sym 11125 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 11126 r_counter_$glb_clk -.sym 11127 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 11129 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 11130 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 11131 w_fetch -.sym 11132 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11133 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 11140 $PACKER_VCC_NET -.sym 11141 rx_09_fifo.wr_addr[6] -.sym 11142 w_rx_09_fifo_pulled_data[9] -.sym 11143 w_rx_09_fifo_data[25] -.sym 11144 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 11146 rx_09_fifo.wr_addr[9] -.sym 11147 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 11149 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 11158 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 11162 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 11180 w_load -.sym 11184 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 11185 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11186 w_cs[0] -.sym 11188 w_fetch -.sym 11196 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 11198 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 11214 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11215 w_fetch -.sym 11216 w_load -.sym 11217 w_cs[0] -.sym 11223 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 11248 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E -.sym 11249 r_counter_$glb_clk -.sym 11250 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 11252 spi_if_ins.r_tx_byte[7] -.sym 11253 spi_if_ins.r_tx_byte[4] -.sym 11254 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 11255 spi_if_ins.r_tx_byte[1] -.sym 11257 spi_if_ins.r_tx_byte[2] -.sym 11258 spi_if_ins.r_tx_byte[5] -.sym 11263 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 11265 w_rx_09_fifo_pulled_data[11] -.sym 11268 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 11272 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 11275 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 11279 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11286 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11293 w_cs[3] -.sym 11295 w_fetch -.sym 11296 w_cs[1] -.sym 11298 w_cs[2] -.sym 11301 w_rx_09_fifo_empty -.sym 11303 w_rx_09_fifo_full -.sym 11304 w_cs[1] -.sym 11308 w_soft_reset -.sym 11313 w_soft_reset -.sym 11316 w_cs[0] -.sym 11317 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 11319 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E -.sym 11321 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11331 w_cs[0] -.sym 11332 w_cs[1] -.sym 11333 w_cs[3] -.sym 11334 w_cs[2] -.sym 11337 w_soft_reset -.sym 11338 w_fetch -.sym 11340 w_cs[1] -.sym 11343 w_fetch -.sym 11344 w_cs[2] -.sym 11345 w_soft_reset -.sym 11346 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 11356 w_rx_09_fifo_full -.sym 11370 w_rx_09_fifo_empty -.sym 11371 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 10635 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 10636 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] +.sym 10637 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] +.sym 10638 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 10639 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] +.sym 10640 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[3] +.sym 10641 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] +.sym 10642 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 10643 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10649 w_rx_09_fifo_data[17] +.sym 10650 rx_09_fifo.rd_addr[1] +.sym 10651 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 10652 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 10653 smi_ctrl_ins.int_cnt_09[3] +.sym 10654 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 10656 rx_09_fifo.rd_addr[6] +.sym 10659 sys_ctrl_ins.reset_cmd +.sym 10661 rx_09_fifo.rd_addr[4] +.sym 10664 rx_09_fifo.rd_addr[4] +.sym 10667 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10671 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 10679 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 10692 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 10694 rx_09_fifo.wr_addr[5] +.sym 10695 rx_09_fifo.wr_addr[8] +.sym 10697 rx_09_fifo.wr_addr[6] +.sym 10701 rx_09_fifo.wr_addr[4] +.sym 10704 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 10706 rx_09_fifo.wr_addr[7] +.sym 10709 $nextpnr_ICESTORM_LC_14$O +.sym 10712 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 10715 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2] +.sym 10717 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 10719 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 10721 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] +.sym 10724 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 10725 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2] +.sym 10727 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4] +.sym 10730 rx_09_fifo.wr_addr[4] +.sym 10731 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] +.sym 10733 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5] +.sym 10735 rx_09_fifo.wr_addr[5] +.sym 10737 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4] +.sym 10739 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] +.sym 10741 rx_09_fifo.wr_addr[6] +.sym 10743 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5] +.sym 10745 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7] +.sym 10748 rx_09_fifo.wr_addr[7] +.sym 10749 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] +.sym 10751 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 10753 rx_09_fifo.wr_addr[8] +.sym 10755 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7] +.sym 10759 rx_09_fifo.wr_addr[4] +.sym 10760 rx_09_fifo.wr_addr[5] +.sym 10761 rx_09_fifo.wr_addr[8] +.sym 10762 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 10763 rx_09_fifo.wr_addr[6] +.sym 10764 rx_09_fifo.wr_addr[7] +.sym 10765 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E +.sym 10766 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 10770 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 10772 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 10773 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 10774 rx_09_fifo.rd_addr[6] +.sym 10775 smi_ctrl_ins.soe_and_reset +.sym 10776 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10778 rx_09_fifo.rd_addr[6] +.sym 10779 smi_ctrl_ins.int_cnt_09[3] +.sym 10780 rx_09_fifo.rd_addr[4] +.sym 10782 rx_09_fifo.rd_addr[5] +.sym 10783 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 10786 w_smi_data_output[0] +.sym 10787 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 10788 w_smi_data_output[3] +.sym 10789 w_rx_09_fifo_empty +.sym 10792 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 10793 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10794 rx_09_fifo.wr_addr[5] +.sym 10795 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 10802 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 10804 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 10806 rx_09_fifo.rd_addr[1] +.sym 10807 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10811 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 10812 rx_09_fifo.wr_addr[9] +.sym 10813 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 10815 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E +.sym 10823 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 10828 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 10829 smi_ctrl_ins.w_fifo_24_pull_trigger +.sym 10832 $nextpnr_ICESTORM_LC_15$I3 +.sym 10834 rx_09_fifo.wr_addr[9] +.sym 10836 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 10842 $nextpnr_ICESTORM_LC_15$I3 +.sym 10852 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E +.sym 10859 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 10860 i_smi_a2_SB_LUT4_I1_O[1] +.sym 10864 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 10866 rx_09_fifo.rd_addr[1] +.sym 10871 smi_ctrl_ins.w_fifo_24_pull_trigger +.sym 10875 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 10876 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 10877 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 10878 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 10880 r_counter_$glb_clk +.sym 10881 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 10882 lvds_rx_24_inst.r_data[26] +.sym 10883 lvds_rx_24_inst.r_data[28] +.sym 10885 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 10887 rx_09_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 10888 lvds_rx_24_inst.r_data[11] +.sym 10889 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 10894 rx_09_fifo.rd_addr[5] +.sym 10896 rx_09_fifo.wr_addr[9] +.sym 10899 w_rx_09_fifo_data[5] +.sym 10900 smi_ctrl_ins.int_cnt_09[4] +.sym 10901 rx_09_fifo.wr_addr[4] +.sym 10903 rx_09_fifo.wr_addr[5] +.sym 10906 w_rx_09_fifo_pulled_data[26] +.sym 10907 smi_ctrl_ins.r_fifo_09_pull +.sym 10910 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 10911 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 10913 w_rx_09_fifo_pulled_data[11] +.sym 10914 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E +.sym 10915 smi_ctrl_ins.r_fifo_24_pull +.sym 10917 w_rx_24_fifo_empty +.sym 10923 i_smi_a2_SB_LUT4_I1_O[0] +.sym 10925 i_smi_a1_SB_LUT4_I1_O +.sym 10926 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 10927 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] +.sym 10928 rx_09_fifo.empty_o_SB_LUT4_I3_I2[2] +.sym 10929 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 10930 w_rx_09_fifo_empty +.sym 10931 i_smi_a2_SB_LUT4_I1_O[0] +.sym 10932 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] +.sym 10934 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] +.sym 10935 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] +.sym 10937 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] +.sym 10938 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 10939 smi_ctrl_ins.soe_and_reset +.sym 10940 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] +.sym 10941 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 10945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] +.sym 10947 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] +.sym 10948 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] +.sym 10949 rx_09_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 10950 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] +.sym 10951 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] +.sym 10952 rx_09_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 10954 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] +.sym 10956 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] +.sym 10957 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] +.sym 10958 i_smi_a2_SB_LUT4_I1_O[0] +.sym 10959 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] +.sym 10968 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 10969 w_rx_09_fifo_empty +.sym 10970 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 10971 rx_09_fifo.empty_o_SB_LUT4_I3_I2[2] +.sym 10974 rx_09_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 10975 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 10976 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 10977 rx_09_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 10980 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] +.sym 10981 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] +.sym 10982 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] +.sym 10983 i_smi_a2_SB_LUT4_I1_O[0] +.sym 10992 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] +.sym 10993 i_smi_a2_SB_LUT4_I1_O[0] +.sym 10994 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] +.sym 10995 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] +.sym 10998 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] +.sym 10999 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] +.sym 11000 i_smi_a2_SB_LUT4_I1_O[0] +.sym 11001 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] +.sym 11002 i_smi_a1_SB_LUT4_I1_O +.sym 11003 smi_ctrl_ins.soe_and_reset +.sym 11005 w_rx_24_fifo_data[17] +.sym 11008 w_rx_24_fifo_data[28] +.sym 11011 w_rx_24_fifo_data[30] +.sym 11016 lvds_rx_24_inst.r_data[21] +.sym 11017 i_smi_a2_SB_LUT4_I1_O[0] +.sym 11018 lvds_rx_24_inst.r_data[11] +.sym 11024 spi_if_ins.w_rx_data[5] +.sym 11025 smi_ctrl_ins.int_cnt_24[4] +.sym 11029 lvds_rx_24_inst.r_data[7] +.sym 11031 rx_24_fifo.wr_addr[2] +.sym 11034 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 11046 w_rx_09_fifo_pulled_data[9] +.sym 11047 w_rx_09_fifo_pulled_data[8] +.sym 11049 smi_ctrl_ins.int_cnt_09[3] +.sym 11051 smi_ctrl_ins.int_cnt_09[4] +.sym 11052 w_rx_09_fifo_empty +.sym 11053 w_rx_09_fifo_pulled_data[27] +.sym 11056 w_rx_09_fifo_pulled_data[10] +.sym 11057 smi_ctrl_ins.int_cnt_09[3] +.sym 11059 smi_ctrl_ins.int_cnt_09[4] +.sym 11064 w_rx_09_fifo_pulled_data[25] +.sym 11066 w_rx_09_fifo_pulled_data[26] +.sym 11067 smi_ctrl_ins.r_fifo_09_pull +.sym 11068 lvds_rx_09_inst.r_data[14] +.sym 11070 smi_ctrl_ins.r_fifo_09_pull_1 +.sym 11072 w_rx_09_fifo_pulled_data[24] +.sym 11073 w_rx_09_fifo_pulled_data[11] +.sym 11085 w_rx_09_fifo_pulled_data[24] +.sym 11086 smi_ctrl_ins.int_cnt_09[4] +.sym 11087 w_rx_09_fifo_pulled_data[8] +.sym 11088 smi_ctrl_ins.int_cnt_09[3] +.sym 11092 smi_ctrl_ins.r_fifo_09_pull_1 +.sym 11093 w_rx_09_fifo_empty +.sym 11094 smi_ctrl_ins.r_fifo_09_pull +.sym 11097 w_rx_09_fifo_pulled_data[10] +.sym 11098 smi_ctrl_ins.int_cnt_09[4] +.sym 11099 smi_ctrl_ins.int_cnt_09[3] +.sym 11100 w_rx_09_fifo_pulled_data[26] +.sym 11103 w_rx_09_fifo_pulled_data[11] +.sym 11104 smi_ctrl_ins.int_cnt_09[3] +.sym 11105 smi_ctrl_ins.int_cnt_09[4] +.sym 11106 w_rx_09_fifo_pulled_data[27] +.sym 11112 lvds_rx_09_inst.r_data[14] +.sym 11115 w_rx_09_fifo_pulled_data[9] +.sym 11116 smi_ctrl_ins.int_cnt_09[3] +.sym 11117 w_rx_09_fifo_pulled_data[25] +.sym 11118 smi_ctrl_ins.int_cnt_09[4] +.sym 11125 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 11126 lvds_clock_$glb_clk +.sym 11128 lvds_rx_24_inst.r_data[24] +.sym 11129 w_rx_24_fifo_empty +.sym 11132 lvds_rx_24_inst.r_data[9] +.sym 11133 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 11137 w_rx_09_fifo_pulled_data[8] +.sym 11140 w_tx_data_smi[2] +.sym 11141 spi_if_ins.w_rx_data[6] +.sym 11143 w_rx_24_fifo_data[28] +.sym 11148 w_tx_data_smi[1] +.sym 11151 lvds_rx_24_inst.r_data[15] +.sym 11153 w_cs[1] +.sym 11154 lvds_rx_09_inst.r_data[14] +.sym 11155 smi_ctrl_ins.int_cnt_24[3] +.sym 11157 lvds_rx_24_inst.r_data[10] +.sym 11158 lvds_rx_24_inst.r_data[16] +.sym 11162 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 11163 w_rx_24_fifo_empty +.sym 11171 rx_24_fifo.rd_addr[1] +.sym 11173 rx_24_fifo.rd_addr[0] +.sym 11181 rx_24_fifo.rd_addr[0] +.sym 11187 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11189 rx_24_fifo.rd_addr[4] +.sym 11190 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 11191 rx_24_fifo.rd_addr[6] +.sym 11192 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 11196 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 11201 $nextpnr_ICESTORM_LC_6$O +.sym 11203 rx_24_fifo.rd_addr[0] +.sym 11207 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[2] +.sym 11209 rx_24_fifo.rd_addr[1] +.sym 11211 rx_24_fifo.rd_addr[0] +.sym 11213 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[3] +.sym 11216 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11217 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[2] +.sym 11219 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[4] +.sym 11221 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 11223 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[3] +.sym 11225 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[5] +.sym 11228 rx_24_fifo.rd_addr[4] +.sym 11229 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[4] +.sym 11231 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[6] +.sym 11234 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 11235 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[5] +.sym 11237 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[7] +.sym 11240 rx_24_fifo.rd_addr[6] +.sym 11241 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[6] +.sym 11243 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[8] +.sym 11246 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 11247 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[7] +.sym 11251 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] +.sym 11252 lvds_rx_24_inst.r_data[16] +.sym 11253 lvds_rx_24_inst.r_data[19] +.sym 11254 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] +.sym 11255 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 11256 lvds_rx_24_inst.r_data[14] +.sym 11257 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 11258 lvds_rx_24_inst.r_data[12] +.sym 11265 smi_ctrl_ins.r_fifo_09_pull +.sym 11269 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 11272 w_rx_09_fifo_pulled_data[10] +.sym 11281 i_smi_a2_SB_LUT4_I1_O[1] +.sym 11282 lvds_rx_24_inst.r_data[22] +.sym 11284 lvds_rx_24_inst.r_data[23] +.sym 11285 spi_if_ins.w_rx_data[5] +.sym 11287 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[8] +.sym 11293 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 11295 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[3] +.sym 11296 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[4] +.sym 11297 rx_24_fifo.rd_addr[6] +.sym 11298 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[6] +.sym 11299 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[7] +.sym 11300 rx_24_fifo.wr_addr[3] +.sym 11303 rx_24_fifo.wr_addr[4] +.sym 11305 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[5] +.sym 11306 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11308 rx_24_fifo.rd_addr[8] +.sym 11309 smi_ctrl_ins.r_fifo_09_pull +.sym 11310 rx_24_fifo.wr_addr[6] +.sym 11314 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 11315 rx_24_fifo.wr_addr[5] +.sym 11317 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 11319 rx_24_fifo.wr_addr[7] +.sym 11323 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 11324 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[9] +.sym 11327 rx_24_fifo.rd_addr[8] +.sym 11328 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[8] +.sym 11330 $nextpnr_ICESTORM_LC_7$I3 +.sym 11332 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 11334 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[9] +.sym 11340 $nextpnr_ICESTORM_LC_7$I3 +.sym 11343 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11344 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 11345 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 11346 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 11350 smi_ctrl_ins.r_fifo_09_pull +.sym 11355 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[3] +.sym 11356 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[4] +.sym 11357 rx_24_fifo.wr_addr[3] +.sym 11358 rx_24_fifo.wr_addr[4] +.sym 11361 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[5] +.sym 11362 rx_24_fifo.wr_addr[5] +.sym 11363 rx_24_fifo.wr_addr[7] +.sym 11364 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[7] +.sym 11367 rx_24_fifo.rd_addr[6] +.sym 11368 rx_24_fifo.wr_addr[6] +.sym 11369 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11370 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[6] .sym 11372 r_counter_$glb_clk -.sym 11373 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11375 r_tx_data[6] -.sym 11376 r_tx_data[3] -.sym 11377 r_tx_data[5] -.sym 11378 r_tx_data[7] -.sym 11379 r_tx_data[1] -.sym 11380 r_tx_data[2] -.sym 11381 r_tx_data[4] -.sym 11399 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11400 w_tx_data_io[7] -.sym 11401 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11407 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11409 w_soft_reset -.sym 11416 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 11417 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11419 w_cs[1] -.sym 11420 spi_if_ins.w_rx_data[5] -.sym 11422 spi_if_ins.w_rx_data[6] -.sym 11423 w_cs[0] -.sym 11430 w_tx_data_smi[0] -.sym 11431 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 11432 w_tx_data_io[0] -.sym 11440 w_cs[3] -.sym 11444 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 11445 w_cs[2] -.sym 11448 w_cs[3] -.sym 11449 w_cs[2] -.sym 11450 w_cs[1] -.sym 11451 w_cs[0] -.sym 11454 spi_if_ins.w_rx_data[5] -.sym 11456 spi_if_ins.w_rx_data[6] -.sym 11466 spi_if_ins.w_rx_data[5] -.sym 11468 spi_if_ins.w_rx_data[6] -.sym 11473 spi_if_ins.w_rx_data[5] -.sym 11475 spi_if_ins.w_rx_data[6] -.sym 11478 w_cs[0] -.sym 11479 w_cs[1] -.sym 11480 w_cs[2] -.sym 11481 w_cs[3] -.sym 11485 spi_if_ins.w_rx_data[6] -.sym 11487 spi_if_ins.w_rx_data[5] -.sym 11490 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 11491 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 11492 w_tx_data_io[0] -.sym 11493 w_tx_data_smi[0] -.sym 11494 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11495 r_counter_$glb_clk -.sym 11496 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 11498 spi_if_ins.o_ioc_SB_LUT4_I2_O[2] -.sym 11499 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O -.sym 11500 r_tx_data[0] -.sym 11513 w_tx_data_io[4] -.sym 11518 w_tx_data_io[3] -.sym 11525 w_ioc[1] -.sym 11527 w_tx_data_io[1] -.sym 11528 w_tx_data_io[2] -.sym 11531 spi_if_ins.w_rx_data[1] -.sym 11538 spi_if_ins.w_rx_data[1] -.sym 11541 spi_if_ins.w_rx_data[3] -.sym 11542 spi_if_ins.w_rx_data[4] -.sym 11543 spi_if_ins.w_rx_data[2] -.sym 11545 w_ioc[4] -.sym 11546 spi_if_ins.w_rx_data[0] -.sym 11547 w_cs[3] -.sym 11549 w_ioc[2] -.sym 11550 w_cs[1] -.sym 11551 w_ioc[3] -.sym 11552 w_cs[2] -.sym 11554 w_cs[0] -.sym 11556 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11571 w_cs[0] -.sym 11572 w_cs[1] -.sym 11573 w_cs[3] -.sym 11574 w_cs[2] -.sym 11577 w_cs[1] -.sym 11578 w_cs[3] -.sym 11579 w_cs[2] -.sym 11580 w_cs[0] -.sym 11586 spi_if_ins.w_rx_data[0] -.sym 11589 spi_if_ins.w_rx_data[2] -.sym 11595 w_ioc[3] -.sym 11596 w_ioc[4] -.sym 11597 w_ioc[2] -.sym 11603 spi_if_ins.w_rx_data[3] -.sym 11609 spi_if_ins.w_rx_data[1] -.sym 11616 spi_if_ins.w_rx_data[4] -.sym 11617 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 11618 r_counter_$glb_clk -.sym 11620 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11621 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11622 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11623 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3] -.sym 11624 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11625 io_ctrl_ins.rf_mode[0] -.sym 11626 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11627 io_ctrl_ins.debug_mode[1] -.sym 11628 spi_if_ins.w_rx_data[0] -.sym 11635 spi_if_ins.w_rx_data[3] -.sym 11637 spi_if_ins.w_rx_data[5] -.sym 11639 w_soft_reset -.sym 11640 $PACKER_VCC_NET -.sym 11644 w_tx_data_io[6] -.sym 11647 io_ctrl_ins.rf_mode[0] -.sym 11648 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11649 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 11650 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 11651 w_rx_data[6] -.sym 11652 w_tx_data_io[5] -.sym 11655 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11661 o_tr_vc1$SB_IO_OUT -.sym 11662 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 11663 w_ioc[0] -.sym 11667 i_button_SB_LUT4_I1_O[0] -.sym 11668 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 11670 io_ctrl_ins.o_pmod[2] -.sym 11671 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 11672 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2] -.sym 11673 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 11674 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11675 i_button_SB_LUT4_I1_O[1] -.sym 11676 i_config[2]$SB_IO_IN -.sym 11678 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11679 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11680 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3] -.sym 11681 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11682 io_ctrl_ins.rf_mode[0] -.sym 11683 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 11685 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11688 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 11691 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11694 i_config[2]$SB_IO_IN -.sym 11695 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11696 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2] -.sym 11697 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3] -.sym 11700 i_button_SB_LUT4_I1_O[1] -.sym 11703 i_button_SB_LUT4_I1_O[0] -.sym 11713 o_tr_vc1$SB_IO_OUT -.sym 11714 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11719 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 11721 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 11724 io_ctrl_ins.rf_mode[0] -.sym 11725 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11726 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11727 io_ctrl_ins.o_pmod[2] -.sym 11730 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11731 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11733 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11736 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 11737 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 11738 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 11739 w_ioc[0] -.sym 11740 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 11741 r_counter_$glb_clk -.sym 11742 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11743 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11744 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 11745 io_ctrl_ins.o_pmod[1] -.sym 11746 io_ctrl_ins.o_pmod[6] -.sym 11747 io_ctrl_ins.o_pmod[0] -.sym 11748 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[2] -.sym 11750 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[3] -.sym 11756 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11757 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 11758 io_ctrl_ins.o_pmod[5] -.sym 11760 io_ctrl_ins.debug_mode[1] -.sym 11761 w_rx_data[2] -.sym 11763 w_rx_data[1] -.sym 11766 io_ctrl_ins.o_pmod[2] -.sym 11767 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11770 w_rx_data[2] -.sym 11784 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11785 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11786 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11788 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11789 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[3] -.sym 11790 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11791 i_config[3]$SB_IO_IN -.sym 11792 io_ctrl_ins.pmod_dir_state[1] -.sym 11793 o_led0$SB_IO_OUT -.sym 11794 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11796 w_ioc[0] -.sym 11797 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 11798 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11799 io_ctrl_ins.pmod_dir_state[0] -.sym 11800 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[2] -.sym 11802 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O -.sym 11804 o_led1$SB_IO_OUT -.sym 11805 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[2] -.sym 11807 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[3] -.sym 11808 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11809 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 11811 io_ctrl_ins.o_pmod[6] -.sym 11812 io_ctrl_ins.o_pmod[0] -.sym 11813 o_shdn_rx_lna$SB_IO_OUT -.sym 11817 io_ctrl_ins.pmod_dir_state[0] -.sym 11818 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11819 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11820 io_ctrl_ins.o_pmod[0] -.sym 11823 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 11826 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 11829 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[2] -.sym 11830 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11831 o_led0$SB_IO_OUT -.sym 11832 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[3] -.sym 11835 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[2] -.sym 11836 o_led1$SB_IO_OUT -.sym 11837 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[3] -.sym 11838 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11847 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11848 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11849 io_ctrl_ins.pmod_dir_state[1] -.sym 11850 o_shdn_rx_lna$SB_IO_OUT -.sym 11853 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11854 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11855 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 11856 w_ioc[0] -.sym 11859 i_config[3]$SB_IO_IN -.sym 11860 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 11861 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 11862 io_ctrl_ins.o_pmod[6] -.sym 11863 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O -.sym 11864 r_counter_$glb_clk -.sym 11865 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 11868 o_shdn_tx_lna$SB_IO_OUT -.sym 11869 io_ctrl_ins.mixer_en_state -.sym 11871 o_shdn_rx_lna$SB_IO_OUT -.sym 11878 w_rx_data[0] -.sym 11879 o_led0$SB_IO_OUT -.sym 11880 i_config[2]$SB_IO_IN -.sym 11885 o_tr_vc1$SB_IO_OUT -.sym 11889 w_rx_data[1] -.sym 11890 o_led1$SB_IO_OUT -.sym 11913 w_rx_data[0] -.sym 11925 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11927 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11930 w_rx_data[2] -.sym 11933 o_shdn_tx_lna$SB_IO_OUT -.sym 11934 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 11935 io_ctrl_ins.pmod_dir_state[2] -.sym 11947 w_rx_data[0] -.sym 11967 w_rx_data[2] -.sym 11970 o_shdn_tx_lna$SB_IO_OUT -.sym 11971 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 11972 io_ctrl_ins.pmod_dir_state[2] -.sym 11973 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 11986 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 11987 r_counter_$glb_clk -.sym 12009 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 12010 w_tx_data_io[3] -.sym 12012 w_tx_data_io[4] -.sym 12013 o_shdn_tx_lna$SB_IO_OUT -.sym 12309 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] +.sym 11373 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 11378 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R +.sym 11380 w_load +.sym 11386 rx_24_fifo.wr_addr[3] +.sym 11387 w_rx_24_fifo_data[12] +.sym 11391 rx_24_fifo.wr_addr[4] +.sym 11394 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 11395 rx_24_fifo.wr_addr[8] +.sym 11401 w_rx_24_fifo_empty +.sym 11402 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11416 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[9] +.sym 11417 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 11418 rx_24_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 11419 rx_24_fifo.rd_addr[4] +.sym 11420 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1] +.sym 11421 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 11422 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 11423 rx_24_fifo.rd_addr[6] +.sym 11424 rx_24_fifo.rd_addr[0] +.sym 11425 lvds_rx_24_inst.r_data[19] +.sym 11426 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 11427 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 11428 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 11429 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 11430 lvds_rx_24_inst.o_debug_state[0] +.sym 11432 rx_24_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 11433 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[2] +.sym 11434 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 11435 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[3] +.sym 11437 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11441 rx_24_fifo.wr_addr[0] +.sym 11442 rx_24_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 11444 lvds_rx_24_inst.r_data[23] +.sym 11445 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 11448 lvds_rx_24_inst.o_debug_state[0] +.sym 11451 lvds_rx_24_inst.r_data[19] +.sym 11454 rx_24_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 11455 rx_24_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 11456 rx_24_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 11457 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11460 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 11461 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 11462 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 11463 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 11466 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[9] +.sym 11467 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 11468 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 11469 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11472 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 11473 rx_24_fifo.rd_addr[6] +.sym 11474 rx_24_fifo.rd_addr[4] +.sym 11475 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 11478 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1] +.sym 11479 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[2] +.sym 11480 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 11481 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[3] +.sym 11484 rx_24_fifo.rd_addr[0] +.sym 11485 rx_24_fifo.wr_addr[0] +.sym 11491 lvds_rx_24_inst.o_debug_state[0] +.sym 11493 lvds_rx_24_inst.r_data[23] +.sym 11494 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 11495 lvds_clock_$glb_clk +.sym 11496 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 11498 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E +.sym 11500 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 11501 w_tx_data_sys[0] +.sym 11502 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 11503 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 11504 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 11507 w_rx_24_fifo_full +.sym 11509 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11510 i_smi_a2$SB_IO_IN +.sym 11515 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 11516 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 11518 rx_24_fifo.rd_addr[0] +.sym 11519 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 11520 rx_24_fifo.rd_addr[8] +.sym 11522 rx_24_fifo.wr_addr[2] +.sym 11523 w_rx_24_fifo_full +.sym 11524 rx_24_fifo.wr_addr[4] +.sym 11525 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 11527 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 11528 rx_24_fifo.full_o_SB_LUT4_I3_O[0] +.sym 11530 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 11540 rx_24_fifo.wr_addr[0] +.sym 11543 rx_24_fifo.wr_addr[5] +.sym 11544 rx_24_fifo.wr_addr[2] +.sym 11548 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 11551 rx_24_fifo.wr_addr[7] +.sym 11553 rx_24_fifo.wr_addr[4] +.sym 11557 rx_24_fifo.wr_addr[6] +.sym 11568 rx_24_fifo.wr_addr[3] +.sym 11570 $nextpnr_ICESTORM_LC_12$O +.sym 11573 rx_24_fifo.wr_addr[0] +.sym 11576 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 11579 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 11580 rx_24_fifo.wr_addr[0] +.sym 11582 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 11585 rx_24_fifo.wr_addr[2] +.sym 11586 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 11588 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 11591 rx_24_fifo.wr_addr[3] +.sym 11592 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 11594 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 11597 rx_24_fifo.wr_addr[4] +.sym 11598 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 11600 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 11603 rx_24_fifo.wr_addr[5] +.sym 11604 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 11606 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 11608 rx_24_fifo.wr_addr[6] +.sym 11610 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 11612 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 11614 rx_24_fifo.wr_addr[7] +.sym 11616 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 11620 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 11621 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3[1] +.sym 11622 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 11624 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0[2] +.sym 11625 w_ioc[4] +.sym 11626 rx_24_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 11637 rx_24_fifo.wr_addr[8] +.sym 11641 rx_24_fifo.wr_addr[6] +.sym 11644 lvds_rx_24_inst.r_data[18] +.sym 11645 w_cs[1] +.sym 11646 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 11650 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 11654 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 11655 lvds_rx_24_inst.r_data[16] +.sym 11656 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 11662 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 11663 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 11665 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 11666 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1] +.sym 11670 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 11671 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[2] +.sym 11673 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11674 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11676 rx_24_fifo.wr_addr[8] +.sym 11683 w_rx_24_fifo_full +.sym 11685 w_rx_24_fifo_push +.sym 11691 rx_24_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 11692 rx_24_fifo.rd_addr[4] +.sym 11693 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 11696 rx_24_fifo.wr_addr[8] +.sym 11697 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 11700 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 11703 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 11708 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 11712 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11713 rx_24_fifo.rd_addr[4] +.sym 11714 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[2] +.sym 11715 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 11718 w_rx_24_fifo_full +.sym 11719 rx_24_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 11720 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11721 w_rx_24_fifo_push +.sym 11726 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1] +.sym 11731 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[2] +.sym 11737 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 11740 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 11741 lvds_clock_$glb_clk +.sym 11742 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 11743 w_rx_24_fifo_data[4] +.sym 11744 w_rx_24_fifo_data[11] +.sym 11745 w_rx_24_fifo_data[6] +.sym 11746 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 11747 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 11749 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 11750 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 11755 spi_if_ins.w_rx_data[4] +.sym 11763 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 11765 w_rx_24_fifo_data[22] +.sym 11766 w_rx_24_fifo_data[23] +.sym 11767 w_rx_data[1] +.sym 11768 lvds_rx_24_inst.r_data[23] +.sym 11769 w_rx_data[7] +.sym 11773 w_rx_data[6] +.sym 11774 lvds_rx_24_inst.r_data[22] +.sym 11778 i_smi_a2_SB_LUT4_I1_O[1] +.sym 11784 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0] +.sym 11785 rx_24_fifo.rd_addr[6] +.sym 11786 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[2] +.sym 11787 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[3] +.sym 11788 rx_24_fifo.full_o_SB_LUT4_I3_O[2] +.sym 11789 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11790 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 11791 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[3] +.sym 11792 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 11793 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 11794 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 11795 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 11796 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[4] +.sym 11797 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 11798 rx_24_fifo.full_o_SB_LUT4_I3_O[0] +.sym 11799 rx_24_fifo.rd_addr[4] +.sym 11800 rx_24_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 11802 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[2] +.sym 11803 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[3] +.sym 11804 rx_24_fifo.full_o_SB_LUT4_I3_O[3] +.sym 11805 w_rx_24_fifo_push +.sym 11807 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 11808 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 11809 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[9] +.sym 11812 rx_24_fifo.full_o_SB_LUT4_I3_O[1] +.sym 11813 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 11814 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1] +.sym 11815 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11817 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 11818 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11819 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 11820 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 11823 rx_24_fifo.full_o_SB_LUT4_I3_O[0] +.sym 11824 rx_24_fifo.full_o_SB_LUT4_I3_O[2] +.sym 11825 rx_24_fifo.full_o_SB_LUT4_I3_O[1] +.sym 11826 rx_24_fifo.full_o_SB_LUT4_I3_O[3] +.sym 11829 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[2] +.sym 11830 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[3] +.sym 11831 rx_24_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 11832 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 11835 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[4] +.sym 11836 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 11837 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 11838 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 11841 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0] +.sym 11842 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1] +.sym 11843 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[2] +.sym 11844 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[3] +.sym 11847 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 11848 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 11849 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 11850 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 11853 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 11854 rx_24_fifo.rd_addr[6] +.sym 11855 rx_24_fifo.rd_addr[4] +.sym 11856 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[3] +.sym 11859 rx_24_fifo.rd_addr[6] +.sym 11860 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[9] +.sym 11861 w_rx_24_fifo_push +.sym 11862 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 11864 lvds_clock_$glb_clk +.sym 11865 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 11866 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E +.sym 11867 w_tx_data_io[2] +.sym 11869 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] +.sym 11870 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[2] +.sym 11872 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] +.sym 11878 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 11882 rx_24_fifo.wr_addr[8] +.sym 11883 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 11885 w_rx_24_fifo_data[4] +.sym 11886 rx_24_fifo.wr_addr[3] +.sym 11887 rx_24_fifo.wr_addr[2] +.sym 11889 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 11898 i_smi_a2_SB_LUT4_I1_O[1] +.sym 11907 lvds_rx_24_inst.o_debug_state[0] +.sym 11912 lvds_rx_24_inst.r_data[20] +.sym 11923 lvds_rx_24_inst.r_data[18] +.sym 11925 lvds_rx_24_inst.r_data[16] +.sym 11930 lvds_rx_24_inst.r_data[1] +.sym 11931 lvds_rx_24_inst.r_data[21] +.sym 11933 w_rx_24_fifo_push +.sym 11936 w_lvds_rx_24_d1 +.sym 11938 i_smi_a2_SB_LUT4_I1_O[1] +.sym 11940 lvds_rx_24_inst.o_debug_state[0] +.sym 11942 lvds_rx_24_inst.r_data[16] +.sym 11946 lvds_rx_24_inst.r_data[20] +.sym 11947 lvds_rx_24_inst.o_debug_state[0] +.sym 11953 lvds_rx_24_inst.r_data[1] +.sym 11954 lvds_rx_24_inst.o_debug_state[0] +.sym 11958 w_rx_24_fifo_push +.sym 11959 i_smi_a2_SB_LUT4_I1_O[1] +.sym 11971 lvds_rx_24_inst.o_debug_state[0] +.sym 11973 lvds_rx_24_inst.r_data[18] +.sym 11977 lvds_rx_24_inst.r_data[21] +.sym 11978 lvds_rx_24_inst.o_debug_state[0] +.sym 11983 lvds_rx_24_inst.o_debug_state[0] +.sym 11985 w_lvds_rx_24_d1 +.sym 11986 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 11987 lvds_clock_$glb_clk +.sym 11988 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 11990 io_ctrl_ins.rf_pin_state[6] +.sym 11992 io_ctrl_ins.rf_pin_state[7] +.sym 11993 io_ctrl_ins.rf_pin_state[2] +.sym 11995 io_ctrl_ins.rf_pin_state[1] +.sym 11997 lvds_rx_24_inst.o_debug_state[0] +.sym 12004 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 12005 io_ctrl_ins.debug_mode[1] +.sym 12006 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 12007 lvds_rx_24_inst.r_data[3] +.sym 12009 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 12016 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 12035 lvds_rx_24_inst.r_data[20] +.sym 12036 lvds_rx_24_inst.r_data[23] +.sym 12039 lvds_rx_24_inst.r_data[22] +.sym 12061 lvds_rx_24_inst.r_data[21] +.sym 12070 lvds_rx_24_inst.r_data[22] +.sym 12077 lvds_rx_24_inst.r_data[21] +.sym 12087 lvds_rx_24_inst.r_data[23] +.sym 12105 lvds_rx_24_inst.r_data[20] +.sym 12109 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 12110 lvds_clock_$glb_clk +.sym 12118 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 12125 rx_24_fifo.wr_addr[5] +.sym 12126 rx_24_fifo.wr_addr[8] +.sym 12127 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 12128 rx_24_fifo.wr_addr[3] +.sym 12133 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 12134 rx_24_fifo.wr_addr[6] +.sym 12135 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 12138 lvds_rx_24_inst.o_debug_state[0] +.sym 12156 lvds_rx_24_inst.o_debug_state[0] +.sym 12159 lvds_rx_24_inst.o_debug_state[1] +.sym 12170 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12173 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 12174 w_rx_24_fifo_full +.sym 12176 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E +.sym 12180 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E +.sym 12192 lvds_rx_24_inst.o_debug_state[0] +.sym 12194 w_rx_24_fifo_full +.sym 12195 lvds_rx_24_inst.o_debug_state[1] +.sym 12204 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E +.sym 12228 lvds_rx_24_inst.o_debug_state[0] +.sym 12229 lvds_rx_24_inst.o_debug_state[1] +.sym 12230 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12231 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 12232 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E +.sym 12233 lvds_clock_$glb_clk +.sym 12234 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 12255 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 12309 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O .sym 12310 w_smi_data_output[0] .sym 12312 i_smi_a3$SB_IO_IN .sym 12313 w_smi_data_output[7] .sym 12315 i_smi_a3$SB_IO_IN -.sym 12320 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] +.sym 12322 w_smi_data_output[7] .sym 12323 i_smi_a3$SB_IO_IN -.sym 12327 w_smi_data_output[7] -.sym 12328 w_smi_data_output[0] +.sym 12326 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O .sym 12331 i_smi_a3$SB_IO_IN -.sym 12340 smi_ctrl_ins.soe_and_reset -.sym 12366 w_smi_data_output[0] +.sym 12332 w_smi_data_output[0] +.sym 12338 w_rx_09_fifo_data[13] +.sym 12341 w_rx_09_fifo_data[14] +.sym 12350 lvds_rx_24_inst.r_data[24] +.sym 12351 lvds_rx_24_inst.r_data[17] +.sym 12353 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 12357 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12367 i_sck$SB_IO_IN .sym 12368 w_smi_data_output[3] -.sym 12463 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_1_O[3] -.sym 12466 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_3_O[3] -.sym 12476 rx_09_fifo.wr_addr[4] -.sym 12480 rx_09_fifo.wr_addr[9] -.sym 12484 w_soft_reset -.sym 12507 i_smi_a3$SB_IO_IN -.sym 12544 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12545 rx_09_fifo.rd_addr[1] -.sym 12558 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 12559 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 12560 rx_09_fifo.rd_addr[4] -.sym 12561 rx_09_fifo.rd_addr[5] -.sym 12562 rx_09_fifo.rd_addr[6] -.sym 12571 rx_09_fifo.rd_addr[7] -.sym 12572 $nextpnr_ICESTORM_LC_5$O -.sym 12575 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12578 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[2] -.sym 12581 rx_09_fifo.rd_addr[1] -.sym 12584 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[3] -.sym 12587 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 12588 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[2] -.sym 12590 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 12593 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 12594 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[3] -.sym 12596 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 12599 rx_09_fifo.rd_addr[4] -.sym 12600 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 12602 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[6] -.sym 12605 rx_09_fifo.rd_addr[5] -.sym 12606 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 12608 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[7] -.sym 12611 rx_09_fifo.rd_addr[6] -.sym 12612 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[6] -.sym 12614 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 12616 rx_09_fifo.rd_addr[7] -.sym 12618 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[7] -.sym 12623 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 12625 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 12627 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 12634 rx_09_fifo.rd_addr[6] -.sym 12635 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12636 w_rx_09_fifo_pulled_data[22] -.sym 12637 rx_09_fifo.wr_addr[7] -.sym 12638 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 12640 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 12644 rx_09_fifo.rd_addr[7] -.sym 12647 lvds_rx_09_inst.r_data[1] -.sym 12648 i_smi_a2$SB_IO_IN -.sym 12649 w_rx_09_fifo_pulled_data[24] -.sym 12650 w_rx_09_fifo_empty -.sym 12651 lvds_rx_09_inst.r_data[3] -.sym 12652 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 12653 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 12658 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 12669 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[6] -.sym 12671 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 12673 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[2] -.sym 12674 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[3] -.sym 12676 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12678 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[7] -.sym 12680 rx_09_fifo.rd_addr[9] -.sym 12683 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12684 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 12686 rx_09_fifo.wr_addr[3] -.sym 12687 rx_09_fifo.rd_addr[8] -.sym 12688 rx_09_fifo.wr_addr[7] -.sym 12689 rx_09_fifo.wr_addr[6] -.sym 12691 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12692 rx_09_fifo.rd_addr[1] -.sym 12693 rx_09_fifo.wr_addr[8] -.sym 12695 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[9] -.sym 12697 rx_09_fifo.rd_addr[8] -.sym 12699 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 12701 $nextpnr_ICESTORM_LC_6$I3 -.sym 12704 rx_09_fifo.rd_addr[9] -.sym 12705 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[9] -.sym 12711 $nextpnr_ICESTORM_LC_6$I3 -.sym 12714 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[2] -.sym 12715 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12716 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 12717 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12720 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[3] -.sym 12721 rx_09_fifo.wr_addr[6] -.sym 12722 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[6] -.sym 12723 rx_09_fifo.wr_addr[3] -.sym 12728 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12729 rx_09_fifo.rd_addr[1] -.sym 12732 rx_09_fifo.wr_addr[7] -.sym 12733 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 12734 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[7] -.sym 12735 rx_09_fifo.wr_addr[8] -.sym 12746 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 12748 i_smi_a2_SB_LUT4_I0_O -.sym 12749 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[3] -.sym 12750 smi_ctrl_ins.w_fifo_09_pull_trigger -.sym 12751 smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_E -.sym 12752 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_15_O[3] -.sym 12758 w_rx_09_fifo_data[23] -.sym 12759 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 12760 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 12761 rx_09_fifo.wr_addr[4] -.sym 12762 rx_09_fifo.wr_addr[3] -.sym 12763 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12764 rx_09_fifo.wr_addr[6] -.sym 12765 lvds_rx_09_inst.r_data[24] -.sym 12767 rx_09_fifo.wr_addr[8] -.sym 12768 w_soft_reset -.sym 12771 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 12775 rx_09_fifo.rd_addr[1] -.sym 12779 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 12780 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 12787 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[9] -.sym 12788 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[10] -.sym 12789 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[1] -.sym 12790 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 12791 lvds_rx_09_inst.o_debug_state[0] -.sym 12792 lvds_rx_09_inst.r_data[1] -.sym 12793 lvds_rx_09_inst.r_data[0] -.sym 12794 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 12797 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 12798 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12799 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12800 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 12802 rx_09_fifo.wr_addr[4] -.sym 12803 rx_09_fifo.wr_addr[9] -.sym 12804 rx_09_fifo.wr_addr[5] -.sym 12806 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[3] -.sym 12808 lvds_rx_09_inst.r_cnt[0] -.sym 12810 lvds_rx_09_inst.r_cnt[1] -.sym 12812 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[1] -.sym 12813 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 12814 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[2] -.sym 12815 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 12816 w_lvds_rx_09_d0 -.sym 12817 w_lvds_rx_09_d1 -.sym 12820 lvds_rx_09_inst.o_debug_state[0] -.sym 12821 lvds_rx_09_inst.r_data[1] -.sym 12825 lvds_rx_09_inst.r_data[0] -.sym 12827 lvds_rx_09_inst.o_debug_state[0] -.sym 12831 rx_09_fifo.wr_addr[4] -.sym 12832 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 12833 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12834 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12837 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[1] -.sym 12838 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[3] -.sym 12839 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[2] -.sym 12840 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[10] -.sym 12843 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 12844 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 12845 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 12846 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[1] -.sym 12849 rx_09_fifo.wr_addr[9] -.sym 12850 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 12851 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[9] -.sym 12852 rx_09_fifo.wr_addr[5] -.sym 12855 w_lvds_rx_09_d1 -.sym 12856 lvds_rx_09_inst.o_debug_state[0] -.sym 12858 lvds_rx_09_inst.r_cnt[1] -.sym 12861 w_lvds_rx_09_d0 -.sym 12862 lvds_rx_09_inst.r_cnt[0] -.sym 12863 lvds_rx_09_inst.o_debug_state[0] -.sym 12865 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 12866 lvds_clock_$glb_clk -.sym 12867 w_soft_reset_$glb_sr -.sym 12868 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E -.sym 12871 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E -.sym 12873 w_smi_data_output[0] -.sym 12875 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 12880 rx_09_fifo.rd_addr[5] -.sym 12882 rx_09_fifo.rd_addr[4] -.sym 12883 rx_09_fifo.rd_addr[9] -.sym 12884 rx_09_fifo.rd_addr[6] -.sym 12885 rx_09_fifo.rd_addr[1] -.sym 12886 rx_09_fifo.rd_addr[7] -.sym 12889 w_soft_reset -.sym 12890 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 12891 rx_09_fifo.rd_addr[8] -.sym 12894 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 12897 i_smi_a3$SB_IO_IN -.sym 12899 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 12901 w_rx_09_fifo_pulled_data[8] -.sym 12903 i_smi_a1$SB_IO_IN -.sym 12909 lvds_rx_09_inst.o_debug_state[1] -.sym 12910 rx_09_fifo.rd_addr[8] -.sym 12911 lvds_rx_09_inst.o_debug_state[0] -.sym 12912 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[3] -.sym 12914 w_soft_reset -.sym 12915 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 12916 w_rx_09_fifo_push -.sym 12917 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 12918 rx_09_fifo.wr_addr[9] -.sym 12919 w_rx_09_fifo_empty -.sym 12920 rx_09_fifo.rd_addr[9] -.sym 12921 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12922 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[0] -.sym 12923 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] -.sym 12924 rx_09_fifo.rd_addr[7] -.sym 12926 rx_09_fifo.wr_addr[7] -.sym 12928 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 12929 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] -.sym 12932 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[3] -.sym 12934 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[1] -.sym 12935 rx_09_fifo.rd_addr[1] -.sym 12937 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12938 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[2] -.sym 12939 rx_09_fifo.wr_addr[8] -.sym 12940 rx_09_fifo.wr_addr[3] -.sym 12943 w_rx_09_fifo_push -.sym 12945 w_soft_reset -.sym 12948 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 12949 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] -.sym 12950 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[3] -.sym 12951 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[2] -.sym 12954 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[1] -.sym 12955 w_rx_09_fifo_empty -.sym 12956 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[0] -.sym 12957 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[3] -.sym 12960 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 12961 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 12967 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 12969 rx_09_fifo.rd_addr[1] -.sym 12972 rx_09_fifo.wr_addr[7] -.sym 12973 rx_09_fifo.rd_addr[7] -.sym 12974 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 12975 rx_09_fifo.wr_addr[3] -.sym 12978 lvds_rx_09_inst.o_debug_state[0] -.sym 12980 lvds_rx_09_inst.o_debug_state[1] -.sym 12981 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] -.sym 12984 rx_09_fifo.rd_addr[8] -.sym 12985 rx_09_fifo.wr_addr[9] -.sym 12986 rx_09_fifo.wr_addr[8] -.sym 12987 rx_09_fifo.rd_addr[9] -.sym 12989 r_counter_$glb_clk -.sym 12990 w_soft_reset_$glb_sr -.sym 12997 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 12998 spi_if_ins.r_tx_data_valid -.sym 13000 w_smi_data_output[0] -.sym 13003 rx_09_fifo.wr_addr[7] -.sym 13004 w_rx_09_fifo_data[9] -.sym 13005 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 13007 lvds_rx_09_inst.o_debug_state[0] -.sym 13008 w_rx_09_fifo_data[22] -.sym 13009 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 13010 w_soft_reset -.sym 13012 w_rx_09_fifo_data[8] -.sym 13013 lvds_rx_09_inst.o_debug_state[1] -.sym 13014 rx_09_fifo.wr_addr[5] -.sym 13020 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13025 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13034 w_soft_reset -.sym 13035 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 13040 lvds_rx_09_inst.o_debug_state[0] -.sym 13047 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 13048 lvds_rx_09_inst.r_push -.sym 13052 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 13054 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 13058 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 13083 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 13084 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 13085 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 13086 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 13101 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 13103 w_soft_reset -.sym 13104 lvds_rx_09_inst.o_debug_state[0] -.sym 13110 lvds_rx_09_inst.r_push +.sym 12380 lvds_rx_24_inst.r_data[15] +.sym 12399 lvds_rx_24_inst.o_debug_state[0] +.sym 12412 lvds_rx_24_inst.o_debug_state[0] +.sym 12413 lvds_rx_24_inst.r_data[15] +.sym 12456 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 12457 lvds_clock_$glb_clk +.sym 12458 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 12466 rx_09_fifo.rd_addr[0] +.sym 12476 w_rx_09_fifo_data[14] +.sym 12478 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 12480 w_rx_09_fifo_data[15] +.sym 12482 rx_09_fifo.wr_addr[4] +.sym 12484 rx_09_fifo.wr_addr[5] +.sym 12485 rx_09_fifo.wr_addr[6] +.sym 12486 rx_09_fifo.wr_addr[8] +.sym 12493 lvds_rx_24_inst.o_debug_state[0] +.sym 12524 rx_09_fifo.rd_addr[1] +.sym 12529 w_rx_09_fifo_data[22] +.sym 12561 rx_09_fifo.wr_addr[4] +.sym 12563 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 12565 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 12566 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 12567 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 12569 rx_09_fifo.wr_addr[6] +.sym 12570 rx_09_fifo.wr_addr[7] +.sym 12571 rx_09_fifo.wr_addr[5] +.sym 12572 $nextpnr_ICESTORM_LC_8$O +.sym 12575 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 12578 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2] +.sym 12581 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 12582 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 12584 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] +.sym 12586 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 12588 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2] +.sym 12590 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4] +.sym 12592 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 12594 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] +.sym 12596 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5] +.sym 12598 rx_09_fifo.wr_addr[4] +.sym 12600 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4] +.sym 12602 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6] +.sym 12604 rx_09_fifo.wr_addr[5] +.sym 12606 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5] +.sym 12608 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7] +.sym 12611 rx_09_fifo.wr_addr[6] +.sym 12612 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6] +.sym 12614 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8] +.sym 12617 rx_09_fifo.wr_addr[7] +.sym 12618 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7] +.sym 12623 rx_09_fifo.rd_addr[1] +.sym 12624 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 12625 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 12626 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[4] +.sym 12627 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[5] +.sym 12628 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[6] +.sym 12629 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[7] +.sym 12636 rx_09_fifo.rd_addr[5] +.sym 12637 rx_09_fifo.rd_addr[0] +.sym 12639 w_rx_09_fifo_pulled_data[6] +.sym 12648 rx_09_fifo.rd_addr[0] +.sym 12649 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12650 rx_09_fifo.wr_addr[8] +.sym 12652 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 12654 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 12656 rx_09_fifo.wr_addr[7] +.sym 12658 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8] +.sym 12663 w_rx_09_fifo_push +.sym 12664 lvds_rx_09_inst.r_data[20] +.sym 12667 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 12669 rx_09_fifo.wr_addr[9] +.sym 12670 w_rx_09_fifo_full +.sym 12676 rx_09_fifo.wr_addr[8] +.sym 12678 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12684 rx_09_fifo.rd_addr[4] +.sym 12691 lvds_rx_09_inst.r_data[19] +.sym 12692 lvds_rx_09_inst.r_data[15] +.sym 12695 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9] +.sym 12698 rx_09_fifo.wr_addr[8] +.sym 12699 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8] +.sym 12703 rx_09_fifo.wr_addr[9] +.sym 12705 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9] +.sym 12708 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 12709 rx_09_fifo.rd_addr[4] +.sym 12710 w_rx_09_fifo_push +.sym 12711 w_rx_09_fifo_full +.sym 12714 lvds_rx_09_inst.r_data[20] +.sym 12723 lvds_rx_09_inst.r_data[19] +.sym 12734 lvds_rx_09_inst.r_data[15] +.sym 12739 w_rx_09_fifo_push +.sym 12741 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12742 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 12743 lvds_clock_$glb_clk +.sym 12745 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[8] +.sym 12746 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[9] +.sym 12747 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[10] +.sym 12748 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] +.sym 12749 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1] +.sym 12750 w_smi_read_req +.sym 12751 smi_ctrl_ins.w_fifo_09_pull_trigger +.sym 12752 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 12757 w_rx_09_fifo_push +.sym 12759 w_rx_09_fifo_data[20] +.sym 12760 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 12761 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 12765 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 12766 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 12767 w_rx_09_fifo_data[21] +.sym 12768 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 12769 rx_09_fifo.rd_addr[6] +.sym 12770 sys_ctrl_ins.reset_cmd +.sym 12775 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12776 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 12777 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 12778 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 12780 lvds_rx_24_inst.o_debug_state[0] +.sym 12787 rx_09_fifo.wr_addr[5] +.sym 12788 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E +.sym 12789 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 12790 rx_09_fifo.wr_addr[6] +.sym 12791 rx_09_fifo.wr_addr[7] +.sym 12792 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[6] +.sym 12794 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] +.sym 12795 rx_09_fifo.rd_addr[1] +.sym 12796 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 12797 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 12799 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[5] +.sym 12800 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 12801 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[7] +.sym 12802 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[8] +.sym 12803 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[9] +.sym 12804 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 12805 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] +.sym 12806 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[3] +.sym 12807 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] +.sym 12808 rx_09_fifo.rd_addr[0] +.sym 12810 rx_09_fifo.wr_addr[8] +.sym 12811 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] +.sym 12812 $PACKER_GND_NET +.sym 12813 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] +.sym 12815 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 12816 rx_09_fifo.wr_addr[9] +.sym 12817 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 12819 rx_09_fifo.rd_addr[0] +.sym 12821 rx_09_fifo.rd_addr[1] +.sym 12825 rx_09_fifo.wr_addr[9] +.sym 12826 rx_09_fifo.wr_addr[6] +.sym 12827 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[9] +.sym 12828 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[6] +.sym 12831 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] +.sym 12832 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 12833 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 12834 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] +.sym 12837 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 12838 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 12839 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 12840 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 12843 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[5] +.sym 12844 rx_09_fifo.wr_addr[5] +.sym 12845 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[8] +.sym 12846 rx_09_fifo.wr_addr[8] +.sym 12849 rx_09_fifo.wr_addr[7] +.sym 12850 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 12851 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 12852 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[7] +.sym 12855 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[3] +.sym 12856 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] +.sym 12857 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] +.sym 12858 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] +.sym 12861 $PACKER_GND_NET +.sym 12865 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E +.sym 12866 r_counter_$glb_clk +.sym 12867 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 12868 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 12869 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2] +.sym 12870 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 12871 spi_if_ins.spi.r_tx_byte[7] +.sym 12872 spi_if_ins.spi.r_tx_byte[1] +.sym 12874 spi_if_ins.spi.r_tx_byte[3] +.sym 12875 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 12882 w_rx_24_fifo_empty +.sym 12884 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E +.sym 12890 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 12891 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 12892 rx_09_fifo.wr_addr[6] +.sym 12893 rx_09_fifo.rd_addr[9] +.sym 12894 rx_09_fifo.wr_addr[7] +.sym 12896 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 12897 lvds_rx_24_inst.r_data[9] +.sym 12898 rx_09_fifo.rd_addr[9] +.sym 12900 rx_09_fifo.wr_addr[4] +.sym 12902 rx_09_fifo.wr_addr[5] +.sym 12903 i_smi_a2_SB_LUT4_I1_O[1] +.sym 12912 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 12914 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 12916 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 12918 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 12920 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 12921 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1] +.sym 12926 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 12927 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 12930 sys_ctrl_ins.reset_cmd +.sym 12933 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 12934 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2] +.sym 12938 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 12945 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 12948 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 12957 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 12961 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 12966 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 12974 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 12981 sys_ctrl_ins.reset_cmd +.sym 12984 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 12985 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 12986 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1] +.sym 12987 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2] +.sym 12988 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O +.sym 12989 lvds_clock_$glb_clk +.sym 12990 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 12992 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 12993 i_smi_a1_SB_LUT4_I1_O +.sym 12994 spi_if_ins.spi.r_tx_byte[2] +.sym 12995 i_smi_a2_SB_LUT4_I1_O[0] +.sym 12996 spi_if_ins.spi.r_tx_byte[5] +.sym 12997 spi_if_ins.spi.r_tx_byte[6] +.sym 12998 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 12999 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 13003 w_rx_09_fifo_data[4] +.sym 13005 rx_09_fifo.wr_addr[7] +.sym 13007 smi_ctrl_ins.int_cnt_09[3] +.sym 13009 rx_09_fifo.wr_addr[8] +.sym 13011 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 13012 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 13013 rx_09_fifo.wr_addr[6] +.sym 13014 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 13015 lvds_rx_24_inst.r_data[24] +.sym 13032 rx_09_fifo.wr_addr[4] +.sym 13033 lvds_rx_24_inst.r_data[24] +.sym 13034 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 13037 rx_09_fifo.rd_addr[4] +.sym 13040 lvds_rx_24_inst.r_data[26] +.sym 13041 rx_09_fifo.rd_addr[6] +.sym 13042 rx_09_fifo.wr_addr[8] +.sym 13044 rx_09_fifo.wr_addr[6] +.sym 13045 rx_09_fifo.wr_addr[7] +.sym 13048 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 13049 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 13050 lvds_rx_24_inst.o_debug_state[0] +.sym 13051 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 13056 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 13057 lvds_rx_24_inst.r_data[9] +.sym 13063 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13066 lvds_rx_24_inst.r_data[24] +.sym 13067 lvds_rx_24_inst.o_debug_state[0] +.sym 13071 lvds_rx_24_inst.r_data[26] +.sym 13074 lvds_rx_24_inst.o_debug_state[0] +.sym 13083 rx_09_fifo.wr_addr[6] +.sym 13084 rx_09_fifo.wr_addr[4] +.sym 13085 rx_09_fifo.rd_addr[4] +.sym 13086 rx_09_fifo.rd_addr[6] +.sym 13095 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 13096 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 13097 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 13098 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 13101 lvds_rx_24_inst.r_data[9] +.sym 13103 lvds_rx_24_inst.o_debug_state[0] +.sym 13107 rx_09_fifo.wr_addr[8] +.sym 13108 rx_09_fifo.wr_addr[7] +.sym 13109 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 13110 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 13111 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce .sym 13112 lvds_clock_$glb_clk -.sym 13113 w_soft_reset_$glb_sr -.sym 13114 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] -.sym 13115 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 13116 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 13117 spi_if_ins.spi.r_tx_byte[7] -.sym 13118 spi_if_ins.spi.r_tx_byte[5] -.sym 13119 spi_if_ins.spi.r_tx_byte[3] -.sym 13120 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 13126 lvds_rx_09_inst.o_debug_state[0] -.sym 13127 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 13133 w_rx_09_fifo_data[10] -.sym 13140 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 13146 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 13157 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 13159 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 13163 spi_if_ins.state_if_SB_DFFESR_Q_D[0] -.sym 13166 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 13167 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13174 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 13177 spi_if_ins.state_if[0] -.sym 13178 spi_if_ins.state_if[1] -.sym 13182 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 13185 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13186 spi_if_ins.state_if[1] -.sym 13188 spi_if_ins.state_if[0] -.sym 13189 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13190 spi_if_ins.state_if[1] -.sym 13191 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13194 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13195 spi_if_ins.state_if[0] -.sym 13196 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13197 spi_if_ins.state_if[1] -.sym 13206 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13208 spi_if_ins.state_if[1] -.sym 13209 spi_if_ins.state_if[0] -.sym 13212 spi_if_ins.state_if[0] -.sym 13213 spi_if_ins.state_if[1] -.sym 13215 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13224 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 13225 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 13227 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13230 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13231 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 13232 spi_if_ins.state_if_SB_DFFESR_Q_D[0] -.sym 13233 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 13234 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 13235 r_counter_$glb_clk -.sym 13237 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 13238 spi_if_ins.spi.r_tx_byte[0] -.sym 13239 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 13240 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 13241 spi_if_ins.spi.r_tx_byte[4] -.sym 13242 spi_if_ins.spi.r_tx_byte[2] -.sym 13243 spi_if_ins.spi.r_tx_byte[1] -.sym 13250 $PACKER_GND_NET -.sym 13251 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 13252 spi_if_ins.spi.r_tx_byte[7] -.sym 13253 spi_if_ins.state_if_SB_DFFE_Q_E -.sym 13254 rx_09_fifo.wr_addr[4] -.sym 13255 rx_09_fifo.wr_addr[3] -.sym 13256 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 13257 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 13259 rx_09_fifo.wr_addr[8] -.sym 13261 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 13262 spi_if_ins.r_tx_byte[0] -.sym 13264 spi_if_ins.r_tx_byte[5] -.sym 13268 spi_if_ins.r_tx_byte[7] -.sym 13270 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 13280 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 13281 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 13283 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 13284 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13288 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 13291 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 13298 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13300 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 13301 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13317 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 13318 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13319 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 13320 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 13323 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13324 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 13331 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13332 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13335 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 13338 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 13341 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 13344 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 13357 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E -.sym 13358 r_counter_$glb_clk -.sym 13359 spi_if_ins.state_if_SB_DFFESR_Q_R -.sym 13361 spi_if_ins.spi.r_tx_byte[6] +.sym 13113 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 13114 w_tx_data_smi[0] +.sym 13116 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 13118 w_tx_data_smi[2] +.sym 13121 w_tx_data_smi[1] +.sym 13128 w_rx_09_fifo_data[6] +.sym 13137 i_smi_a1_SB_LUT4_I1_O +.sym 13141 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13146 i_smi_a3$SB_IO_IN +.sym 13149 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 13163 lvds_rx_24_inst.r_data[26] +.sym 13164 lvds_rx_24_inst.r_data[28] +.sym 13167 lvds_rx_24_inst.r_data[15] +.sym 13191 lvds_rx_24_inst.r_data[15] +.sym 13206 lvds_rx_24_inst.r_data[26] +.sym 13226 lvds_rx_24_inst.r_data[28] +.sym 13234 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 13235 lvds_clock_$glb_clk +.sym 13238 smi_ctrl_ins.r_fifo_09_pull +.sym 13241 smi_ctrl_ins.r_fifo_24_pull_1 +.sym 13250 w_rx_09_fifo_empty +.sym 13252 spi_if_ins.w_rx_data[5] +.sym 13253 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 13254 rx_24_fifo.rd_addr[4] +.sym 13255 w_rx_09_fifo_data[18] +.sym 13257 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 13258 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 13261 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 13268 w_cs[2] +.sym 13269 sys_ctrl_ins.reset_cmd +.sym 13270 w_rx_24_fifo_data[30] +.sym 13286 smi_ctrl_ins.r_fifo_24_pull +.sym 13290 lvds_rx_24_inst.r_data[7] +.sym 13297 w_rx_24_fifo_empty +.sym 13298 smi_ctrl_ins.r_fifo_24_pull_1 +.sym 13305 lvds_rx_24_inst.r_data[22] +.sym 13306 lvds_rx_24_inst.o_debug_state[0] +.sym 13311 lvds_rx_24_inst.r_data[22] +.sym 13312 lvds_rx_24_inst.o_debug_state[0] +.sym 13317 w_rx_24_fifo_empty +.sym 13336 lvds_rx_24_inst.o_debug_state[0] +.sym 13338 lvds_rx_24_inst.r_data[7] +.sym 13341 w_rx_24_fifo_empty +.sym 13343 smi_ctrl_ins.r_fifo_24_pull +.sym 13344 smi_ctrl_ins.r_fifo_24_pull_1 +.sym 13357 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 13358 lvds_clock_$glb_clk +.sym 13359 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 13360 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13361 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E .sym 13362 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 13363 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 13382 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 13387 w_fetch -.sym 13388 $PACKER_VCC_NET -.sym 13394 spi_if_ins.r_tx_byte[3] -.sym 13403 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 13404 w_fetch -.sym 13412 r_tx_data[5] -.sym 13413 r_tx_data[7] -.sym 13414 r_tx_data[1] -.sym 13415 r_tx_data[2] -.sym 13416 r_tx_data[4] -.sym 13428 w_load -.sym 13429 w_cs[1] -.sym 13442 r_tx_data[7] -.sym 13446 r_tx_data[4] -.sym 13452 w_fetch -.sym 13454 w_cs[1] -.sym 13455 w_load -.sym 13458 r_tx_data[1] -.sym 13471 r_tx_data[2] -.sym 13479 r_tx_data[5] -.sym 13480 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 13481 r_counter_$glb_clk -.sym 13483 spi_if_ins.r_tx_byte[0] -.sym 13486 spi_if_ins.r_tx_byte[3] -.sym 13490 spi_if_ins.r_tx_byte[6] -.sym 13498 spi_if_ins.w_rx_data[1] -.sym 13510 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 13524 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 13526 w_tx_data_io[5] -.sym 13528 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 13530 w_tx_data_io[6] -.sym 13534 w_tx_data_io[3] -.sym 13535 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 13539 w_tx_data_io[4] -.sym 13541 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13543 w_tx_data_io[2] -.sym 13549 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 13550 w_tx_data_io[1] -.sym 13551 w_tx_data_io[7] -.sym 13553 w_tx_data_smi[1] -.sym 13565 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13566 w_tx_data_io[6] -.sym 13570 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13572 w_tx_data_io[3] -.sym 13576 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 13577 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13578 w_tx_data_io[5] -.sym 13581 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 13583 w_tx_data_io[7] -.sym 13584 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13587 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13588 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 13589 w_tx_data_io[1] -.sym 13590 w_tx_data_smi[1] -.sym 13594 w_tx_data_io[2] -.sym 13595 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 13596 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13599 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 13602 w_tx_data_io[4] -.sym 13603 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 13604 i_glob_clock$SB_IO_IN_$glb_clk -.sym 13605 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 13610 io_ctrl_ins.debug_mode[0] -.sym 13611 io_ctrl_ins.rf_mode[2] -.sym 13613 io_ctrl_ins.rf_mode[1] -.sym 13618 w_rx_data[6] -.sym 13622 w_tx_data_io[5] -.sym 13626 w_tx_data_io[6] -.sym 13633 io_ctrl_ins.debug_mode[1] -.sym 13637 o_rx_h_tx_l_b$SB_IO_OUT -.sym 13647 w_soft_reset -.sym 13650 w_ioc[2] -.sym 13652 w_ioc[3] -.sym 13655 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 13656 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 13659 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 13665 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 13670 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 13673 w_tx_data_sys[0] -.sym 13678 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 13686 w_ioc[2] -.sym 13688 w_ioc[3] -.sym 13692 w_soft_reset -.sym 13693 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 13695 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 13698 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 13699 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 13700 w_tx_data_sys[0] -.sym 13701 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 13726 spi_if_ins.o_cs_SB_LUT4_I1_1_O -.sym 13727 i_glob_clock$SB_IO_IN_$glb_clk -.sym 13729 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 13730 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 13731 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O -.sym 13732 i_button_SB_LUT4_I1_O[1] -.sym 13733 io_ctrl_ins.pmod_dir_state[6] -.sym 13734 io_ctrl_ins.pmod_dir_state[7] -.sym 13736 i_button_SB_LUT4_I1_O[0] -.sym 13748 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 13751 w_rx_data[2] -.sym 13753 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 13757 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 13759 io_ctrl_ins.rf_mode[2] -.sym 13760 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 13761 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 13762 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 13763 io_ctrl_ins.rf_mode[1] -.sym 13771 w_rx_data[2] -.sym 13772 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O -.sym 13776 io_ctrl_ins.o_pmod[5] -.sym 13779 spi_if_ins.o_ioc_SB_LUT4_I2_O[2] -.sym 13780 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 13781 w_rx_data[1] -.sym 13788 w_ioc[0] -.sym 13790 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 13793 w_ioc[4] -.sym 13794 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 13796 w_ioc[0] -.sym 13799 io_ctrl_ins.pmod_dir_state[5] -.sym 13800 w_ioc[1] -.sym 13801 w_ioc[4] -.sym 13803 w_ioc[4] +.sym 13364 w_rx_24_fifo_data[15] +.sym 13365 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 13366 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 13368 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 13372 rx_24_fifo.rd_addr[0] +.sym 13373 w_rx_09_fifo_pulled_data[11] +.sym 13374 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 13376 smi_ctrl_ins.r_fifo_24_pull +.sym 13380 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 13381 smi_ctrl_ins.r_fifo_09_pull +.sym 13384 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 13385 spi_if_ins.w_rx_data[2] +.sym 13387 spi_if_ins.w_rx_data[3] +.sym 13389 lvds_rx_24_inst.r_data[9] +.sym 13391 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13392 lvds_rx_24_inst.o_debug_state[0] +.sym 13393 spi_if_ins.w_rx_data[6] +.sym 13395 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13401 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] +.sym 13403 rx_24_fifo.wr_addr[8] +.sym 13404 rx_24_fifo.wr_addr[2] +.sym 13406 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 13409 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[8] +.sym 13410 lvds_rx_24_inst.r_data[10] +.sym 13411 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[10] +.sym 13413 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 13414 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 13415 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] +.sym 13417 lvds_rx_24_inst.r_data[17] +.sym 13418 lvds_rx_24_inst.o_debug_state[0] +.sym 13419 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[2] +.sym 13422 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13426 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[1] +.sym 13428 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] +.sym 13430 lvds_rx_24_inst.r_data[14] +.sym 13432 lvds_rx_24_inst.r_data[12] +.sym 13434 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[1] +.sym 13435 rx_24_fifo.wr_addr[2] +.sym 13436 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[2] +.sym 13437 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 13442 lvds_rx_24_inst.o_debug_state[0] +.sym 13443 lvds_rx_24_inst.r_data[14] +.sym 13447 lvds_rx_24_inst.o_debug_state[0] +.sym 13448 lvds_rx_24_inst.r_data[17] +.sym 13452 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[8] +.sym 13453 rx_24_fifo.wr_addr[8] +.sym 13454 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[10] +.sym 13455 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 13459 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13460 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 13464 lvds_rx_24_inst.o_debug_state[0] +.sym 13465 lvds_rx_24_inst.r_data[12] +.sym 13470 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] +.sym 13471 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 13472 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] +.sym 13473 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] +.sym 13476 lvds_rx_24_inst.o_debug_state[0] +.sym 13477 lvds_rx_24_inst.r_data[10] +.sym 13480 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 13481 lvds_clock_$glb_clk +.sym 13482 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 13483 w_cs[3] +.sym 13484 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 13488 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E +.sym 13497 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 13501 lvds_rx_24_inst.r_data[19] +.sym 13502 rx_24_fifo.wr_addr[2] +.sym 13504 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 13505 lvds_rx_24_inst.r_data[7] +.sym 13510 rx_24_fifo.rd_addr[1] +.sym 13511 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 13512 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 13518 rx_24_fifo.rd_addr[8] +.sym 13532 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13537 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 13542 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 13552 w_cs[0] +.sym 13582 w_cs[0] +.sym 13594 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 13603 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E +.sym 13604 r_counter_$glb_clk +.sym 13605 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 13606 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 13607 w_rx_data[1] +.sym 13608 w_rx_data[3] +.sym 13609 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] +.sym 13610 w_rx_data[4] +.sym 13611 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 13612 w_rx_data[6] +.sym 13613 w_rx_data[7] +.sym 13614 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 13615 r_tx_data[7] +.sym 13619 lvds_rx_24_inst.r_data[18] +.sym 13620 spi_if_ins.w_rx_data[5] +.sym 13621 $PACKER_VCC_NET +.sym 13623 smi_ctrl_ins.int_cnt_24[4] +.sym 13627 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 13628 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 13629 smi_ctrl_ins.int_cnt_24[3] +.sym 13630 i_smi_a3$SB_IO_IN +.sym 13635 i_config_SB_LUT4_I0_I1[2] +.sym 13637 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 13638 w_cs[0] +.sym 13641 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13649 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 13651 i_config_SB_LUT4_I0_I1[2] +.sym 13653 w_load +.sym 13657 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 13658 spi_if_ins.w_rx_data[5] +.sym 13663 spi_if_ins.w_rx_data[6] +.sym 13664 w_fetch +.sym 13665 w_cs[0] +.sym 13668 w_cs[1] +.sym 13670 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 13671 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 13672 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13678 rx_24_fifo.rd_addr[8] +.sym 13686 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 13687 w_load +.sym 13688 w_fetch +.sym 13689 w_cs[0] +.sym 13699 spi_if_ins.w_rx_data[6] +.sym 13701 spi_if_ins.w_rx_data[5] +.sym 13704 i_config_SB_LUT4_I0_I1[2] +.sym 13710 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 13711 w_cs[0] +.sym 13712 w_fetch +.sym 13716 rx_24_fifo.rd_addr[8] +.sym 13717 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 13722 w_fetch +.sym 13724 w_cs[1] +.sym 13725 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13726 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 13727 r_counter_$glb_clk +.sym 13729 w_ioc[1] +.sym 13730 w_ioc[0] +.sym 13731 w_cs[0] +.sym 13732 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O +.sym 13733 w_ioc[3] +.sym 13734 w_ioc[2] +.sym 13739 i_smi_a2_SB_LUT4_I1_O[1] +.sym 13742 w_rx_data[6] +.sym 13743 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E +.sym 13746 w_rx_data[7] +.sym 13748 rx_24_fifo.wr_addr[7] +.sym 13750 w_rx_data[1] +.sym 13751 w_tx_data_sys[0] +.sym 13752 w_rx_data[3] +.sym 13754 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 13756 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 13760 w_rx_24_fifo_data[11] +.sym 13761 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 13762 w_rx_24_fifo_data[6] +.sym 13763 w_rx_data[7] +.sym 13764 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 13775 spi_if_ins.w_rx_data[4] +.sym 13776 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 13780 rx_24_fifo.rd_addr[1] +.sym 13781 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 13783 w_ioc[4] +.sym 13785 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 13787 w_ioc[0] +.sym 13789 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 13791 w_ioc[2] +.sym 13794 w_ioc[1] +.sym 13795 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 13796 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 13797 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 13798 w_ioc[3] +.sym 13803 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] .sym 13804 w_ioc[1] -.sym 13805 spi_if_ins.o_ioc_SB_LUT4_I2_O[2] -.sym 13806 w_ioc[0] -.sym 13809 w_ioc[4] -.sym 13810 spi_if_ins.o_ioc_SB_LUT4_I2_O[2] +.sym 13805 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 13806 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 13809 w_ioc[0] +.sym 13810 w_ioc[4] .sym 13811 w_ioc[1] -.sym 13812 w_ioc[0] -.sym 13816 w_ioc[0] -.sym 13817 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 13818 w_ioc[1] -.sym 13821 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 13822 io_ctrl_ins.o_pmod[5] -.sym 13823 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 13824 io_ctrl_ins.pmod_dir_state[5] -.sym 13827 w_ioc[0] -.sym 13828 w_ioc[1] -.sym 13829 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 13833 w_rx_data[2] -.sym 13840 w_ioc[1] -.sym 13841 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 13842 w_ioc[0] -.sym 13846 w_rx_data[1] -.sym 13849 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O +.sym 13815 w_ioc[4] +.sym 13816 w_ioc[2] +.sym 13818 w_ioc[3] +.sym 13828 w_ioc[3] +.sym 13830 w_ioc[2] +.sym 13835 spi_if_ins.w_rx_data[4] +.sym 13839 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 13840 rx_24_fifo.rd_addr[1] +.sym 13841 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 13842 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 13849 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] .sym 13850 r_counter_$glb_clk -.sym 13851 w_soft_reset_$glb_sr -.sym 13852 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[2] -.sym 13853 io_ctrl_ins.pmod_dir_state[3] -.sym 13854 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[2] -.sym 13855 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O -.sym 13856 io_ctrl_ins.pmod_dir_state[1] -.sym 13857 io_ctrl_ins.pmod_dir_state[5] -.sym 13858 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 13859 io_ctrl_ins.pmod_dir_state[4] -.sym 13866 w_soft_reset -.sym 13868 o_rx_h_tx_l$SB_IO_OUT -.sym 13873 o_led1$SB_IO_OUT -.sym 13880 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 13886 w_rx_data[2] -.sym 13887 w_rx_data[1] -.sym 13893 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 13894 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 13895 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O -.sym 13896 w_rx_data[6] -.sym 13897 w_rx_data[1] -.sym 13898 w_ioc[1] -.sym 13900 io_ctrl_ins.debug_mode[1] -.sym 13901 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 13902 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 13903 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 13904 io_ctrl_ins.mixer_en_state -.sym 13905 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 13906 w_rx_data[0] -.sym 13911 io_ctrl_ins.o_pmod[1] -.sym 13923 io_ctrl_ins.debug_mode[0] -.sym 13926 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 13927 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 13928 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 13929 w_ioc[1] -.sym 13932 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 13934 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 13938 w_rx_data[1] -.sym 13944 w_rx_data[6] -.sym 13950 w_rx_data[0] -.sym 13956 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 13957 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 13958 io_ctrl_ins.debug_mode[1] -.sym 13959 io_ctrl_ins.o_pmod[1] -.sym 13968 io_ctrl_ins.debug_mode[0] -.sym 13969 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 13970 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 13971 io_ctrl_ins.mixer_en_state -.sym 13972 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O -.sym 13973 r_counter_$glb_clk -.sym 13977 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 13978 io_ctrl_ins.rf_pin_state[2] -.sym 13980 io_ctrl_ins.rf_pin_state[1] -.sym 13981 io_ctrl_ins.rf_pin_state[0] -.sym 13982 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 13990 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O -.sym 13993 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 14022 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 14027 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 14030 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 14031 io_ctrl_ins.rf_mode[2] -.sym 14035 io_ctrl_ins.rf_mode[1] -.sym 14037 io_ctrl_ins.rf_pin_state[1] -.sym 14043 io_ctrl_ins.rf_pin_state[2] -.sym 14046 io_ctrl_ins.rf_pin_state[0] -.sym 14061 io_ctrl_ins.rf_pin_state[2] -.sym 14062 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 14063 io_ctrl_ins.rf_mode[2] -.sym 14064 io_ctrl_ins.rf_mode[1] -.sym 14067 io_ctrl_ins.rf_mode[1] -.sym 14068 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 14069 io_ctrl_ins.rf_pin_state[0] -.sym 14070 io_ctrl_ins.rf_mode[2] -.sym 14079 io_ctrl_ins.rf_mode[1] -.sym 14080 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 14081 io_ctrl_ins.rf_pin_state[1] -.sym 14095 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 13852 io_ctrl_ins.o_pmod[2] +.sym 13853 io_ctrl_ins.o_pmod[3] +.sym 13854 i_config_SB_LUT4_I0_I1[2] +.sym 13855 io_ctrl_ins.o_pmod[7] +.sym 13856 io_ctrl_ins.o_pmod[6] +.sym 13857 io_ctrl_ins.o_pmod[4] +.sym 13858 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 13859 i_config_SB_LUT4_I0_I1[0] +.sym 13865 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 13866 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 13868 spi_if_ins.w_rx_data[1] +.sym 13869 rx_24_fifo.wr_addr[5] +.sym 13870 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 13872 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 13873 spi_if_ins.w_rx_data[3] +.sym 13874 spi_if_ins.w_rx_data[0] +.sym 13875 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 13876 w_rx_data[2] +.sym 13877 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 13878 spi_if_ins.w_rx_data[2] +.sym 13880 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 13882 lvds_rx_24_inst.r_data[9] +.sym 13883 w_tx_data_io[2] +.sym 13893 w_ioc[1] +.sym 13894 w_ioc[0] +.sym 13897 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0[2] +.sym 13898 w_ioc[4] +.sym 13901 lvds_rx_24_inst.r_data[2] +.sym 13902 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3[1] +.sym 13905 w_ioc[3] +.sym 13906 w_ioc[2] +.sym 13908 lvds_rx_24_inst.r_data[9] +.sym 13913 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 13918 lvds_rx_24_inst.r_data[4] +.sym 13927 lvds_rx_24_inst.r_data[2] +.sym 13933 lvds_rx_24_inst.r_data[9] +.sym 13938 lvds_rx_24_inst.r_data[4] +.sym 13945 w_ioc[2] +.sym 13946 w_ioc[3] +.sym 13947 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3[1] +.sym 13950 w_ioc[1] +.sym 13951 w_ioc[0] +.sym 13962 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0[2] +.sym 13964 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3[1] +.sym 13968 w_ioc[4] +.sym 13969 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 13971 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0[2] +.sym 13972 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 13973 lvds_clock_$glb_clk +.sym 13975 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 13976 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 13977 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] +.sym 13978 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 13979 io_ctrl_ins.pmod_dir_state[6] +.sym 13980 io_ctrl_ins.pmod_dir_state[7] +.sym 13981 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] +.sym 13982 io_ctrl_ins.pmod_dir_state[4] +.sym 13987 lvds_rx_24_inst.r_data[2] +.sym 13995 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 13996 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 13997 rx_24_fifo.wr_addr[4] +.sym 14001 io_ctrl_ins.o_pmod[7] +.sym 14002 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 14005 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 14007 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E +.sym 14010 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 14018 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E +.sym 14019 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 14020 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 14022 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 14024 io_ctrl_ins.o_pmod[2] +.sym 14026 i_config_SB_LUT4_I0_I1[2] +.sym 14027 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 14030 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 14031 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 14035 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] +.sym 14036 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[2] +.sym 14037 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 14038 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] +.sym 14042 o_shdn_tx_lna$SB_IO_OUT +.sym 14044 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[2] +.sym 14047 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] +.sym 14049 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 14050 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[2] +.sym 14051 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 14052 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 14055 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] +.sym 14056 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] +.sym 14057 i_config_SB_LUT4_I0_I1[2] +.sym 14058 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] +.sym 14067 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 14069 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 14073 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 14074 i_config_SB_LUT4_I0_I1[2] +.sym 14075 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 14076 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 14085 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 14086 io_ctrl_ins.o_pmod[2] +.sym 14087 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 14088 o_shdn_tx_lna$SB_IO_OUT +.sym 14095 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E .sym 14096 r_counter_$glb_clk -.sym 14114 io_ctrl_ins.rf_mode[0] -.sym 14116 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 14121 i_config[0]$SB_IO_IN -.sym 14227 r_counter +.sym 14097 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[2] +.sym 14098 o_rx_h_tx_l_b$SB_IO_OUT +.sym 14099 i_button_SB_LUT4_I0_O[0] +.sym 14100 o_shdn_tx_lna$SB_IO_OUT +.sym 14101 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 14102 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 14103 o_shdn_rx_lna$SB_IO_OUT +.sym 14105 o_rx_h_tx_l$SB_IO_OUT +.sym 14112 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E +.sym 14113 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 14117 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 14121 lvds_rx_24_inst.o_debug_state[0] +.sym 14122 i_smi_a3$SB_IO_IN +.sym 14128 lvds_rx_24_inst.o_debug_state[1] +.sym 14140 w_rx_data[1] +.sym 14142 w_rx_data[7] +.sym 14148 w_rx_data[2] +.sym 14154 w_rx_data[6] +.sym 14166 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 14181 w_rx_data[6] +.sym 14192 w_rx_data[7] +.sym 14196 w_rx_data[2] +.sym 14209 w_rx_data[1] +.sym 14218 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 14219 r_counter_$glb_clk +.sym 14229 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 14232 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 14244 o_shdn_tx_lna$SB_IO_OUT +.sym 14288 lvds_rx_24_inst.o_debug_state[1] +.sym 14292 i_smi_a2_SB_LUT4_I1_O[1] +.sym 14293 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 14332 i_smi_a2_SB_LUT4_I1_O[1] +.sym 14333 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 14334 lvds_rx_24_inst.o_debug_state[1] .sym 14344 i_smi_a1$SB_IO_IN -.sym 14388 lvds_clock -.sym 14410 lvds_clock -.sym 14418 smi_ctrl_ins.soe_and_reset +.sym 14388 i_smi_a2_SB_LUT4_I1_O[1] +.sym 14403 i_smi_a2_SB_LUT4_I1_O[1] +.sym 14418 i_sck$SB_IO_IN .sym 14419 w_smi_data_output[3] .sym 14421 i_smi_a3$SB_IO_IN -.sym 14431 i_smi_a3$SB_IO_IN -.sym 14433 smi_ctrl_ins.soe_and_reset +.sym 14436 i_smi_a3$SB_IO_IN +.sym 14440 i_sck$SB_IO_IN .sym 14441 w_smi_data_output[3] -.sym 14445 lvds_rx_09_inst.r_data[31] -.sym 14446 lvds_rx_09_inst.r_data[28] -.sym 14447 lvds_rx_09_inst.r_data[30] -.sym 14448 lvds_rx_09_inst.r_data[26] -.sym 14451 lvds_rx_09_inst.r_data[29] -.sym 14466 w_lvds_rx_09_d0 -.sym 14474 i_smi_a1$SB_IO_IN +.sym 14445 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] +.sym 14447 smi_ctrl_ins.soe_and_reset +.sym 14463 smi_ctrl_ins.w_fifo_09_pull_trigger .sym 14476 i_smi_a3$SB_IO_IN -.sym 14488 w_soft_reset -.sym 14495 i_smi_soe_se$SB_IO_IN -.sym 14550 i_smi_soe_se$SB_IO_IN -.sym 14552 w_soft_reset -.sym 14573 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_5_O[3] -.sym 14576 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_7_O[3] -.sym 14577 w_smi_data_output[6] -.sym 14578 w_smi_data_output[7] -.sym 14588 rx_09_fifo.rd_addr[5] -.sym 14589 rx_09_fifo.rd_addr[4] +.sym 14495 lvds_rx_09_inst.r_data[12] +.sym 14501 lvds_rx_09_inst.r_data[11] +.sym 14540 lvds_rx_09_inst.r_data[11] +.sym 14557 lvds_rx_09_inst.r_data[12] +.sym 14565 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 14566 lvds_clock_$glb_clk +.sym 14574 lvds_rx_24_inst.r_data[15] +.sym 14578 lvds_rx_24_inst.r_data[13] +.sym 14586 w_rx_09_fifo_pulled_data[5] +.sym 14587 rx_09_fifo.wr_addr[7] +.sym 14588 i_smi_a2_SB_LUT4_I1_O[1] +.sym 14591 w_rx_09_fifo_pulled_data[4] +.sym 14593 lvds_rx_09_inst.r_data[11] +.sym 14595 lvds_rx_09_inst.r_data[12] .sym 14597 i_smi_soe_se$SB_IO_IN -.sym 14614 w_smi_data_output[7] -.sym 14617 lvds_rx_09_inst.r_data[27] -.sym 14621 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 14628 smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_E -.sym 14641 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O -.sym 14659 w_rx_09_fifo_pulled_data[23] -.sym 14664 w_rx_09_fifo_pulled_data[22] -.sym 14669 smi_ctrl_ins.int_cnt_09[3] -.sym 14671 w_rx_09_fifo_pulled_data[30] -.sym 14672 smi_ctrl_ins.int_cnt_09[4] -.sym 14677 smi_ctrl_ins.int_cnt_09[3] -.sym 14678 w_rx_09_fifo_pulled_data[31] -.sym 14682 w_rx_09_fifo_pulled_data[31] -.sym 14683 w_rx_09_fifo_pulled_data[23] -.sym 14684 smi_ctrl_ins.int_cnt_09[3] -.sym 14685 smi_ctrl_ins.int_cnt_09[4] -.sym 14700 smi_ctrl_ins.int_cnt_09[3] -.sym 14701 w_rx_09_fifo_pulled_data[30] -.sym 14702 smi_ctrl_ins.int_cnt_09[4] -.sym 14703 w_rx_09_fifo_pulled_data[22] -.sym 14731 i_smi_a1_SB_LUT4_I1_O -.sym 14735 smi_ctrl_ins.int_cnt_09[3] -.sym 14738 smi_ctrl_ins.int_cnt_09[4] -.sym 14749 w_rx_09_fifo_pulled_data[20] -.sym 14755 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 14757 w_rx_09_fifo_pulled_data[16] -.sym 14761 w_smi_data_output[6] -.sym 14776 w_soft_reset -.sym 14777 smi_ctrl_ins.w_fifo_09_pull_trigger -.sym 14785 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 14789 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 14793 w_rx_09_fifo_empty -.sym 14812 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 14823 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 14824 w_soft_reset -.sym 14825 w_rx_09_fifo_empty -.sym 14826 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 14835 smi_ctrl_ins.w_fifo_09_pull_trigger +.sym 14606 w_rx_09_fifo_pulled_data[23] +.sym 14611 smi_ctrl_ins.soe_and_reset +.sym 14622 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E +.sym 14629 rx_09_fifo.rd_addr[5] +.sym 14634 w_smi_data_output[7] +.sym 14640 smi_ctrl_ins.soe_and_reset +.sym 14651 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 14676 rx_09_fifo.rd_addr[0] +.sym 14701 rx_09_fifo.rd_addr[0] +.sym 14728 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 14729 r_counter_$glb_clk +.sym 14730 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 14733 sys_ctrl_ins.reset_count[2] +.sym 14734 sys_ctrl_ins.reset_count[3] +.sym 14735 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E +.sym 14736 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 14737 sys_ctrl_ins.reset_count[1] +.sym 14738 sys_ctrl_ins.reset_count[0] +.sym 14744 rx_09_fifo.rd_addr[6] +.sym 14745 lvds_rx_24_inst.o_debug_state[0] +.sym 14746 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 14747 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 14749 rx_09_fifo.rd_addr[6] +.sym 14750 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 14751 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 14752 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 14753 $PACKER_VCC_NET +.sym 14754 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 14757 w_rx_09_fifo_empty +.sym 14758 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] +.sym 14760 smi_ctrl_ins.int_cnt_09[4] +.sym 14762 i_smi_a1_SB_LUT4_I1_O +.sym 14763 lvds_rx_24_inst.r_data[13] +.sym 14765 rx_09_fifo.rd_addr[1] +.sym 14773 rx_09_fifo.rd_addr[1] +.sym 14783 rx_09_fifo.rd_addr[0] +.sym 14790 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 14792 rx_09_fifo.rd_addr[4] +.sym 14795 rx_09_fifo.rd_addr[5] +.sym 14799 rx_09_fifo.rd_addr_SB_DFFESR_Q_E +.sym 14800 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 14801 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 14802 rx_09_fifo.rd_addr[6] +.sym 14804 $nextpnr_ICESTORM_LC_4$O +.sym 14807 rx_09_fifo.rd_addr[0] +.sym 14810 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[2] +.sym 14813 rx_09_fifo.rd_addr[1] +.sym 14814 rx_09_fifo.rd_addr[0] +.sym 14816 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[3] +.sym 14819 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 14820 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[2] +.sym 14822 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[4] +.sym 14825 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 14826 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[3] +.sym 14828 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[5] +.sym 14831 rx_09_fifo.rd_addr[4] +.sym 14832 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[4] +.sym 14834 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[6] +.sym 14837 rx_09_fifo.rd_addr[5] +.sym 14838 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[5] +.sym 14840 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[7] +.sym 14842 rx_09_fifo.rd_addr[6] +.sym 14844 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[6] +.sym 14846 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[8] +.sym 14848 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 14850 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[7] +.sym 14851 rx_09_fifo.rd_addr_SB_DFFESR_Q_E .sym 14852 r_counter_$glb_clk -.sym 14853 w_soft_reset_$glb_sr -.sym 14855 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 14859 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 14860 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3 -.sym 14868 i_smi_a1$SB_IO_IN -.sym 14869 i_smi_a3$SB_IO_IN -.sym 14870 w_rx_09_fifo_data[24] -.sym 14874 i_smi_a3$SB_IO_IN -.sym 14888 smi_ctrl_ins.int_cnt_09[4] -.sym 14889 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 14897 w_soft_reset -.sym 14899 smi_ctrl_ins.int_cnt_09[3] -.sym 14900 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 14902 smi_ctrl_ins.int_cnt_09[4] -.sym 14904 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 14905 w_soft_reset -.sym 14906 smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_E -.sym 14907 smi_ctrl_ins.int_cnt_09[3] -.sym 14908 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 14909 i_smi_a2$SB_IO_IN -.sym 14910 w_rx_09_fifo_pulled_data[24] -.sym 14914 i_smi_a1$SB_IO_IN -.sym 14917 w_rx_09_fifo_pulled_data[16] -.sym 14920 i_smi_a3$SB_IO_IN -.sym 14921 w_rx_09_fifo_empty -.sym 14922 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 14934 w_rx_09_fifo_empty -.sym 14935 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 14936 w_soft_reset -.sym 14937 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 14946 i_smi_a1$SB_IO_IN -.sym 14947 i_smi_a3$SB_IO_IN -.sym 14948 i_smi_a2$SB_IO_IN -.sym 14949 w_soft_reset -.sym 14952 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 14953 w_rx_09_fifo_empty -.sym 14954 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 14955 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 14958 smi_ctrl_ins.int_cnt_09[4] -.sym 14959 smi_ctrl_ins.int_cnt_09[3] -.sym 14960 w_rx_09_fifo_empty -.sym 14967 w_soft_reset -.sym 14970 smi_ctrl_ins.int_cnt_09[4] -.sym 14971 w_rx_09_fifo_pulled_data[16] -.sym 14972 smi_ctrl_ins.int_cnt_09[3] -.sym 14973 w_rx_09_fifo_pulled_data[24] -.sym 14974 smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_E -.sym 14975 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 14978 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] -.sym 14979 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] -.sym 14980 lvds_rx_09_inst.r_phase_count[0] -.sym 14981 w_rx_09_fifo_data[27] -.sym 14982 lvds_rx_09_inst.r_phase_count[1] -.sym 14993 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 14997 rx_09_fifo.wr_addr[7] -.sym 15002 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15009 lvds_rx_09_inst.r_data[27] -.sym 15012 i_ss$SB_IO_IN -.sym 15018 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E -.sym 15024 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 15027 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 15029 w_rx_09_fifo_pulled_data[0] -.sym 15031 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 15032 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3 -.sym 15033 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_15_O[3] -.sym 15036 i_smi_a1_SB_LUT4_I1_O -.sym 15039 w_lvds_rx_09_d0 -.sym 15042 w_rx_09_fifo_pulled_data[8] -.sym 15044 w_lvds_rx_09_d1 -.sym 15048 smi_ctrl_ins.int_cnt_09[4] -.sym 15049 lvds_rx_09_inst.o_debug_state[1] -.sym 15051 lvds_rx_09_inst.o_debug_state[1] -.sym 15052 w_lvds_rx_09_d1 -.sym 15053 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 15054 w_lvds_rx_09_d0 -.sym 15070 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E -.sym 15081 w_rx_09_fifo_pulled_data[8] -.sym 15082 w_rx_09_fifo_pulled_data[0] -.sym 15083 smi_ctrl_ins.int_cnt_09[4] -.sym 15084 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_15_O[3] -.sym 15094 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 15095 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3 -.sym 15096 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 15097 i_smi_a1_SB_LUT4_I1_O -.sym 15098 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 15101 int_miso -.sym 15104 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 14853 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 14857 w_smi_data_output[7] +.sym 14859 spi_if_ins.spi.r_tx_bit_count[2] +.sym 14869 rx_09_fifo.wr_addr[5] +.sym 14870 rx_09_fifo.rd_addr[1] +.sym 14872 rx_09_fifo.wr_addr[9] +.sym 14873 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 14875 rx_09_fifo.rd_addr[9] +.sym 14876 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 14877 rx_09_fifo.wr_addr[4] +.sym 14878 rx_09_fifo.rd_addr[4] +.sym 14879 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 14880 spi_if_ins.r_tx_byte[1] +.sym 14881 spi_if_ins.r_tx_byte[6] +.sym 14883 lvds_rx_24_inst.r_data[11] +.sym 14884 spi_if_ins.r_tx_byte[4] +.sym 14885 spi_if_ins.r_tx_byte[3] +.sym 14886 i_smi_a2_SB_LUT4_I1_O[0] +.sym 14888 smi_ctrl_ins.soe_and_reset +.sym 14889 spi_if_ins.r_tx_byte[5] +.sym 14890 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[8] +.sym 14895 smi_ctrl_ins.soe_and_reset +.sym 14897 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 14901 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[6] +.sym 14902 w_rx_24_fifo_empty +.sym 14905 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[10] +.sym 14907 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[4] +.sym 14908 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[5] +.sym 14910 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[7] +.sym 14911 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[8] +.sym 14912 rx_09_fifo.wr_addr[5] +.sym 14913 rx_09_fifo.wr_addr[8] +.sym 14916 rx_09_fifo.wr_addr[7] +.sym 14917 w_rx_09_fifo_empty +.sym 14919 rx_09_fifo.wr_addr[4] +.sym 14920 smi_ctrl_ins.int_cnt_09[4] +.sym 14921 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 14923 rx_09_fifo.wr_addr[6] +.sym 14924 rx_09_fifo.rd_addr[9] +.sym 14925 smi_ctrl_ins.int_cnt_09[3] +.sym 14926 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 14927 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[9] +.sym 14929 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 14931 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[8] +.sym 14933 $nextpnr_ICESTORM_LC_5$I3 +.sym 14935 rx_09_fifo.rd_addr[9] +.sym 14937 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[9] +.sym 14943 $nextpnr_ICESTORM_LC_5$I3 +.sym 14946 rx_09_fifo.wr_addr[4] +.sym 14947 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[8] +.sym 14948 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[4] +.sym 14949 rx_09_fifo.wr_addr[8] +.sym 14952 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[5] +.sym 14953 rx_09_fifo.wr_addr[5] +.sym 14954 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 14955 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[10] +.sym 14958 w_rx_24_fifo_empty +.sym 14961 w_rx_09_fifo_empty +.sym 14964 w_rx_09_fifo_empty +.sym 14966 smi_ctrl_ins.int_cnt_09[4] +.sym 14967 smi_ctrl_ins.int_cnt_09[3] +.sym 14970 rx_09_fifo.wr_addr[7] +.sym 14971 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[6] +.sym 14972 rx_09_fifo.wr_addr[6] +.sym 14973 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[7] +.sym 14974 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E +.sym 14975 smi_ctrl_ins.soe_and_reset +.sym 14978 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 14979 spi_if_ins.r_tx_data_valid +.sym 14980 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 14982 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 14983 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 14984 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 14990 rx_09_fifo.rd_addr[1] +.sym 14993 w_rx_09_fifo_data[23] +.sym 14995 w_rx_09_fifo_data[22] +.sym 15003 i_ss$SB_IO_IN +.sym 15005 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 15008 w_smi_read_req +.sym 15009 i_smi_a2$SB_IO_IN +.sym 15011 spi_if_ins.r_tx_byte[2] +.sym 15019 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 15020 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 15023 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15027 rx_09_fifo.wr_addr[5] +.sym 15029 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15030 spi_if_ins.spi.r_tx_byte[1] +.sym 15031 spi_if_ins.spi.r_tx_byte[5] +.sym 15033 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 15034 rx_09_fifo.rd_addr[5] +.sym 15039 spi_if_ins.r_tx_byte[7] +.sym 15040 spi_if_ins.r_tx_byte[1] +.sym 15041 rx_09_fifo.rd_addr[9] +.sym 15042 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 15044 rx_09_fifo.wr_addr[9] +.sym 15045 spi_if_ins.r_tx_byte[3] +.sym 15047 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15049 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15051 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 15052 spi_if_ins.spi.r_tx_bit_count[2] +.sym 15053 spi_if_ins.spi.r_tx_byte[5] +.sym 15054 spi_if_ins.spi.r_tx_byte[1] +.sym 15057 rx_09_fifo.rd_addr[9] +.sym 15058 rx_09_fifo.wr_addr[5] +.sym 15059 rx_09_fifo.wr_addr[9] +.sym 15060 rx_09_fifo.rd_addr[5] +.sym 15065 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15069 spi_if_ins.r_tx_byte[7] +.sym 15077 spi_if_ins.r_tx_byte[1] +.sym 15089 spi_if_ins.r_tx_byte[3] +.sym 15093 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 15094 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 15095 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 15096 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 15097 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15098 r_counter_$glb_clk +.sym 15099 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15100 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 15101 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 15102 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 15103 i_ss_SB_LUT4_I3_O +.sym 15104 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 15105 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 15107 spi_if_ins.spi.r_temp_rx_byte[1] .sym 15111 i_smi_a1$SB_IO_IN -.sym 15114 rx_09_fifo.wr_addr[9] -.sym 15115 w_rx_09_fifo_pulled_data[0] -.sym 15128 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15135 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 15152 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E -.sym 15161 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15164 spi_if_ins.r_tx_data_valid -.sym 15169 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 15172 i_ss$SB_IO_IN -.sym 15210 i_ss$SB_IO_IN -.sym 15211 spi_if_ins.r_tx_data_valid -.sym 15216 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 15220 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 15117 rx_09_fifo.rd_addr[0] +.sym 15118 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 15125 spi_if_ins.r_tx_byte[7] +.sym 15127 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 15129 w_tx_data_smi[0] +.sym 15130 w_rx_09_fifo_full +.sym 15131 rx_09_fifo.rd_addr[9] +.sym 15132 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15133 spi_if_ins.r_tx_byte[0] +.sym 15143 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15144 spi_if_ins.r_tx_byte[0] +.sym 15148 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15151 spi_if_ins.r_tx_byte[6] +.sym 15154 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15156 spi_if_ins.r_tx_byte[4] +.sym 15159 spi_if_ins.r_tx_byte[5] +.sym 15161 i_smi_a3$SB_IO_IN +.sym 15169 i_smi_a2$SB_IO_IN +.sym 15171 spi_if_ins.r_tx_byte[2] +.sym 15172 i_smi_a1$SB_IO_IN +.sym 15183 spi_if_ins.r_tx_byte[4] +.sym 15186 i_smi_a3$SB_IO_IN +.sym 15187 i_smi_a2$SB_IO_IN +.sym 15188 i_smi_a1$SB_IO_IN +.sym 15189 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15194 spi_if_ins.r_tx_byte[2] +.sym 15198 i_smi_a1$SB_IO_IN +.sym 15200 i_smi_a3$SB_IO_IN +.sym 15201 i_smi_a2$SB_IO_IN +.sym 15207 spi_if_ins.r_tx_byte[5] +.sym 15213 spi_if_ins.r_tx_byte[6] +.sym 15218 spi_if_ins.r_tx_byte[0] +.sym 15220 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E .sym 15221 r_counter_$glb_clk -.sym 15222 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15225 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15226 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 15227 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15228 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 15229 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 15230 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 15235 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 15238 spi_if_ins.r_tx_byte[7] -.sym 15241 w_rx_09_fifo_data[11] -.sym 15244 int_miso -.sym 15256 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15258 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 15264 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 15267 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 15270 spi_if_ins.spi.r_tx_byte[1] -.sym 15275 spi_if_ins.r_tx_byte[3] -.sym 15277 spi_if_ins.spi.r_tx_byte[3] -.sym 15278 spi_if_ins.spi.r_tx_byte[7] -.sym 15280 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] -.sym 15281 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 15282 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15283 spi_if_ins.r_tx_byte[7] -.sym 15284 spi_if_ins.spi.r_tx_byte[5] -.sym 15286 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 15287 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 15290 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15291 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 15293 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15295 spi_if_ins.r_tx_byte[5] -.sym 15297 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 15298 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 15299 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 15300 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 15304 spi_if_ins.spi.r_tx_byte[1] -.sym 15305 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15306 spi_if_ins.spi.r_tx_byte[5] -.sym 15309 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 15310 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 15311 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] -.sym 15312 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 15317 spi_if_ins.r_tx_byte[7] -.sym 15321 spi_if_ins.r_tx_byte[5] -.sym 15330 spi_if_ins.r_tx_byte[3] -.sym 15333 spi_if_ins.spi.r_tx_byte[3] -.sym 15334 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15335 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 15336 spi_if_ins.spi.r_tx_byte[7] -.sym 15343 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15222 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 15227 spi_if_ins.state_if[2] +.sym 15235 $PACKER_VCC_NET +.sym 15237 lvds_rx_24_inst.o_debug_state[0] +.sym 15238 i_ss_SB_LUT4_I3_O +.sym 15243 w_rx_09_fifo_data[7] +.sym 15248 i_smi_a1_SB_LUT4_I1_O +.sym 15255 lvds_rx_24_inst.r_data[13] +.sym 15266 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15268 w_rx_09_fifo_empty +.sym 15281 w_rx_24_fifo_empty +.sym 15284 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 15286 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 15290 w_rx_09_fifo_full +.sym 15297 w_rx_09_fifo_empty +.sym 15311 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 15322 w_rx_24_fifo_empty +.sym 15341 w_rx_09_fifo_full +.sym 15343 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E .sym 15344 r_counter_$glb_clk -.sym 15345 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15348 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15349 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15360 $PACKER_VCC_NET -.sym 15361 spi_if_ins.r_tx_byte[3] -.sym 15376 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 15379 i_ss$SB_IO_IN -.sym 15388 spi_if_ins.spi.r_tx_byte[0] -.sym 15390 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 15391 spi_if_ins.spi.r_tx_byte[4] -.sym 15396 spi_if_ins.spi.r_tx_byte[6] -.sym 15397 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15400 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15403 spi_if_ins.r_tx_byte[0] -.sym 15405 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15407 spi_if_ins.r_tx_byte[1] -.sym 15409 spi_if_ins.r_tx_byte[2] -.sym 15413 spi_if_ins.r_tx_byte[4] -.sym 15414 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15415 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 15416 spi_if_ins.spi.r_tx_byte[2] -.sym 15421 spi_if_ins.spi.r_tx_byte[0] -.sym 15422 spi_if_ins.spi.r_tx_byte[4] -.sym 15423 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15429 spi_if_ins.r_tx_byte[0] -.sym 15432 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15433 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 15438 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 15439 spi_if_ins.spi.r_tx_byte[6] -.sym 15440 spi_if_ins.spi.r_tx_bit_count[2] -.sym 15441 spi_if_ins.spi.r_tx_byte[2] -.sym 15445 spi_if_ins.r_tx_byte[4] -.sym 15451 spi_if_ins.r_tx_byte[2] -.sym 15458 spi_if_ins.r_tx_byte[1] -.sym 15466 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E +.sym 15345 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 15346 spi_if_ins.state_if_SB_DFFESR_Q_D[0] +.sym 15347 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 15348 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 15350 spi_if_ins.state_if[1] +.sym 15351 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 15352 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 15353 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 15358 spi_if_ins.w_rx_data[2] +.sym 15360 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15361 rx_09_fifo.wr_addr[5] +.sym 15362 spi_if_ins.w_rx_data[6] +.sym 15363 rx_09_fifo.wr_addr[4] +.sym 15364 rx_24_fifo.rd_addr[6] +.sym 15365 $PACKER_VCC_NET +.sym 15366 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 15367 rx_09_fifo.wr_addr[6] +.sym 15368 spi_if_ins.w_rx_data[3] +.sym 15370 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 15371 spi_if_ins.r_tx_byte[1] +.sym 15372 lvds_rx_24_inst.r_data[3] +.sym 15373 spi_if_ins.r_tx_byte[6] +.sym 15374 spi_if_ins.state_if[2] +.sym 15375 spi_if_ins.r_tx_byte[4] +.sym 15376 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 15377 spi_if_ins.r_tx_byte[3] +.sym 15378 lvds_rx_24_inst.r_data[25] +.sym 15379 w_cs[1] +.sym 15380 lvds_rx_24_inst.o_debug_state[0] +.sym 15381 spi_if_ins.r_tx_byte[5] +.sym 15402 smi_ctrl_ins.r_fifo_24_pull +.sym 15407 smi_ctrl_ins.w_fifo_09_pull_trigger +.sym 15427 smi_ctrl_ins.w_fifo_09_pull_trigger +.sym 15444 smi_ctrl_ins.r_fifo_24_pull .sym 15467 r_counter_$glb_clk -.sym 15468 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15476 spi_if_ins.spi.r_rx_done -.sym 15484 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 15512 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15517 spi_if_ins.r_tx_byte[6] -.sym 15519 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15520 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 15539 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15549 spi_if_ins.r_tx_byte[6] +.sym 15468 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 15469 lvds_rx_24_inst.r_data[7] +.sym 15470 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15471 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 15472 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[2] +.sym 15473 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 15474 lvds_rx_24_inst.r_data[27] +.sym 15475 lvds_rx_24_inst.r_data[29] +.sym 15476 lvds_rx_24_inst.r_data[5] +.sym 15482 rx_24_fifo.rd_addr[8] +.sym 15484 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 15485 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 15486 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 15488 w_rx_09_fifo_data[19] +.sym 15490 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 15491 lvds_rx_24_inst.o_debug_state[1] +.sym 15492 rx_24_fifo.rd_addr[1] +.sym 15493 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 15495 spi_if_ins.r_tx_byte[2] +.sym 15497 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15499 spi_if_ins.w_rx_data[1] +.sym 15500 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 15502 lvds_rx_24_inst.r_data[7] +.sym 15503 spi_if_ins.w_rx_data[4] +.sym 15514 spi_if_ins.state_if[1] +.sym 15527 lvds_rx_24_inst.r_data[13] +.sym 15530 spi_if_ins.state_if[0] +.sym 15534 spi_if_ins.state_if[2] +.sym 15535 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15536 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 15538 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 15543 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15549 spi_if_ins.state_if[2] +.sym 15550 spi_if_ins.state_if[0] +.sym 15551 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 15552 spi_if_ins.state_if[1] .sym 15558 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 15564 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 15589 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 15590 r_counter_$glb_clk -.sym 15591 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 15596 w_rx_data[6] -.sym 15599 w_rx_data[7] -.sym 15604 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 15606 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 15617 w_rx_data[6] -.sym 15623 w_rx_data[7] -.sym 15635 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 15642 r_tx_data[6] -.sym 15643 r_tx_data[3] -.sym 15652 r_tx_data[0] -.sym 15669 r_tx_data[0] -.sym 15684 r_tx_data[3] -.sym 15711 r_tx_data[6] -.sym 15712 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 15568 lvds_rx_24_inst.r_data[13] +.sym 15573 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 15574 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 15575 spi_if_ins.state_if[2] +.sym 15579 spi_if_ins.state_if[0] +.sym 15580 spi_if_ins.state_if[2] +.sym 15581 spi_if_ins.state_if[1] +.sym 15582 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 15589 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 15590 lvds_clock_$glb_clk +.sym 15592 spi_if_ins.r_tx_byte[1] +.sym 15593 spi_if_ins.r_tx_byte[6] +.sym 15594 spi_if_ins.r_tx_byte[4] +.sym 15595 spi_if_ins.r_tx_byte[3] +.sym 15596 spi_if_ins.r_tx_byte[7] +.sym 15597 spi_if_ins.r_tx_byte[5] +.sym 15598 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 15599 spi_if_ins.r_tx_byte[2] +.sym 15606 w_rx_24_fifo_data[31] +.sym 15609 lvds_rx_24_inst.r_data[5] +.sym 15614 w_rx_24_fifo_data[15] +.sym 15615 $PACKER_VCC_NET +.sym 15616 spi_if_ins.state_if[0] +.sym 15617 spi_if_ins.r_tx_byte[7] +.sym 15621 w_tx_data_smi[0] +.sym 15622 spi_if_ins.state_if[0] +.sym 15623 w_cs[1] +.sym 15625 w_fetch +.sym 15627 w_cs[2] +.sym 15636 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15638 spi_if_ins.w_rx_data[6] +.sym 15646 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 15647 w_cs[2] +.sym 15648 spi_if_ins.w_rx_data[5] +.sym 15649 w_cs[1] +.sym 15653 i_smi_a3$SB_IO_IN +.sym 15656 i_smi_a1$SB_IO_IN +.sym 15657 w_cs[3] +.sym 15658 i_smi_a2$SB_IO_IN +.sym 15660 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 15662 w_cs[0] +.sym 15666 spi_if_ins.w_rx_data[5] +.sym 15669 spi_if_ins.w_rx_data[6] +.sym 15672 w_cs[3] +.sym 15673 w_cs[1] +.sym 15674 w_cs[2] +.sym 15675 w_cs[0] +.sym 15696 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15697 i_smi_a3$SB_IO_IN +.sym 15698 i_smi_a1$SB_IO_IN +.sym 15699 i_smi_a2$SB_IO_IN +.sym 15712 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] .sym 15713 r_counter_$glb_clk -.sym 15715 w_rx_data[2] -.sym 15717 w_rx_data[4] -.sym 15720 w_rx_data[5] -.sym 15721 w_rx_data[3] -.sym 15722 w_rx_data[0] -.sym 15736 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 15739 io_ctrl_ins.debug_mode[0] -.sym 15740 i_button$SB_IO_IN -.sym 15741 io_ctrl_ins.rf_mode[2] -.sym 15742 w_rx_data[5] -.sym 15743 w_rx_data[6] -.sym 15744 w_rx_data[3] -.sym 15745 io_ctrl_ins.rf_mode[1] -.sym 15746 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 15747 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 15749 w_rx_data[7] -.sym 15758 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O -.sym 15774 w_rx_data[4] -.sym 15778 w_rx_data[3] -.sym 15779 w_rx_data[0] -.sym 15814 w_rx_data[0] -.sym 15820 w_rx_data[4] -.sym 15832 w_rx_data[3] -.sym 15835 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O +.sym 15714 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 15715 w_rx_data[5] +.sym 15716 w_rx_data[2] +.sym 15717 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 15718 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3] +.sym 15719 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 15720 w_rx_data[0] +.sym 15721 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 15722 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1] +.sym 15729 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E +.sym 15731 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 15733 smi_ctrl_ins.int_cnt_24[3] +.sym 15735 w_cs[2] +.sym 15737 w_rx_24_fifo_data[30] +.sym 15739 w_rx_data[4] +.sym 15742 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15747 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 15748 w_cs[0] +.sym 15749 w_rx_data[1] +.sym 15750 w_rx_data[2] +.sym 15756 spi_if_ins.w_rx_data[6] +.sym 15758 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 15759 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] +.sym 15764 w_ioc[1] +.sym 15766 spi_if_ins.w_rx_data[3] +.sym 15767 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 15770 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15771 spi_if_ins.w_rx_data[1] +.sym 15774 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 15775 spi_if_ins.w_rx_data[4] +.sym 15783 w_cs[1] +.sym 15785 w_fetch +.sym 15786 w_load +.sym 15787 w_cs[2] +.sym 15789 w_fetch +.sym 15791 w_cs[1] +.sym 15792 w_load +.sym 15798 spi_if_ins.w_rx_data[1] +.sym 15802 spi_if_ins.w_rx_data[3] +.sym 15807 w_ioc[1] +.sym 15808 w_cs[2] +.sym 15809 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15810 w_fetch +.sym 15814 spi_if_ins.w_rx_data[4] +.sym 15820 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 15821 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] +.sym 15827 spi_if_ins.w_rx_data[6] +.sym 15832 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 15835 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 15836 r_counter_$glb_clk -.sym 15837 w_soft_reset_$glb_sr -.sym 15838 io_ctrl_ins.led1_state_SB_DFFESR_Q_E -.sym 15839 io_ctrl_ins.o_pmod[4] -.sym 15840 io_ctrl_ins.o_pmod[3] -.sym 15841 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 15842 io_ctrl_ins.o_pmod[7] -.sym 15844 io_ctrl_ins.o_pmod[2] -.sym 15845 io_ctrl_ins.o_pmod[5] -.sym 15846 spi_if_ins.w_rx_data[3] -.sym 15856 w_rx_data[1] -.sym 15857 w_rx_data[2] -.sym 15859 $PACKER_VCC_NET -.sym 15862 w_rx_data[4] -.sym 15869 io_ctrl_ins.rf_mode[2] -.sym 15872 w_rx_data[0] -.sym 15873 io_ctrl_ins.rf_mode[1] -.sym 15879 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 15881 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 15882 o_rx_h_tx_l_b$SB_IO_OUT -.sym 15884 io_ctrl_ins.pmod_dir_state[7] -.sym 15885 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 15886 o_rx_h_tx_l$SB_IO_OUT -.sym 15887 w_rx_data[6] -.sym 15888 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 15889 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15891 io_ctrl_ins.pmod_dir_state[6] -.sym 15893 w_rx_data[7] -.sym 15894 w_soft_reset -.sym 15900 i_button$SB_IO_IN -.sym 15903 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 15906 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 15907 io_ctrl_ins.o_pmod[7] -.sym 15912 w_soft_reset -.sym 15913 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15918 o_rx_h_tx_l_b$SB_IO_OUT -.sym 15919 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 15920 io_ctrl_ins.pmod_dir_state[6] -.sym 15921 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 15924 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 15927 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 15930 io_ctrl_ins.o_pmod[7] -.sym 15931 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 15932 i_button$SB_IO_IN -.sym 15933 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 15937 w_rx_data[6] -.sym 15942 w_rx_data[7] -.sym 15954 o_rx_h_tx_l$SB_IO_OUT -.sym 15955 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 15956 io_ctrl_ins.pmod_dir_state[7] -.sym 15957 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 15958 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 15838 io_ctrl_ins.debug_mode[1] +.sym 15839 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 15840 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 15842 io_ctrl_ins.debug_mode[0] +.sym 15843 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 15844 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 15845 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 15851 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 15852 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 15853 w_tx_data_io[2] +.sym 15855 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 15856 $PACKER_VCC_NET +.sym 15859 w_rx_data[2] +.sym 15861 lvds_rx_24_inst.o_debug_state[0] +.sym 15862 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 15863 w_rx_data[3] +.sym 15864 lvds_rx_24_inst.r_data[3] +.sym 15865 i_config_SB_LUT4_I0_I1[0] +.sym 15867 w_rx_data[4] +.sym 15868 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] +.sym 15871 w_rx_data[6] +.sym 15873 w_tx_data_io[3] +.sym 15879 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 15884 spi_if_ins.w_rx_data[0] +.sym 15886 spi_if_ins.w_rx_data[1] +.sym 15889 spi_if_ins.w_rx_data[3] +.sym 15890 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 15894 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15898 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 15901 spi_if_ins.w_rx_data[2] +.sym 15906 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 15915 spi_if_ins.w_rx_data[1] +.sym 15918 spi_if_ins.w_rx_data[0] +.sym 15926 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 15930 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 15931 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 15933 i_smi_a2_SB_LUT4_I1_O[1] +.sym 15937 spi_if_ins.w_rx_data[3] +.sym 15945 spi_if_ins.w_rx_data[2] +.sym 15958 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] .sym 15959 r_counter_$glb_clk -.sym 15961 io_ctrl_ins.rf_pin_state[5] -.sym 15964 io_ctrl_ins.rf_pin_state[3] -.sym 15965 io_ctrl_ins.rf_pin_state[4] -.sym 15966 io_ctrl_ins.rf_pin_state[7] -.sym 15967 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 15968 io_ctrl_ins.rf_pin_state[6] -.sym 15977 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 15979 o_led0$SB_IO_OUT -.sym 15988 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 16002 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 16004 io_ctrl_ins.o_pmod[3] -.sym 16005 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 16012 w_rx_data[5] -.sym 16013 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 16014 w_rx_data[3] -.sym 16017 io_ctrl_ins.pmod_dir_state[4] -.sym 16019 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 16020 w_rx_data[1] -.sym 16022 w_rx_data[4] -.sym 16023 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 16026 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 16027 io_ctrl_ins.pmod_dir_state[3] -.sym 16028 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 16029 io_ctrl_ins.rf_mode[2] -.sym 16030 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 16035 io_ctrl_ins.pmod_dir_state[4] -.sym 16036 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 16037 io_ctrl_ins.rf_mode[2] -.sym 16038 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] +.sym 15961 io_ctrl_ins.pmod_dir_state[0] +.sym 15962 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] +.sym 15963 io_ctrl_ins.led1_state_SB_DFFESR_Q_E +.sym 15964 io_ctrl_ins.pmod_dir_state[5] +.sym 15965 i_config_SB_LUT4_I0_I1[3] +.sym 15967 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 15968 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] +.sym 15974 rx_24_fifo.wr_addr[3] +.sym 15975 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 15977 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 15978 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 15979 rx_24_fifo.wr_addr[2] +.sym 15980 rx_24_fifo.wr_addr[5] +.sym 15981 rx_24_fifo.wr_addr[4] +.sym 15982 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 15986 w_tx_data_io[7] +.sym 15990 rx_24_fifo.wr_addr[0] +.sym 15991 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 15993 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 15995 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 16004 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 16007 io_ctrl_ins.o_pmod[4] +.sym 16008 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 16009 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16010 w_ioc[1] +.sym 16011 w_ioc[0] +.sym 16013 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 16016 w_rx_data[7] +.sym 16020 w_rx_data[2] +.sym 16023 w_rx_data[3] +.sym 16027 w_rx_data[4] +.sym 16028 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 16031 w_rx_data[6] +.sym 16035 w_rx_data[2] .sym 16041 w_rx_data[3] -.sym 16047 io_ctrl_ins.o_pmod[3] -.sym 16048 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 16049 io_ctrl_ins.pmod_dir_state[3] -.sym 16050 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 16053 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 16054 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 16055 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 16061 w_rx_data[1] -.sym 16067 w_rx_data[5] -.sym 16072 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 16078 w_rx_data[4] +.sym 16048 w_ioc[1] +.sym 16049 w_ioc[0] +.sym 16050 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 16055 w_rx_data[7] +.sym 16061 w_rx_data[6] +.sym 16068 w_rx_data[4] +.sym 16071 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 16072 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16073 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 16074 io_ctrl_ins.o_pmod[4] +.sym 16077 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 16078 w_ioc[0] +.sym 16079 w_ioc[1] .sym 16081 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 16082 r_counter_$glb_clk -.sym 16084 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[3] -.sym 16088 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[3] +.sym 16084 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] +.sym 16085 w_tx_data_io[0] +.sym 16086 w_tx_data_io[1] +.sym 16087 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] +.sym 16088 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R .sym 16089 w_tx_data_io[3] .sym 16090 w_tx_data_io[4] -.sym 16104 o_rx_h_tx_l_b$SB_IO_OUT -.sym 16106 io_ctrl_ins.debug_mode[1] -.sym 16126 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 16127 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 16132 w_rx_data[1] -.sym 16133 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 16139 w_rx_data[2] -.sym 16144 w_rx_data[0] -.sym 16148 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 16173 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 16176 w_rx_data[2] -.sym 16188 w_rx_data[1] -.sym 16195 w_rx_data[0] -.sym 16200 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 16202 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 16204 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 16091 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 16102 i_smi_a2_SB_LUT4_I1_O[1] +.sym 16106 $PACKER_VCC_NET +.sym 16109 i_config_SB_LUT4_I0_I1[2] +.sym 16116 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 16117 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 16118 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 16119 i_config_SB_LUT4_I0_I1[0] +.sym 16126 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 16127 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 16129 io_ctrl_ins.o_pmod[6] +.sym 16130 o_shdn_rx_lna$SB_IO_OUT +.sym 16131 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 16135 i_config_SB_LUT4_I0_I1[2] +.sym 16136 w_rx_data[7] +.sym 16137 w_rx_data[4] +.sym 16138 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 16139 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 16141 w_rx_data[6] +.sym 16143 io_ctrl_ins.debug_mode[1] +.sym 16144 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 16145 io_ctrl_ins.pmod_dir_state[6] +.sym 16147 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 16148 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16151 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 16153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 16160 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 16161 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 16164 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 16165 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 16166 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16167 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 16170 io_ctrl_ins.o_pmod[6] +.sym 16171 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16172 io_ctrl_ins.pmod_dir_state[6] +.sym 16173 i_config_SB_LUT4_I0_I1[2] +.sym 16176 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 16177 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 16178 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 16179 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 16184 w_rx_data[6] +.sym 16191 w_rx_data[7] +.sym 16194 io_ctrl_ins.debug_mode[1] +.sym 16195 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 16196 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 16197 o_shdn_rx_lna$SB_IO_OUT +.sym 16200 w_rx_data[4] +.sym 16204 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O .sym 16205 r_counter_$glb_clk -.sym 16222 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 16228 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 16230 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 16232 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 16236 i_button$SB_IO_IN -.sym 16240 i_config[3]$SB_IO_IN -.sym 16385 r_counter -.sym 16443 r_counter -.sym 16451 i_glob_clock$SB_IO_IN_$glb_clk +.sym 16207 w_tx_data_io[7] +.sym 16208 i_button_SB_LUT4_I0_O[1] +.sym 16209 w_tx_data_io[5] +.sym 16210 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16211 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[3] +.sym 16212 w_tx_data_io[6] +.sym 16213 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 16214 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] +.sym 16219 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 16223 w_rx_24_fifo_data[6] +.sym 16224 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 16225 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 16227 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 16229 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16232 i_config[3]$SB_IO_IN +.sym 16237 o_rx_h_tx_l$SB_IO_OUT +.sym 16248 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 16250 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 16251 io_ctrl_ins.rf_pin_state[7] +.sym 16252 io_ctrl_ins.rf_pin_state[2] +.sym 16254 io_ctrl_ins.o_pmod[7] +.sym 16255 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16257 io_ctrl_ins.rf_pin_state[6] +.sym 16259 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 16261 io_ctrl_ins.pmod_dir_state[7] +.sym 16262 io_ctrl_ins.rf_pin_state[1] +.sym 16265 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 16267 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 16269 i_config_SB_LUT4_I0_I1[2] +.sym 16275 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16276 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 16281 io_ctrl_ins.rf_pin_state[6] +.sym 16282 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 16283 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16287 i_config_SB_LUT4_I0_I1[2] +.sym 16288 io_ctrl_ins.o_pmod[7] +.sym 16289 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 16290 io_ctrl_ins.pmod_dir_state[7] +.sym 16293 io_ctrl_ins.rf_pin_state[2] +.sym 16294 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 16295 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16296 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 16300 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 16305 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 16306 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 16307 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16308 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 16311 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 16312 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16313 io_ctrl_ins.rf_pin_state[1] +.sym 16323 io_ctrl_ins.rf_pin_state[7] +.sym 16324 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 16325 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 16327 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 16328 r_counter_$glb_clk +.sym 16336 io_ctrl_ins.pmod_dir_state[3] +.sym 16342 o_rx_h_tx_l_b$SB_IO_OUT +.sym 16346 $PACKER_VCC_NET +.sym 16349 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 16353 lvds_rx_24_inst.o_debug_state[0] +.sym 16356 w_rx_data[3] +.sym 16362 i_button$SB_IO_IN .sym 16453 i_config[3]$SB_IO_IN .sym 16455 i_button$SB_IO_IN -.sym 16497 r_counter -.sym 16521 r_counter -.sym 16554 w_rx_09_fifo_data[30] -.sym 16555 w_rx_09_fifo_data[28] -.sym 16557 w_rx_09_fifo_data[31] -.sym 16558 $PACKER_VCC_NET -.sym 16559 w_rx_09_fifo_data[29] -.sym 16579 i_smi_a1_SB_LUT4_I1_O +.sym 16497 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 16521 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O +.sym 16523 i_smi_a3$SB_IO_IN +.sym 16524 lvds_rx_24_inst.o_debug_state[1] +.sym 16554 w_smi_data_output[6] +.sym 16556 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] +.sym 16557 w_smi_data_output[5] +.sym 16558 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] +.sym 16559 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] +.sym 16560 w_smi_data_output[4] +.sym 16581 smi_ctrl_ins.soe_and_reset .sym 16585 i_smi_soe_se$SB_IO_IN -.sym 16602 lvds_rx_09_inst.r_data[29] -.sym 16607 lvds_rx_09_inst.r_data[26] -.sym 16615 lvds_rx_09_inst.r_data[27] -.sym 16621 lvds_rx_09_inst.r_data[28] -.sym 16623 lvds_rx_09_inst.r_data[24] -.sym 16636 lvds_rx_09_inst.r_data[29] -.sym 16643 lvds_rx_09_inst.r_data[26] -.sym 16646 lvds_rx_09_inst.r_data[28] -.sym 16653 lvds_rx_09_inst.r_data[24] -.sym 16673 lvds_rx_09_inst.r_data[27] -.sym 16674 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2]_$glb_ce -.sym 16675 lvds_clock_$glb_clk -.sym 16676 w_soft_reset_$glb_sr -.sym 16683 i_smi_a1_SB_LUT4_I1_O -.sym 16685 w_smi_data_output[5] -.sym 16686 w_smi_data_output[4] -.sym 16701 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 16718 lvds_rx_09_inst.r_data[24] -.sym 16721 w_smi_data_output[4] -.sym 16723 lvds_rx_09_inst.r_data[26] -.sym 16733 w_rx_09_fifo_pulled_data[28] -.sym 16734 w_rx_09_fifo_pulled_data[29] -.sym 16741 i_smi_a1_SB_LUT4_I1_O -.sym 16743 w_smi_data_output[1] -.sym 16758 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_1_O[3] -.sym 16759 w_rx_09_fifo_pulled_data[20] -.sym 16760 w_rx_09_fifo_pulled_data[7] -.sym 16762 smi_ctrl_ins.int_cnt_09[3] -.sym 16765 smi_ctrl_ins.int_cnt_09[4] -.sym 16768 w_rx_09_fifo_pulled_data[6] -.sym 16769 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_3_O[3] -.sym 16773 smi_ctrl_ins.int_cnt_09[4] -.sym 16775 w_rx_09_fifo_pulled_data[14] -.sym 16780 w_rx_09_fifo_pulled_data[21] -.sym 16785 i_smi_a1_SB_LUT4_I1_O -.sym 16786 w_rx_09_fifo_pulled_data[15] -.sym 16788 w_rx_09_fifo_pulled_data[29] -.sym 16789 w_rx_09_fifo_pulled_data[28] -.sym 16797 smi_ctrl_ins.int_cnt_09[4] -.sym 16798 w_rx_09_fifo_pulled_data[21] -.sym 16799 w_rx_09_fifo_pulled_data[29] -.sym 16800 smi_ctrl_ins.int_cnt_09[3] -.sym 16815 smi_ctrl_ins.int_cnt_09[3] -.sym 16816 w_rx_09_fifo_pulled_data[20] -.sym 16817 w_rx_09_fifo_pulled_data[28] -.sym 16818 smi_ctrl_ins.int_cnt_09[4] -.sym 16821 w_rx_09_fifo_pulled_data[14] -.sym 16822 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_3_O[3] -.sym 16823 w_rx_09_fifo_pulled_data[6] -.sym 16824 smi_ctrl_ins.int_cnt_09[4] -.sym 16827 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_1_O[3] -.sym 16828 smi_ctrl_ins.int_cnt_09[4] -.sym 16829 w_rx_09_fifo_pulled_data[7] -.sym 16830 w_rx_09_fifo_pulled_data[15] -.sym 16837 i_smi_a1_SB_LUT4_I1_O -.sym 16838 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 16841 w_rx_09_fifo_pulled_data[14] -.sym 16844 w_rx_09_fifo_pulled_data[15] -.sym 16845 w_rx_09_fifo_data[24] -.sym 16847 w_rx_09_fifo_data[21] -.sym 16854 w_rx_09_fifo_pulled_data[6] -.sym 16856 w_rx_09_fifo_pulled_data[7] -.sym 16857 rx_09_fifo.rd_addr[9] -.sym 16864 lvds_rx_09_inst.o_debug_state[1] -.sym 16866 w_rx_09_fifo_pulled_data[21] -.sym 16869 rx_09_fifo.wr_addr[5] -.sym 16870 lvds_rx_09_inst.o_debug_state[0] -.sym 16872 i_smi_a1_SB_LUT4_I1_O -.sym 16873 lvds_rx_09_inst.o_debug_state[0] -.sym 16875 w_rx_09_fifo_pulled_data[25] -.sym 16887 i_smi_a3$SB_IO_IN -.sym 16888 i_smi_a2$SB_IO_IN -.sym 16896 i_smi_a1$SB_IO_IN -.sym 16898 w_soft_reset -.sym 16904 smi_ctrl_ins.int_cnt_09[4] -.sym 16908 i_smi_a2_SB_LUT4_I0_O -.sym 16909 smi_ctrl_ins.int_cnt_09[3] -.sym 16914 i_smi_a1$SB_IO_IN -.sym 16915 i_smi_a2$SB_IO_IN -.sym 16916 i_smi_a3$SB_IO_IN -.sym 16917 w_soft_reset -.sym 16941 smi_ctrl_ins.int_cnt_09[3] -.sym 16956 smi_ctrl_ins.int_cnt_09[4] -.sym 16958 smi_ctrl_ins.int_cnt_09[3] -.sym 16960 i_smi_a2_SB_LUT4_I0_O -.sym 16961 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 16962 w_soft_reset_$glb_sr -.sym 16965 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_9_O[3] -.sym 16966 w_smi_data_output[1] -.sym 16968 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_13_O[3] -.sym 16969 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_11_O[3] -.sym 16979 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 16981 i_ss$SB_IO_IN -.sym 16987 w_smi_data_output[2] -.sym 16989 rx_09_fifo.rd_addr[1] -.sym 16991 rx_09_fifo.rd_addr[8] -.sym 16993 rx_09_fifo.rd_addr[9] -.sym 16996 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 16998 smi_ctrl_ins.int_cnt_09[4] -.sym 17005 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] -.sym 17006 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] -.sym 17021 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 17024 lvds_rx_09_inst.o_debug_state[1] -.sym 17027 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 17030 lvds_rx_09_inst.o_debug_state[0] -.sym 17031 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E -.sym 17033 lvds_rx_09_inst.o_debug_state[0] -.sym 17043 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 17044 lvds_rx_09_inst.o_debug_state[0] -.sym 17067 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 17068 lvds_rx_09_inst.o_debug_state[1] -.sym 17069 lvds_rx_09_inst.o_debug_state[0] -.sym 17070 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] -.sym 17073 lvds_rx_09_inst.o_debug_state[0] -.sym 17074 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] -.sym 17075 lvds_rx_09_inst.o_debug_state[1] -.sym 17076 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 17083 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E -.sym 17084 lvds_clock_$glb_clk -.sym 17085 w_soft_reset_$glb_sr -.sym 17091 w_smi_data_output[3] -.sym 17092 w_smi_data_output[2] -.sym 17101 w_rx_09_fifo_pulled_data[27] -.sym 17102 w_rx_09_fifo_pulled_data[26] -.sym 17105 $PACKER_VCC_NET -.sym 17110 lvds_rx_09_inst.r_data[26] -.sym 17111 $PACKER_VCC_NET -.sym 17115 w_rx_09_fifo_pulled_data[9] -.sym 17117 $PACKER_VCC_NET -.sym 17118 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17127 $PACKER_VCC_NET -.sym 17132 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 17133 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3 -.sym 17136 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 17138 lvds_rx_09_inst.r_phase_count[0] -.sym 17146 lvds_rx_09_inst.r_phase_count[0] -.sym 17148 lvds_rx_09_inst.r_phase_count[1] -.sym 17152 lvds_rx_09_inst.r_data[27] -.sym 17159 $nextpnr_ICESTORM_LC_7$O -.sym 17161 lvds_rx_09_inst.r_phase_count[0] -.sym 17165 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] -.sym 17167 $PACKER_VCC_NET -.sym 17168 lvds_rx_09_inst.r_phase_count[1] -.sym 17169 lvds_rx_09_inst.r_phase_count[0] -.sym 17172 $PACKER_VCC_NET -.sym 17173 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 17175 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] -.sym 17181 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 17184 lvds_rx_09_inst.r_data[27] -.sym 17193 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3 -.sym 17206 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 17207 lvds_clock_$glb_clk -.sym 17215 w_rx_09_fifo_data[26] -.sym 17222 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 17223 w_rx_09_fifo_pulled_data[16] -.sym 17229 w_rx_09_fifo_pulled_data[10] -.sym 17238 w_rx_09_fifo_data[27] -.sym 17239 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 17241 $PACKER_GND_NET -.sym 17244 w_rx_09_fifo_pulled_data[11] -.sym 17252 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 17256 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 17264 spi_if_ins.r_tx_byte[7] -.sym 17276 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 17289 spi_if_ins.r_tx_byte[7] -.sym 17291 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 17292 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 17309 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 17329 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 17330 r_counter_$glb_clk -.sym 17333 spi_if_ins.spi.SCKr[2] -.sym 17334 $PACKER_GND_NET -.sym 17337 spi_if_ins.spi.SCKr[0] -.sym 17338 spi_if_ins.spi.SCKr[1] -.sym 17348 i_ss$SB_IO_IN -.sym 17375 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E -.sym 17376 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 17377 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 17383 spi_if_ins.spi.r_tx_bit_count[2] -.sym 17387 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 17394 $PACKER_VCC_NET -.sym 17395 spi_if_ins.spi.SCKr[1] -.sym 17398 spi_if_ins.spi.SCKr[2] -.sym 17402 $PACKER_VCC_NET -.sym 17403 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 17404 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 17405 $nextpnr_ICESTORM_LC_4$O -.sym 17407 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 17411 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 17413 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 17414 $PACKER_VCC_NET -.sym 17419 spi_if_ins.spi.r_tx_bit_count[2] -.sym 17420 $PACKER_VCC_NET -.sym 17421 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 17424 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 17430 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 17431 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 17433 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 17437 spi_if_ins.spi.SCKr[1] -.sym 17438 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 17439 spi_if_ins.spi.SCKr[2] -.sym 17442 spi_if_ins.spi.SCKr[1] -.sym 17443 spi_if_ins.spi.r_tx_bit_count[2] -.sym 17444 spi_if_ins.spi.SCKr[2] -.sym 17445 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 17448 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 17449 $PACKER_VCC_NET -.sym 17451 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 17452 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 16596 i_smi_soe_se$SB_IO_IN +.sym 16605 w_rx_09_fifo_pulled_data[23] +.sym 16610 i_smi_a2_SB_LUT4_I1_O[1] +.sym 16612 smi_ctrl_ins.int_cnt_09[3] +.sym 16620 w_rx_09_fifo_pulled_data[7] +.sym 16626 smi_ctrl_ins.int_cnt_09[4] +.sym 16634 smi_ctrl_ins.int_cnt_09[3] +.sym 16635 w_rx_09_fifo_pulled_data[7] +.sym 16636 w_rx_09_fifo_pulled_data[23] +.sym 16637 smi_ctrl_ins.int_cnt_09[4] +.sym 16647 i_smi_a2_SB_LUT4_I1_O[1] +.sym 16648 i_smi_soe_se$SB_IO_IN +.sym 16684 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] +.sym 16686 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] +.sym 16688 int_miso +.sym 16697 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] +.sym 16699 w_rx_09_fifo_data[12] +.sym 16701 w_rx_09_fifo_data[13] +.sym 16702 w_smi_data_output[6] +.sym 16710 i_ss$SB_IO_IN +.sym 16712 i_smi_a2_SB_LUT4_I1_O[0] +.sym 16714 w_rx_09_fifo_pulled_data[7] +.sym 16715 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] +.sym 16718 i_smi_a2_SB_LUT4_I1_O[0] +.sym 16721 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] +.sym 16725 smi_ctrl_ins.int_cnt_09[3] +.sym 16731 lvds_rx_24_inst.r_data[15] +.sym 16738 smi_ctrl_ins.soe_and_reset +.sym 16739 smi_ctrl_ins.int_cnt_09[4] +.sym 16743 int_miso +.sym 16747 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] +.sym 16759 lvds_rx_24_inst.r_data[11] +.sym 16764 lvds_rx_24_inst.r_data[13] +.sym 16765 lvds_rx_24_inst.o_debug_state[0] +.sym 16804 lvds_rx_24_inst.o_debug_state[0] +.sym 16805 lvds_rx_24_inst.r_data[13] +.sym 16828 lvds_rx_24_inst.r_data[11] +.sym 16830 lvds_rx_24_inst.o_debug_state[0] +.sym 16837 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 16838 lvds_clock_$glb_clk +.sym 16839 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 16842 spi_if_ins.spi.r_tx_bit_count[2] +.sym 16843 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 16844 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 16845 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 16847 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 16848 spi_if_ins.r_tx_byte[7] +.sym 16851 spi_if_ins.r_tx_byte[7] +.sym 16856 w_rx_09_fifo_pulled_data[23] +.sym 16860 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 16862 rx_09_fifo.rd_addr[4] +.sym 16863 lvds_rx_24_inst.r_data[11] +.sym 16865 lvds_rx_24_inst.r_data[15] +.sym 16866 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 16871 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 16872 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] +.sym 16874 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 16875 smi_ctrl_ins.int_cnt_09[4] +.sym 16883 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E +.sym 16884 sys_ctrl_ins.reset_count[3] +.sym 16891 sys_ctrl_ins.reset_count[2] +.sym 16892 sys_ctrl_ins.reset_count[3] +.sym 16894 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 16895 sys_ctrl_ins.reset_count[1] +.sym 16901 sys_ctrl_ins.reset_cmd +.sym 16912 sys_ctrl_ins.reset_count[0] +.sym 16913 $nextpnr_ICESTORM_LC_9$O +.sym 16916 sys_ctrl_ins.reset_count[0] +.sym 16919 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 16922 sys_ctrl_ins.reset_count[1] +.sym 16925 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 16926 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 16927 sys_ctrl_ins.reset_count[2] +.sym 16929 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 16933 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 16934 sys_ctrl_ins.reset_count[3] +.sym 16935 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 16938 sys_ctrl_ins.reset_cmd +.sym 16940 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 16944 sys_ctrl_ins.reset_count[1] +.sym 16945 sys_ctrl_ins.reset_count[3] +.sym 16946 sys_ctrl_ins.reset_count[2] +.sym 16947 sys_ctrl_ins.reset_count[0] +.sym 16950 sys_ctrl_ins.reset_count[0] +.sym 16952 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 16953 sys_ctrl_ins.reset_count[1] +.sym 16959 sys_ctrl_ins.reset_count[0] +.sym 16960 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E +.sym 16961 r_counter_$glb_clk +.sym 16962 sys_ctrl_ins.reset_cmd +.sym 16964 spi_if_ins.spi.SCKr[0] +.sym 16965 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 16966 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 16967 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 16968 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] +.sym 16969 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 16970 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] +.sym 16973 w_tx_data_io[0] +.sym 16976 $PACKER_VCC_NET +.sym 16977 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 16979 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E +.sym 16982 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 16983 w_smi_read_req +.sym 16986 i_ss$SB_IO_IN +.sym 16987 spi_if_ins.spi.r_tx_bit_count[2] +.sym 16988 i_ss$SB_IO_IN +.sym 16989 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] +.sym 16992 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] +.sym 16993 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 16994 i_smi_a2_SB_LUT4_I1_O[0] +.sym 16996 i_ss$SB_IO_IN +.sym 16998 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] +.sym 17006 spi_if_ins.spi.r_tx_bit_count[2] +.sym 17007 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] +.sym 17015 i_smi_a1_SB_LUT4_I1_O +.sym 17019 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] +.sym 17021 i_smi_a2_SB_LUT4_I1_O[0] +.sym 17029 smi_ctrl_ins.soe_and_reset +.sym 17035 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] +.sym 17055 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] +.sym 17056 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] +.sym 17057 i_smi_a2_SB_LUT4_I1_O[0] +.sym 17058 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] +.sym 17070 spi_if_ins.spi.r_tx_bit_count[2] +.sym 17083 i_smi_a1_SB_LUT4_I1_O +.sym 17084 smi_ctrl_ins.soe_and_reset +.sym 17088 spi_if_ins.spi.r_rx_bit_count[2] +.sym 17089 spi_if_ins.spi.r_rx_bit_count[0] +.sym 17092 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 17093 spi_if_ins.spi.r_rx_bit_count[1] +.sym 17099 rx_09_fifo.rd_addr[9] +.sym 17102 $PACKER_GND_NET +.sym 17105 i_sck$SB_IO_IN +.sym 17110 w_rx_09_fifo_data[17] +.sym 17111 i_mosi$SB_IO_IN +.sym 17115 lvds_rx_24_inst.r_data[15] +.sym 17118 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 17129 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 17130 spi_if_ins.spi.r_tx_byte[7] +.sym 17133 spi_if_ins.spi.r_tx_byte[3] +.sym 17138 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 17140 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17141 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 17142 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 17145 spi_if_ins.r_tx_data_valid +.sym 17146 spi_if_ins.spi.r_tx_byte[2] +.sym 17147 spi_if_ins.spi.r_tx_bit_count[2] +.sym 17148 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17149 spi_if_ins.spi.r_tx_byte[6] +.sym 17150 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 17153 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 17154 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 17156 i_ss$SB_IO_IN +.sym 17158 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 17166 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 17167 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 17168 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 17169 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 17174 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 17178 spi_if_ins.spi.r_tx_byte[7] +.sym 17179 spi_if_ins.spi.r_tx_byte[3] +.sym 17180 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 17181 spi_if_ins.spi.r_tx_bit_count[2] +.sym 17191 spi_if_ins.r_tx_data_valid +.sym 17193 i_ss$SB_IO_IN +.sym 17196 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 17197 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 17199 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 17202 spi_if_ins.spi.r_tx_byte[2] +.sym 17203 spi_if_ins.spi.r_tx_byte[6] +.sym 17204 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 17205 spi_if_ins.spi.r_tx_bit_count[2] +.sym 17206 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 17207 r_counter_$glb_clk +.sym 17208 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17211 spi_if_ins.spi.r_rx_byte[4] +.sym 17212 spi_if_ins.spi.r_rx_byte[6] +.sym 17213 spi_if_ins.spi.r_rx_byte[3] +.sym 17216 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 17221 rx_09_fifo.wr_addr[6] +.sym 17233 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 17234 rx_09_fifo.rd_addr[4] +.sym 17235 spi_if_ins.w_rx_data[5] +.sym 17236 rx_09_fifo.rd_addr[5] +.sym 17237 smi_ctrl_ins.soe_and_reset +.sym 17238 rx_09_fifo.rd_addr[6] +.sym 17241 spi_if_ins.w_rx_data[0] +.sym 17242 i_smi_a2_SB_LUT4_I1_O[1] +.sym 17243 spi_if_ins.w_rx_data[4] +.sym 17244 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 17256 i_ss$SB_IO_IN +.sym 17261 i_ss_SB_LUT4_I3_O +.sym 17267 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 17270 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 17271 i_mosi$SB_IO_IN +.sym 17276 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 17279 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 17281 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 17284 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 17292 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 17298 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 17302 i_ss$SB_IO_IN +.sym 17308 i_mosi$SB_IO_IN +.sym 17314 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 17328 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 17329 i_ss_SB_LUT4_I3_O +.sym 17330 i_sck$SB_IO_IN_$glb_clk +.sym 17332 spi_if_ins.w_rx_data[3] +.sym 17333 spi_if_ins.w_rx_data[1] +.sym 17334 spi_if_ins.w_rx_data[0] +.sym 17335 spi_if_ins.w_rx_data[4] +.sym 17336 spi_if_ins.w_rx_data[2] +.sym 17337 spi_if_ins.w_rx_data[6] +.sym 17338 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17339 spi_if_ins.w_rx_data[5] +.sym 17345 rx_09_fifo.rd_addr[4] +.sym 17349 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 17350 i_smi_a1_SB_LUT4_I1_O +.sym 17352 i_ss_SB_LUT4_I3_O +.sym 17353 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17357 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 17358 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 17361 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 17363 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] +.sym 17367 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 17375 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 17383 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17393 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17433 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17452 spi_if_ins.state_if_SB_DFFE_Q_E .sym 17453 r_counter_$glb_clk -.sym 17454 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R -.sym 17457 spi_if_ins.spi.r_rx_bit_count[2] -.sym 17460 spi_if_ins.spi.r_rx_bit_count[1] -.sym 17461 spi_if_ins.spi.r_rx_bit_count[0] -.sym 17468 i_sck$SB_IO_IN -.sym 17469 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 17454 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17455 spi_if_ins.spi.r_rx_byte[5] +.sym 17456 spi_if_ins.spi.r_rx_byte[1] +.sym 17457 spi_if_ins.spi.r_rx_byte[7] +.sym 17461 spi_if_ins.spi.r_rx_byte[0] +.sym 17462 spi_if_ins.spi.r_rx_byte[2] +.sym 17467 i_ss$SB_IO_IN +.sym 17470 spi_if_ins.w_rx_data[4] +.sym 17471 w_rx_09_fifo_pulled_data[9] .sym 17472 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 17500 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17516 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17541 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 17550 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17473 $PACKER_VCC_NET +.sym 17474 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 17475 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 17476 spi_if_ins.w_rx_data[1] +.sym 17477 spi_if_ins.state_if[2] +.sym 17478 i_smi_a2$SB_IO_IN +.sym 17479 lvds_rx_24_inst.r_data[11] +.sym 17481 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] +.sym 17485 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 17486 smi_ctrl_ins.int_cnt_24[4] +.sym 17487 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17488 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] +.sym 17489 spi_if_ins.w_rx_data[5] +.sym 17490 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] +.sym 17500 spi_if_ins.state_if[2] +.sym 17503 spi_if_ins.state_if[0] +.sym 17508 spi_if_ins.state_if[1] +.sym 17509 lvds_rx_24_inst.o_debug_state[1] +.sym 17511 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17512 i_smi_a2_SB_LUT4_I1_O[1] +.sym 17514 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 17515 lvds_rx_24_inst.o_debug_state[0] +.sym 17518 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 17520 spi_if_ins.state_if_SB_DFFESR_Q_D[0] +.sym 17522 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17529 spi_if_ins.state_if[2] +.sym 17530 spi_if_ins.state_if[1] +.sym 17532 spi_if_ins.state_if[0] +.sym 17535 spi_if_ins.state_if[0] +.sym 17536 spi_if_ins.state_if[2] +.sym 17537 spi_if_ins.state_if[1] +.sym 17541 spi_if_ins.state_if[2] +.sym 17542 spi_if_ins.state_if[0] +.sym 17544 spi_if_ins.state_if[1] +.sym 17553 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17554 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17555 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 17556 spi_if_ins.state_if_SB_DFFESR_Q_D[0] +.sym 17559 spi_if_ins.state_if[0] +.sym 17560 spi_if_ins.state_if[2] +.sym 17561 spi_if_ins.state_if[1] +.sym 17562 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17565 spi_if_ins.state_if[2] +.sym 17566 spi_if_ins.state_if[0] +.sym 17567 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17568 spi_if_ins.state_if[1] +.sym 17572 lvds_rx_24_inst.o_debug_state[1] +.sym 17573 lvds_rx_24_inst.o_debug_state[0] +.sym 17574 i_smi_a2_SB_LUT4_I1_O[1] +.sym 17575 spi_if_ins.state_if_SB_DFFE_Q_E .sym 17576 r_counter_$glb_clk -.sym 17578 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17580 spi_if_ins.spi.r2_rx_done -.sym 17582 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 17584 spi_if_ins.spi.r3_rx_done -.sym 17585 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17591 i_ss$SB_IO_IN -.sym 17613 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17621 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17632 i_ss$SB_IO_IN -.sym 17642 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17696 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17698 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17699 i_sck$SB_IO_IN_$glb_clk -.sym 17700 i_ss$SB_IO_IN -.sym 17717 i_ss$SB_IO_IN -.sym 17718 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 17720 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E -.sym 17725 w_rx_data[1] -.sym 17730 w_rx_data[2] -.sym 17733 $PACKER_GND_NET -.sym 17744 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 17752 spi_if_ins.w_rx_data[6] -.sym 17769 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17800 spi_if_ins.w_rx_data[6] -.sym 17820 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 17821 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 17578 w_rx_24_fifo_data[14] +.sym 17579 w_rx_24_fifo_data[31] +.sym 17580 w_rx_24_fifo_data[21] +.sym 17581 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] +.sym 17582 w_rx_24_fifo_data[13] +.sym 17583 w_rx_24_fifo_data[29] +.sym 17584 w_rx_24_fifo_data[20] +.sym 17585 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] +.sym 17589 io_ctrl_ins.debug_mode[1] +.sym 17590 spi_if_ins.state_if_SB_DFFESR_Q_D[0] +.sym 17592 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 17595 spi_if_ins.r_tx_byte[0] +.sym 17598 rx_09_fifo.rd_addr[9] +.sym 17599 spi_if_ins.state_if[0] +.sym 17602 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17603 w_tx_data_smi[2] +.sym 17607 w_rx_24_fifo_data[28] +.sym 17609 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E +.sym 17611 spi_if_ins.w_rx_data[2] +.sym 17612 w_tx_data_smi[1] +.sym 17620 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17621 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17623 lvds_rx_24_inst.r_data[25] +.sym 17624 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 17625 lvds_rx_24_inst.o_debug_state[0] +.sym 17628 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 17629 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17630 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 17631 spi_if_ins.state_if[1] +.sym 17632 lvds_rx_24_inst.r_data[27] +.sym 17633 lvds_rx_24_inst.r_data[3] +.sym 17637 spi_if_ins.state_if[0] +.sym 17638 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[2] +.sym 17642 lvds_rx_24_inst.r_data[5] +.sym 17653 lvds_rx_24_inst.r_data[5] +.sym 17654 lvds_rx_24_inst.o_debug_state[0] +.sym 17658 spi_if_ins.state_if[1] +.sym 17659 spi_if_ins.state_if[0] +.sym 17664 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 17665 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[2] +.sym 17667 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 17670 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17672 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17673 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 17676 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 17679 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 17683 lvds_rx_24_inst.r_data[25] +.sym 17685 lvds_rx_24_inst.o_debug_state[0] +.sym 17688 lvds_rx_24_inst.r_data[27] +.sym 17690 lvds_rx_24_inst.o_debug_state[0] +.sym 17694 lvds_rx_24_inst.r_data[3] +.sym 17695 lvds_rx_24_inst.o_debug_state[0] +.sym 17698 w_lvds_rx_24_d1_SB_LUT4_I1_O[2]_$glb_ce +.sym 17699 lvds_clock_$glb_clk +.sym 17700 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 17702 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 17703 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 17704 smi_ctrl_ins.int_cnt_24[4] +.sym 17705 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] +.sym 17706 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] +.sym 17707 smi_ctrl_ins.int_cnt_24[3] +.sym 17716 rx_24_fifo.wr_addr[6] +.sym 17717 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 17719 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 17721 lvds_rx_24_inst.r_data[12] +.sym 17723 $PACKER_VCC_NET +.sym 17726 spi_if_ins.w_rx_data[0] +.sym 17727 spi_if_ins.w_rx_data[5] +.sym 17729 w_tx_data_io[4] +.sym 17730 i_smi_a2_SB_LUT4_I1_O[1] +.sym 17731 spi_if_ins.w_rx_data[4] +.sym 17733 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 17734 smi_ctrl_ins.soe_and_reset +.sym 17742 w_cs[3] +.sym 17745 w_cs[2] +.sym 17747 r_tx_data[7] +.sym 17750 w_cs[1] +.sym 17751 r_tx_data[3] +.sym 17760 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 17762 r_tx_data[6] +.sym 17763 r_tx_data[2] +.sym 17764 r_tx_data[4] +.sym 17768 r_tx_data[1] +.sym 17771 w_cs[0] +.sym 17773 r_tx_data[5] +.sym 17778 r_tx_data[1] +.sym 17784 r_tx_data[6] +.sym 17789 r_tx_data[4] +.sym 17796 r_tx_data[3] +.sym 17802 r_tx_data[7] +.sym 17806 r_tx_data[5] +.sym 17811 w_cs[3] +.sym 17812 w_cs[1] +.sym 17813 w_cs[0] +.sym 17814 w_cs[2] +.sym 17819 r_tx_data[2] +.sym 17821 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O .sym 17822 r_counter_$glb_clk -.sym 17830 w_rx_data[1] -.sym 17840 spi_if_ins.w_rx_data[6] -.sym 17848 o_led0$SB_IO_OUT -.sym 17853 w_rx_data[1] -.sym 17854 w_rx_data[0] -.sym 17866 spi_if_ins.w_rx_data[2] -.sym 17867 spi_if_ins.w_rx_data[4] -.sym 17868 spi_if_ins.w_rx_data[3] -.sym 17870 spi_if_ins.w_rx_data[5] -.sym 17874 spi_if_ins.w_rx_data[0] -.sym 17883 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 17899 spi_if_ins.w_rx_data[2] -.sym 17912 spi_if_ins.w_rx_data[4] -.sym 17928 spi_if_ins.w_rx_data[5] -.sym 17937 spi_if_ins.w_rx_data[3] -.sym 17941 spi_if_ins.w_rx_data[0] +.sym 17824 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 17825 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 17826 r_tx_data[1] +.sym 17828 r_tx_data[6] +.sym 17829 r_tx_data[2] +.sym 17830 r_tx_data[4] +.sym 17831 r_tx_data[5] +.sym 17837 r_tx_data[3] +.sym 17838 w_tx_data_io[3] +.sym 17839 lvds_rx_24_inst.o_debug_state[0] +.sym 17841 $PACKER_VCC_NET +.sym 17844 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 17850 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 17856 w_rx_data[5] +.sym 17866 w_tx_data_smi[0] +.sym 17867 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 17868 w_cs[1] +.sym 17871 w_tx_data_io[2] +.sym 17873 w_tx_data_smi[2] +.sym 17876 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 17880 w_cs[2] +.sym 17881 spi_if_ins.w_rx_data[2] +.sym 17882 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 17883 w_cs[0] +.sym 17886 spi_if_ins.w_rx_data[0] +.sym 17887 spi_if_ins.w_rx_data[5] +.sym 17889 w_cs[3] +.sym 17890 w_tx_data_io[0] +.sym 17898 spi_if_ins.w_rx_data[5] +.sym 17907 spi_if_ins.w_rx_data[2] +.sym 17910 w_cs[2] +.sym 17911 w_cs[1] +.sym 17912 w_cs[0] +.sym 17913 w_cs[3] +.sym 17916 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 17917 w_tx_data_io[0] +.sym 17918 w_tx_data_smi[0] +.sym 17919 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 17922 w_cs[0] +.sym 17923 w_cs[3] +.sym 17924 w_cs[2] +.sym 17925 w_cs[1] +.sym 17930 spi_if_ins.w_rx_data[0] +.sym 17934 w_cs[0] +.sym 17935 w_cs[1] +.sym 17936 w_cs[2] +.sym 17937 w_cs[3] +.sym 17940 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 17941 w_tx_data_io[2] +.sym 17942 w_tx_data_smi[2] +.sym 17943 spi_if_ins.o_cs_SB_LUT4_I2_O[2] .sym 17944 spi_if_ins.o_data_in_SB_DFFE_Q_E .sym 17945 r_counter_$glb_clk -.sym 17952 o_led1$SB_IO_OUT -.sym 17953 o_led0$SB_IO_OUT -.sym 17960 spi_if_ins.w_rx_data[0] -.sym 17961 spi_if_ins.w_rx_data[4] -.sym 17966 spi_if_ins.w_rx_data[5] -.sym 17970 spi_if_ins.w_rx_data[2] -.sym 17972 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 17981 io_ctrl_ins.o_pmod[4] -.sym 17990 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O -.sym 17994 w_rx_data[3] -.sym 17995 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 17996 w_rx_data[2] -.sym 17998 w_rx_data[4] -.sym 18001 w_rx_data[5] -.sym 18002 w_rx_data[7] -.sym 18006 w_soft_reset -.sym 18008 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 18016 io_ctrl_ins.debug_mode[0] -.sym 18018 io_ctrl_ins.debug_mode[1] -.sym 18021 w_soft_reset -.sym 18022 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 18023 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 18029 w_rx_data[4] -.sym 18035 w_rx_data[3] -.sym 18039 io_ctrl_ins.debug_mode[0] -.sym 18041 io_ctrl_ins.debug_mode[1] -.sym 18046 w_rx_data[7] -.sym 18058 w_rx_data[2] -.sym 18064 w_rx_data[5] -.sym 18067 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 17947 io_ctrl_ins.o_pmod[5] +.sym 17949 io_ctrl_ins.o_pmod[0] +.sym 17951 io_ctrl_ins.led1_state_SB_LUT4_I1_O[0] +.sym 17959 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 17961 w_fetch +.sym 17962 spi_if_ins.o_data_in_SB_DFFE_Q_E +.sym 17965 rx_24_fifo.wr_addr[0] +.sym 17966 w_tx_data_io[7] +.sym 17967 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3] +.sym 17968 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 17969 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 17971 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 17972 io_ctrl_ins.led1_state_SB_LUT4_I1_O[0] +.sym 17973 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 17974 rx_24_fifo.rd_addr[8] +.sym 17975 w_tx_data_io[1] +.sym 17976 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 17977 rx_24_fifo.rd_addr[0] +.sym 17978 w_rx_data[0] +.sym 17979 io_ctrl_ins.debug_mode[1] +.sym 17981 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 17982 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 17989 w_rx_data[2] +.sym 17993 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 17994 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 17999 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O +.sym 18000 i_smi_a2_SB_LUT4_I1_O[1] +.sym 18001 w_rx_data[0] +.sym 18004 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 18006 w_rx_data[3] +.sym 18013 w_rx_data[1] +.sym 18016 w_rx_data[4] +.sym 18023 w_rx_data[1] +.sym 18027 w_rx_data[2] +.sym 18033 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 18034 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 18045 w_rx_data[0] +.sym 18051 i_smi_a2_SB_LUT4_I1_O[1] +.sym 18052 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 18060 w_rx_data[4] +.sym 18066 w_rx_data[3] +.sym 18067 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O .sym 18068 r_counter_$glb_clk -.sym 18070 o_tr_vc2$SB_IO_OUT -.sym 18071 o_tr_vc1$SB_IO_OUT -.sym 18073 o_rx_h_tx_l$SB_IO_OUT -.sym 18074 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18075 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 18077 o_rx_h_tx_l_b$SB_IO_OUT -.sym 18097 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 18100 o_tr_vc1_b$SB_IO_OUT -.sym 18104 i_config[1]$SB_IO_IN -.sym 18113 w_rx_data[5] -.sym 18114 io_ctrl_ins.rf_mode[2] -.sym 18115 w_rx_data[3] -.sym 18116 io_ctrl_ins.debug_mode[1] -.sym 18120 io_ctrl_ins.debug_mode[0] -.sym 18122 w_rx_data[7] -.sym 18123 w_rx_data[4] -.sym 18124 w_rx_data[6] -.sym 18126 io_ctrl_ins.rf_mode[1] -.sym 18129 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 18146 w_rx_data[5] -.sym 18165 w_rx_data[3] -.sym 18169 w_rx_data[4] -.sym 18175 w_rx_data[7] -.sym 18180 io_ctrl_ins.rf_mode[1] -.sym 18181 io_ctrl_ins.rf_mode[2] -.sym 18182 io_ctrl_ins.debug_mode[0] -.sym 18183 io_ctrl_ins.debug_mode[1] -.sym 18187 w_rx_data[6] -.sym 18190 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 18069 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 18071 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] +.sym 18072 io_ctrl_ins.rf_pin_state[0] +.sym 18073 io_ctrl_ins.rf_pin_state[4] +.sym 18076 io_ctrl_ins.rf_pin_state[5] +.sym 18077 io_ctrl_ins.rf_pin_state[3] +.sym 18092 w_fetch +.sym 18095 w_rx_24_fifo_data[28] +.sym 18096 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 18098 w_tx_data_io[5] +.sym 18099 io_ctrl_ins.debug_mode[0] +.sym 18103 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18104 w_tx_data_io[6] +.sym 18105 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18112 i_smi_a2_SB_LUT4_I1_O[1] +.sym 18113 i_config_SB_LUT4_I0_I1[2] +.sym 18114 w_rx_data[1] +.sym 18116 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 18119 io_ctrl_ins.pmod_dir_state[0] +.sym 18120 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 18121 w_rx_data[2] +.sym 18122 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 18126 i_config_SB_LUT4_I0_I1[0] +.sym 18128 w_rx_data[5] +.sym 18135 o_led0$SB_IO_OUT +.sym 18138 w_rx_data[0] +.sym 18146 w_rx_data[0] +.sym 18152 w_rx_data[2] +.sym 18156 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 18157 i_smi_a2_SB_LUT4_I1_O[1] +.sym 18158 i_config_SB_LUT4_I0_I1[0] +.sym 18162 w_rx_data[5] +.sym 18171 w_rx_data[1] +.sym 18180 i_config_SB_LUT4_I0_I1[2] +.sym 18181 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 18186 o_led0$SB_IO_OUT +.sym 18187 i_config_SB_LUT4_I0_I1[2] +.sym 18188 io_ctrl_ins.pmod_dir_state[0] +.sym 18189 i_config_SB_LUT4_I0_I1[0] +.sym 18190 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O .sym 18191 r_counter_$glb_clk -.sym 18194 o_tr_vc1_b$SB_IO_OUT -.sym 18196 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 18210 io_ctrl_ins.rf_mode[2] -.sym 18213 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O -.sym 18214 io_ctrl_ins.rf_mode[1] -.sym 18236 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 18238 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 18240 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 18242 o_tr_vc2$SB_IO_OUT -.sym 18244 io_ctrl_ins.rf_mode[1] -.sym 18246 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[3] -.sym 18250 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[2] -.sym 18251 o_tr_vc1_b$SB_IO_OUT -.sym 18253 io_ctrl_ins.o_pmod[4] -.sym 18254 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 18258 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[3] -.sym 18259 i_config[0]$SB_IO_IN -.sym 18260 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[2] -.sym 18261 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O -.sym 18263 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 18264 i_config[1]$SB_IO_IN -.sym 18267 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 18268 o_tr_vc2$SB_IO_OUT -.sym 18269 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 18270 io_ctrl_ins.rf_mode[1] -.sym 18291 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 18292 o_tr_vc1_b$SB_IO_OUT -.sym 18293 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 18294 io_ctrl_ins.o_pmod[4] -.sym 18297 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[2] -.sym 18298 i_config[0]$SB_IO_IN +.sym 18193 o_led0$SB_IO_OUT +.sym 18195 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[2] +.sym 18196 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] +.sym 18199 o_led1$SB_IO_OUT +.sym 18205 o_rx_h_tx_l$SB_IO_OUT +.sym 18209 rx_24_fifo.wr_addr[6] +.sym 18210 w_rx_24_fifo_full +.sym 18214 w_rx_data[4] +.sym 18217 io_ctrl_ins.rf_pin_state[0] +.sym 18219 io_ctrl_ins.rf_pin_state[4] +.sym 18221 w_tx_data_io[4] +.sym 18227 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 18234 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] +.sym 18235 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 18237 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18238 i_config_SB_LUT4_I0_I1[3] +.sym 18239 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 18240 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] +.sym 18241 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] +.sym 18242 io_ctrl_ins.led1_state_SB_LUT4_I1_O[0] +.sym 18243 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] +.sym 18245 io_ctrl_ins.pmod_dir_state[5] +.sym 18246 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[3] +.sym 18247 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18248 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 18249 io_ctrl_ins.pmod_dir_state[4] +.sym 18250 i_config_SB_LUT4_I0_I1[2] +.sym 18251 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] +.sym 18252 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[2] +.sym 18254 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 18255 i_config[1]$SB_IO_IN +.sym 18256 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 18257 i_config_SB_LUT4_I0_I1[0] +.sym 18258 i_config_SB_LUT4_I0_I1[2] +.sym 18259 io_ctrl_ins.o_pmod[3] +.sym 18260 o_tr_vc1_b$SB_IO_OUT +.sym 18261 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3_SB_LUT4_I3_O +.sym 18263 o_tr_vc1$SB_IO_OUT +.sym 18264 o_led1$SB_IO_OUT +.sym 18265 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 18267 i_config_SB_LUT4_I0_I1[2] +.sym 18268 i_config_SB_LUT4_I0_I1[0] +.sym 18269 i_config_SB_LUT4_I0_I1[3] +.sym 18270 o_led1$SB_IO_OUT +.sym 18273 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] +.sym 18274 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] +.sym 18275 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] +.sym 18276 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18279 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] +.sym 18280 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 18281 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] +.sym 18282 io_ctrl_ins.led1_state_SB_LUT4_I1_O[0] +.sym 18285 i_config_SB_LUT4_I0_I1[2] +.sym 18286 o_tr_vc1$SB_IO_OUT +.sym 18287 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18288 io_ctrl_ins.pmod_dir_state[5] +.sym 18292 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 18294 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 18297 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 18298 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[2] .sym 18299 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[3] -.sym 18300 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 18303 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 18304 i_config[1]$SB_IO_IN -.sym 18305 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[2] -.sym 18306 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[3] -.sym 18313 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O +.sym 18300 io_ctrl_ins.o_pmod[3] +.sym 18303 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 18304 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18305 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 18306 o_tr_vc1_b$SB_IO_OUT +.sym 18309 i_config_SB_LUT4_I0_I1[0] +.sym 18310 io_ctrl_ins.pmod_dir_state[4] +.sym 18311 i_config[1]$SB_IO_IN +.sym 18312 i_config_SB_LUT4_I0_I1[2] +.sym 18313 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3_SB_LUT4_I3_O .sym 18314 r_counter_$glb_clk -.sym 18315 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S +.sym 18315 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R +.sym 18317 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] +.sym 18318 o_tr_vc1_b$SB_IO_OUT +.sym 18320 o_tr_vc2$SB_IO_OUT +.sym 18321 o_tr_vc1$SB_IO_OUT +.sym 18323 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 18329 lvds_rx_24_inst.o_debug_state[0] +.sym 18337 lvds_rx_24_inst.o_debug_state[1] +.sym 18338 i_config_SB_LUT4_I0_I1[0] +.sym 18341 i_config[1]$SB_IO_IN .sym 18345 i_config[2]$SB_IO_IN +.sym 18357 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18358 i_button_SB_LUT4_I0_O[1] +.sym 18360 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] +.sym 18362 i_config_SB_LUT4_I0_I1[2] +.sym 18363 io_ctrl_ins.pmod_dir_state[3] +.sym 18364 o_rx_h_tx_l$SB_IO_OUT +.sym 18365 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18366 i_button_SB_LUT4_I0_O[0] +.sym 18368 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] +.sym 18369 io_ctrl_ins.debug_mode[0] +.sym 18370 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 18372 i_config_SB_LUT4_I0_I1[0] +.sym 18373 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18375 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18376 io_ctrl_ins.debug_mode[1] +.sym 18381 i_config[3]$SB_IO_IN +.sym 18383 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] +.sym 18384 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 18385 i_button$SB_IO_IN +.sym 18387 i_config[0]$SB_IO_IN +.sym 18388 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] +.sym 18391 i_button_SB_LUT4_I0_O[1] +.sym 18392 i_button_SB_LUT4_I0_O[0] +.sym 18396 i_button$SB_IO_IN +.sym 18397 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18398 o_rx_h_tx_l$SB_IO_OUT +.sym 18399 i_config_SB_LUT4_I0_I1[0] +.sym 18404 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] +.sym 18405 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] +.sym 18408 io_ctrl_ins.debug_mode[0] +.sym 18410 io_ctrl_ins.debug_mode[1] +.sym 18414 i_config_SB_LUT4_I0_I1[0] +.sym 18415 i_config[0]$SB_IO_IN +.sym 18416 io_ctrl_ins.pmod_dir_state[3] +.sym 18417 i_config_SB_LUT4_I0_I1[2] +.sym 18421 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] +.sym 18422 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] +.sym 18426 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 18427 io_ctrl_ins.debug_mode[1] +.sym 18428 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 18429 io_ctrl_ins.debug_mode[0] +.sym 18432 i_config[3]$SB_IO_IN +.sym 18433 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 18434 o_rx_h_tx_l_b$SB_IO_OUT +.sym 18435 i_config_SB_LUT4_I0_I1[0] +.sym 18436 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E +.sym 18437 r_counter_$glb_clk +.sym 18438 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 18440 w_rx_24_fifo_data[5] +.sym 18445 i_config[0]$SB_IO_IN +.sym 18457 rx_24_fifo.wr_addr[0] +.sym 18468 lvds_rx_24_inst.r_data[3] +.sym 18491 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 18507 w_rx_data[3] +.sym 18551 w_rx_data[3] +.sym 18559 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 18560 r_counter_$glb_clk .sym 18562 i_config[1]$SB_IO_IN .sym 18564 i_config[2]$SB_IO_IN -.sym 18591 i_config[1]$SB_IO_IN +.sym 18575 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O +.sym 18580 lvds_rx_24_inst.o_debug_state[1] .sym 18636 w_smi_data_output[4] .sym 18638 i_smi_a3$SB_IO_IN .sym 18641 i_smi_a3$SB_IO_IN .sym 18645 i_smi_a3$SB_IO_IN .sym 18653 i_smi_a3$SB_IO_IN .sym 18660 w_smi_data_output[4] -.sym 18662 w_rx_09_fifo_pulled_data[4] -.sym 18666 w_rx_09_fifo_pulled_data[5] -.sym 18683 $PACKER_VCC_NET -.sym 18704 lvds_rx_09_inst.r_data[31] -.sym 18706 lvds_rx_09_inst.r_data[30] -.sym 18710 lvds_rx_09_inst.r_data[29] -.sym 18713 lvds_rx_09_inst.r_data[28] -.sym 18732 $PACKER_VCC_NET -.sym 18742 lvds_rx_09_inst.r_data[30] -.sym 18751 lvds_rx_09_inst.r_data[28] -.sym 18761 lvds_rx_09_inst.r_data[31] -.sym 18769 $PACKER_VCC_NET -.sym 18773 lvds_rx_09_inst.r_data[29] -.sym 18782 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 18783 lvds_clock_$glb_clk +.sym 18662 w_rx_09_fifo_pulled_data[20] +.sym 18666 w_rx_09_fifo_pulled_data[21] +.sym 18695 i_ss$SB_IO_IN +.sym 18696 int_miso +.sym 18704 smi_ctrl_ins.int_cnt_09[4] +.sym 18705 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] +.sym 18706 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] +.sym 18707 smi_ctrl_ins.int_cnt_09[4] +.sym 18708 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] +.sym 18709 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] +.sym 18710 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] +.sym 18711 smi_ctrl_ins.int_cnt_09[3] +.sym 18712 smi_ctrl_ins.soe_and_reset +.sym 18713 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] +.sym 18714 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] +.sym 18715 i_smi_a2_SB_LUT4_I1_O[0] +.sym 18716 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] +.sym 18718 i_smi_a2_SB_LUT4_I1_O[0] +.sym 18720 w_rx_09_fifo_pulled_data[20] +.sym 18721 w_rx_09_fifo_pulled_data[5] +.sym 18724 w_rx_09_fifo_pulled_data[21] +.sym 18725 w_rx_09_fifo_pulled_data[6] +.sym 18726 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] +.sym 18728 w_rx_09_fifo_pulled_data[22] +.sym 18730 i_smi_a1_SB_LUT4_I1_O +.sym 18732 w_rx_09_fifo_pulled_data[4] +.sym 18742 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] +.sym 18743 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] +.sym 18744 i_smi_a2_SB_LUT4_I1_O[0] +.sym 18745 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] +.sym 18754 smi_ctrl_ins.int_cnt_09[3] +.sym 18755 w_rx_09_fifo_pulled_data[5] +.sym 18756 w_rx_09_fifo_pulled_data[21] +.sym 18757 smi_ctrl_ins.int_cnt_09[4] +.sym 18760 i_smi_a2_SB_LUT4_I1_O[0] +.sym 18761 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] +.sym 18762 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] +.sym 18763 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] +.sym 18766 smi_ctrl_ins.int_cnt_09[4] +.sym 18767 w_rx_09_fifo_pulled_data[22] +.sym 18768 smi_ctrl_ins.int_cnt_09[3] +.sym 18769 w_rx_09_fifo_pulled_data[6] +.sym 18772 w_rx_09_fifo_pulled_data[4] +.sym 18773 w_rx_09_fifo_pulled_data[20] +.sym 18774 smi_ctrl_ins.int_cnt_09[4] +.sym 18775 smi_ctrl_ins.int_cnt_09[3] +.sym 18778 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] +.sym 18779 i_smi_a2_SB_LUT4_I1_O[0] +.sym 18780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] +.sym 18781 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] +.sym 18782 i_smi_a1_SB_LUT4_I1_O +.sym 18783 smi_ctrl_ins.soe_and_reset .sym 18785 i_smi_soe_se$SB_IO_IN -.sym 18790 w_rx_09_fifo_pulled_data[6] -.sym 18794 w_rx_09_fifo_pulled_data[7] -.sym 18803 rx_09_fifo.wr_addr[6] -.sym 18809 rx_09_fifo.wr_addr[3] -.sym 18812 rx_09_fifo.wr_addr[5] -.sym 18821 rx_09_fifo.wr_addr[7] -.sym 18823 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 18826 w_smi_data_output[5] -.sym 18827 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 18835 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 18839 rx_09_fifo.wr_addr[8] -.sym 18858 w_smi_data_output[3] -.sym 18867 w_rx_09_fifo_pulled_data[4] -.sym 18868 i_smi_a1_SB_LUT4_I1_O -.sym 18871 w_rx_09_fifo_pulled_data[5] -.sym 18875 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_5_O[3] -.sym 18878 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_7_O[3] -.sym 18882 i_smi_a1_SB_LUT4_I1_O -.sym 18889 smi_ctrl_ins.int_cnt_09[4] -.sym 18891 w_rx_09_fifo_pulled_data[12] -.sym 18895 w_rx_09_fifo_pulled_data[13] -.sym 18897 smi_ctrl_ins.int_cnt_09[4] -.sym 18911 i_smi_a1_SB_LUT4_I1_O -.sym 18923 w_rx_09_fifo_pulled_data[13] -.sym 18924 w_rx_09_fifo_pulled_data[5] -.sym 18925 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_5_O[3] -.sym 18926 smi_ctrl_ins.int_cnt_09[4] -.sym 18929 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_7_O[3] -.sym 18930 w_rx_09_fifo_pulled_data[12] -.sym 18931 w_rx_09_fifo_pulled_data[4] -.sym 18932 smi_ctrl_ins.int_cnt_09[4] -.sym 18945 i_smi_a1_SB_LUT4_I1_O -.sym 18946 smi_ctrl_ins.soe_and_reset_$glb_clk +.sym 18790 w_rx_09_fifo_pulled_data[22] +.sym 18794 w_rx_09_fifo_pulled_data[23] +.sym 18800 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 18801 smi_ctrl_ins.int_cnt_09[3] +.sym 18802 smi_ctrl_ins.int_cnt_09[4] +.sym 18805 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] +.sym 18808 rx_09_fifo.wr_addr[9] +.sym 18809 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 18819 w_rx_09_fifo_pulled_data[6] +.sym 18821 w_rx_09_fifo_pulled_data[30] +.sym 18824 i_smi_a1_SB_LUT4_I1_O +.sym 18837 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 18838 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 18844 i_mosi$SB_IO_IN +.sym 18845 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 18846 w_rx_09_fifo_pulled_data[14] +.sym 18848 w_rx_09_fifo_pulled_data[31] +.sym 18853 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 18868 w_rx_09_fifo_pulled_data[14] +.sym 18869 spi_if_ins.r_tx_byte[7] +.sym 18872 smi_ctrl_ins.int_cnt_09[3] +.sym 18874 smi_ctrl_ins.int_cnt_09[4] +.sym 18877 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 18879 w_rx_09_fifo_pulled_data[30] +.sym 18880 smi_ctrl_ins.int_cnt_09[3] +.sym 18887 w_rx_09_fifo_pulled_data[13] +.sym 18888 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 18896 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 18897 w_rx_09_fifo_pulled_data[29] +.sym 18917 w_rx_09_fifo_pulled_data[13] +.sym 18918 w_rx_09_fifo_pulled_data[29] +.sym 18919 smi_ctrl_ins.int_cnt_09[4] +.sym 18920 smi_ctrl_ins.int_cnt_09[3] +.sym 18929 smi_ctrl_ins.int_cnt_09[4] +.sym 18930 w_rx_09_fifo_pulled_data[14] +.sym 18931 smi_ctrl_ins.int_cnt_09[3] +.sym 18932 w_rx_09_fifo_pulled_data[30] +.sym 18941 spi_if_ins.r_tx_byte[7] +.sym 18943 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 18944 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 18945 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 18946 r_counter_$glb_clk .sym 18949 w_rx_09_fifo_pulled_data[12] .sym 18953 w_rx_09_fifo_pulled_data[13] -.sym 18965 rx_09_fifo.rd_addr[8] -.sym 18966 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 18968 rx_09_fifo.rd_addr[1] -.sym 18974 rx_09_fifo.wr_addr[5] -.sym 18980 w_rx_09_fifo_data[22] -.sym 18982 w_smi_data_output[3] -.sym 18983 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 18991 lvds_rx_09_inst.r_data[21] -.sym 19006 w_rx_09_fifo_pulled_data[14] -.sym 19008 lvds_rx_09_inst.r_data[24] -.sym 19018 w_rx_09_fifo_pulled_data[15] -.sym 19028 w_rx_09_fifo_pulled_data[14] -.sym 19046 w_rx_09_fifo_pulled_data[15] -.sym 19052 lvds_rx_09_inst.r_data[24] -.sym 19067 lvds_rx_09_inst.r_data[21] -.sym 19068 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 19069 lvds_clock_$glb_clk +.sym 18970 smi_ctrl_ins.int_cnt_09[4] +.sym 18973 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 18974 w_rx_09_fifo_data[15] +.sym 18975 smi_ctrl_ins.int_cnt_09[3] +.sym 18977 rx_09_fifo.wr_addr[7] +.sym 18978 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 18979 w_rx_09_fifo_data[14] +.sym 18980 rx_09_fifo.wr_addr[8] +.sym 18981 rx_09_fifo.wr_addr[6] +.sym 18983 w_rx_09_fifo_pulled_data[29] +.sym 18991 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 18993 $PACKER_VCC_NET +.sym 19007 spi_if_ins.spi.r_tx_bit_count[2] +.sym 19008 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19009 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R +.sym 19010 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 19012 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 19021 $nextpnr_ICESTORM_LC_0$O +.sym 19023 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 19027 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 19029 $PACKER_VCC_NET +.sym 19030 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 19034 spi_if_ins.spi.r_tx_bit_count[2] +.sym 19036 $PACKER_VCC_NET +.sym 19037 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 19043 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 19049 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19052 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 19053 $PACKER_VCC_NET +.sym 19054 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 19064 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 19068 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 19069 r_counter_$glb_clk +.sym 19070 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R .sym 19072 w_rx_09_fifo_pulled_data[14] .sym 19076 w_rx_09_fifo_pulled_data[15] -.sym 19083 $PACKER_VCC_NET -.sym 19088 rx_09_fifo.wr_addr[9] -.sym 19091 $PACKER_VCC_NET -.sym 19094 w_rx_09_fifo_data[20] -.sym 19095 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 19098 w_rx_09_fifo_pulled_data[18] -.sym 19101 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 19102 w_rx_09_fifo_pulled_data[2] -.sym 19106 w_rx_09_fifo_pulled_data[19] -.sym 19114 i_smi_a1_SB_LUT4_I1_O -.sym 19119 w_rx_09_fifo_pulled_data[25] -.sym 19122 w_rx_09_fifo_pulled_data[18] -.sym 19126 w_rx_09_fifo_pulled_data[27] -.sym 19127 w_rx_09_fifo_pulled_data[26] -.sym 19130 w_rx_09_fifo_pulled_data[19] -.sym 19132 smi_ctrl_ins.int_cnt_09[3] -.sym 19133 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_13_O[3] -.sym 19135 smi_ctrl_ins.int_cnt_09[4] -.sym 19137 w_rx_09_fifo_pulled_data[9] -.sym 19141 w_rx_09_fifo_pulled_data[17] -.sym 19143 w_rx_09_fifo_pulled_data[1] -.sym 19157 smi_ctrl_ins.int_cnt_09[3] -.sym 19158 w_rx_09_fifo_pulled_data[27] -.sym 19159 w_rx_09_fifo_pulled_data[19] -.sym 19160 smi_ctrl_ins.int_cnt_09[4] -.sym 19163 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_13_O[3] -.sym 19164 w_rx_09_fifo_pulled_data[1] -.sym 19165 smi_ctrl_ins.int_cnt_09[4] -.sym 19166 w_rx_09_fifo_pulled_data[9] -.sym 19175 w_rx_09_fifo_pulled_data[25] -.sym 19176 w_rx_09_fifo_pulled_data[17] -.sym 19177 smi_ctrl_ins.int_cnt_09[4] -.sym 19178 smi_ctrl_ins.int_cnt_09[3] -.sym 19181 w_rx_09_fifo_pulled_data[26] -.sym 19182 w_rx_09_fifo_pulled_data[18] -.sym 19183 smi_ctrl_ins.int_cnt_09[3] -.sym 19184 smi_ctrl_ins.int_cnt_09[4] -.sym 19191 i_smi_a1_SB_LUT4_I1_O -.sym 19192 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 19195 w_rx_09_fifo_pulled_data[16] -.sym 19199 w_rx_09_fifo_pulled_data[17] -.sym 19208 i_smi_a1_SB_LUT4_I1_O -.sym 19211 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 19214 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 19218 w_rx_09_fifo_data[23] -.sym 19220 rx_09_fifo.wr_addr[3] -.sym 19223 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 19227 rx_09_fifo.wr_addr[8] -.sym 19229 w_rx_09_fifo_pulled_data[1] -.sym 19238 w_rx_09_fifo_pulled_data[10] -.sym 19241 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_11_O[3] -.sym 19242 smi_ctrl_ins.int_cnt_09[4] -.sym 19245 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_9_O[3] -.sym 19246 i_smi_a1_SB_LUT4_I1_O -.sym 19250 smi_ctrl_ins.int_cnt_09[4] -.sym 19258 w_rx_09_fifo_pulled_data[11] -.sym 19262 w_rx_09_fifo_pulled_data[2] -.sym 19266 w_rx_09_fifo_pulled_data[3] -.sym 19298 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_9_O[3] -.sym 19299 w_rx_09_fifo_pulled_data[3] -.sym 19300 w_rx_09_fifo_pulled_data[11] -.sym 19301 smi_ctrl_ins.int_cnt_09[4] -.sym 19304 w_rx_09_fifo_pulled_data[2] -.sym 19305 w_rx_09_fifo_pulled_data[10] -.sym 19306 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_11_O[3] -.sym 19307 smi_ctrl_ins.int_cnt_09[4] -.sym 19314 i_smi_a1_SB_LUT4_I1_O -.sym 19315 smi_ctrl_ins.soe_and_reset_$glb_clk -.sym 19318 w_rx_09_fifo_pulled_data[18] -.sym 19322 w_rx_09_fifo_pulled_data[19] -.sym 19329 rx_09_fifo.wr_addr[5] -.sym 19332 rx_09_fifo.wr_addr[6] -.sym 19334 i_smi_a1_SB_LUT4_I1_O -.sym 19339 rx_09_fifo.wr_addr[4] -.sym 19341 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 19343 rx_09_fifo.rd_addr[4] -.sym 19344 rx_09_fifo.rd_addr[8] -.sym 19345 rx_09_fifo.rd_addr[5] -.sym 19346 rx_09_fifo.rd_addr[7] -.sym 19347 rx_09_fifo.rd_addr[6] -.sym 19350 rx_09_fifo.rd_addr[1] -.sym 19351 rx_09_fifo.rd_addr[9] -.sym 19352 w_rx_09_fifo_pulled_data[3] -.sym 19370 lvds_rx_09_inst.r_data[26] -.sym 19428 lvds_rx_09_inst.r_data[26] -.sym 19437 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce -.sym 19438 lvds_clock_$glb_clk -.sym 19441 w_rx_09_fifo_pulled_data[0] -.sym 19445 w_rx_09_fifo_pulled_data[1] -.sym 19453 rx_09_fifo.rd_addr[9] -.sym 19457 rx_09_fifo.rd_addr[1] -.sym 19459 rx_09_fifo.rd_addr[8] -.sym 19462 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 19466 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 19472 rx_09_fifo.wr_addr[5] -.sym 19473 w_rx_09_fifo_data[26] -.sym 19485 i_sck$SB_IO_IN -.sym 19487 spi_if_ins.spi.SCKr[1] -.sym 19510 spi_if_ins.spi.SCKr[0] -.sym 19523 spi_if_ins.spi.SCKr[1] -.sym 19547 i_sck$SB_IO_IN -.sym 19552 spi_if_ins.spi.SCKr[0] +.sym 19083 i_mosi$SB_IO_IN +.sym 19092 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 19096 $PACKER_VCC_NET +.sym 19097 i_smi_a1_SB_LUT4_I1_O +.sym 19098 w_rx_09_fifo_pulled_data[30] +.sym 19100 $PACKER_VCC_NET +.sym 19105 rx_09_fifo.rd_addr[0] +.sym 19106 rx_09_fifo.rd_addr[5] +.sym 19113 w_rx_09_fifo_pulled_data[12] +.sym 19114 spi_if_ins.spi.r_tx_bit_count[2] +.sym 19116 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 19119 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 19120 i_sck$SB_IO_IN +.sym 19125 w_rx_09_fifo_pulled_data[31] +.sym 19127 smi_ctrl_ins.int_cnt_09[4] +.sym 19129 spi_if_ins.spi.SCKr[0] +.sym 19133 w_rx_09_fifo_pulled_data[15] +.sym 19135 smi_ctrl_ins.int_cnt_09[3] +.sym 19137 w_rx_09_fifo_pulled_data[28] +.sym 19141 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19142 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 19151 i_sck$SB_IO_IN +.sym 19157 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 19159 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 19160 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 19163 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 19164 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 19165 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 19166 spi_if_ins.spi.r_tx_bit_count[2] +.sym 19172 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 19175 w_rx_09_fifo_pulled_data[12] +.sym 19176 smi_ctrl_ins.int_cnt_09[4] +.sym 19177 smi_ctrl_ins.int_cnt_09[3] +.sym 19178 w_rx_09_fifo_pulled_data[28] +.sym 19184 spi_if_ins.spi.SCKr[0] +.sym 19187 w_rx_09_fifo_pulled_data[15] +.sym 19188 w_rx_09_fifo_pulled_data[31] +.sym 19189 smi_ctrl_ins.int_cnt_09[3] +.sym 19190 smi_ctrl_ins.int_cnt_09[4] +.sym 19192 r_counter_$glb_clk +.sym 19195 w_rx_09_fifo_pulled_data[28] +.sym 19199 w_rx_09_fifo_pulled_data[29] +.sym 19207 rx_09_fifo.rd_addr[6] +.sym 19208 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 19211 rx_09_fifo.rd_addr[4] +.sym 19212 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 19213 rx_09_fifo.rd_addr[5] +.sym 19223 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 19224 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 19226 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 19228 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 19238 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19248 i_ss$SB_IO_IN +.sym 19261 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19266 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19267 $nextpnr_ICESTORM_LC_13$O +.sym 19269 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19273 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 19275 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19281 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19283 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 19288 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19304 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19305 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19306 i_ss$SB_IO_IN +.sym 19307 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19310 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19313 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19315 i_sck$SB_IO_IN_$glb_clk +.sym 19316 i_ss$SB_IO_IN +.sym 19318 w_rx_09_fifo_pulled_data[30] +.sym 19322 w_rx_09_fifo_pulled_data[31] +.sym 19331 rx_09_fifo.wr_addr[9] +.sym 19332 w_rx_09_fifo_data[5] +.sym 19336 rx_09_fifo.wr_addr[4] +.sym 19338 rx_09_fifo.wr_addr[5] +.sym 19341 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 19342 i_mosi$SB_IO_IN +.sym 19344 w_rx_09_fifo_pulled_data[31] +.sym 19346 spi_if_ins.w_rx_data[3] +.sym 19348 spi_if_ins.w_rx_data[1] +.sym 19350 spi_if_ins.w_rx_data[0] +.sym 19352 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 19358 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 19360 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19363 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 19367 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19368 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19369 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19373 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19405 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 19410 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 19418 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 19433 spi_if_ins.spi.r_rx_bit_count[2] +.sym 19434 spi_if_ins.spi.r_rx_bit_count[1] +.sym 19436 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19437 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19438 i_sck$SB_IO_IN_$glb_clk +.sym 19441 w_rx_09_fifo_pulled_data[8] +.sym 19445 w_rx_09_fifo_pulled_data[9] +.sym 19456 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19472 rx_09_fifo.wr_addr[8] +.sym 19473 spi_if_ins.spi.r_rx_byte[7] +.sym 19474 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 19475 rx_09_fifo.wr_addr[7] +.sym 19482 spi_if_ins.spi.r_rx_byte[1] +.sym 19483 spi_if_ins.spi.r_rx_byte[4] +.sym 19484 spi_if_ins.spi.r_rx_byte[6] +.sym 19485 spi_if_ins.spi.r_rx_byte[3] +.sym 19488 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19489 spi_if_ins.spi.r_rx_byte[5] +.sym 19492 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 19494 i_ss$SB_IO_IN +.sym 19495 spi_if_ins.spi.r_rx_byte[0] +.sym 19496 spi_if_ins.spi.r_rx_byte[2] +.sym 19514 spi_if_ins.spi.r_rx_byte[3] +.sym 19522 spi_if_ins.spi.r_rx_byte[1] +.sym 19529 spi_if_ins.spi.r_rx_byte[0] +.sym 19535 spi_if_ins.spi.r_rx_byte[4] +.sym 19540 spi_if_ins.spi.r_rx_byte[2] +.sym 19544 spi_if_ins.spi.r_rx_byte[6] +.sym 19552 i_ss$SB_IO_IN +.sym 19553 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 19556 spi_if_ins.spi.r_rx_byte[5] +.sym 19560 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .sym 19561 r_counter_$glb_clk -.sym 19564 w_rx_09_fifo_pulled_data[2] -.sym 19568 w_rx_09_fifo_pulled_data[3] -.sym 19578 w_rx_09_fifo_data[25] -.sym 19581 rx_09_fifo.wr_addr[9] -.sym 19585 $PACKER_VCC_NET -.sym 19586 rx_09_fifo.wr_addr[6] -.sym 19598 w_rx_09_fifo_pulled_data[2] -.sym 19608 i_ss$SB_IO_IN -.sym 19609 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19626 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19630 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19636 $nextpnr_ICESTORM_LC_2$O -.sym 19639 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19642 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 19645 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19650 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19652 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 19669 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19670 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19675 spi_if_ins.spi.r_rx_bit_count[0] +.sym 19564 w_rx_09_fifo_pulled_data[10] +.sym 19568 w_rx_09_fifo_pulled_data[11] +.sym 19576 w_rx_09_fifo_data[17] +.sym 19577 spi_if_ins.w_rx_data[6] +.sym 19585 spi_if_ins.w_rx_data[2] +.sym 19587 lvds_rx_24_inst.r_data[18] +.sym 19592 $PACKER_VCC_NET +.sym 19593 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 19594 w_rx_24_fifo_pulled_data[31] +.sym 19598 spi_if_ins.w_rx_data[5] +.sym 19605 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 19609 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 19611 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 19612 i_mosi$SB_IO_IN +.sym 19619 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 19631 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 19638 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 19643 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 19649 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 19676 i_mosi$SB_IO_IN +.sym 19681 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 19683 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O .sym 19684 i_sck$SB_IO_IN_$glb_clk -.sym 19685 i_ss$SB_IO_IN -.sym 19699 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 19704 w_rx_09_fifo_data[27] -.sym 19710 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 19729 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19734 i_ss$SB_IO_IN -.sym 19740 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19741 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19742 spi_if_ins.spi.r_rx_done -.sym 19745 spi_if_ins.spi.r2_rx_done -.sym 19757 spi_if_ins.spi.r3_rx_done -.sym 19760 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19761 i_ss$SB_IO_IN -.sym 19762 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19763 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19774 spi_if_ins.spi.r_rx_done -.sym 19786 spi_if_ins.spi.r2_rx_done -.sym 19787 spi_if_ins.spi.r3_rx_done -.sym 19798 spi_if_ins.spi.r2_rx_done -.sym 19802 spi_if_ins.spi.r_rx_bit_count[0] -.sym 19803 spi_if_ins.spi.r_rx_bit_count[1] -.sym 19805 spi_if_ins.spi.r_rx_bit_count[2] -.sym 19807 r_counter_$glb_clk -.sym 19960 spi_if_ins.w_rx_data[1] -.sym 19967 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 19975 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 19978 spi_if_ins.w_rx_data[1] -.sym 20043 spi_if_ins.w_rx_data[1] -.sym 20052 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 20053 r_counter_$glb_clk -.sym 20067 spi_if_ins.w_rx_data[5] -.sym 20075 $PACKER_VCC_NET -.sym 20077 spi_if_ins.w_rx_data[3] -.sym 20084 o_tr_vc2$SB_IO_OUT -.sym 20086 o_tr_vc1$SB_IO_OUT -.sym 20088 io_ctrl_ins.rf_mode[0] -.sym 20102 w_rx_data[1] -.sym 20107 io_ctrl_ins.led1_state_SB_DFFESR_Q_E -.sym 20119 w_rx_data[0] -.sym 20160 w_rx_data[1] -.sym 20168 w_rx_data[0] -.sym 20175 io_ctrl_ins.led1_state_SB_DFFESR_Q_E +.sym 19687 w_rx_24_fifo_pulled_data[20] +.sym 19691 w_rx_24_fifo_pulled_data[21] +.sym 19698 rx_09_fifo.rd_addr[4] +.sym 19699 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 19700 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 19704 rx_09_fifo.rd_addr[6] +.sym 19707 w_rx_09_fifo_pulled_data[10] +.sym 19708 rx_09_fifo.rd_addr[5] +.sym 19710 w_rx_24_fifo_pulled_data[5] +.sym 19712 rx_24_fifo.rd_addr[4] +.sym 19713 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 19714 w_rx_24_fifo_data[20] +.sym 19715 w_rx_09_fifo_data[18] +.sym 19716 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 19717 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19720 rx_24_fifo.wr_addr[7] +.sym 19721 w_rx_24_fifo_pulled_data[4] +.sym 19728 w_rx_24_fifo_pulled_data[4] +.sym 19730 lvds_rx_24_inst.r_data[12] +.sym 19732 lvds_rx_24_inst.r_data[27] +.sym 19733 smi_ctrl_ins.int_cnt_24[3] +.sym 19736 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19737 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19739 lvds_rx_24_inst.r_data[11] +.sym 19741 lvds_rx_24_inst.r_data[29] +.sym 19744 lvds_rx_24_inst.r_data[19] +.sym 19747 lvds_rx_24_inst.r_data[18] +.sym 19748 w_rx_24_fifo_pulled_data[23] +.sym 19752 w_rx_24_fifo_pulled_data[20] +.sym 19757 w_rx_24_fifo_pulled_data[7] +.sym 19763 lvds_rx_24_inst.r_data[12] +.sym 19768 lvds_rx_24_inst.r_data[29] +.sym 19775 lvds_rx_24_inst.r_data[19] +.sym 19778 w_rx_24_fifo_pulled_data[4] +.sym 19779 smi_ctrl_ins.int_cnt_24[3] +.sym 19780 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19781 w_rx_24_fifo_pulled_data[20] +.sym 19787 lvds_rx_24_inst.r_data[11] +.sym 19792 lvds_rx_24_inst.r_data[27] +.sym 19796 lvds_rx_24_inst.r_data[18] +.sym 19802 w_rx_24_fifo_pulled_data[7] +.sym 19803 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19804 w_rx_24_fifo_pulled_data[23] +.sym 19805 smi_ctrl_ins.int_cnt_24[3] +.sym 19806 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 19807 lvds_clock_$glb_clk +.sym 19810 w_rx_24_fifo_pulled_data[22] +.sym 19814 w_rx_24_fifo_pulled_data[23] +.sym 19823 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 19825 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 19826 rx_24_fifo.wr_addr[8] +.sym 19827 w_rx_24_fifo_data[12] +.sym 19829 rx_24_fifo.wr_addr[4] +.sym 19831 rx_24_fifo.wr_addr[3] +.sym 19833 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 19834 w_rx_24_fifo_data[21] +.sym 19835 rx_24_fifo.wr_addr[5] +.sym 19836 spi_if_ins.w_rx_data[1] +.sym 19837 rx_24_fifo.rd_addr[0] +.sym 19838 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 19839 spi_if_ins.w_rx_data[3] +.sym 19840 w_rx_24_fifo_data[29] +.sym 19841 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 19842 spi_if_ins.w_rx_data[0] +.sym 19843 w_rx_24_fifo_pulled_data[7] +.sym 19844 w_rx_24_fifo_pulled_data[15] +.sym 19850 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19851 w_rx_24_fifo_pulled_data[15] +.sym 19855 w_rx_24_fifo_pulled_data[21] +.sym 19856 smi_ctrl_ins.int_cnt_24[3] +.sym 19859 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19861 smi_ctrl_ins.int_cnt_24[4] +.sym 19864 w_rx_24_fifo_pulled_data[31] +.sym 19866 smi_ctrl_ins.soe_and_reset +.sym 19867 w_rx_24_fifo_pulled_data[22] +.sym 19868 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E +.sym 19869 smi_ctrl_ins.int_cnt_24[4] +.sym 19870 w_rx_24_fifo_pulled_data[5] +.sym 19872 w_rx_24_fifo_pulled_data[6] +.sym 19873 w_rx_24_fifo_pulled_data[28] +.sym 19875 w_rx_24_fifo_pulled_data[12] +.sym 19880 smi_ctrl_ins.int_cnt_24[3] +.sym 19889 w_rx_24_fifo_pulled_data[15] +.sym 19890 smi_ctrl_ins.int_cnt_24[4] +.sym 19891 w_rx_24_fifo_pulled_data[31] +.sym 19892 smi_ctrl_ins.int_cnt_24[3] +.sym 19895 w_rx_24_fifo_pulled_data[12] +.sym 19896 w_rx_24_fifo_pulled_data[28] +.sym 19897 smi_ctrl_ins.int_cnt_24[3] +.sym 19898 smi_ctrl_ins.int_cnt_24[4] +.sym 19901 smi_ctrl_ins.int_cnt_24[3] +.sym 19904 smi_ctrl_ins.int_cnt_24[4] +.sym 19907 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19908 w_rx_24_fifo_pulled_data[22] +.sym 19909 w_rx_24_fifo_pulled_data[6] +.sym 19910 smi_ctrl_ins.int_cnt_24[3] +.sym 19913 smi_ctrl_ins.int_cnt_24[3] +.sym 19914 w_rx_24_fifo_pulled_data[5] +.sym 19915 w_rx_24_fifo_pulled_data[21] +.sym 19916 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 19919 smi_ctrl_ins.int_cnt_24[3] +.sym 19929 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E +.sym 19930 smi_ctrl_ins.soe_and_reset +.sym 19931 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 19933 w_rx_24_fifo_pulled_data[12] +.sym 19937 w_rx_24_fifo_pulled_data[13] +.sym 19944 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 19945 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 19947 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 19951 rx_24_fifo.rd_addr[8] +.sym 19953 rx_24_fifo.rd_addr[0] +.sym 19954 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 19958 w_rx_24_fifo_pulled_data[6] +.sym 19959 w_rx_24_fifo_pulled_data[28] +.sym 19967 w_rx_24_fifo_pulled_data[29] +.sym 19973 i_glob_clock$SB_IO_IN +.sym 19974 w_rx_24_fifo_pulled_data[29] +.sym 19975 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 19976 smi_ctrl_ins.int_cnt_24[4] +.sym 19977 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 19978 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 19979 smi_ctrl_ins.int_cnt_24[3] +.sym 19980 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1] +.sym 19981 w_tx_data_io[4] +.sym 19983 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 19984 w_tx_data_smi[1] +.sym 19985 w_tx_data_io[6] +.sym 19986 w_tx_data_io[5] +.sym 19987 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 19989 w_tx_data_io[1] +.sym 19996 w_rx_24_fifo_pulled_data[30] +.sym 19998 w_rx_24_fifo_pulled_data[14] +.sym 20002 w_rx_24_fifo_pulled_data[13] +.sym 20006 w_rx_24_fifo_pulled_data[14] +.sym 20007 w_rx_24_fifo_pulled_data[30] +.sym 20008 smi_ctrl_ins.int_cnt_24[3] +.sym 20009 smi_ctrl_ins.int_cnt_24[4] +.sym 20012 w_rx_24_fifo_pulled_data[29] +.sym 20013 w_rx_24_fifo_pulled_data[13] +.sym 20014 smi_ctrl_ins.int_cnt_24[4] +.sym 20015 smi_ctrl_ins.int_cnt_24[3] +.sym 20018 w_tx_data_io[1] +.sym 20019 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 20020 w_tx_data_smi[1] +.sym 20021 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 20031 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 20033 w_tx_data_io[6] +.sym 20036 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 20038 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1] +.sym 20043 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 20045 w_tx_data_io[4] +.sym 20048 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 20050 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 20051 w_tx_data_io[5] +.sym 20052 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 20053 i_glob_clock$SB_IO_IN +.sym 20054 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 20056 w_rx_24_fifo_pulled_data[14] +.sym 20060 w_rx_24_fifo_pulled_data[15] +.sym 20067 i_glob_clock$SB_IO_IN +.sym 20069 rx_24_fifo.wr_addr[6] +.sym 20070 rx_24_fifo.wr_addr[8] +.sym 20073 w_tx_data_io[6] +.sym 20074 w_tx_data_io[5] +.sym 20076 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 20082 w_rx_24_fifo_pulled_data[30] +.sym 20083 $PACKER_VCC_NET +.sym 20085 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 20086 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 20087 io_ctrl_ins.o_pmod[5] +.sym 20090 w_rx_24_fifo_pulled_data[31] +.sym 20098 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O +.sym 20112 w_rx_data[5] +.sym 20122 w_rx_data[1] +.sym 20125 w_rx_data[0] +.sym 20129 w_rx_data[5] +.sym 20143 w_rx_data[0] +.sym 20156 w_rx_data[1] +.sym 20175 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O .sym 20176 r_counter_$glb_clk -.sym 20177 w_soft_reset_$glb_sr -.sym 20201 $PACKER_GND_NET -.sym 20208 o_rx_h_tx_l_b$SB_IO_OUT -.sym 20209 o_led1$SB_IO_OUT -.sym 20223 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20224 io_ctrl_ins.rf_pin_state[7] -.sym 20225 io_ctrl_ins.rf_mode[2] -.sym 20226 io_ctrl_ins.rf_pin_state[6] -.sym 20227 io_ctrl_ins.rf_pin_state[5] -.sym 20229 io_ctrl_ins.rf_mode[1] -.sym 20230 io_ctrl_ins.rf_pin_state[3] -.sym 20232 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20237 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 20238 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20248 io_ctrl_ins.rf_mode[0] -.sym 20252 io_ctrl_ins.rf_mode[2] -.sym 20253 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20254 io_ctrl_ins.rf_pin_state[3] -.sym 20255 io_ctrl_ins.rf_mode[1] -.sym 20258 io_ctrl_ins.rf_pin_state[5] -.sym 20260 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20261 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20270 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20272 io_ctrl_ins.rf_pin_state[7] -.sym 20273 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20276 io_ctrl_ins.rf_mode[2] -.sym 20277 io_ctrl_ins.rf_mode[1] -.sym 20278 io_ctrl_ins.rf_mode[0] -.sym 20279 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20282 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20283 io_ctrl_ins.rf_mode[0] -.sym 20284 io_ctrl_ins.rf_mode[1] -.sym 20285 io_ctrl_ins.rf_mode[2] -.sym 20294 io_ctrl_ins.rf_pin_state[6] -.sym 20296 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20297 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20298 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 20179 w_rx_24_fifo_pulled_data[28] +.sym 20183 w_rx_24_fifo_pulled_data[29] +.sym 20193 w_rx_24_fifo_data[22] +.sym 20195 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 20201 w_rx_24_fifo_data[23] +.sym 20204 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 20205 w_rx_24_fifo_pulled_data[4] +.sym 20206 rx_24_fifo.wr_addr[7] +.sym 20208 w_rx_data[1] +.sym 20209 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 20210 w_rx_data[3] +.sym 20212 rx_24_fifo.rd_addr[4] +.sym 20213 w_rx_24_fifo_pulled_data[5] +.sym 20221 w_rx_data[4] +.sym 20222 w_rx_data[0] +.sym 20228 w_rx_data[5] +.sym 20229 io_ctrl_ins.o_pmod[0] +.sym 20230 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 20236 w_rx_data[3] +.sym 20238 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 20239 io_ctrl_ins.debug_mode[0] +.sym 20246 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 20258 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 20259 io_ctrl_ins.debug_mode[0] +.sym 20260 io_ctrl_ins.o_pmod[0] +.sym 20261 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 20265 w_rx_data[0] +.sym 20271 w_rx_data[4] +.sym 20288 w_rx_data[5] +.sym 20296 w_rx_data[3] +.sym 20298 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O .sym 20299 r_counter_$glb_clk -.sym 20317 o_tr_vc1$SB_IO_OUT -.sym 20321 o_rx_h_tx_l$SB_IO_OUT -.sym 20328 o_rx_h_tx_l$SB_IO_OUT -.sym 20346 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20349 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20353 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 20362 io_ctrl_ins.rf_pin_state[4] -.sym 20364 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 20382 io_ctrl_ins.rf_pin_state[4] -.sym 20383 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 20384 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 20394 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 20421 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E +.sym 20302 w_rx_24_fifo_pulled_data[30] +.sym 20306 w_rx_24_fifo_pulled_data[31] +.sym 20314 w_rx_24_fifo_data[4] +.sym 20315 rx_24_fifo.wr_addr[2] +.sym 20318 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 20320 rx_24_fifo.wr_addr[8] +.sym 20321 rx_24_fifo.wr_addr[3] +.sym 20323 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 20327 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 20328 w_rx_24_fifo_data[29] +.sym 20329 rx_24_fifo.rd_addr[0] +.sym 20330 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 20332 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 20334 io_ctrl_ins.rf_pin_state[5] +.sym 20336 io_ctrl_ins.rf_pin_state[3] +.sym 20348 w_rx_data[0] +.sym 20354 o_tr_vc2$SB_IO_OUT +.sym 20355 i_config_SB_LUT4_I0_I1[0] +.sym 20357 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20358 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 20359 io_ctrl_ins.o_pmod[5] +.sym 20360 io_ctrl_ins.led1_state_SB_DFFESR_Q_E +.sym 20366 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 20367 i_config[2]$SB_IO_IN +.sym 20368 w_rx_data[1] +.sym 20370 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 20375 w_rx_data[0] +.sym 20387 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20388 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 20389 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 20390 o_tr_vc2$SB_IO_OUT +.sym 20393 io_ctrl_ins.o_pmod[5] +.sym 20394 i_config[2]$SB_IO_IN +.sym 20395 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 20396 i_config_SB_LUT4_I0_I1[0] +.sym 20414 w_rx_data[1] +.sym 20421 io_ctrl_ins.led1_state_SB_DFFESR_Q_E .sym 20422 r_counter_$glb_clk -.sym 20444 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 20568 o_tr_vc1_b$SB_IO_OUT -.sym 20579 i_config[0]$SB_IO_IN +.sym 20423 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 20425 w_rx_24_fifo_pulled_data[4] +.sym 20429 w_rx_24_fifo_pulled_data[5] +.sym 20436 o_led0$SB_IO_OUT +.sym 20437 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 20438 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 20440 rx_24_fifo.rd_addr[8] +.sym 20442 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 20445 rx_24_fifo.rd_addr[0] +.sym 20447 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 20454 w_rx_24_fifo_pulled_data[6] +.sym 20455 w_rx_24_fifo_data[5] +.sym 20457 o_led1$SB_IO_OUT +.sym 20467 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20468 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20469 io_ctrl_ins.rf_pin_state[0] +.sym 20471 io_ctrl_ins.rf_pin_state[4] +.sym 20472 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20473 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 20476 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 20487 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 20494 io_ctrl_ins.rf_pin_state[5] +.sym 20496 io_ctrl_ins.rf_pin_state[3] +.sym 20504 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 20505 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20506 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20507 io_ctrl_ins.rf_pin_state[0] +.sym 20511 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20512 io_ctrl_ins.rf_pin_state[4] +.sym 20513 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20522 io_ctrl_ins.rf_pin_state[3] +.sym 20523 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 20524 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20525 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20528 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 20529 io_ctrl_ins.rf_pin_state[5] +.sym 20530 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20540 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 20541 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 20542 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 20543 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 20544 io_ctrl_ins.debug_mode_SB_LUT4_I0_O +.sym 20545 r_counter_$glb_clk +.sym 20548 w_rx_24_fifo_pulled_data[6] +.sym 20552 w_rx_24_fifo_pulled_data[7] +.sym 20560 rx_24_fifo.wr_addr[8] +.sym 20561 rx_24_fifo.wr_addr[3] +.sym 20562 rx_24_fifo.wr_addr[6] +.sym 20564 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 20565 o_tr_vc1_b$SB_IO_OUT +.sym 20567 w_rx_24_fifo_data[28] +.sym 20568 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 20570 rx_24_fifo.wr_addr[5] +.sym 20576 o_tr_vc2$SB_IO_OUT +.sym 20578 o_tr_vc1$SB_IO_OUT +.sym 20610 i_config[0]$SB_IO_IN +.sym 20616 lvds_rx_24_inst.r_data[3] +.sym 20627 lvds_rx_24_inst.r_data[3] +.sym 20657 i_config[0]$SB_IO_IN +.sym 20667 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 20668 lvds_clock_$glb_clk .sym 20672 i_config[0]$SB_IO_IN -.sym 20697 o_led1$SB_IO_OUT +.sym 20685 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 20692 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 20696 rx_24_fifo.rd_addr[4] +.sym 20698 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] .sym 20748 w_smi_data_output[5] .sym 20750 i_smi_a3$SB_IO_IN -.sym 20765 i_smi_a3$SB_IO_IN +.sym 20758 i_smi_a3$SB_IO_IN .sym 20766 w_smi_data_output[5] .sym 20781 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 20805 i_smi_a3$SB_IO_IN -.sym 20812 w_rx_09_fifo_data[28] -.sym 20813 rx_09_fifo.wr_addr[3] -.sym 20814 rx_09_fifo.wr_addr[4] -.sym 20816 w_rx_09_fifo_data[29] -.sym 20818 rx_09_fifo.wr_addr[7] -.sym 20820 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 20822 rx_09_fifo.wr_addr[5] -.sym 20823 $PACKER_VCC_NET -.sym 20824 rx_09_fifo.wr_addr[9] -.sym 20825 rx_09_fifo.wr_addr[6] -.sym 20826 rx_09_fifo.wr_addr[8] -.sym 20832 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] +.sym 20791 rx_24_fifo.wr_addr[0] +.sym 20802 i_sck$SB_IO_IN +.sym 20804 i_mosi$SB_IO_IN +.sym 20810 rx_09_fifo.wr_addr[6] +.sym 20817 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 20818 rx_09_fifo.wr_addr[9] +.sym 20819 rx_09_fifo.wr_addr[4] +.sym 20820 rx_09_fifo.wr_addr[5] +.sym 20821 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 20823 rx_09_fifo.wr_addr[8] +.sym 20830 w_rx_09_fifo_data[12] +.sym 20831 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 20832 w_rx_09_fifo_data[13] .sym 20837 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 20839 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] +.sym 20839 $PACKER_VCC_NET +.sym 20840 rx_09_fifo.wr_addr[7] +.sym 20841 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] .sym 20844 i_mosi$SB_IO_IN -.sym 20862 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 20863 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 20865 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 20866 rx_09_fifo.wr_addr[3] +.sym 20862 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 20863 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 20865 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 20866 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 20867 rx_09_fifo.wr_addr[4] .sym 20868 rx_09_fifo.wr_addr[5] .sym 20869 rx_09_fifo.wr_addr[6] @@ -8248,67 +10488,71 @@ .sym 20872 rx_09_fifo.wr_addr[9] .sym 20873 lvds_clock_$glb_clk .sym 20874 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 20876 w_rx_09_fifo_data[28] -.sym 20880 w_rx_09_fifo_data[29] +.sym 20876 w_rx_09_fifo_data[12] +.sym 20880 w_rx_09_fifo_data[13] .sym 20883 $PACKER_VCC_NET -.sym 20894 rx_09_fifo.wr_addr[4] -.sym 20896 rx_09_fifo.wr_addr[9] -.sym 20906 int_miso -.sym 20914 o_miso_$_TBUF__Y_E -.sym 20931 rx_09_fifo.wr_addr[7] -.sym 20933 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 20952 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 20954 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 20955 rx_09_fifo.rd_addr[1] -.sym 20958 rx_09_fifo.rd_addr[8] -.sym 20959 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 20960 rx_09_fifo.rd_addr[7] -.sym 20961 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 20963 rx_09_fifo.rd_addr[6] +.sym 20889 rx_09_fifo.wr_addr[4] +.sym 20890 rx_09_fifo.wr_addr[5] +.sym 20895 rx_09_fifo.wr_addr[8] +.sym 20897 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 20898 rx_09_fifo.wr_addr[6] +.sym 20904 i_ss_SB_LUT4_I3_O +.sym 20908 $PACKER_VCC_NET +.sym 20914 $PACKER_VCC_NET +.sym 20919 rx_09_fifo.rd_addr[1] +.sym 20922 $PACKER_VCC_NET +.sym 20925 rx_09_fifo.rd_addr[9] +.sym 20926 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 20954 rx_09_fifo.rd_addr[0] +.sym 20963 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 20965 $PACKER_VCC_NET -.sym 20971 rx_09_fifo.rd_addr[9] -.sym 20972 w_rx_09_fifo_data[31] -.sym 20975 rx_09_fifo.rd_addr[5] -.sym 20977 w_rx_09_fifo_data[30] -.sym 20981 rx_09_fifo.rd_addr[4] -.sym 21000 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 20966 rx_09_fifo.rd_addr[5] +.sym 20968 rx_09_fifo.rd_addr[4] +.sym 20971 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 20972 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 20974 w_rx_09_fifo_data[15] +.sym 20975 rx_09_fifo.rd_addr[1] +.sym 20977 rx_09_fifo.rd_addr[6] +.sym 20978 rx_09_fifo.rd_addr[9] +.sym 20979 w_rx_09_fifo_data[14] +.sym 20981 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 20982 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 21000 rx_09_fifo.rd_addr[0] .sym 21001 rx_09_fifo.rd_addr[1] -.sym 21003 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 21004 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 21003 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21004 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 21005 rx_09_fifo.rd_addr[4] .sym 21006 rx_09_fifo.rd_addr[5] .sym 21007 rx_09_fifo.rd_addr[6] -.sym 21008 rx_09_fifo.rd_addr[7] -.sym 21009 rx_09_fifo.rd_addr[8] +.sym 21008 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21009 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 21010 rx_09_fifo.rd_addr[9] .sym 21011 r_counter_$glb_clk -.sym 21012 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 21012 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 21013 $PACKER_VCC_NET -.sym 21017 w_rx_09_fifo_data[31] -.sym 21021 w_rx_09_fifo_data[30] -.sym 21031 rx_09_fifo.rd_addr[6] -.sym 21035 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 21036 rx_09_fifo.rd_addr[7] -.sym 21041 rx_09_fifo.rd_addr[5] -.sym 21047 rx_09_fifo.rd_addr[4] -.sym 21054 rx_09_fifo.wr_addr[8] -.sym 21056 rx_09_fifo.wr_addr[4] -.sym 21057 rx_09_fifo.wr_addr[3] -.sym 21058 w_rx_09_fifo_data[20] -.sym 21060 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 21062 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21063 rx_09_fifo.wr_addr[6] -.sym 21065 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] +.sym 21017 w_rx_09_fifo_data[15] +.sym 21021 w_rx_09_fifo_data[14] +.sym 21025 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21030 rx_09_fifo.rd_addr[0] +.sym 21049 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 21054 w_rx_09_fifo_data[21] +.sym 21056 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 21060 w_rx_09_fifo_data[20] +.sym 21063 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] .sym 21067 $PACKER_VCC_NET -.sym 21068 rx_09_fifo.wr_addr[9] -.sym 21069 w_rx_09_fifo_data[21] -.sym 21072 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 21073 rx_09_fifo.wr_addr[5] -.sym 21075 rx_09_fifo.wr_addr[7] -.sym 21102 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 21103 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21105 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 21106 rx_09_fifo.wr_addr[3] +.sym 21070 rx_09_fifo.wr_addr[6] +.sym 21071 rx_09_fifo.wr_addr[9] +.sym 21072 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 21074 rx_09_fifo.wr_addr[4] +.sym 21075 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21078 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 21079 rx_09_fifo.wr_addr[8] +.sym 21082 rx_09_fifo.wr_addr[7] +.sym 21084 rx_09_fifo.wr_addr[5] +.sym 21102 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 21103 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21105 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 21106 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 21107 rx_09_fifo.wr_addr[4] .sym 21108 rx_09_fifo.wr_addr[5] .sym 21109 rx_09_fifo.wr_addr[6] @@ -8320,74 +10564,73 @@ .sym 21116 w_rx_09_fifo_data[20] .sym 21120 w_rx_09_fifo_data[21] .sym 21123 $PACKER_VCC_NET -.sym 21128 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21129 rx_09_fifo.wr_addr[6] -.sym 21131 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 21132 rx_09_fifo.wr_addr[4] -.sym 21133 rx_09_fifo.wr_addr[3] -.sym 21136 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 21138 rx_09_fifo.wr_addr[8] -.sym 21144 o_miso_$_TBUF__Y_E -.sym 21146 int_miso -.sym 21147 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 21156 rx_09_fifo.rd_addr[8] -.sym 21158 rx_09_fifo.rd_addr[4] -.sym 21159 rx_09_fifo.rd_addr[5] -.sym 21160 w_rx_09_fifo_data[22] -.sym 21162 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 21164 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 21166 rx_09_fifo.rd_addr[9] -.sym 21167 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 21168 rx_09_fifo.rd_addr[7] -.sym 21169 rx_09_fifo.rd_addr[6] -.sym 21170 rx_09_fifo.rd_addr[1] -.sym 21171 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 21176 w_rx_09_fifo_data[23] -.sym 21185 $PACKER_VCC_NET -.sym 21204 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 21136 w_rx_09_fifo_data[20] +.sym 21138 w_rx_09_fifo_data[21] +.sym 21140 rx_09_fifo.rd_addr[6] +.sym 21141 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 21143 $PACKER_VCC_NET +.sym 21144 i_ss_SB_LUT4_I3_O +.sym 21145 lvds_rx_24_inst.o_debug_state[0] +.sym 21146 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 21150 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21151 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21157 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21160 rx_09_fifo.rd_addr[6] +.sym 21162 rx_09_fifo.rd_addr[4] +.sym 21163 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 21164 rx_09_fifo.rd_addr[5] +.sym 21167 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 21171 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 21173 rx_09_fifo.rd_addr[9] +.sym 21174 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21176 $PACKER_VCC_NET +.sym 21181 w_rx_09_fifo_data[22] +.sym 21183 rx_09_fifo.rd_addr[0] +.sym 21184 rx_09_fifo.rd_addr[1] +.sym 21187 w_rx_09_fifo_data[23] +.sym 21191 spi_if_ins.spi.r_rx_done +.sym 21204 rx_09_fifo.rd_addr[0] .sym 21205 rx_09_fifo.rd_addr[1] -.sym 21207 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 21208 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 21207 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21208 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 21209 rx_09_fifo.rd_addr[4] .sym 21210 rx_09_fifo.rd_addr[5] .sym 21211 rx_09_fifo.rd_addr[6] -.sym 21212 rx_09_fifo.rd_addr[7] -.sym 21213 rx_09_fifo.rd_addr[8] +.sym 21212 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21213 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 21214 rx_09_fifo.rd_addr[9] .sym 21215 r_counter_$glb_clk -.sym 21216 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 21216 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 21217 $PACKER_VCC_NET .sym 21221 w_rx_09_fifo_data[23] .sym 21225 w_rx_09_fifo_data[22] -.sym 21230 rx_09_fifo.rd_addr[8] -.sym 21232 rx_09_fifo.rd_addr[4] -.sym 21234 rx_09_fifo.rd_addr[9] -.sym 21235 rx_09_fifo.rd_addr[5] -.sym 21236 rx_09_fifo.rd_addr[7] -.sym 21237 rx_09_fifo.rd_addr[6] -.sym 21238 rx_09_fifo.rd_addr[1] -.sym 21240 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 21242 $PACKER_VCC_NET -.sym 21247 $PACKER_VCC_NET -.sym 21248 w_rx_09_fifo_data[24] -.sym 21262 $PACKER_VCC_NET -.sym 21263 rx_09_fifo.wr_addr[5] -.sym 21264 rx_09_fifo.wr_addr[6] -.sym 21266 rx_09_fifo.wr_addr[7] -.sym 21267 w_rx_09_fifo_data[9] -.sym 21269 w_rx_09_fifo_data[8] -.sym 21270 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21271 rx_09_fifo.wr_addr[4] -.sym 21274 rx_09_fifo.wr_addr[8] -.sym 21277 rx_09_fifo.wr_addr[3] -.sym 21278 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 21281 rx_09_fifo.wr_addr[9] -.sym 21283 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] +.sym 21243 rx_09_fifo.rd_addr[9] +.sym 21245 $PACKER_VCC_NET +.sym 21248 rx_09_fifo.rd_addr[1] +.sym 21250 rx_09_fifo.wr_addr[9] +.sym 21253 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 21258 rx_09_fifo.wr_addr[4] +.sym 21262 rx_09_fifo.wr_addr[8] +.sym 21264 w_rx_09_fifo_data[5] +.sym 21265 rx_09_fifo.wr_addr[9] +.sym 21266 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 21268 rx_09_fifo.wr_addr[5] +.sym 21269 w_rx_09_fifo_data[4] +.sym 21270 rx_09_fifo.wr_addr[7] +.sym 21271 $PACKER_VCC_NET +.sym 21274 rx_09_fifo.wr_addr[6] +.sym 21278 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 21283 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] .sym 21285 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 21306 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 21307 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21309 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 21310 rx_09_fifo.wr_addr[3] +.sym 21286 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21291 spi_if_ins.spi.r3_rx_done +.sym 21292 spi_if_ins.spi.r2_rx_done +.sym 21295 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 21296 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 21306 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 21307 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21309 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 21310 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 21311 rx_09_fifo.wr_addr[4] .sym 21312 rx_09_fifo.wr_addr[5] .sym 21313 rx_09_fifo.wr_addr[6] @@ -8396,69 +10639,65 @@ .sym 21316 rx_09_fifo.wr_addr[9] .sym 21317 lvds_clock_$glb_clk .sym 21318 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 21320 w_rx_09_fifo_data[8] -.sym 21324 w_rx_09_fifo_data[9] +.sym 21320 w_rx_09_fifo_data[4] +.sym 21324 w_rx_09_fifo_data[5] .sym 21327 $PACKER_VCC_NET -.sym 21332 rx_09_fifo.wr_addr[7] -.sym 21333 w_rx_09_fifo_data[9] -.sym 21337 w_rx_09_fifo_data[8] -.sym 21347 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 21354 rx_09_fifo.wr_addr[7] -.sym 21355 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 21360 rx_09_fifo.rd_addr[8] -.sym 21362 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 21369 w_rx_09_fifo_data[10] -.sym 21372 rx_09_fifo.rd_addr[9] -.sym 21373 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 21374 rx_09_fifo.rd_addr[1] -.sym 21375 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 21377 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 21380 $PACKER_VCC_NET -.sym 21381 rx_09_fifo.rd_addr[5] -.sym 21385 w_rx_09_fifo_data[11] -.sym 21387 rx_09_fifo.rd_addr[4] -.sym 21388 rx_09_fifo.rd_addr[7] -.sym 21391 rx_09_fifo.rd_addr[6] -.sym 21408 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 21337 w_rx_09_fifo_data[4] +.sym 21338 rx_09_fifo.wr_addr[8] +.sym 21347 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 21351 rx_09_fifo.rd_addr[1] +.sym 21362 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 21366 w_rx_09_fifo_data[6] +.sym 21368 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 21369 rx_09_fifo.rd_addr[6] +.sym 21370 rx_09_fifo.rd_addr[5] +.sym 21371 rx_09_fifo.rd_addr[0] +.sym 21378 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21379 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21381 rx_09_fifo.rd_addr[9] +.sym 21385 rx_09_fifo.rd_addr[4] +.sym 21386 rx_09_fifo.rd_addr[1] +.sym 21387 w_rx_09_fifo_data[7] +.sym 21389 $PACKER_VCC_NET +.sym 21391 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 21395 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 21408 rx_09_fifo.rd_addr[0] .sym 21409 rx_09_fifo.rd_addr[1] -.sym 21411 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 21412 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 21411 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21412 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 21413 rx_09_fifo.rd_addr[4] .sym 21414 rx_09_fifo.rd_addr[5] .sym 21415 rx_09_fifo.rd_addr[6] -.sym 21416 rx_09_fifo.rd_addr[7] -.sym 21417 rx_09_fifo.rd_addr[8] +.sym 21416 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21417 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 21418 rx_09_fifo.rd_addr[9] .sym 21419 r_counter_$glb_clk -.sym 21420 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 21420 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 21421 $PACKER_VCC_NET -.sym 21425 w_rx_09_fifo_data[11] -.sym 21429 w_rx_09_fifo_data[10] -.sym 21435 w_rx_09_fifo_data[10] -.sym 21456 w_rx_09_fifo_pulled_data[0] -.sym 21462 rx_09_fifo.wr_addr[8] -.sym 21463 rx_09_fifo.wr_addr[9] -.sym 21464 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 21466 rx_09_fifo.wr_addr[6] -.sym 21468 w_rx_09_fifo_data[25] -.sym 21470 rx_09_fifo.wr_addr[3] -.sym 21471 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 21473 rx_09_fifo.wr_addr[4] -.sym 21475 $PACKER_VCC_NET -.sym 21476 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21477 w_rx_09_fifo_data[24] -.sym 21479 rx_09_fifo.wr_addr[5] +.sym 21425 w_rx_09_fifo_data[7] +.sym 21429 w_rx_09_fifo_data[6] +.sym 21442 w_rx_09_fifo_data[6] +.sym 21448 rx_09_fifo.rd_addr[0] +.sym 21454 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 21466 w_rx_09_fifo_data[17] +.sym 21471 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 21473 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 21474 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21475 w_rx_09_fifo_data[16] +.sym 21479 rx_09_fifo.wr_addr[9] +.sym 21480 rx_09_fifo.wr_addr[6] +.sym 21481 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 21482 $PACKER_VCC_NET +.sym 21484 rx_09_fifo.wr_addr[4] +.sym 21487 rx_09_fifo.wr_addr[8] +.sym 21488 rx_09_fifo.wr_addr[7] .sym 21489 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 21492 rx_09_fifo.wr_addr[7] -.sym 21494 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 21495 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 21496 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 21499 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 21501 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 21510 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 21511 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21513 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 21514 rx_09_fifo.wr_addr[3] +.sym 21492 rx_09_fifo.wr_addr[5] +.sym 21499 spi_if_ins.state_if[0] +.sym 21510 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 21511 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21513 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 21514 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] .sym 21515 rx_09_fifo.wr_addr[4] .sym 21516 rx_09_fifo.wr_addr[5] .sym 21517 rx_09_fifo.wr_addr[6] @@ -8467,1154 +10706,2022 @@ .sym 21520 rx_09_fifo.wr_addr[9] .sym 21521 lvds_clock_$glb_clk .sym 21522 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O -.sym 21524 w_rx_09_fifo_data[24] -.sym 21528 w_rx_09_fifo_data[25] +.sym 21524 w_rx_09_fifo_data[16] +.sym 21528 w_rx_09_fifo_data[17] .sym 21531 $PACKER_VCC_NET -.sym 21536 rx_09_fifo.wr_addr[3] -.sym 21537 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 21539 rx_09_fifo.wr_addr[4] -.sym 21540 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 21544 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 21546 rx_09_fifo.wr_addr[8] -.sym 21554 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 21555 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 21557 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 21558 o_miso_$_TBUF__Y_E -.sym 21565 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 21566 rx_09_fifo.rd_addr[8] -.sym 21567 rx_09_fifo.rd_addr[9] -.sym 21568 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 21535 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 21550 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 21553 lvds_rx_24_inst.o_debug_state[0] +.sym 21555 $PACKER_VCC_NET +.sym 21566 rx_09_fifo.mem_i.0.0.0_RCLKE +.sym 21567 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 21569 rx_09_fifo.rd_addr[5] -.sym 21570 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 21572 rx_09_fifo.rd_addr[1] -.sym 21573 w_rx_09_fifo_data[27] -.sym 21575 rx_09_fifo.rd_addr[4] -.sym 21576 rx_09_fifo.rd_addr[7] -.sym 21577 w_rx_09_fifo_data[26] -.sym 21579 rx_09_fifo.rd_addr[6] -.sym 21582 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 21584 $PACKER_VCC_NET -.sym 21597 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 21598 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 21599 spi_if_ins.w_rx_data[1] -.sym 21602 spi_if_ins.w_rx_data[4] -.sym 21603 spi_if_ins.w_rx_data[6] -.sym 21612 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] +.sym 21573 rx_09_fifo.rd_addr[6] +.sym 21576 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21577 rx_09_fifo.rd_addr[4] +.sym 21578 rx_09_fifo.rd_addr[1] +.sym 21579 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 21580 w_rx_09_fifo_data[19] +.sym 21584 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21586 rx_09_fifo.rd_addr[0] +.sym 21589 w_rx_09_fifo_data[18] +.sym 21593 $PACKER_VCC_NET +.sym 21594 rx_09_fifo.rd_addr[9] +.sym 21597 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 21599 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 21600 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 21601 $PACKER_VCC_NET +.sym 21612 rx_09_fifo.rd_addr[0] .sym 21613 rx_09_fifo.rd_addr[1] -.sym 21615 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 21616 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] +.sym 21615 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 21616 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 21617 rx_09_fifo.rd_addr[4] .sym 21618 rx_09_fifo.rd_addr[5] .sym 21619 rx_09_fifo.rd_addr[6] -.sym 21620 rx_09_fifo.rd_addr[7] -.sym 21621 rx_09_fifo.rd_addr[8] +.sym 21620 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 21621 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] .sym 21622 rx_09_fifo.rd_addr[9] .sym 21623 r_counter_$glb_clk -.sym 21624 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O +.sym 21624 rx_09_fifo.mem_i.0.0.0_RCLKE .sym 21625 $PACKER_VCC_NET -.sym 21629 w_rx_09_fifo_data[27] -.sym 21633 w_rx_09_fifo_data[26] -.sym 21650 $PACKER_VCC_NET -.sym 21698 spi_if_ins.spi.r_rx_byte[5] -.sym 21699 spi_if_ins.spi.r_rx_byte[3] -.sym 21700 spi_if_ins.spi.r_rx_byte[2] -.sym 21701 spi_if_ins.spi.r_rx_byte[4] -.sym 21704 spi_if_ins.spi.r_rx_byte[0] -.sym 21743 spi_if_ins.w_rx_data[1] -.sym 21800 spi_if_ins.w_rx_data[3] -.sym 21802 spi_if_ins.w_rx_data[0] -.sym 21804 spi_if_ins.w_rx_data[5] -.sym 21806 spi_if_ins.w_rx_data[2] -.sym 21953 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 22165 o_led0$SB_IO_OUT -.sym 22252 o_tr_vc2$SB_IO_OUT -.sym 22258 o_tr_vc1$SB_IO_OUT -.sym 22361 o_rx_h_tx_l_b$SB_IO_OUT +.sym 21629 w_rx_09_fifo_data[19] +.sym 21633 w_rx_09_fifo_data[18] +.sym 21637 rx_24_fifo.rd_addr[1] +.sym 21640 w_rx_09_fifo_pulled_data[11] +.sym 21649 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 21650 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 21655 rx_24_fifo.rd_addr[6] +.sym 21657 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 21660 $PACKER_VCC_NET +.sym 21661 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 21668 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 21670 w_rx_24_fifo_data[13] +.sym 21671 rx_24_fifo.wr_addr[3] +.sym 21672 rx_24_fifo.wr_addr[8] +.sym 21673 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 21675 w_rx_24_fifo_data[12] +.sym 21677 rx_24_fifo.wr_addr[4] +.sym 21679 rx_24_fifo.wr_addr[2] +.sym 21685 rx_24_fifo.wr_addr[7] +.sym 21686 rx_24_fifo.wr_addr[0] +.sym 21693 rx_24_fifo.wr_addr[6] +.sym 21694 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21695 $PACKER_VCC_NET +.sym 21696 rx_24_fifo.wr_addr[5] +.sym 21699 r_tx_data[7] +.sym 21700 r_tx_data[3] +.sym 21701 $PACKER_VCC_NET +.sym 21702 $PACKER_VCC_NET +.sym 21714 rx_24_fifo.wr_addr[0] +.sym 21715 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21717 rx_24_fifo.wr_addr[2] +.sym 21718 rx_24_fifo.wr_addr[3] +.sym 21719 rx_24_fifo.wr_addr[4] +.sym 21720 rx_24_fifo.wr_addr[5] +.sym 21721 rx_24_fifo.wr_addr[6] +.sym 21722 rx_24_fifo.wr_addr[7] +.sym 21723 rx_24_fifo.wr_addr[8] +.sym 21724 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 21725 lvds_clock_$glb_clk +.sym 21726 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 21728 w_rx_24_fifo_data[12] +.sym 21732 w_rx_24_fifo_data[13] +.sym 21735 $PACKER_VCC_NET +.sym 21738 w_rx_24_fifo_pulled_data[7] +.sym 21747 rx_24_fifo.wr_addr[2] +.sym 21750 spi_if_ins.spi.r_rx_byte[7] +.sym 21752 rx_24_fifo.rd_addr[8] +.sym 21753 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 21755 lvds_rx_24_inst.o_debug_state[1] +.sym 21756 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 21757 rx_24_fifo.wr_addr[2] +.sym 21758 rx_24_fifo.wr_addr[3] +.sym 21759 rx_24_fifo.wr_addr[4] +.sym 21760 rx_24_fifo.rd_addr[1] +.sym 21761 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 21762 rx_24_fifo.wr_addr[5] +.sym 21763 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 21768 rx_24_fifo.rd_addr[8] +.sym 21770 rx_24_fifo.rd_addr[0] +.sym 21772 $PACKER_VCC_NET +.sym 21773 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21774 rx_24_fifo.rd_addr[4] +.sym 21775 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 21780 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 21781 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 21782 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 21784 w_rx_24_fifo_data[14] +.sym 21785 rx_24_fifo.rd_addr[1] +.sym 21788 w_rx_24_fifo_data[15] +.sym 21793 rx_24_fifo.rd_addr[6] +.sym 21795 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 21805 r_tx_data[0] +.sym 21816 rx_24_fifo.rd_addr[0] +.sym 21817 rx_24_fifo.rd_addr[1] +.sym 21819 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 21820 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 21821 rx_24_fifo.rd_addr[4] +.sym 21822 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 21823 rx_24_fifo.rd_addr[6] +.sym 21824 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21825 rx_24_fifo.rd_addr[8] +.sym 21826 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 21827 r_counter_$glb_clk +.sym 21828 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 21829 $PACKER_VCC_NET +.sym 21833 w_rx_24_fifo_data[15] +.sym 21837 w_rx_24_fifo_data[14] +.sym 21845 $PACKER_VCC_NET +.sym 21854 w_rx_24_fifo_data[15] +.sym 21856 $PACKER_VCC_NET +.sym 21863 lvds_rx_24_inst.r_data[5] +.sym 21865 w_rx_24_fifo_data[31] +.sym 21871 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21874 $PACKER_VCC_NET +.sym 21875 rx_24_fifo.wr_addr[7] +.sym 21876 rx_24_fifo.wr_addr[8] +.sym 21881 w_rx_24_fifo_data[20] +.sym 21882 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 21883 w_rx_24_fifo_data[21] +.sym 21885 rx_24_fifo.wr_addr[6] +.sym 21888 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 21890 rx_24_fifo.wr_addr[0] +.sym 21895 rx_24_fifo.wr_addr[2] +.sym 21896 rx_24_fifo.wr_addr[3] +.sym 21897 rx_24_fifo.wr_addr[4] +.sym 21900 rx_24_fifo.wr_addr[5] +.sym 21906 w_tx_data_smi[3] +.sym 21918 rx_24_fifo.wr_addr[0] +.sym 21919 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 21921 rx_24_fifo.wr_addr[2] +.sym 21922 rx_24_fifo.wr_addr[3] +.sym 21923 rx_24_fifo.wr_addr[4] +.sym 21924 rx_24_fifo.wr_addr[5] +.sym 21925 rx_24_fifo.wr_addr[6] +.sym 21926 rx_24_fifo.wr_addr[7] +.sym 21927 rx_24_fifo.wr_addr[8] +.sym 21928 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 21929 lvds_clock_$glb_clk +.sym 21930 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 21932 w_rx_24_fifo_data[20] +.sym 21936 w_rx_24_fifo_data[21] +.sym 21939 $PACKER_VCC_NET +.sym 21943 rx_24_fifo.wr_addr[0] +.sym 21947 w_rx_24_fifo_data[20] +.sym 21950 w_tx_data_sys[0] +.sym 21951 rx_24_fifo.wr_addr[7] +.sym 21956 w_rx_24_fifo_data[30] +.sym 21961 lvds_rx_24_inst.o_debug_state[0] +.sym 21976 w_rx_24_fifo_data[23] +.sym 21977 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 21978 w_rx_24_fifo_data[22] +.sym 21980 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 21981 rx_24_fifo.rd_addr[8] +.sym 21985 rx_24_fifo.rd_addr[0] +.sym 21986 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 21989 rx_24_fifo.rd_addr[1] +.sym 21990 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 21991 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 21994 rx_24_fifo.rd_addr[4] +.sym 21997 rx_24_fifo.rd_addr[6] +.sym 22001 $PACKER_VCC_NET +.sym 22003 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 22004 w_rx_24_fifo_data[7] +.sym 22009 w_lvds_rx_24_d0 +.sym 22020 rx_24_fifo.rd_addr[0] +.sym 22021 rx_24_fifo.rd_addr[1] +.sym 22023 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 22024 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 22025 rx_24_fifo.rd_addr[4] +.sym 22026 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 22027 rx_24_fifo.rd_addr[6] +.sym 22028 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22029 rx_24_fifo.rd_addr[8] +.sym 22030 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 22031 r_counter_$glb_clk +.sym 22032 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 22033 $PACKER_VCC_NET +.sym 22037 w_rx_24_fifo_data[23] +.sym 22041 w_rx_24_fifo_data[22] +.sym 22059 rx_24_fifo.rd_addr[6] +.sym 22061 $PACKER_VCC_NET +.sym 22062 $PACKER_VCC_NET +.sym 22063 rx_24_fifo.rd_addr[6] +.sym 22064 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 22066 lvds_rx_24_inst.o_debug_state[0] +.sym 22074 rx_24_fifo.wr_addr[8] +.sym 22076 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 22077 rx_24_fifo.wr_addr[3] +.sym 22078 w_rx_24_fifo_data[4] +.sym 22079 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 22080 w_rx_24_fifo_data[5] +.sym 22085 rx_24_fifo.wr_addr[4] +.sym 22089 rx_24_fifo.wr_addr[2] +.sym 22091 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 22092 rx_24_fifo.wr_addr[6] +.sym 22094 rx_24_fifo.wr_addr[0] +.sym 22095 rx_24_fifo.wr_addr[7] +.sym 22098 rx_24_fifo.wr_addr[5] +.sym 22103 $PACKER_VCC_NET +.sym 22108 lvds_rx_24_inst.o_debug_state[0] +.sym 22111 lvds_rx_24_inst.o_debug_state[1] +.sym 22122 rx_24_fifo.wr_addr[0] +.sym 22123 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 22125 rx_24_fifo.wr_addr[2] +.sym 22126 rx_24_fifo.wr_addr[3] +.sym 22127 rx_24_fifo.wr_addr[4] +.sym 22128 rx_24_fifo.wr_addr[5] +.sym 22129 rx_24_fifo.wr_addr[6] +.sym 22130 rx_24_fifo.wr_addr[7] +.sym 22131 rx_24_fifo.wr_addr[8] +.sym 22132 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 22133 lvds_clock_$glb_clk +.sym 22134 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 22136 w_rx_24_fifo_data[4] +.sym 22140 w_rx_24_fifo_data[5] +.sym 22143 $PACKER_VCC_NET +.sym 22150 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 22151 rx_24_fifo.wr_addr[4] +.sym 22156 w_rx_24_fifo_data[5] +.sym 22162 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 22163 lvds_rx_24_inst.o_debug_state[1] +.sym 22164 rx_24_fifo.wr_addr[5] +.sym 22165 rx_24_fifo.wr_addr[2] +.sym 22167 rx_24_fifo.wr_addr[4] +.sym 22168 rx_24_fifo.rd_addr[1] +.sym 22170 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 22176 w_rx_24_fifo_data[7] +.sym 22177 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 22178 rx_24_fifo.rd_addr[0] +.sym 22180 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 22182 rx_24_fifo.rd_addr[4] +.sym 22183 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22187 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 22188 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 22189 $PACKER_VCC_NET +.sym 22190 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 22191 rx_24_fifo.rd_addr[8] +.sym 22201 rx_24_fifo.rd_addr[6] +.sym 22204 rx_24_fifo.rd_addr[1] +.sym 22207 w_rx_24_fifo_data[6] +.sym 22224 rx_24_fifo.rd_addr[0] +.sym 22225 rx_24_fifo.rd_addr[1] +.sym 22227 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 22228 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 22229 rx_24_fifo.rd_addr[4] +.sym 22230 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 22231 rx_24_fifo.rd_addr[6] +.sym 22232 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22233 rx_24_fifo.rd_addr[8] +.sym 22234 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 22235 r_counter_$glb_clk +.sym 22236 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 22237 $PACKER_VCC_NET +.sym 22241 w_rx_24_fifo_data[7] +.sym 22245 w_rx_24_fifo_data[6] +.sym 22251 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 22253 o_tr_vc1$SB_IO_OUT +.sym 22256 o_tr_vc2$SB_IO_OUT +.sym 22258 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E +.sym 22261 lvds_rx_24_inst.o_debug_state[0] +.sym 22262 $PACKER_VCC_NET +.sym 22268 lvds_rx_24_inst.o_debug_state[1] +.sym 22269 w_rx_24_fifo_data[31] +.sym 22280 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 22281 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 22282 rx_24_fifo.wr_addr[8] +.sym 22283 rx_24_fifo.wr_addr[7] +.sym 22284 rx_24_fifo.wr_addr[6] +.sym 22285 rx_24_fifo.wr_addr[3] +.sym 22289 w_rx_24_fifo_data[28] +.sym 22290 rx_24_fifo.wr_addr[5] +.sym 22291 $PACKER_VCC_NET +.sym 22292 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 22293 w_rx_24_fifo_data[29] +.sym 22298 rx_24_fifo.wr_addr[0] +.sym 22303 rx_24_fifo.wr_addr[2] +.sym 22305 rx_24_fifo.wr_addr[4] +.sym 22326 rx_24_fifo.wr_addr[0] +.sym 22327 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 22329 rx_24_fifo.wr_addr[2] +.sym 22330 rx_24_fifo.wr_addr[3] +.sym 22331 rx_24_fifo.wr_addr[4] +.sym 22332 rx_24_fifo.wr_addr[5] +.sym 22333 rx_24_fifo.wr_addr[6] +.sym 22334 rx_24_fifo.wr_addr[7] +.sym 22335 rx_24_fifo.wr_addr[8] +.sym 22336 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 22337 lvds_clock_$glb_clk +.sym 22338 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_1_O +.sym 22340 w_rx_24_fifo_data[28] +.sym 22344 w_rx_24_fifo_data[29] +.sym 22347 $PACKER_VCC_NET +.sym 22372 w_rx_24_fifo_data[30] +.sym 22382 w_rx_24_fifo_data[30] +.sym 22384 rx_24_fifo.rd_addr[8] +.sym 22388 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 22391 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 22393 rx_24_fifo.rd_addr[0] +.sym 22397 rx_24_fifo.rd_addr[1] +.sym 22398 rx_24_fifo.rd_addr[4] +.sym 22399 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 22400 $PACKER_VCC_NET +.sym 22402 rx_24_fifo.rd_addr[6] +.sym 22407 w_rx_24_fifo_data[31] +.sym 22408 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22410 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 22411 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 22424 rx_24_fifo.rd_addr[0] +.sym 22425 rx_24_fifo.rd_addr[1] +.sym 22427 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 22428 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 22429 rx_24_fifo.rd_addr[4] +.sym 22430 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 22431 rx_24_fifo.rd_addr[6] +.sym 22432 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 22433 rx_24_fifo.rd_addr[8] +.sym 22434 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 22435 r_counter_$glb_clk +.sym 22436 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O +.sym 22437 $PACKER_VCC_NET +.sym 22441 w_rx_24_fifo_data[31] +.sym 22445 w_rx_24_fifo_data[30] +.sym 22464 rx_24_fifo.rd_addr[6] .sym 22487 o_led1$SB_IO_OUT -.sym 22502 o_led1$SB_IO_OUT +.sym 22496 o_led1$SB_IO_OUT .sym 22517 int_miso -.sym 22519 o_miso_$_TBUF__Y_E -.sym 22531 o_miso_$_TBUF__Y_E -.sym 22532 int_miso -.sym 22563 i_mosi$SB_IO_IN +.sym 22519 i_ss_SB_LUT4_I3_O +.sym 22537 int_miso +.sym 22538 i_ss_SB_LUT4_I3_O .sym 22666 i_sck$SB_IO_IN .sym 22668 i_ss$SB_IO_IN .sym 22698 i_ss$SB_IO_IN -.sym 22711 i_sck$SB_IO_IN .sym 22715 i_ss$SB_IO_IN -.sym 22724 i_ss$SB_IO_IN .sym 22729 i_sck$SB_IO_IN -.sym 22972 i_smi_a3$SB_IO_IN -.sym 22973 i_smi_a3$SB_IO_IN -.sym 22984 i_ss$SB_IO_IN -.sym 23089 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O -.sym 23108 i_sck$SB_IO_IN -.sym 23198 o_miso_$_TBUF__Y_E -.sym 23222 i_ss$SB_IO_IN -.sym 23226 i_sck$SB_IO_IN -.sym 23231 o_miso_$_TBUF__Y_E -.sym 23340 o_miso_$_TBUF__Y_E -.sym 23348 i_ss$SB_IO_IN -.sym 23447 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 23450 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 23471 spi_if_ins.w_rx_data[6] -.sym 23478 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23498 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23500 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23501 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23503 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23508 i_mosi$SB_IO_IN -.sym 23512 o_miso_$_TBUF__Y_E -.sym 23520 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 23527 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23532 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23548 i_mosi$SB_IO_IN -.sym 23561 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23564 o_miso_$_TBUF__Y_E -.sym 23565 i_sck$SB_IO_IN_$glb_clk -.sym 23567 spi_if_ins.spi.r_rx_byte[6] -.sym 23569 spi_if_ins.spi.r_rx_byte[1] -.sym 23572 spi_if_ins.spi.r_rx_byte[7] -.sym 23592 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23595 spi_if_ins.w_rx_data[4] -.sym 23611 spi_if_ins.spi.r_rx_byte[4] -.sym 23618 i_ss$SB_IO_IN +.sym 22976 i_ss$SB_IO_IN +.sym 22978 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23099 $PACKER_VCC_NET +.sym 23100 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23105 i_ss$SB_IO_IN +.sym 23118 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 23136 i_ss$SB_IO_IN +.sym 23138 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23170 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 23195 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E +.sym 23196 i_sck$SB_IO_IN_$glb_clk +.sym 23197 i_ss$SB_IO_IN +.sym 23225 $PACKER_GND_NET +.sym 23233 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 23248 spi_if_ins.spi.r3_rx_done +.sym 23250 spi_if_ins.spi.r_rx_done +.sym 23253 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23265 spi_if_ins.spi.r2_rx_done +.sym 23278 spi_if_ins.spi.r2_rx_done +.sym 23286 spi_if_ins.spi.r_rx_done +.sym 23304 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 23310 spi_if_ins.spi.r3_rx_done +.sym 23311 spi_if_ins.spi.r2_rx_done +.sym 23319 r_counter_$glb_clk +.sym 23352 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 23386 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23389 i_ss_SB_LUT4_I3_O +.sym 23413 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 23441 i_ss_SB_LUT4_I3_O +.sym 23442 i_sck$SB_IO_IN_$glb_clk +.sym 23475 i_ss_SB_LUT4_I3_O +.sym 23489 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 23496 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 23514 spi_if_ins.state_if_SB_DFFESR_Q_D[0] +.sym 23549 spi_if_ins.state_if_SB_DFFESR_Q_D[0] +.sym 23564 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 23565 r_counter_$glb_clk +.sym 23566 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 23571 r_counter +.sym 23591 spi_if_ins.state_if[2] +.sym 23595 w_fetch +.sym 23600 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 23601 w_tx_data_io[7] +.sym 23602 $PACKER_VCC_NET +.sym 23611 $PACKER_VCC_NET +.sym 23613 spi_if_ins.spi.r_rx_byte[7] .sym 23619 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23630 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 23632 spi_if_ins.spi.r_rx_byte[6] -.sym 23634 spi_if_ins.spi.r_rx_byte[1] -.sym 23637 spi_if_ins.spi.r_rx_byte[7] -.sym 23648 spi_if_ins.spi.r_rx_byte[7] -.sym 23654 i_ss$SB_IO_IN -.sym 23655 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 23661 spi_if_ins.spi.r_rx_byte[1] -.sym 23680 spi_if_ins.spi.r_rx_byte[4] -.sym 23685 spi_if_ins.spi.r_rx_byte[6] +.sym 23622 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 23625 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 23647 spi_if_ins.spi.r_rx_byte[7] +.sym 23661 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 23668 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 23673 $PACKER_VCC_NET .sym 23687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O .sym 23688 r_counter_$glb_clk -.sym 23706 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] +.sym 23690 w_fetch +.sym 23697 $PACKER_GND_NET .sym 23707 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23733 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23737 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23739 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23750 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23752 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23758 i_mosi$SB_IO_IN -.sym 23767 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 23773 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 23779 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 23784 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 23802 i_mosi$SB_IO_IN -.sym 23810 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 23811 i_sck$SB_IO_IN_$glb_clk -.sym 23854 spi_if_ins.spi.r_rx_byte[5] -.sym 23855 spi_if_ins.spi.r_rx_byte[3] -.sym 23856 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23860 spi_if_ins.spi.r_rx_byte[0] -.sym 23864 spi_if_ins.spi.r_rx_byte[2] -.sym 23888 spi_if_ins.spi.r_rx_byte[3] -.sym 23901 spi_if_ins.spi.r_rx_byte[0] -.sym 23911 spi_if_ins.spi.r_rx_byte[5] -.sym 23926 spi_if_ins.spi.r_rx_byte[2] -.sym 23933 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 23934 r_counter_$glb_clk -.sym 24588 o_led0$SB_IO_OUT +.sym 23716 spi_if_ins.r_tx_byte[0] +.sym 23719 i_glob_clock$SB_IO_IN +.sym 23721 $PACKER_GND_NET +.sym 23722 w_tx_data_smi[3] +.sym 23723 w_fetch +.sym 23731 i_glob_clock$SB_IO_IN +.sym 23734 $PACKER_VCC_NET +.sym 23735 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 23741 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 23742 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 23748 w_tx_data_smi[3] +.sym 23750 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 23758 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 23760 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 23761 w_tx_data_io[7] +.sym 23762 w_tx_data_io[3] +.sym 23770 w_tx_data_io[7] +.sym 23772 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 23773 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 23776 w_tx_data_io[3] +.sym 23777 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 23778 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 23779 w_tx_data_smi[3] +.sym 23789 $PACKER_VCC_NET +.sym 23810 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 23811 i_glob_clock$SB_IO_IN +.sym 23812 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 23820 spi_if_ins.r_tx_byte[0] +.sym 23825 i_glob_clock$SB_IO_IN +.sym 23827 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 23833 $PACKER_VCC_NET +.sym 23840 $PACKER_VCC_NET +.sym 23843 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 23845 w_rx_24_fifo_full +.sym 23854 i_glob_clock$SB_IO_IN +.sym 23855 w_tx_data_sys[0] +.sym 23863 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 23872 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 23875 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 23881 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3] +.sym 23917 w_tx_data_sys[0] +.sym 23918 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3] +.sym 23919 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 23920 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 23933 spi_if_ins.o_cs_SB_LUT4_I3_1_O +.sym 23934 i_glob_clock$SB_IO_IN +.sym 23948 i_glob_clock$SB_IO_IN +.sym 23949 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 23951 $PACKER_VCC_NET +.sym 23959 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 23964 lvds_rx_24_inst.o_debug_state[0] +.sym 23990 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 23995 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 24005 w_rx_24_fifo_full +.sym 24037 w_rx_24_fifo_full +.sym 24056 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E +.sym 24057 r_counter_$glb_clk +.sym 24058 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 24078 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 24107 w_lvds_rx_24_d0 +.sym 24108 lvds_rx_24_inst.r_data[5] +.sym 24136 lvds_rx_24_inst.r_data[5] +.sym 24163 w_lvds_rx_24_d0 +.sym 24179 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O_$glb_ce +.sym 24180 lvds_clock_$glb_clk +.sym 24192 w_lvds_rx_24_d1 +.sym 24208 lvds_rx_24_inst.o_debug_state[1] +.sym 24228 w_lvds_rx_24_d0 +.sym 24234 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E +.sym 24236 lvds_rx_24_inst.o_debug_state[1] +.sym 24245 w_lvds_rx_24_d1 +.sym 24249 lvds_rx_24_inst.o_debug_state[0] +.sym 24268 w_lvds_rx_24_d1 +.sym 24269 w_lvds_rx_24_d0 +.sym 24270 lvds_rx_24_inst.o_debug_state[1] +.sym 24271 lvds_rx_24_inst.o_debug_state[0] +.sym 24286 lvds_rx_24_inst.o_debug_state[0] +.sym 24287 w_lvds_rx_24_d1 +.sym 24288 w_lvds_rx_24_d0 +.sym 24289 lvds_rx_24_inst.o_debug_state[1] +.sym 24302 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E +.sym 24303 lvds_clock_$glb_clk +.sym 24304 i_smi_a2_SB_LUT4_I1_O[1]_$glb_sr +.sym 24450 o_rx_h_tx_l_b$SB_IO_OUT .sym 24596 o_led0$SB_IO_OUT -.sym 24614 o_led0$SB_IO_OUT -.sym 24655 i_ss$SB_IO_IN -.sym 24664 i_ss$SB_IO_IN -.sym 25491 i_ss$SB_IO_IN -.sym 25508 i_ss$SB_IO_IN +.sym 24607 o_led0$SB_IO_OUT +.sym 24621 i_smi_a3$SB_IO_IN +.sym 24623 o_led0$SB_IO_OUT +.sym 25108 w_smi_read_req .sym 25711 i_glob_clock$SB_IO_IN -.sym 25784 o_miso_$_TBUF__Y_E -.sym 25791 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 25796 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25833 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25851 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 25861 o_miso_$_TBUF__Y_E -.sym 25862 i_sck$SB_IO_IN_$glb_clk -.sym 25876 o_miso_$_TBUF__Y_E -.sym 25879 i_sck$SB_IO_IN -.sym 25939 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 25940 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 25951 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25958 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 25973 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 25983 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 26000 spi_if_ins.spi.r_temp_rx_byte[6] -.sym 26016 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 26017 i_sck$SB_IO_IN_$glb_clk -.sym 27283 $PACKER_VCC_NET +.sym 25725 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 25878 i_glob_clock$SB_IO_IN +.sym 25957 r_counter +.sym 25962 i_glob_clock$SB_IO_IN +.sym 25994 r_counter +.sym 26017 i_glob_clock$SB_IO_IN +.sym 26096 spi_if_ins.state_if[2] +.sym 26112 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 26118 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26119 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 26125 spi_if_ins.state_if[2] +.sym 26126 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 26171 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 26172 r_counter_$glb_clk +.sym 26173 spi_if_ins.state_if_SB_DFFESR_Q_R +.sym 26260 r_tx_data[0] +.sym 26265 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 26323 r_tx_data[0] +.sym 26326 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O +.sym 26327 r_counter_$glb_clk +.sym 26500 $PACKER_GND_NET +.sym 26647 o_rx_h_tx_l$SB_IO_OUT +.sym 27275 i_smi_a3$SB_IO_IN +.sym 27283 w_smi_read_req .sym 27285 i_smi_a3$SB_IO_IN -.sym 27291 i_smi_a3$SB_IO_IN -.sym 27292 $PACKER_VCC_NET -.sym 27367 i_glob_clock$SB_IO_IN -.sym 27428 $PACKER_VCC_NET -.sym 27429 i_sck$SB_IO_IN -.sym 27444 i_sck$SB_IO_IN -.sym 27459 i_glob_clock$SB_IO_IN +.sym 27290 w_smi_read_req +.sym 27293 i_smi_a3$SB_IO_IN +.sym 27395 i_smi_a3$SB_IO_IN +.sym 27397 i_glob_clock$SB_IO_IN +.sym 27398 $PACKER_VCC_NET +.sym 27427 i_glob_clock$SB_IO_IN +.sym 27429 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 27440 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 27459 r_counter .sym 27460 $PACKER_VCC_NET -.sym 27479 i_glob_clock$SB_IO_IN -.sym 27480 $PACKER_VCC_NET +.sym 27481 r_counter +.sym 27484 $PACKER_VCC_NET +.sym 27514 i_smi_a3$SB_IO_IN .sym 27552 $PACKER_GND_NET -.sym 27570 $PACKER_GND_NET +.sym 27572 $PACKER_GND_NET .sym 27582 o_rx_h_tx_l$SB_IO_OUT -.sym 27591 o_rx_h_tx_l$SB_IO_OUT +.sym 27596 o_rx_h_tx_l$SB_IO_OUT .sym 27605 o_tr_vc1$SB_IO_OUT .sym 27608 o_tr_vc2$SB_IO_OUT -.sym 27620 o_tr_vc1$SB_IO_OUT -.sym 27624 o_tr_vc2$SB_IO_OUT +.sym 27625 o_tr_vc1$SB_IO_OUT +.sym 27626 o_tr_vc2$SB_IO_OUT .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT .sym 27634 o_tr_vc1_b$SB_IO_OUT -.sym 27650 o_tr_vc1_b$SB_IO_OUT -.sym 27655 o_rx_h_tx_l_b$SB_IO_OUT -.sym 27694 lvds_rx_09_inst.r_data[14] -.sym 27726 lvds_rx_09_inst.r_data[12] -.sym 27738 lvds_rx_09_inst.r_data[14] -.sym 27746 lvds_rx_09_inst.r_data[23] -.sym 27750 lvds_rx_09_inst.r_data[17] -.sym 27758 lvds_rx_09_inst.r_data[16] -.sym 27762 lvds_rx_09_inst.r_data[21] -.sym 27766 lvds_rx_09_inst.r_data[19] -.sym 27790 lvds_rx_09_inst.r_data[2] -.sym 27798 lvds_rx_09_inst.r_data[4] -.sym 27810 lvds_rx_09_inst.r_data[9] -.sym 27814 lvds_rx_09_inst.r_data[6] -.sym 27818 lvds_rx_09_inst.r_data[8] -.sym 27838 lvds_rx_09_inst.r_data[7] -.sym 27874 $PACKER_GND_NET -.sym 27910 w_soft_reset -.sym 27911 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 27912 lvds_rx_09_inst.o_debug_state[1] -.sym 27913 lvds_rx_09_inst.o_debug_state[0] -.sym 27938 lvds_rx_09_inst.o_debug_state[1] -.sym 27939 w_lvds_rx_09_d1 -.sym 27940 w_lvds_rx_09_d0 -.sym 27941 lvds_rx_09_inst.o_debug_state[0] -.sym 27950 lvds_rx_09_inst.o_debug_state[1] -.sym 27951 w_lvds_rx_09_d1 -.sym 27952 w_lvds_rx_09_d0 -.sym 27953 lvds_rx_09_inst.o_debug_state[0] -.sym 27958 lvds_rx_09_inst.o_debug_state[0] -.sym 27959 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 27960 w_soft_reset -.sym 27961 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3[3] -.sym 27978 lvds_rx_09_inst.o_debug_state[1] -.sym 27979 lvds_rx_09_inst.o_debug_state[0] -.sym 27980 w_lvds_rx_09_d0 -.sym 27981 w_lvds_rx_09_d1 -.sym 28198 lvds_rx_09_inst.r_data[12] -.sym 28202 lvds_rx_09_inst.r_data[13] -.sym 28218 lvds_rx_09_inst.r_data[15] -.sym 28234 lvds_rx_09_inst.r_data[10] -.sym 28242 lvds_rx_09_inst.r_data[11] -.sym 28246 lvds_rx_09_inst.r_data[13] -.sym 28254 lvds_rx_09_inst.r_data[15] -.sym 28266 lvds_rx_09_inst.r_data[16] -.sym 28270 lvds_rx_09_inst.r_data[5] -.sym 28274 lvds_rx_09_inst.r_data[19] -.sym 28278 lvds_rx_09_inst.r_data[23] -.sym 28286 lvds_rx_09_inst.r_data[7] -.sym 28306 lvds_rx_09_inst.r_data[4] -.sym 28314 lvds_rx_09_inst.r_data[6] -.sym 28318 lvds_rx_09_inst.r_data[2] -.sym 28322 lvds_rx_09_inst.r_data[11] -.sym 28330 lvds_rx_09_inst.r_data[8] -.sym 28342 lvds_rx_09_inst.r_data[9] -.sym 28350 lvds_rx_09_inst.r_data[10] -.sym 28356 lvds_rx_09_inst.r_cnt[0] -.sym 28357 lvds_rx_09_inst.r_cnt[1] -.sym 28361 lvds_rx_09_inst.r_cnt[0] -.sym 28362 lvds_rx_09_inst.o_debug_state[0] -.sym 28363 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 28364 lvds_rx_09_inst.o_debug_state[1] -.sym 28365 w_soft_reset -.sym 28375 lvds_rx_09_inst.o_debug_state[1] +.sym 27641 o_tr_vc1_b$SB_IO_OUT +.sym 27653 o_rx_h_tx_l_b$SB_IO_OUT +.sym 27760 lvds_rx_09_inst.o_debug_state[0] +.sym 27761 lvds_rx_09_inst.r_data[19] +.sym 27772 lvds_rx_09_inst.o_debug_state[0] +.sym 27773 lvds_rx_09_inst.r_data[17] +.sym 27776 lvds_rx_09_inst.o_debug_state[0] +.sym 27777 lvds_rx_09_inst.r_data[15] +.sym 27804 lvds_rx_09_inst.o_debug_state[0] +.sym 27805 lvds_rx_09_inst.r_data[23] +.sym 27808 lvds_rx_09_inst.o_debug_state[0] +.sym 27809 lvds_rx_09_inst.r_data[21] +.sym 27826 lvds_rx_09_inst.r_data[23] +.sym 27867 smi_ctrl_ins.int_cnt_24[3] +.sym 27868 smi_ctrl_ins.int_cnt_24[4] +.sym 27869 w_rx_24_fifo_empty +.sym 27894 lvds_rx_09_inst.r_push +.sym 27918 lvds_rx_09_inst.o_debug_state[0] +.sym 27919 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 27920 i_smi_a2_SB_LUT4_I1_O[1] +.sym 27921 lvds_rx_09_inst.o_debug_state[1] +.sym 27935 w_rx_09_fifo_full +.sym 27936 lvds_rx_09_inst.o_debug_state[0] +.sym 27937 lvds_rx_09_inst.o_debug_state[1] +.sym 27959 i_smi_a2_SB_LUT4_I1_O[1] +.sym 27960 lvds_rx_09_inst.o_debug_state[0] +.sym 27961 lvds_rx_09_inst.o_debug_state[1] +.sym 28034 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 28035 lvds_rx_09_inst.o_debug_state[0] +.sym 28036 lvds_rx_09_inst.o_debug_state[1] +.sym 28037 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 28046 lvds_rx_09_inst.o_debug_state[1] +.sym 28047 w_lvds_rx_09_d1 +.sym 28048 w_lvds_rx_09_d0 +.sym 28049 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 28051 i_smi_a2_SB_LUT4_I1_O[1] +.sym 28052 w_lvds_rx_09_d1_SB_LUT4_I1_O[1] +.sym 28053 w_lvds_rx_09_d1_SB_LUT4_I1_O[2] +.sym 28057 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 28067 lvds_rx_09_inst.r_phase_count[0] +.sym 28071 lvds_rx_09_inst.r_phase_count[1] +.sym 28072 $PACKER_VCC_NET +.sym 28073 lvds_rx_09_inst.r_phase_count[0] +.sym 28074 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 28076 $PACKER_VCC_NET +.sym 28077 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 28078 lvds_rx_09_inst.o_debug_state[1] +.sym 28079 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 28080 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 28081 lvds_rx_09_inst.o_debug_state[0] +.sym 28082 lvds_rx_09_inst.o_debug_state[1] +.sym 28083 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 28084 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 28085 lvds_rx_09_inst.o_debug_state[0] +.sym 28093 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 28094 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 28095 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 28096 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 28097 lvds_rx_09_inst.o_debug_state[0] +.sym 28101 w_lvds_rx_24_d1 +.sym 28102 lvds_rx_24_inst.o_debug_state[1] +.sym 28103 lvds_rx_24_inst.o_debug_state[0] +.sym 28104 w_lvds_rx_24_d0 +.sym 28105 w_lvds_rx_24_d1 +.sym 28106 w_lvds_rx_09_d0 +.sym 28107 lvds_rx_09_inst.o_debug_state[1] +.sym 28108 lvds_rx_09_inst.o_debug_state[0] +.sym 28109 w_lvds_rx_09_d1 +.sym 28115 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 28116 lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 28117 i_smi_a2_SB_LUT4_I1_O[1] +.sym 28118 lvds_rx_09_inst.o_debug_state[1] +.sym 28119 w_lvds_rx_09_d1 +.sym 28120 w_lvds_rx_09_d0 +.sym 28121 lvds_rx_09_inst.o_debug_state[0] +.sym 28122 lvds_rx_09_inst.o_debug_state[1] +.sym 28123 w_lvds_rx_09_d1 +.sym 28124 lvds_rx_09_inst.o_debug_state[0] +.sym 28125 w_lvds_rx_09_d0 +.sym 28130 lvds_rx_24_inst.o_debug_state[1] +.sym 28131 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 28132 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2] +.sym 28133 lvds_rx_24_inst.o_debug_state[0] +.sym 28198 lvds_rx_09_inst.r_data[26] +.sym 28202 lvds_rx_09_inst.r_data[27] +.sym 28210 lvds_rx_09_inst.r_data[28] +.sym 28214 lvds_rx_09_inst.r_data[29] +.sym 28228 lvds_rx_09_inst.o_debug_state[0] +.sym 28229 lvds_rx_09_inst.r_data[26] +.sym 28232 lvds_rx_09_inst.o_debug_state[0] +.sym 28233 lvds_rx_09_inst.r_data[27] +.sym 28236 lvds_rx_09_inst.o_debug_state[0] +.sym 28237 lvds_rx_09_inst.r_data[6] +.sym 28240 lvds_rx_09_inst.o_debug_state[0] +.sym 28241 lvds_rx_09_inst.r_data[9] +.sym 28244 lvds_rx_09_inst.o_debug_state[0] +.sym 28245 lvds_rx_09_inst.r_data[10] +.sym 28248 lvds_rx_09_inst.o_debug_state[0] +.sym 28249 lvds_rx_09_inst.r_data[11] +.sym 28252 lvds_rx_09_inst.o_debug_state[0] +.sym 28253 lvds_rx_09_inst.r_data[13] +.sym 28256 lvds_rx_09_inst.o_debug_state[0] +.sym 28257 lvds_rx_09_inst.r_data[8] +.sym 28258 lvds_rx_09_inst.r_data[9] +.sym 28262 lvds_rx_09_inst.r_data[8] +.sym 28266 lvds_rx_09_inst.r_data[7] +.sym 28278 lvds_rx_09_inst.r_data[18] +.sym 28282 lvds_rx_09_inst.r_data[6] +.sym 28286 lvds_rx_09_inst.r_data[21] +.sym 28292 lvds_rx_09_inst.o_debug_state[0] +.sym 28293 lvds_rx_09_inst.r_data[25] +.sym 28296 lvds_rx_09_inst.o_debug_state[0] +.sym 28297 lvds_rx_09_inst.r_data[7] +.sym 28300 lvds_rx_09_inst.o_debug_state[0] +.sym 28301 lvds_rx_09_inst.r_data[18] +.sym 28304 lvds_rx_09_inst.o_debug_state[0] +.sym 28305 lvds_rx_09_inst.r_data[22] +.sym 28308 lvds_rx_09_inst.o_debug_state[0] +.sym 28309 lvds_rx_09_inst.r_data[5] +.sym 28312 lvds_rx_09_inst.o_debug_state[0] +.sym 28313 lvds_rx_09_inst.r_data[4] +.sym 28316 lvds_rx_09_inst.o_debug_state[0] +.sym 28317 lvds_rx_09_inst.r_data[20] +.sym 28320 lvds_rx_09_inst.o_debug_state[0] +.sym 28321 lvds_rx_09_inst.r_data[24] +.sym 28322 lvds_rx_09_inst.r_data[5] +.sym 28326 lvds_rx_09_inst.r_data[3] +.sym 28330 lvds_rx_09_inst.r_data[2] +.sym 28334 lvds_rx_09_inst.r_data[24] +.sym 28342 lvds_rx_09_inst.r_data[22] +.sym 28346 lvds_rx_09_inst.r_data[4] +.sym 28350 lvds_rx_09_inst.r_data[25] +.sym 28356 lvds_rx_09_inst.o_debug_state[0] +.sym 28357 lvds_rx_09_inst.r_data[1] +.sym 28360 lvds_rx_09_inst.o_debug_state[0] +.sym 28361 lvds_rx_09_inst.r_data[0] +.sym 28368 lvds_rx_09_inst.o_debug_state[0] +.sym 28369 lvds_rx_09_inst.r_data[14] +.sym 28372 lvds_rx_09_inst.o_debug_state[0] +.sym 28373 lvds_rx_09_inst.r_data[3] .sym 28376 lvds_rx_09_inst.o_debug_state[0] -.sym 28377 lvds_rx_09_inst.r_cnt_SB_DFFESR_Q_E[2] -.sym 28390 lvds_rx_09_inst.r_data[17] -.sym 28405 sys_ctrl_ins.reset_cmd -.sym 28406 lvds_rx_09_inst.r_data[18] -.sym 28739 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 28744 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 28745 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 28748 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 28749 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[2] -.sym 28752 rx_09_fifo.wr_addr[3] -.sym 28753 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[3] -.sym 28756 rx_09_fifo.wr_addr[4] -.sym 28757 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[4] -.sym 28760 rx_09_fifo.wr_addr[5] -.sym 28761 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[5] -.sym 28764 rx_09_fifo.wr_addr[6] -.sym 28765 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[6] -.sym 28768 rx_09_fifo.wr_addr[7] -.sym 28769 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[7] -.sym 28772 rx_09_fifo.wr_addr[8] -.sym 28773 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[8] -.sym 28776 rx_09_fifo.wr_addr[9] -.sym 28777 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[9] -.sym 28778 lvds_rx_09_inst.r_data[25] -.sym 28782 lvds_rx_09_inst.r_data[5] -.sym 28786 lvds_rx_09_inst.r_data[3] -.sym 28790 lvds_rx_09_inst.r_data[20] -.sym 28794 lvds_rx_09_inst.r_data[18] -.sym 28798 lvds_rx_09_inst.r_data[22] +.sym 28377 lvds_rx_09_inst.r_data[12] +.sym 28380 lvds_rx_09_inst.o_debug_state[0] +.sym 28381 lvds_rx_09_inst.r_data[16] +.sym 28384 lvds_rx_09_inst.o_debug_state[0] +.sym 28385 lvds_rx_09_inst.r_data[2] +.sym 28386 lvds_rx_09_inst.r_data[0] +.sym 28390 lvds_rx_09_inst.r_data[1] +.sym 28402 lvds_rx_09_inst.r_data[16] +.sym 28406 w_lvds_rx_09_d0 +.sym 28410 w_lvds_rx_09_d1 +.sym 28414 lvds_rx_09_inst.r_data[17] +.sym 28432 w_lvds_rx_09_d0 +.sym 28433 lvds_rx_09_inst.o_debug_state[0] +.sym 28440 lvds_rx_09_inst.o_debug_state[0] +.sym 28441 w_lvds_rx_09_d1 +.sym 28482 w_rx_24_fifo_pulled_data[3] +.sym 28483 w_rx_24_fifo_pulled_data[19] +.sym 28484 smi_ctrl_ins.int_cnt_24[3] +.sym 28485 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 28486 w_rx_24_fifo_pulled_data[1] +.sym 28487 w_rx_24_fifo_pulled_data[17] +.sym 28488 smi_ctrl_ins.int_cnt_24[3] +.sym 28489 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 28498 w_rx_24_fifo_pulled_data[9] +.sym 28499 w_rx_24_fifo_pulled_data[25] +.sym 28500 smi_ctrl_ins.int_cnt_24[3] +.sym 28501 smi_ctrl_ins.int_cnt_24[4] +.sym 28504 lvds_rx_24_inst.o_debug_state[0] +.sym 28505 lvds_rx_24_inst.r_data[8] +.sym 28510 w_rx_24_fifo_pulled_data[11] +.sym 28511 w_rx_24_fifo_pulled_data[27] +.sym 28512 smi_ctrl_ins.int_cnt_24[3] +.sym 28513 smi_ctrl_ins.int_cnt_24[4] +.sym 28520 lvds_rx_24_inst.o_debug_state[0] +.sym 28521 lvds_rx_24_inst.r_data[6] +.sym 28546 w_lvds_rx_24_d0 +.sym 28550 lvds_rx_24_inst.r_data[0] +.sym 28557 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E +.sym 28558 lvds_rx_24_inst.r_data[8] +.sym 28566 w_lvds_rx_24_d1 +.sym 28570 lvds_rx_24_inst.r_data[6] +.sym 28580 lvds_rx_24_inst.o_debug_state[0] +.sym 28581 lvds_rx_24_inst.r_data[0] +.sym 28584 lvds_rx_24_inst.o_debug_state[0] +.sym 28585 lvds_rx_24_inst.r_data[4] +.sym 28592 lvds_rx_24_inst.o_debug_state[0] +.sym 28593 w_lvds_rx_24_d0 +.sym 28608 lvds_rx_24_inst.o_debug_state[0] +.sym 28609 lvds_rx_24_inst.r_data[2] +.sym 28610 lvds_rx_24_inst.o_debug_state[1] +.sym 28611 w_lvds_rx_24_d1 +.sym 28612 w_lvds_rx_24_d0 +.sym 28613 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 28615 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 28616 lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] +.sym 28617 i_smi_a2_SB_LUT4_I1_O[1] +.sym 28621 lvds_rx_24_inst.o_debug_state[1] +.sym 28623 i_smi_a2_SB_LUT4_I1_O[1] +.sym 28624 w_lvds_rx_24_d1_SB_LUT4_I1_O[1] +.sym 28625 w_lvds_rx_24_d1_SB_LUT4_I1_O[2] +.sym 28643 lvds_rx_24_inst.r_phase_count[0] +.sym 28647 lvds_rx_24_inst.r_phase_count[1] +.sym 28648 $PACKER_VCC_NET +.sym 28649 lvds_rx_24_inst.r_phase_count[0] +.sym 28650 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 28652 $PACKER_VCC_NET +.sym 28653 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2] +.sym 28657 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 28658 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 28659 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 28660 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2] +.sym 28661 lvds_rx_24_inst.o_debug_state[0] +.sym 28665 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[1] +.sym 28666 lvds_rx_24_inst.o_debug_state[1] +.sym 28667 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 28668 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1] +.sym 28669 lvds_rx_24_inst.o_debug_state[0] +.sym 28670 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0] +.sym 28671 lvds_rx_24_inst.o_debug_state[0] +.sym 28672 lvds_rx_24_inst.o_debug_state[1] +.sym 28673 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 28722 lvds_rx_09_inst.r_data[13] +.sym 28739 rx_09_fifo.rd_addr[0] +.sym 28744 rx_09_fifo.rd_addr[1] +.sym 28748 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 28749 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 28752 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 28753 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 28756 rx_09_fifo.rd_addr[4] +.sym 28757 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 28760 rx_09_fifo.rd_addr[5] +.sym 28761 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 28764 rx_09_fifo.rd_addr[6] +.sym 28765 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 28768 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 28769 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 28772 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 28773 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 28776 rx_09_fifo.rd_addr[9] +.sym 28777 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 28790 rx_09_fifo.rd_addr[4] +.sym 28791 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3] +.sym 28792 rx_09_fifo.rd_addr[5] +.sym 28793 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4] +.sym 28802 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] .sym 28803 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 28808 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 28809 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 28812 rx_09_fifo.wr_addr[3] +.sym 28804 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 28805 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 28806 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] +.sym 28807 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] +.sym 28808 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 28809 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] +.sym 28810 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 28811 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 28812 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] .sym 28813 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[2] -.sym 28816 rx_09_fifo.wr_addr[4] -.sym 28817 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[3] -.sym 28820 rx_09_fifo.wr_addr[5] -.sym 28821 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[4] -.sym 28824 rx_09_fifo.wr_addr[6] -.sym 28825 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5] -.sym 28828 rx_09_fifo.wr_addr[7] -.sym 28829 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] -.sym 28832 rx_09_fifo.wr_addr[8] -.sym 28833 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7] -.sym 28836 rx_09_fifo.wr_addr[9] -.sym 28837 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] -.sym 28841 $nextpnr_ICESTORM_LC_9$I3 -.sym 28842 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] -.sym 28843 rx_09_fifo.rd_addr[8] -.sym 28844 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7] -.sym 28845 w_rx_09_fifo_push -.sym 28846 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 28847 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2] -.sym 28848 rx_09_fifo.rd_addr[9] -.sym 28849 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] -.sym 28850 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 28851 rx_09_fifo.wr_addr[3] -.sym 28852 rx_09_fifo.rd_addr[4] -.sym 28853 rx_09_fifo.wr_addr[4] -.sym 28854 lvds_rx_09_inst.r_data[3] -.sym 28858 lvds_rx_09_inst.r_data[25] -.sym 28862 lvds_rx_09_inst.r_data[1] -.sym 28867 w_rx_09_fifo_full -.sym 28868 lvds_rx_09_inst.o_debug_state[0] -.sym 28869 lvds_rx_09_inst.o_debug_state[1] -.sym 28870 rx_09_fifo.rd_addr[4] -.sym 28871 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] -.sym 28872 rx_09_fifo.rd_addr[7] -.sym 28873 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] -.sym 28876 w_soft_reset +.sym 28814 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 28815 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 28816 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[9] +.sym 28817 w_rx_09_fifo_push +.sym 28820 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 28821 rx_09_fifo.rd_addr[0] +.sym 28822 rx_09_fifo.rd_addr[6] +.sym 28823 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 28824 rx_09_fifo.rd_addr[9] +.sym 28825 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[8] +.sym 28826 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 28827 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[7] +.sym 28828 rx_09_fifo.empty_o_SB_LUT4_I3_I2[2] +.sym 28829 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 28830 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 28831 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] +.sym 28832 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 28833 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 28834 w_rx_09_fifo_pulled_data[0] +.sym 28835 w_rx_09_fifo_pulled_data[16] +.sym 28836 smi_ctrl_ins.int_cnt_09[3] +.sym 28837 smi_ctrl_ins.int_cnt_09[4] +.sym 28838 w_rx_09_fifo_pulled_data[2] +.sym 28839 w_rx_09_fifo_pulled_data[18] +.sym 28840 smi_ctrl_ins.int_cnt_09[3] +.sym 28841 smi_ctrl_ins.int_cnt_09[4] +.sym 28844 smi_ctrl_ins.int_cnt_09[4] +.sym 28845 smi_ctrl_ins.int_cnt_09[3] +.sym 28846 w_rx_09_fifo_pulled_data[1] +.sym 28847 w_rx_09_fifo_pulled_data[17] +.sym 28848 smi_ctrl_ins.int_cnt_09[3] +.sym 28849 smi_ctrl_ins.int_cnt_09[4] +.sym 28850 w_rx_09_fifo_pulled_data[3] +.sym 28851 w_rx_09_fifo_pulled_data[19] +.sym 28852 smi_ctrl_ins.int_cnt_09[3] +.sym 28853 smi_ctrl_ins.int_cnt_09[4] +.sym 28857 smi_ctrl_ins.int_cnt_09[3] +.sym 28864 i_smi_a2_SB_LUT4_I1_O[0] +.sym 28865 i_smi_a2_SB_LUT4_I1_O[1] +.sym 28876 i_smi_a2_SB_LUT4_I1_O[1] .sym 28877 w_rx_09_fifo_push -.sym 28885 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 28889 rx_09_fifo.wr_addr[5] -.sym 28899 sys_ctrl_ins.reset_count[0] -.sym 28904 sys_ctrl_ins.reset_count[1] -.sym 28906 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 28908 sys_ctrl_ins.reset_count[2] -.sym 28909 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 28910 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 28912 sys_ctrl_ins.reset_count[3] -.sym 28913 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] -.sym 28914 sys_ctrl_ins.reset_count[3] -.sym 28915 sys_ctrl_ins.reset_count[1] -.sym 28916 sys_ctrl_ins.reset_count[2] -.sym 28917 sys_ctrl_ins.reset_count[0] -.sym 28921 sys_ctrl_ins.reset_count[0] -.sym 28924 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 28925 sys_ctrl_ins.reset_cmd -.sym 28926 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S -.sym 28928 sys_ctrl_ins.reset_count[1] -.sym 28929 sys_ctrl_ins.reset_count[0] -.sym 28950 $PACKER_VCC_NET -.sym 28957 w_cs[0] -.sym 28994 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] -.sym 29028 w_ioc[1] -.sym 29029 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 29031 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 29032 w_cs[0] -.sym 29033 w_fetch -.sym 29046 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 29071 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 29072 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 29073 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 29105 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E -.sym 29108 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[0] -.sym 29109 io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2[1] -.sym 29113 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S -.sym 29219 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29224 rx_09_fifo.rd_addr[1] -.sym 29228 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29229 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 29232 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 29233 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] -.sym 29236 rx_09_fifo.rd_addr[4] -.sym 29237 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] -.sym 29240 rx_09_fifo.rd_addr[5] -.sym 29241 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] -.sym 29244 rx_09_fifo.rd_addr[6] -.sym 29245 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] -.sym 29248 rx_09_fifo.rd_addr[7] -.sym 29249 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] -.sym 29252 rx_09_fifo.rd_addr[8] -.sym 29253 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] -.sym 29256 rx_09_fifo.rd_addr[9] -.sym 29257 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] -.sym 29258 rx_09_fifo.rd_addr[4] -.sym 29259 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] -.sym 29260 rx_09_fifo.rd_addr[5] -.sym 29261 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 29269 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29272 rx_09_fifo.rd_addr[1] -.sym 29273 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29274 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 29275 rx_09_fifo.rd_addr[7] -.sym 29276 w_rx_09_fifo_push -.sym 29277 w_rx_09_fifo_full -.sym 29278 rx_09_fifo.rd_addr[7] -.sym 29279 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 29280 rx_09_fifo.rd_addr[9] -.sym 29281 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 29282 lvds_rx_09_inst.r_data[22] -.sym 29286 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 29287 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 29288 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] -.sym 29289 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] -.sym 29290 lvds_rx_09_inst.r_data[0] -.sym 29294 lvds_rx_09_inst.r_data[20] -.sym 29302 rx_09_fifo.rd_addr[6] -.sym 29303 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 29304 rx_09_fifo.rd_addr[8] -.sym 29305 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 29306 rx_09_fifo.rd_addr[1] -.sym 29307 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 29308 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29309 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 29310 rx_09_fifo.full_o_SB_LUT4_I3_O[0] -.sym 29311 rx_09_fifo.full_o_SB_LUT4_I3_O[1] -.sym 29312 rx_09_fifo.full_o_SB_LUT4_I3_O[2] -.sym 29313 rx_09_fifo.full_o_SB_LUT4_I3_O[3] -.sym 29314 rx_09_fifo.rd_addr[5] -.sym 29315 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4] -.sym 29316 rx_09_fifo.rd_addr[6] -.sym 29317 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5] -.sym 29318 rx_09_fifo.full_o_SB_LUT4_I3_I0[7] -.sym 29322 rx_09_fifo.full_o_SB_LUT4_I3_I0[6] -.sym 29329 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 29330 rx_09_fifo.full_o_SB_LUT4_I3_I0[1] -.sym 29334 rx_09_fifo.full_o_SB_LUT4_I3_I0[2] -.sym 29338 rx_09_fifo.full_o_SB_LUT4_I3_I0[8] -.sym 29342 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] -.sym 29346 rx_09_fifo.full_o_SB_LUT4_I3_I0[4] -.sym 29350 rx_09_fifo.full_o_SB_LUT4_I3_I0[9] -.sym 29354 rx_09_fifo.full_o_SB_LUT4_I3_I0[5] -.sym 29358 rx_09_fifo.rd_addr[5] -.sym 29359 rx_09_fifo.wr_addr[5] -.sym 29360 rx_09_fifo.rd_addr[6] -.sym 29361 rx_09_fifo.wr_addr[6] -.sym 29363 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29364 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] -.sym 29365 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2] -.sym 29366 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29367 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 29368 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[2] -.sym 29369 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[3] -.sym 29373 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 29374 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[0] -.sym 29375 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] -.sym 29376 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[2] -.sym 29377 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[3] -.sym 29402 spi_if_ins.state_if_SB_DFFESR_Q_D[0] -.sym 29409 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29411 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29412 spi_if_ins.state_if[0] -.sym 29413 spi_if_ins.state_if[1] -.sym 29426 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 29434 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29435 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29436 spi_if_ins.state_if[0] -.sym 29437 spi_if_ins.state_if[1] -.sym 29440 spi_if_ins.state_if[0] -.sym 29441 spi_if_ins.state_if[1] -.sym 29450 w_fetch -.sym 29451 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 29452 w_load -.sym 29453 w_cs[0] -.sym 29454 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 29478 w_cs[0] -.sym 29479 w_cs[3] -.sym 29480 w_cs[2] -.sym 29481 w_cs[1] -.sym 29483 w_soft_reset -.sym 29484 w_cs[1] -.sym 29485 w_fetch -.sym 29486 w_soft_reset -.sym 29487 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 29488 w_cs[2] -.sym 29489 w_fetch -.sym 29494 w_rx_09_fifo_full -.sym 29502 w_rx_09_fifo_empty -.sym 29506 w_cs[0] -.sym 29507 w_cs[3] -.sym 29508 w_cs[1] -.sym 29509 w_cs[2] -.sym 29512 spi_if_ins.w_rx_data[6] -.sym 29513 spi_if_ins.w_rx_data[5] -.sym 29520 spi_if_ins.w_rx_data[6] -.sym 29521 spi_if_ins.w_rx_data[5] -.sym 29524 spi_if_ins.w_rx_data[6] -.sym 29525 spi_if_ins.w_rx_data[5] -.sym 29526 w_cs[0] -.sym 29527 w_cs[3] -.sym 29528 w_cs[1] -.sym 29529 w_cs[2] -.sym 29532 spi_if_ins.w_rx_data[5] -.sym 29533 spi_if_ins.w_rx_data[6] -.sym 29534 w_tx_data_smi[0] -.sym 29535 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 29536 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 29537 w_tx_data_io[0] -.sym 29538 w_cs[3] -.sym 29539 w_cs[1] -.sym 29540 w_cs[2] -.sym 29541 w_cs[0] -.sym 29542 w_cs[0] -.sym 29543 w_cs[1] -.sym 29544 w_cs[2] -.sym 29545 w_cs[3] -.sym 29546 spi_if_ins.w_rx_data[0] -.sym 29550 spi_if_ins.w_rx_data[2] -.sym 29555 w_ioc[2] -.sym 29556 w_ioc[4] -.sym 29557 w_ioc[3] -.sym 29558 spi_if_ins.w_rx_data[3] -.sym 29562 spi_if_ins.w_rx_data[1] -.sym 29566 spi_if_ins.w_rx_data[4] -.sym 29570 i_config[2]$SB_IO_IN -.sym 29571 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 29572 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2] -.sym 29573 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3] -.sym 29576 i_button_SB_LUT4_I1_O[0] -.sym 29577 i_button_SB_LUT4_I1_O[1] -.sym 29584 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 29585 o_tr_vc1$SB_IO_OUT -.sym 29588 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] -.sym 29589 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] -.sym 29590 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 29591 io_ctrl_ins.rf_mode[0] -.sym 29592 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 29593 io_ctrl_ins.o_pmod[2] -.sym 29595 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 29596 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 29597 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 29598 w_ioc[0] -.sym 29599 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 29600 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2] -.sym 29601 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 29602 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 29603 io_ctrl_ins.pmod_dir_state[0] -.sym 29604 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 29605 io_ctrl_ins.o_pmod[0] -.sym 29608 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 29609 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 29610 o_led0$SB_IO_OUT -.sym 29611 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 29612 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[2] -.sym 29613 io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O[3] -.sym 29614 o_led1$SB_IO_OUT -.sym 29615 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 29616 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[2] -.sym 29617 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[3] -.sym 29622 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 29623 io_ctrl_ins.pmod_dir_state[1] -.sym 29624 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 29625 o_shdn_rx_lna$SB_IO_OUT -.sym 29626 w_ioc[0] -.sym 29627 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 29628 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 29629 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 29630 i_config[3]$SB_IO_IN -.sym 29631 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 29632 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 29633 io_ctrl_ins.o_pmod[6] -.sym 29638 w_rx_data[0] -.sym 29650 w_rx_data[2] -.sym 29654 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 29655 io_ctrl_ins.pmod_dir_state[2] -.sym 29656 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 29657 o_shdn_tx_lna$SB_IO_OUT -.sym 29763 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29768 rx_09_fifo.rd_addr[1] -.sym 29772 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] -.sym 29773 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[2] -.sym 29776 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 29777 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[3] -.sym 29780 rx_09_fifo.rd_addr[4] -.sym 29781 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 29784 rx_09_fifo.rd_addr[5] -.sym 29785 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 29788 rx_09_fifo.rd_addr[6] -.sym 29789 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[6] -.sym 29792 rx_09_fifo.rd_addr[7] -.sym 29793 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[7] -.sym 29796 rx_09_fifo.rd_addr[8] -.sym 29797 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 29800 rx_09_fifo.rd_addr[9] -.sym 29801 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[9] -.sym 29805 $nextpnr_ICESTORM_LC_6$I3 -.sym 29806 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 29807 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29808 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_I2[1] -.sym 29809 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[2] -.sym 29810 rx_09_fifo.wr_addr[3] -.sym 29811 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[3] -.sym 29812 rx_09_fifo.wr_addr[6] -.sym 29813 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[6] -.sym 29816 rx_09_fifo.rd_addr[1] -.sym 29817 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29818 rx_09_fifo.wr_addr[7] -.sym 29819 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[7] -.sym 29820 rx_09_fifo.wr_addr[8] -.sym 29821 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[8] -.sym 29828 lvds_rx_09_inst.r_data[1] -.sym 29829 lvds_rx_09_inst.o_debug_state[0] -.sym 29832 lvds_rx_09_inst.r_data[0] -.sym 29833 lvds_rx_09_inst.o_debug_state[0] -.sym 29834 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29835 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 29836 rx_09_fifo.wr_addr[4] -.sym 29837 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[4] -.sym 29838 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[10] -.sym 29839 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[1] -.sym 29840 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[2] -.sym 29841 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O[3] -.sym 29842 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[0] -.sym 29843 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[1] -.sym 29844 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[2] -.sym 29845 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0[3] -.sym 29846 rx_09_fifo.wr_addr[5] -.sym 29847 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[5] -.sym 29848 rx_09_fifo.wr_addr[9] -.sym 29849 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0[9] -.sym 29851 lvds_rx_09_inst.r_cnt[1] -.sym 29852 w_lvds_rx_09_d1 -.sym 29853 lvds_rx_09_inst.o_debug_state[0] -.sym 29855 lvds_rx_09_inst.r_cnt[0] -.sym 29856 w_lvds_rx_09_d0 -.sym 29857 lvds_rx_09_inst.o_debug_state[0] -.sym 29860 w_soft_reset -.sym 29861 w_rx_09_fifo_push -.sym 29862 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 29863 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O[1] -.sym 29864 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[2] -.sym 29865 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_I1[3] -.sym 29866 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[0] -.sym 29867 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[1] -.sym 29868 w_rx_09_fifo_empty -.sym 29869 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O[3] -.sym 29872 rx_09_fifo.full_o_SB_LUT4_I3_I0_SB_LUT4_O_I3[1] -.sym 29873 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_LUT4_I0_O_SB_LUT4_O_1_I0[1] -.sym 29876 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0[1] -.sym 29877 rx_09_fifo.rd_addr[1] -.sym 29878 rx_09_fifo.wr_addr[3] -.sym 29879 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0] -.sym 29880 rx_09_fifo.rd_addr[7] -.sym 29881 rx_09_fifo.wr_addr[7] -.sym 29883 lvds_rx_09_inst.o_debug_state[1] -.sym 29884 lvds_rx_09_inst.o_debug_state[0] -.sym 29885 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_O[2] -.sym 29886 rx_09_fifo.rd_addr[8] -.sym 29887 rx_09_fifo.wr_addr[8] -.sym 29888 rx_09_fifo.rd_addr[9] -.sym 29889 rx_09_fifo.wr_addr[9] -.sym 29902 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0] -.sym 29903 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1] -.sym 29904 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2] -.sym 29905 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 29915 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 29916 lvds_rx_09_inst.o_debug_state[0] -.sym 29917 w_soft_reset -.sym 29918 lvds_rx_09_inst.r_push -.sym 29922 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29923 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29924 spi_if_ins.state_if[0] -.sym 29925 spi_if_ins.state_if[1] -.sym 29926 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29927 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29928 spi_if_ins.state_if[0] -.sym 29929 spi_if_ins.state_if[1] -.sym 29935 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29936 spi_if_ins.state_if[1] -.sym 29937 spi_if_ins.state_if[0] -.sym 29939 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29940 spi_if_ins.state_if[0] -.sym 29941 spi_if_ins.state_if[1] -.sym 29947 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29948 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 29949 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2] -.sym 29950 spi_if_ins.state_if_SB_DFFESR_Q_D[0] -.sym 29951 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 29952 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 29953 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29958 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29959 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 29960 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[2] -.sym 29961 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 29964 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1] -.sym 29965 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29968 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 29969 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29972 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[0] -.sym 29973 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[3] -.sym 29976 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] -.sym 29977 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 29990 r_tx_data[7] -.sym 29994 r_tx_data[4] -.sym 29999 w_fetch -.sym 30000 w_cs[1] -.sym 30001 w_load -.sym 30002 r_tx_data[1] -.sym 30010 r_tx_data[2] -.sym 30014 r_tx_data[5] -.sym 30024 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 30025 w_tx_data_io[6] -.sym 30028 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 30029 w_tx_data_io[3] -.sym 30031 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 30032 w_tx_data_io[5] -.sym 30033 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 30035 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 30036 w_tx_data_io[7] -.sym 30037 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 30038 w_tx_data_smi[1] -.sym 30039 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[1] -.sym 30040 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 30041 w_tx_data_io[1] -.sym 30043 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 30044 w_tx_data_io[2] -.sym 30045 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 30048 smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1[2] -.sym 30049 w_tx_data_io[4] -.sym 30056 w_ioc[3] -.sym 30057 w_ioc[2] -.sym 30059 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 30060 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 30061 w_soft_reset -.sym 30062 w_tx_data_sys[0] -.sym 30063 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[1] -.sym 30064 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[2] -.sym 30065 smi_ctrl_ins.o_data_out_SB_LUT4_I0_O[3] -.sym 30082 w_ioc[0] -.sym 30083 w_ioc[1] -.sym 30084 w_ioc[4] -.sym 30085 spi_if_ins.o_ioc_SB_LUT4_I2_O[2] -.sym 30086 w_ioc[1] -.sym 30087 w_ioc[4] -.sym 30088 spi_if_ins.o_ioc_SB_LUT4_I2_O[2] +.sym 28884 spi_if_ins.w_rx_data[6] +.sym 28885 spi_if_ins.w_rx_data[5] +.sym 28892 spi_if_ins.w_rx_data[5] +.sym 28893 spi_if_ins.w_rx_data[6] +.sym 28899 rx_24_fifo.rd_addr[0] +.sym 28904 rx_24_fifo.rd_addr[1] +.sym 28908 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 28909 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 28912 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 28913 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 28916 rx_24_fifo.rd_addr[4] +.sym 28917 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 28920 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 28921 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 28924 rx_24_fifo.rd_addr[6] +.sym 28925 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 28928 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 28929 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 28932 rx_24_fifo.rd_addr[8] +.sym 28933 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 28936 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 28937 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 28940 rx_24_fifo.rd_addr[1] +.sym 28941 rx_24_fifo.rd_addr[0] +.sym 28949 rx_24_fifo.rd_addr[0] +.sym 28956 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 28957 i_smi_a2_SB_LUT4_I1_O[1] +.sym 28962 lvds_rx_24_inst.r_data[10] +.sym 28970 lvds_rx_24_inst.r_data[25] +.sym 28974 lvds_rx_24_inst.r_data[17] +.sym 28986 lvds_rx_24_inst.r_data[14] +.sym 28990 lvds_rx_24_inst.r_data[16] +.sym 28998 w_rx_24_fifo_pulled_data[2] +.sym 28999 w_rx_24_fifo_pulled_data[18] +.sym 29000 smi_ctrl_ins.int_cnt_24[3] +.sym 29001 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 29002 $PACKER_VCC_NET +.sym 29006 w_rx_24_fifo_pulled_data[10] +.sym 29007 w_rx_24_fifo_pulled_data[26] +.sym 29008 smi_ctrl_ins.int_cnt_24[3] +.sym 29009 smi_ctrl_ins.int_cnt_24[4] +.sym 29010 w_rx_24_fifo_pulled_data[0] +.sym 29011 w_rx_24_fifo_pulled_data[16] +.sym 29012 smi_ctrl_ins.int_cnt_24[3] +.sym 29013 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 29016 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 29017 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 29018 w_rx_24_fifo_pulled_data[8] +.sym 29019 w_rx_24_fifo_pulled_data[24] +.sym 29020 smi_ctrl_ins.int_cnt_24[3] +.sym 29021 smi_ctrl_ins.int_cnt_24[4] +.sym 29026 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 29027 rx_24_fifo.wr_addr[7] +.sym 29028 rx_24_fifo.rd_addr[8] +.sym 29029 rx_24_fifo.wr_addr[8] +.sym 29030 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29031 rx_24_fifo.wr_addr[2] +.sym 29032 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 29033 rx_24_fifo.wr_addr[3] +.sym 29037 rx_24_fifo.wr_addr[0] +.sym 29038 w_rx_24_fifo_empty +.sym 29039 rx_24_fifo.empty_o_SB_LUT4_I0_I1[1] +.sym 29040 rx_24_fifo.empty_o_SB_LUT4_I0_I1[2] +.sym 29041 rx_24_fifo.empty_o_SB_LUT4_I0_I1[3] +.sym 29042 rx_24_fifo.rd_addr[4] +.sym 29043 rx_24_fifo.wr_addr[4] +.sym 29044 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 29045 rx_24_fifo.wr_addr[5] +.sym 29046 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 29060 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29061 rx_24_fifo.rd_addr[1] +.sym 29062 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 29068 i_smi_a2_SB_LUT4_I1_O[1] +.sym 29069 w_rx_24_fifo_push +.sym 29070 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 29074 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 29075 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[1] +.sym 29076 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[2] +.sym 29077 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2[3] +.sym 29078 rx_24_fifo.rd_addr[8] +.sym 29079 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 29080 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 29081 rx_24_fifo.rd_addr[6] +.sym 29082 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 29086 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 29091 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29096 rx_24_fifo.wr_addr[2] +.sym 29097 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29100 rx_24_fifo.wr_addr[3] +.sym 29101 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2] +.sym 29104 rx_24_fifo.wr_addr[4] +.sym 29105 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[3] +.sym 29108 rx_24_fifo.wr_addr[5] +.sym 29109 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[4] +.sym 29112 rx_24_fifo.wr_addr[6] +.sym 29113 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[5] +.sym 29116 rx_24_fifo.wr_addr[7] +.sym 29117 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[6] +.sym 29118 rx_24_fifo.rd_addr[8] +.sym 29120 rx_24_fifo.wr_addr[8] +.sym 29121 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7] +.sym 29122 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 29124 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 29125 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 29129 $nextpnr_ICESTORM_LC_2$I3 +.sym 29130 lvds_rx_24_inst.r_data[1] +.sym 29142 lvds_rx_24_inst.r_data[7] +.sym 29162 lvds_rx_24_inst.r_push +.sym 29231 i_smi_a2_SB_LUT4_I1_O[1] +.sym 29232 lvds_rx_09_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[3] +.sym 29233 lvds_rx_09_inst.o_debug_state[1] +.sym 29242 lvds_rx_09_inst.r_data[10] +.sym 29254 rx_09_fifo.rd_addr[5] +.sym 29255 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 29256 rx_09_fifo.rd_addr[6] +.sym 29257 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 29266 lvds_rx_24_inst.r_data[24] +.sym 29280 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 29281 i_smi_a2_SB_LUT4_I1_O[1] +.sym 29282 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 29283 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 29284 rx_09_fifo.rd_addr[9] +.sym 29285 rx_09_fifo.full_o_SB_LUT4_I3_I2[9] +.sym 29289 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 29290 rx_09_fifo.full_o_SB_LUT4_I3_I2[1] +.sym 29295 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 29296 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 29297 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[2] +.sym 29298 rx_09_fifo.full_o_SB_LUT4_I3_O[0] +.sym 29299 rx_09_fifo.full_o_SB_LUT4_I3_O[1] +.sym 29300 rx_09_fifo.full_o_SB_LUT4_I3_O[2] +.sym 29301 rx_09_fifo.full_o_SB_LUT4_I3_O[3] +.sym 29302 rx_09_fifo.rd_addr[1] +.sym 29303 rx_09_fifo.full_o_SB_LUT4_I3_I2[1] +.sym 29304 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 29305 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 29306 rx_09_fifo.full_o_SB_LUT4_I3_I2[9] +.sym 29310 rx_09_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 29315 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29320 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 29321 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29324 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 29325 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[2] +.sym 29328 rx_09_fifo.wr_addr[4] +.sym 29329 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[3] +.sym 29332 rx_09_fifo.wr_addr[5] +.sym 29333 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[4] +.sym 29336 rx_09_fifo.wr_addr[6] +.sym 29337 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[5] +.sym 29340 rx_09_fifo.wr_addr[7] +.sym 29341 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[6] +.sym 29344 rx_09_fifo.wr_addr[8] +.sym 29345 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[7] +.sym 29348 rx_09_fifo.wr_addr[9] +.sym 29349 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[8] +.sym 29353 $nextpnr_ICESTORM_LC_15$I3 +.sym 29361 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E +.sym 29364 i_smi_a2_SB_LUT4_I1_O[1] +.sym 29365 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 29368 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29369 rx_09_fifo.rd_addr[1] +.sym 29370 smi_ctrl_ins.w_fifo_24_pull_trigger +.sym 29374 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 29375 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29376 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 29377 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 29378 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0] +.sym 29379 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1] +.sym 29380 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2] +.sym 29381 i_smi_a2_SB_LUT4_I1_O[0] +.sym 29386 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 29387 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 29388 rx_09_fifo.empty_o_SB_LUT4_I3_I2[2] +.sym 29389 w_rx_09_fifo_empty +.sym 29390 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 29391 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 29392 rx_09_fifo.empty_o_SB_LUT4_I3_O[2] +.sym 29393 rx_09_fifo.empty_o_SB_LUT4_I3_O[3] +.sym 29394 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[0] +.sym 29395 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1] +.sym 29396 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2] +.sym 29397 i_smi_a2_SB_LUT4_I1_O[0] +.sym 29402 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0] +.sym 29403 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1] +.sym 29404 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2] +.sym 29405 i_smi_a2_SB_LUT4_I1_O[0] +.sym 29406 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0] +.sym 29407 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1] +.sym 29408 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2] +.sym 29409 i_smi_a2_SB_LUT4_I1_O[0] +.sym 29414 w_rx_09_fifo_pulled_data[8] +.sym 29415 w_rx_09_fifo_pulled_data[24] +.sym 29416 smi_ctrl_ins.int_cnt_09[4] +.sym 29417 smi_ctrl_ins.int_cnt_09[3] +.sym 29419 smi_ctrl_ins.r_fifo_09_pull_1 +.sym 29420 w_rx_09_fifo_empty +.sym 29421 smi_ctrl_ins.r_fifo_09_pull +.sym 29422 w_rx_09_fifo_pulled_data[10] +.sym 29423 w_rx_09_fifo_pulled_data[26] +.sym 29424 smi_ctrl_ins.int_cnt_09[4] +.sym 29425 smi_ctrl_ins.int_cnt_09[3] +.sym 29426 w_rx_09_fifo_pulled_data[11] +.sym 29427 w_rx_09_fifo_pulled_data[27] +.sym 29428 smi_ctrl_ins.int_cnt_09[4] +.sym 29429 smi_ctrl_ins.int_cnt_09[3] +.sym 29430 lvds_rx_09_inst.r_data[14] +.sym 29434 w_rx_09_fifo_pulled_data[9] +.sym 29435 w_rx_09_fifo_pulled_data[25] +.sym 29436 smi_ctrl_ins.int_cnt_09[4] +.sym 29437 smi_ctrl_ins.int_cnt_09[3] +.sym 29443 rx_24_fifo.rd_addr[0] +.sym 29448 rx_24_fifo.rd_addr[1] +.sym 29449 rx_24_fifo.rd_addr[0] +.sym 29452 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29453 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[2] +.sym 29456 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 29457 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[3] +.sym 29460 rx_24_fifo.rd_addr[4] +.sym 29461 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[4] +.sym 29464 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 29465 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[5] +.sym 29468 rx_24_fifo.rd_addr[6] +.sym 29469 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[6] +.sym 29472 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 29473 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[7] +.sym 29476 rx_24_fifo.rd_addr[8] +.sym 29477 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[8] +.sym 29480 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 29481 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0[9] +.sym 29485 $nextpnr_ICESTORM_LC_7$I3 +.sym 29486 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0] +.sym 29487 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29488 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 29489 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3] +.sym 29490 smi_ctrl_ins.r_fifo_09_pull +.sym 29494 rx_24_fifo.wr_addr[3] +.sym 29495 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[3] +.sym 29496 rx_24_fifo.wr_addr[4] +.sym 29497 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[4] +.sym 29498 rx_24_fifo.wr_addr[5] +.sym 29499 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[5] +.sym 29500 rx_24_fifo.wr_addr[7] +.sym 29501 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[7] +.sym 29502 rx_24_fifo.rd_addr[6] +.sym 29503 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[6] +.sym 29504 rx_24_fifo.wr_addr[6] +.sym 29505 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29508 lvds_rx_24_inst.o_debug_state[0] +.sym 29509 lvds_rx_24_inst.r_data[19] +.sym 29510 rx_24_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 29511 rx_24_fifo.empty_o_SB_LUT4_I0_O[1] +.sym 29512 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29513 rx_24_fifo.empty_o_SB_LUT4_I0_O[3] +.sym 29514 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[0] +.sym 29515 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[1] +.sym 29516 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 29517 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[3] +.sym 29518 rx_24_fifo.full_o_SB_LUT4_I3_I2[0] +.sym 29519 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[9] +.sym 29520 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 29521 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29522 rx_24_fifo.rd_addr[6] +.sym 29523 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[6] +.sym 29524 rx_24_fifo.rd_addr[4] +.sym 29525 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 29526 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 29527 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1] +.sym 29528 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[2] +.sym 29529 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[3] +.sym 29532 rx_24_fifo.wr_addr[0] +.sym 29533 rx_24_fifo.rd_addr[0] +.sym 29536 lvds_rx_24_inst.o_debug_state[0] +.sym 29537 lvds_rx_24_inst.r_data[23] +.sym 29539 rx_24_fifo.wr_addr[0] +.sym 29544 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29545 rx_24_fifo.wr_addr[0] +.sym 29548 rx_24_fifo.wr_addr[2] +.sym 29549 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 29552 rx_24_fifo.wr_addr[3] +.sym 29553 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 29556 rx_24_fifo.wr_addr[4] +.sym 29557 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] +.sym 29560 rx_24_fifo.wr_addr[5] +.sym 29561 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] +.sym 29564 rx_24_fifo.wr_addr[6] +.sym 29565 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] +.sym 29568 rx_24_fifo.wr_addr[7] +.sym 29569 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] +.sym 29572 rx_24_fifo.wr_addr[8] +.sym 29573 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] +.sym 29576 rx_24_fifo.full_o_SB_LUT4_I3_I2[2] +.sym 29577 rx_24_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] +.sym 29578 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 29582 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 29583 rx_24_fifo.rd_addr[4] +.sym 29584 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29585 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[2] +.sym 29586 w_rx_24_fifo_push +.sym 29587 rx_24_fifo.full_o_SB_LUT4_I3_I1[1] +.sym 29588 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29589 w_rx_24_fifo_full +.sym 29590 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1] +.sym 29594 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[2] +.sym 29598 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[4] +.sym 29602 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 29603 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29604 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1] +.sym 29605 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3] +.sym 29606 rx_24_fifo.full_o_SB_LUT4_I3_O[0] +.sym 29607 rx_24_fifo.full_o_SB_LUT4_I3_O[1] +.sym 29608 rx_24_fifo.full_o_SB_LUT4_I3_O[2] +.sym 29609 rx_24_fifo.full_o_SB_LUT4_I3_O[3] +.sym 29610 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 29611 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[2] +.sym 29612 rx_24_fifo.empty_o_SB_LUT4_I0_O[0] +.sym 29613 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[3] +.sym 29614 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0] +.sym 29615 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[4] +.sym 29616 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[2] +.sym 29617 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[3] +.sym 29618 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0] +.sym 29619 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1] +.sym 29620 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[2] +.sym 29621 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[3] +.sym 29622 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[1] +.sym 29623 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1] +.sym 29624 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0[2] +.sym 29625 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[6] +.sym 29626 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 29627 rx_24_fifo.rd_addr[6] +.sym 29628 rx_24_fifo.rd_addr[4] +.sym 29629 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[3] +.sym 29630 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5] +.sym 29631 rx_24_fifo.rd_addr[6] +.sym 29632 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[9] +.sym 29633 w_rx_24_fifo_push +.sym 29636 lvds_rx_24_inst.o_debug_state[0] +.sym 29637 lvds_rx_24_inst.r_data[16] +.sym 29640 lvds_rx_24_inst.o_debug_state[0] +.sym 29641 lvds_rx_24_inst.r_data[20] +.sym 29644 lvds_rx_24_inst.o_debug_state[0] +.sym 29645 lvds_rx_24_inst.r_data[1] +.sym 29648 i_smi_a2_SB_LUT4_I1_O[1] +.sym 29649 w_rx_24_fifo_push +.sym 29656 lvds_rx_24_inst.o_debug_state[0] +.sym 29657 lvds_rx_24_inst.r_data[18] +.sym 29660 lvds_rx_24_inst.o_debug_state[0] +.sym 29661 lvds_rx_24_inst.r_data[21] +.sym 29664 lvds_rx_24_inst.o_debug_state[0] +.sym 29665 w_lvds_rx_24_d1 +.sym 29670 lvds_rx_24_inst.r_data[22] +.sym 29674 lvds_rx_24_inst.r_data[21] +.sym 29682 lvds_rx_24_inst.r_data[23] +.sym 29694 lvds_rx_24_inst.r_data[20] +.sym 29703 w_rx_24_fifo_full +.sym 29704 lvds_rx_24_inst.o_debug_state[0] +.sym 29705 lvds_rx_24_inst.o_debug_state[1] +.sym 29713 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E +.sym 29726 lvds_rx_24_inst.o_debug_state[0] +.sym 29727 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 29728 i_smi_a2_SB_LUT4_I1_O[1] +.sym 29729 lvds_rx_24_inst.o_debug_state[1] +.sym 29732 lvds_rx_24_inst.o_debug_state[0] +.sym 29733 lvds_rx_24_inst.r_data[15] +.sym 29763 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 29768 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29769 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1] +.sym 29772 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 29773 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2] +.sym 29776 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 29777 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3] +.sym 29780 rx_09_fifo.wr_addr[4] +.sym 29781 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4] +.sym 29784 rx_09_fifo.wr_addr[5] +.sym 29785 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5] +.sym 29788 rx_09_fifo.wr_addr[6] +.sym 29789 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6] +.sym 29792 rx_09_fifo.wr_addr[7] +.sym 29793 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7] +.sym 29796 rx_09_fifo.wr_addr[8] +.sym 29797 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8] +.sym 29800 rx_09_fifo.wr_addr[9] +.sym 29801 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[9] +.sym 29802 w_rx_09_fifo_push +.sym 29803 rx_09_fifo.rd_addr[4] +.sym 29804 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 29805 w_rx_09_fifo_full +.sym 29806 lvds_rx_09_inst.r_data[20] +.sym 29810 lvds_rx_09_inst.r_data[19] +.sym 29818 lvds_rx_09_inst.r_data[15] +.sym 29824 i_smi_a2_SB_LUT4_I1_O[1] +.sym 29825 w_rx_09_fifo_push +.sym 29828 rx_09_fifo.rd_addr[1] +.sym 29829 rx_09_fifo.rd_addr[0] +.sym 29830 rx_09_fifo.wr_addr[6] +.sym 29831 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[6] +.sym 29832 rx_09_fifo.wr_addr[9] +.sym 29833 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[9] +.sym 29834 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29835 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] +.sym 29836 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[2] +.sym 29837 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2[3] +.sym 29838 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 29839 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 29840 rx_09_fifo.empty_o_SB_LUT4_I3_O[1] +.sym 29841 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[3] +.sym 29842 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[8] +.sym 29843 rx_09_fifo.wr_addr[8] +.sym 29844 rx_09_fifo.wr_addr[5] +.sym 29845 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[5] +.sym 29846 rx_09_fifo.wr_addr[7] +.sym 29847 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[7] +.sym 29848 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 29849 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[2] +.sym 29850 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[0] +.sym 29851 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[1] +.sym 29852 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[2] +.sym 29853 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O_I0[3] +.sym 29854 $PACKER_GND_NET +.sym 29858 rx_09_fifo.full_o_SB_LUT4_I3_I2[4] +.sym 29862 rx_09_fifo.full_o_SB_LUT4_I3_I2[5] +.sym 29866 rx_09_fifo.full_o_SB_LUT4_I3_I2[8] +.sym 29870 rx_09_fifo.full_o_SB_LUT4_I3_I2[3] +.sym 29874 rx_09_fifo.full_o_SB_LUT4_I3_I2[6] +.sym 29878 rx_09_fifo.full_o_SB_LUT4_I3_I2[7] +.sym 29885 sys_ctrl_ins.reset_cmd +.sym 29886 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0] +.sym 29887 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1] +.sym 29888 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2] +.sym 29889 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2] +.sym 29892 lvds_rx_24_inst.o_debug_state[0] +.sym 29893 lvds_rx_24_inst.r_data[24] +.sym 29896 lvds_rx_24_inst.o_debug_state[0] +.sym 29897 lvds_rx_24_inst.r_data[26] +.sym 29902 rx_09_fifo.rd_addr[4] +.sym 29903 rx_09_fifo.wr_addr[4] +.sym 29904 rx_09_fifo.rd_addr[6] +.sym 29905 rx_09_fifo.wr_addr[6] +.sym 29910 rx_09_fifo.empty_o_SB_LUT4_I3_I2[0] +.sym 29911 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 29912 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[2] +.sym 29913 rx_09_fifo.empty_o_SB_LUT4_I3_O_SB_LUT4_O_I2[3] +.sym 29916 lvds_rx_24_inst.o_debug_state[0] +.sym 29917 lvds_rx_24_inst.r_data[9] +.sym 29918 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 29919 rx_09_fifo.wr_addr[7] +.sym 29920 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 29921 rx_09_fifo.wr_addr[8] +.sym 29922 lvds_rx_24_inst.r_data[15] +.sym 29934 lvds_rx_24_inst.r_data[26] +.sym 29946 lvds_rx_24_inst.r_data[28] +.sym 29956 lvds_rx_24_inst.o_debug_state[0] +.sym 29957 lvds_rx_24_inst.r_data[22] +.sym 29961 w_rx_24_fifo_empty +.sym 29972 lvds_rx_24_inst.o_debug_state[0] +.sym 29973 lvds_rx_24_inst.r_data[7] +.sym 29975 smi_ctrl_ins.r_fifo_24_pull_1 +.sym 29976 w_rx_24_fifo_empty +.sym 29977 smi_ctrl_ins.r_fifo_24_pull +.sym 29986 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[1] +.sym 29987 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[1] +.sym 29988 rx_24_fifo.wr_addr[2] +.sym 29989 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[2] +.sym 29992 lvds_rx_24_inst.o_debug_state[0] +.sym 29993 lvds_rx_24_inst.r_data[14] +.sym 29996 lvds_rx_24_inst.o_debug_state[0] +.sym 29997 lvds_rx_24_inst.r_data[17] +.sym 29998 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[10] +.sym 29999 rx_24_fifo.wr_addr[8] +.sym 30000 rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1[8] +.sym 30001 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 30004 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30005 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3] +.sym 30008 lvds_rx_24_inst.o_debug_state[0] +.sym 30009 lvds_rx_24_inst.r_data[12] +.sym 30010 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[0] +.sym 30011 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[1] +.sym 30012 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[2] +.sym 30013 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O[3] +.sym 30016 lvds_rx_24_inst.o_debug_state[0] +.sym 30017 lvds_rx_24_inst.r_data[10] +.sym 30037 w_cs[0] +.sym 30042 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30054 w_fetch +.sym 30055 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30056 w_load +.sym 30057 w_cs[0] +.sym 30064 spi_if_ins.w_rx_data[5] +.sym 30065 spi_if_ins.w_rx_data[6] +.sym 30066 i_config_SB_LUT4_I0_I1[2] +.sym 30071 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30072 w_cs[0] +.sym 30073 w_fetch +.sym 30076 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[8] +.sym 30077 rx_24_fifo.rd_addr[8] +.sym 30079 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30080 w_cs[1] +.sym 30081 w_fetch +.sym 30082 w_ioc[1] +.sym 30083 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30084 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 30085 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30087 w_ioc[1] +.sym 30088 w_ioc[4] .sym 30089 w_ioc[0] -.sym 30091 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 30092 w_ioc[0] -.sym 30093 w_ioc[1] -.sym 30094 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 30095 io_ctrl_ins.pmod_dir_state[5] -.sym 30096 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 30097 io_ctrl_ins.o_pmod[5] -.sym 30099 w_ioc[1] -.sym 30100 w_ioc[0] -.sym 30101 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 30102 w_rx_data[2] -.sym 30107 w_ioc[0] -.sym 30108 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 30109 w_ioc[1] -.sym 30110 w_rx_data[1] -.sym 30114 w_ioc[1] -.sym 30115 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] -.sym 30116 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 30117 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 30120 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 30121 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 30122 w_rx_data[1] -.sym 30126 w_rx_data[6] -.sym 30130 w_rx_data[0] -.sym 30134 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 30135 io_ctrl_ins.debug_mode[1] -.sym 30136 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 30137 io_ctrl_ins.o_pmod[1] -.sym 30142 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 30143 io_ctrl_ins.debug_mode[0] -.sym 30144 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 30145 io_ctrl_ins.mixer_en_state -.sym 30154 io_ctrl_ins.rf_mode[1] -.sym 30155 io_ctrl_ins.rf_mode[2] -.sym 30156 io_ctrl_ins.rf_pin_state[2] -.sym 30157 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 30158 io_ctrl_ins.rf_pin_state[0] -.sym 30159 io_ctrl_ins.rf_mode[2] -.sym 30160 io_ctrl_ins.rf_mode[1] -.sym 30161 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 30167 io_ctrl_ins.rf_pin_state[1] -.sym 30168 io_ctrl_ins.rf_mode[1] -.sym 30169 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 30264 w_soft_reset -.sym 30265 i_smi_soe_se$SB_IO_IN -.sym 30274 w_rx_09_fifo_pulled_data[23] -.sym 30275 w_rx_09_fifo_pulled_data[31] -.sym 30276 smi_ctrl_ins.int_cnt_09[4] -.sym 30277 smi_ctrl_ins.int_cnt_09[3] -.sym 30286 w_rx_09_fifo_pulled_data[22] -.sym 30287 w_rx_09_fifo_pulled_data[30] -.sym 30288 smi_ctrl_ins.int_cnt_09[4] -.sym 30289 smi_ctrl_ins.int_cnt_09[3] -.sym 30310 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 30318 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 30319 w_rx_09_fifo_empty -.sym 30320 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 30321 w_soft_reset -.sym 30326 smi_ctrl_ins.w_fifo_09_pull_trigger -.sym 30342 w_soft_reset -.sym 30343 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 30344 w_rx_09_fifo_empty -.sym 30345 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 30350 i_smi_a2$SB_IO_IN -.sym 30351 i_smi_a1$SB_IO_IN -.sym 30352 i_smi_a3$SB_IO_IN -.sym 30353 w_soft_reset -.sym 30354 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[0] -.sym 30355 w_rx_09_fifo_empty -.sym 30356 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3] -.sym 30357 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I3[3] -.sym 30359 smi_ctrl_ins.int_cnt_09[4] -.sym 30360 smi_ctrl_ins.int_cnt_09[3] +.sym 30091 w_ioc[2] +.sym 30092 w_ioc[4] +.sym 30093 w_ioc[3] +.sym 30100 w_ioc[3] +.sym 30101 w_ioc[2] +.sym 30102 spi_if_ins.w_rx_data[4] +.sym 30106 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[3] +.sym 30107 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3[0] +.sym 30108 rx_24_fifo.rd_addr[1] +.sym 30109 rx_24_fifo.wr_addr_SB_DFFESR_Q_D[1] +.sym 30114 lvds_rx_24_inst.r_data[2] +.sym 30118 lvds_rx_24_inst.r_data[9] +.sym 30122 lvds_rx_24_inst.r_data[4] +.sym 30127 w_ioc[2] +.sym 30128 w_ioc[3] +.sym 30129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3[1] +.sym 30132 w_ioc[1] +.sym 30133 w_ioc[0] +.sym 30140 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0[2] +.sym 30141 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3[1] +.sym 30143 w_ioc[4] +.sym 30144 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 30145 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0[2] +.sym 30146 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 30147 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30148 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[2] +.sym 30149 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 30150 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0] +.sym 30151 i_config_SB_LUT4_I0_I1[2] +.sym 30152 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2] +.sym 30153 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3] +.sym 30160 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 30161 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 30162 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 30163 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30164 i_config_SB_LUT4_I0_I1[2] +.sym 30165 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 30170 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30171 io_ctrl_ins.o_pmod[2] +.sym 30172 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 30173 o_shdn_tx_lna$SB_IO_OUT +.sym 30182 w_rx_data[6] +.sym 30190 w_rx_data[7] +.sym 30194 w_rx_data[2] +.sym 30202 w_rx_data[1] +.sym 30235 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30236 lvds_rx_24_inst.r_push_SB_DFFESR_Q_E_SB_LUT4_O_I1[1] +.sym 30237 lvds_rx_24_inst.o_debug_state[1] +.sym 30254 lvds_rx_09_inst.r_data[11] +.sym 30266 lvds_rx_09_inst.r_data[12] +.sym 30289 rx_09_fifo.rd_addr[0] +.sym 30307 rx_09_fifo.rd_addr[0] +.sym 30312 rx_09_fifo.rd_addr[1] +.sym 30313 rx_09_fifo.rd_addr[0] +.sym 30316 rx_09_fifo.empty_o_SB_LUT4_I3_I2[1] +.sym 30317 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[2] +.sym 30320 rx_09_fifo.empty_o_SB_LUT4_I3_O[0] +.sym 30321 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[3] +.sym 30324 rx_09_fifo.rd_addr[4] +.sym 30325 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[4] +.sym 30328 rx_09_fifo.rd_addr[5] +.sym 30329 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[5] +.sym 30332 rx_09_fifo.rd_addr[6] +.sym 30333 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[6] +.sym 30336 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O[0] +.sym 30337 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[7] +.sym 30340 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 30341 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[8] +.sym 30344 rx_09_fifo.rd_addr[9] +.sym 30345 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2[9] +.sym 30349 $nextpnr_ICESTORM_LC_5$I3 +.sym 30350 rx_09_fifo.wr_addr[8] +.sym 30351 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[8] +.sym 30352 rx_09_fifo.wr_addr[4] +.sym 30353 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[4] +.sym 30354 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[5] +.sym 30355 rx_09_fifo.wr_addr[5] +.sym 30356 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[10] +.sym 30357 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I3[3] +.sym 30360 w_rx_24_fifo_empty .sym 30361 w_rx_09_fifo_empty -.sym 30365 w_soft_reset -.sym 30366 w_rx_09_fifo_pulled_data[16] -.sym 30367 w_rx_09_fifo_pulled_data[24] -.sym 30368 smi_ctrl_ins.int_cnt_09[4] -.sym 30369 smi_ctrl_ins.int_cnt_09[3] -.sym 30370 lvds_rx_09_inst.o_debug_state[1] -.sym 30371 w_lvds_rx_09_d1 -.sym 30372 w_lvds_rx_09_d0 -.sym 30373 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E[3] -.sym 30385 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E -.sym 30390 w_rx_09_fifo_pulled_data[0] -.sym 30391 w_rx_09_fifo_pulled_data[8] -.sym 30392 smi_ctrl_ins.int_cnt_09[4] -.sym 30393 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_15_O[3] -.sym 30399 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 30400 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3 -.sym 30401 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 30428 i_ss$SB_IO_IN -.sym 30429 spi_if_ins.r_tx_data_valid -.sym 30430 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 30434 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0] -.sym 30435 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1] -.sym 30436 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 30437 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 30439 spi_if_ins.spi.r_tx_byte[1] -.sym 30440 spi_if_ins.spi.r_tx_byte[5] -.sym 30441 spi_if_ins.spi.r_tx_bit_count[2] -.sym 30442 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] -.sym 30443 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] -.sym 30444 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 30445 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3] -.sym 30446 spi_if_ins.r_tx_byte[7] -.sym 30450 spi_if_ins.r_tx_byte[5] -.sym 30454 spi_if_ins.r_tx_byte[3] -.sym 30458 spi_if_ins.spi.r_tx_byte[3] -.sym 30459 spi_if_ins.spi.r_tx_byte[7] -.sym 30460 spi_if_ins.spi.r_tx_bit_count[2] -.sym 30461 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 30467 spi_if_ins.spi.r_tx_byte[0] -.sym 30468 spi_if_ins.spi.r_tx_byte[4] -.sym 30469 spi_if_ins.spi.r_tx_bit_count[2] -.sym 30470 spi_if_ins.r_tx_byte[0] -.sym 30476 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] -.sym 30477 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] -.sym 30478 spi_if_ins.spi.r_tx_byte[2] -.sym 30479 spi_if_ins.spi.r_tx_byte[6] -.sym 30480 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 30481 spi_if_ins.spi.r_tx_bit_count[2] -.sym 30482 spi_if_ins.r_tx_byte[4] -.sym 30486 spi_if_ins.r_tx_byte[2] -.sym 30490 spi_if_ins.r_tx_byte[1] -.sym 30502 spi_if_ins.r_tx_byte[6] +.sym 30363 smi_ctrl_ins.int_cnt_09[4] +.sym 30364 smi_ctrl_ins.int_cnt_09[3] +.sym 30365 w_rx_09_fifo_empty +.sym 30366 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[7] +.sym 30367 rx_09_fifo.wr_addr[7] +.sym 30368 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0[6] +.sym 30369 rx_09_fifo.wr_addr[6] +.sym 30370 spi_if_ins.spi.r_tx_byte[1] +.sym 30371 spi_if_ins.spi.r_tx_byte[5] +.sym 30372 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 30373 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30374 rx_09_fifo.rd_addr[5] +.sym 30375 rx_09_fifo.wr_addr[5] +.sym 30376 rx_09_fifo.rd_addr[9] +.sym 30377 rx_09_fifo.wr_addr[9] +.sym 30381 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30382 spi_if_ins.r_tx_byte[7] +.sym 30386 spi_if_ins.r_tx_byte[1] +.sym 30394 spi_if_ins.r_tx_byte[3] +.sym 30398 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0] +.sym 30399 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1] +.sym 30400 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 30401 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 30406 spi_if_ins.r_tx_byte[4] +.sym 30410 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30411 i_smi_a1$SB_IO_IN +.sym 30412 i_smi_a2$SB_IO_IN +.sym 30413 i_smi_a3$SB_IO_IN +.sym 30414 spi_if_ins.r_tx_byte[2] +.sym 30419 i_smi_a2$SB_IO_IN +.sym 30420 i_smi_a1$SB_IO_IN +.sym 30421 i_smi_a3$SB_IO_IN +.sym 30422 spi_if_ins.r_tx_byte[5] +.sym 30426 spi_if_ins.r_tx_byte[6] +.sym 30430 spi_if_ins.r_tx_byte[0] +.sym 30434 w_rx_09_fifo_empty +.sym 30445 spi_if_ins.state_if_SB_DFFE_Q_E +.sym 30450 w_rx_24_fifo_empty +.sym 30462 w_rx_09_fifo_full +.sym 30470 smi_ctrl_ins.w_fifo_09_pull_trigger +.sym 30482 smi_ctrl_ins.r_fifo_24_pull +.sym 30501 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30502 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 30503 spi_if_ins.state_if[2] +.sym 30504 spi_if_ins.state_if[0] +.sym 30505 spi_if_ins.state_if[1] .sym 30509 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O -.sym 30513 spi_if_ins.o_data_in_SB_DFFE_Q_E -.sym 30530 r_tx_data[0] -.sym 30542 r_tx_data[3] -.sym 30558 r_tx_data[6] -.sym 30578 w_rx_data[0] -.sym 30582 w_rx_data[4] -.sym 30590 w_rx_data[3] -.sym 30596 w_soft_reset -.sym 30597 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 30598 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 30599 io_ctrl_ins.pmod_dir_state[6] -.sym 30600 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 30601 o_rx_h_tx_l_b$SB_IO_OUT -.sym 30604 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 30605 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 30606 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 30607 i_button$SB_IO_IN -.sym 30608 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 30609 io_ctrl_ins.o_pmod[7] -.sym 30610 w_rx_data[6] -.sym 30614 w_rx_data[7] -.sym 30622 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 30623 io_ctrl_ins.pmod_dir_state[7] -.sym 30624 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 30625 o_rx_h_tx_l$SB_IO_OUT -.sym 30626 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 30627 io_ctrl_ins.pmod_dir_state[4] -.sym 30628 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 30629 io_ctrl_ins.rf_mode[2] +.sym 30514 lvds_rx_24_inst.r_data[13] +.sym 30519 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 30520 spi_if_ins.state_if[2] +.sym 30521 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 30522 spi_if_ins.state_if[2] +.sym 30523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 30524 spi_if_ins.state_if[0] +.sym 30525 spi_if_ins.state_if[1] +.sym 30532 spi_if_ins.w_rx_data[5] +.sym 30533 spi_if_ins.w_rx_data[6] +.sym 30534 w_cs[0] +.sym 30535 w_cs[1] +.sym 30536 w_cs[3] +.sym 30537 w_cs[2] +.sym 30550 i_smi_a1$SB_IO_IN +.sym 30551 i_smi_a3$SB_IO_IN +.sym 30552 i_smi_a2$SB_IO_IN +.sym 30553 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30563 w_fetch +.sym 30564 w_cs[1] +.sym 30565 w_load +.sym 30566 spi_if_ins.w_rx_data[1] +.sym 30570 spi_if_ins.w_rx_data[3] +.sym 30574 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30575 w_ioc[1] +.sym 30576 w_cs[2] +.sym 30577 w_fetch +.sym 30578 spi_if_ins.w_rx_data[4] +.sym 30584 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30585 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1] +.sym 30586 spi_if_ins.w_rx_data[6] +.sym 30590 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 30594 spi_if_ins.w_rx_data[1] +.sym 30598 spi_if_ins.w_rx_data[0] +.sym 30602 sys_ctrl_ins.i_cs_SB_DFFE_Q_D[0] +.sym 30607 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 30608 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 30609 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30610 spi_if_ins.w_rx_data[3] +.sym 30614 spi_if_ins.w_rx_data[2] +.sym 30626 w_rx_data[2] .sym 30630 w_rx_data[3] -.sym 30634 sys_ctrl_ins.o_data_out_SB_DFFE_Q_D[2] -.sym 30635 io_ctrl_ins.pmod_dir_state[3] -.sym 30636 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 30637 io_ctrl_ins.o_pmod[3] -.sym 30639 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2[1] -.sym 30640 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[0] -.sym 30641 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[3] -.sym 30642 w_rx_data[1] -.sym 30646 w_rx_data[5] -.sym 30653 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 30654 w_rx_data[4] -.sym 30669 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O -.sym 30670 w_rx_data[2] -.sym 30678 w_rx_data[1] -.sym 30682 w_rx_data[0] -.sym 30688 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 30689 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] -.sym 30749 r_counter -.sym 30758 lvds_rx_09_inst.r_data[29] -.sym 30762 lvds_rx_09_inst.r_data[26] -.sym 30766 lvds_rx_09_inst.r_data[28] -.sym 30770 lvds_rx_09_inst.r_data[24] -.sym 30782 lvds_rx_09_inst.r_data[27] -.sym 30790 w_rx_09_fifo_pulled_data[21] -.sym 30791 w_rx_09_fifo_pulled_data[29] -.sym 30792 smi_ctrl_ins.int_cnt_09[4] -.sym 30793 smi_ctrl_ins.int_cnt_09[3] -.sym 30802 w_rx_09_fifo_pulled_data[20] -.sym 30803 w_rx_09_fifo_pulled_data[28] -.sym 30804 smi_ctrl_ins.int_cnt_09[4] -.sym 30805 smi_ctrl_ins.int_cnt_09[3] -.sym 30806 w_rx_09_fifo_pulled_data[6] -.sym 30807 w_rx_09_fifo_pulled_data[14] -.sym 30808 smi_ctrl_ins.int_cnt_09[4] -.sym 30809 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_3_O[3] -.sym 30810 w_rx_09_fifo_pulled_data[7] -.sym 30811 w_rx_09_fifo_pulled_data[15] -.sym 30812 smi_ctrl_ins.int_cnt_09[4] -.sym 30813 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_1_O[3] -.sym 30818 w_soft_reset -.sym 30819 i_smi_a1$SB_IO_IN -.sym 30820 i_smi_a2$SB_IO_IN -.sym 30821 i_smi_a3$SB_IO_IN -.sym 30837 smi_ctrl_ins.int_cnt_09[3] -.sym 30848 smi_ctrl_ins.int_cnt_09[4] -.sym 30849 smi_ctrl_ins.int_cnt_09[3] -.sym 30856 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 30857 lvds_rx_09_inst.o_debug_state[0] -.sym 30870 lvds_rx_09_inst.o_debug_state[1] -.sym 30871 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 30872 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[2] -.sym 30873 lvds_rx_09_inst.o_debug_state[0] -.sym 30874 lvds_rx_09_inst.o_debug_state[1] -.sym 30875 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O[0] -.sym 30876 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[1] -.sym 30877 lvds_rx_09_inst.o_debug_state[0] -.sym 30883 lvds_rx_09_inst.r_phase_count[0] -.sym 30887 lvds_rx_09_inst.r_phase_count[1] -.sym 30888 $PACKER_VCC_NET -.sym 30889 lvds_rx_09_inst.r_phase_count[0] -.sym 30890 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_I3[2] -.sym 30892 $PACKER_VCC_NET -.sym 30893 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2] -.sym 30897 lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O[0] -.sym 30898 lvds_rx_09_inst.r_data[27] -.sym 30905 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3 -.sym 30919 spi_if_ins.r_tx_byte[7] -.sym 30920 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] -.sym 30921 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 30933 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 30947 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 30951 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 30952 $PACKER_VCC_NET -.sym 30955 spi_if_ins.spi.r_tx_bit_count[2] -.sym 30956 $PACKER_VCC_NET -.sym 30957 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] -.sym 30961 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 30963 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 30964 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] -.sym 30965 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 30967 spi_if_ins.spi.SCKr[2] -.sym 30968 spi_if_ins.spi.SCKr[1] -.sym 30969 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O -.sym 30970 spi_if_ins.spi.SCKr[2] -.sym 30971 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 30972 spi_if_ins.spi.r_tx_bit_count[2] -.sym 30973 spi_if_ins.spi.SCKr[1] -.sym 30975 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] -.sym 30976 $PACKER_VCC_NET -.sym 30977 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3] -.sym 30989 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E -.sym 30990 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O -.sym 31038 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 31058 spi_if_ins.w_rx_data[6] -.sym 31070 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O[1] -.sym 31074 spi_if_ins.w_rx_data[2] -.sym 31082 spi_if_ins.w_rx_data[4] -.sym 31094 spi_if_ins.w_rx_data[5] -.sym 31098 spi_if_ins.w_rx_data[3] -.sym 31102 spi_if_ins.w_rx_data[0] -.sym 31107 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] -.sym 31108 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 31109 w_soft_reset -.sym 31110 w_rx_data[4] -.sym 31114 w_rx_data[3] -.sym 31120 io_ctrl_ins.debug_mode[0] -.sym 31121 io_ctrl_ins.debug_mode[1] -.sym 31122 w_rx_data[7] -.sym 31130 w_rx_data[2] -.sym 31134 w_rx_data[5] -.sym 31138 w_rx_data[5] -.sym 31150 w_rx_data[3] -.sym 31154 w_rx_data[4] -.sym 31158 w_rx_data[7] -.sym 31162 io_ctrl_ins.debug_mode[0] -.sym 31163 io_ctrl_ins.rf_mode[1] -.sym 31164 io_ctrl_ins.rf_mode[2] -.sym 31165 io_ctrl_ins.debug_mode[1] -.sym 31166 w_rx_data[6] -.sym 31170 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S[1] -.sym 31171 io_ctrl_ins.rf_mode[1] -.sym 31172 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 31173 o_tr_vc2$SB_IO_OUT -.sym 31186 spi_if_ins.o_ioc_SB_LUT4_I0_O[3] -.sym 31187 io_ctrl_ins.o_pmod[4] -.sym 31188 spi_if_ins.o_ioc_SB_LUT4_I0_O[2] -.sym 31189 o_tr_vc1_b$SB_IO_OUT -.sym 31190 i_config[0]$SB_IO_IN -.sym 31191 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] +.sym 30635 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30636 w_ioc[1] +.sym 30637 w_ioc[0] +.sym 30638 w_rx_data[7] +.sym 30642 w_rx_data[6] +.sym 30646 w_rx_data[4] +.sym 30650 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 30651 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 30652 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30653 io_ctrl_ins.o_pmod[4] +.sym 30655 w_ioc[0] +.sym 30656 w_ioc[1] +.sym 30657 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30660 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 30661 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 30662 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 30663 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30664 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30665 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 30666 i_config_SB_LUT4_I0_I1[2] +.sym 30667 io_ctrl_ins.pmod_dir_state[6] +.sym 30668 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30669 io_ctrl_ins.o_pmod[6] +.sym 30670 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R[0] +.sym 30671 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[2] +.sym 30672 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 30673 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3[3] +.sym 30674 w_rx_data[6] +.sym 30678 w_rx_data[7] +.sym 30682 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 30683 io_ctrl_ins.debug_mode[1] +.sym 30684 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 30685 o_shdn_rx_lna$SB_IO_OUT +.sym 30686 w_rx_data[4] +.sym 30691 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 30692 io_ctrl_ins.rf_pin_state[6] +.sym 30693 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 30694 i_config_SB_LUT4_I0_I1[2] +.sym 30695 io_ctrl_ins.pmod_dir_state[7] +.sym 30696 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 30697 io_ctrl_ins.o_pmod[7] +.sym 30698 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 30699 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 30700 io_ctrl_ins.rf_pin_state[2] +.sym 30701 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 30705 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O +.sym 30706 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 30707 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 30708 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 30709 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 30711 io_ctrl_ins.rf_pin_state[1] +.sym 30712 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 30713 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 30719 io_ctrl_ins.rf_pin_state[7] +.sym 30720 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 30721 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 30758 w_rx_09_fifo_pulled_data[7] +.sym 30759 w_rx_09_fifo_pulled_data[23] +.sym 30760 smi_ctrl_ins.int_cnt_09[3] +.sym 30761 smi_ctrl_ins.int_cnt_09[4] +.sym 30768 i_smi_a2_SB_LUT4_I1_O[1] +.sym 30769 i_smi_soe_se$SB_IO_IN +.sym 30796 lvds_rx_24_inst.o_debug_state[0] +.sym 30797 lvds_rx_24_inst.r_data[13] +.sym 30812 lvds_rx_24_inst.o_debug_state[0] +.sym 30813 lvds_rx_24_inst.r_data[11] +.sym 30819 sys_ctrl_ins.reset_count[0] +.sym 30824 sys_ctrl_ins.reset_count[1] +.sym 30826 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 30828 sys_ctrl_ins.reset_count[2] +.sym 30829 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 30830 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 30832 sys_ctrl_ins.reset_count[3] +.sym 30833 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] +.sym 30836 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 30837 sys_ctrl_ins.reset_cmd +.sym 30838 sys_ctrl_ins.reset_count[3] +.sym 30839 sys_ctrl_ins.reset_count[1] +.sym 30840 sys_ctrl_ins.reset_count[2] +.sym 30841 sys_ctrl_ins.reset_count[0] +.sym 30842 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S +.sym 30844 sys_ctrl_ins.reset_count[1] +.sym 30845 sys_ctrl_ins.reset_count[0] +.sym 30849 sys_ctrl_ins.reset_count[0] +.sym 30862 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0] +.sym 30863 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1] +.sym 30864 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2] +.sym 30865 i_smi_a2_SB_LUT4_I1_O[0] +.sym 30873 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30886 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0] +.sym 30887 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1] +.sym 30888 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] +.sym 30889 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 30890 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 30894 spi_if_ins.spi.r_tx_byte[3] +.sym 30895 spi_if_ins.spi.r_tx_byte[7] +.sym 30896 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30897 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 30904 i_ss$SB_IO_IN +.sym 30905 spi_if_ins.r_tx_data_valid +.sym 30907 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 30908 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1] +.sym 30909 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 30910 spi_if_ins.spi.r_tx_byte[2] +.sym 30911 spi_if_ins.spi.r_tx_byte[6] +.sym 30912 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 30913 spi_if_ins.spi.r_tx_bit_count[2] +.sym 30914 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 30918 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 30922 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 30929 i_ss$SB_IO_IN +.sym 30930 i_mosi$SB_IO_IN +.sym 30934 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 30942 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 30962 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30979 spi_if_ins.state_if[2] +.sym 30980 spi_if_ins.state_if[0] +.sym 30981 spi_if_ins.state_if[1] +.sym 30983 spi_if_ins.state_if[2] +.sym 30984 spi_if_ins.state_if[0] +.sym 30985 spi_if_ins.state_if[1] +.sym 30987 spi_if_ins.state_if[2] +.sym 30988 spi_if_ins.state_if[1] +.sym 30989 spi_if_ins.state_if[0] +.sym 30994 spi_if_ins.state_if_SB_DFFESR_Q_D[0] +.sym 30995 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 30996 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 30997 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 30998 spi_if_ins.state_if[0] +.sym 30999 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 31000 spi_if_ins.state_if[2] +.sym 31001 spi_if_ins.state_if[1] +.sym 31002 spi_if_ins.state_if[2] +.sym 31003 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 31004 spi_if_ins.state_if[0] +.sym 31005 spi_if_ins.state_if[1] +.sym 31007 i_smi_a2_SB_LUT4_I1_O[1] +.sym 31008 lvds_rx_24_inst.o_debug_state[0] +.sym 31009 lvds_rx_24_inst.o_debug_state[1] +.sym 31012 lvds_rx_24_inst.o_debug_state[0] +.sym 31013 lvds_rx_24_inst.r_data[5] +.sym 31016 spi_if_ins.state_if[0] +.sym 31017 spi_if_ins.state_if[1] +.sym 31019 spi_if_ins.state_if_SB_DFFESR_Q_D[1] +.sym 31020 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[1] +.sym 31021 spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O[2] +.sym 31023 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0] +.sym 31024 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 31025 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 31028 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 31029 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1] +.sym 31032 lvds_rx_24_inst.o_debug_state[0] +.sym 31033 lvds_rx_24_inst.r_data[25] +.sym 31036 lvds_rx_24_inst.o_debug_state[0] +.sym 31037 lvds_rx_24_inst.r_data[27] +.sym 31040 lvds_rx_24_inst.o_debug_state[0] +.sym 31041 lvds_rx_24_inst.r_data[3] +.sym 31042 r_tx_data[1] +.sym 31046 r_tx_data[6] +.sym 31050 r_tx_data[4] +.sym 31054 r_tx_data[3] +.sym 31058 r_tx_data[7] +.sym 31062 r_tx_data[5] +.sym 31066 w_cs[0] +.sym 31067 w_cs[1] +.sym 31068 w_cs[2] +.sym 31069 w_cs[3] +.sym 31070 r_tx_data[2] +.sym 31074 spi_if_ins.w_rx_data[5] +.sym 31078 spi_if_ins.w_rx_data[2] +.sym 31082 w_cs[0] +.sym 31083 w_cs[2] +.sym 31084 w_cs[3] +.sym 31085 w_cs[1] +.sym 31086 w_tx_data_smi[0] +.sym 31087 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 31088 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 31089 w_tx_data_io[0] +.sym 31090 w_cs[1] +.sym 31091 w_cs[2] +.sym 31092 w_cs[3] +.sym 31093 w_cs[0] +.sym 31094 spi_if_ins.w_rx_data[0] +.sym 31098 w_cs[0] +.sym 31099 w_cs[1] +.sym 31100 w_cs[2] +.sym 31101 w_cs[3] +.sym 31102 w_tx_data_smi[2] +.sym 31103 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 31104 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 31105 w_tx_data_io[2] +.sym 31106 w_rx_data[1] +.sym 31110 w_rx_data[2] +.sym 31116 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 31117 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 31122 w_rx_data[0] +.sym 31128 i_smi_a2_SB_LUT4_I1_O[1] +.sym 31129 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 31130 w_rx_data[4] +.sym 31134 w_rx_data[3] +.sym 31138 w_rx_data[0] +.sym 31142 w_rx_data[2] +.sym 31147 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1] +.sym 31148 i_config_SB_LUT4_I0_I1[0] +.sym 31149 i_smi_a2_SB_LUT4_I1_O[1] +.sym 31150 w_rx_data[5] +.sym 31154 w_rx_data[1] +.sym 31164 i_config_SB_LUT4_I0_I1[2] +.sym 31165 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1] +.sym 31166 i_config_SB_LUT4_I0_I1[0] +.sym 31167 o_led0$SB_IO_OUT +.sym 31168 i_config_SB_LUT4_I0_I1[2] +.sym 31169 io_ctrl_ins.pmod_dir_state[0] +.sym 31170 i_config_SB_LUT4_I0_I1[0] +.sym 31171 o_led1$SB_IO_OUT +.sym 31172 i_config_SB_LUT4_I0_I1[2] +.sym 31173 i_config_SB_LUT4_I0_I1[3] +.sym 31174 io_ctrl_ins.led0_state_SB_LUT4_I1_O[0] +.sym 31175 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 31176 io_ctrl_ins.led0_state_SB_LUT4_I1_O[2] +.sym 31177 io_ctrl_ins.led0_state_SB_LUT4_I1_O[3] +.sym 31178 io_ctrl_ins.led1_state_SB_LUT4_I1_O[0] +.sym 31179 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 31180 io_ctrl_ins.led1_state_SB_LUT4_I1_O[2] +.sym 31181 io_ctrl_ins.led1_state_SB_LUT4_I1_O[3] +.sym 31182 i_config_SB_LUT4_I0_I1[2] +.sym 31183 io_ctrl_ins.pmod_dir_state[5] +.sym 31184 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 31185 o_tr_vc1$SB_IO_OUT +.sym 31188 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[0] +.sym 31189 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 31190 io_ctrl_ins.o_pmod[3] +.sym 31191 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] .sym 31192 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[2] .sym 31193 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O[3] -.sym 31194 i_config[1]$SB_IO_IN -.sym 31195 io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O[1] -.sym 31196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[2] -.sym 31197 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O[3] -.sym 31270 lvds_rx_09_inst.r_data[30] -.sym 31274 lvds_rx_09_inst.r_data[28] -.sym 31282 lvds_rx_09_inst.r_data[31] -.sym 31289 $PACKER_VCC_NET -.sym 31290 lvds_rx_09_inst.r_data[29] -.sym 31309 i_smi_a1_SB_LUT4_I1_O -.sym 31314 w_rx_09_fifo_pulled_data[5] -.sym 31315 w_rx_09_fifo_pulled_data[13] -.sym 31316 smi_ctrl_ins.int_cnt_09[4] -.sym 31317 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_5_O[3] -.sym 31318 w_rx_09_fifo_pulled_data[4] -.sym 31319 w_rx_09_fifo_pulled_data[12] +.sym 31194 o_tr_vc1_b$SB_IO_OUT +.sym 31195 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 31196 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[2] +.sym 31197 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2[3] +.sym 31198 i_config[1]$SB_IO_IN +.sym 31199 i_config_SB_LUT4_I0_I1[0] +.sym 31200 i_config_SB_LUT4_I0_I1[2] +.sym 31201 io_ctrl_ins.pmod_dir_state[4] +.sym 31204 i_button_SB_LUT4_I0_O[0] +.sym 31205 i_button_SB_LUT4_I0_O[1] +.sym 31206 i_button$SB_IO_IN +.sym 31207 i_config_SB_LUT4_I0_I1[0] +.sym 31208 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 31209 o_rx_h_tx_l$SB_IO_OUT +.sym 31212 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[0] +.sym 31213 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[1] +.sym 31216 io_ctrl_ins.debug_mode[0] +.sym 31217 io_ctrl_ins.debug_mode[1] +.sym 31218 i_config_SB_LUT4_I0_I1[0] +.sym 31219 i_config[0]$SB_IO_IN +.sym 31220 i_config_SB_LUT4_I0_I1[2] +.sym 31221 io_ctrl_ins.pmod_dir_state[3] +.sym 31224 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[0] +.sym 31225 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1] +.sym 31226 io_ctrl_ins.debug_mode[0] +.sym 31227 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31228 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 31229 io_ctrl_ins.debug_mode[1] +.sym 31230 i_config_SB_LUT4_I0_I1[0] +.sym 31231 i_config[3]$SB_IO_IN +.sym 31232 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 31233 o_rx_h_tx_l_b$SB_IO_OUT +.sym 31258 w_rx_data[3] +.sym 31270 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[0] +.sym 31271 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[1] +.sym 31272 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0[2] +.sym 31273 i_smi_a2_SB_LUT4_I1_O[0] +.sym 31278 w_rx_09_fifo_pulled_data[5] +.sym 31279 w_rx_09_fifo_pulled_data[21] +.sym 31280 smi_ctrl_ins.int_cnt_09[3] +.sym 31281 smi_ctrl_ins.int_cnt_09[4] +.sym 31282 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0] +.sym 31283 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1] +.sym 31284 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2] +.sym 31285 i_smi_a2_SB_LUT4_I1_O[0] +.sym 31286 w_rx_09_fifo_pulled_data[6] +.sym 31287 w_rx_09_fifo_pulled_data[22] +.sym 31288 smi_ctrl_ins.int_cnt_09[3] +.sym 31289 smi_ctrl_ins.int_cnt_09[4] +.sym 31290 w_rx_09_fifo_pulled_data[4] +.sym 31291 w_rx_09_fifo_pulled_data[20] +.sym 31292 smi_ctrl_ins.int_cnt_09[3] +.sym 31293 smi_ctrl_ins.int_cnt_09[4] +.sym 31294 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0] +.sym 31295 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1] +.sym 31296 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2] +.sym 31297 i_smi_a2_SB_LUT4_I1_O[0] +.sym 31310 w_rx_09_fifo_pulled_data[13] +.sym 31311 w_rx_09_fifo_pulled_data[29] +.sym 31312 smi_ctrl_ins.int_cnt_09[4] +.sym 31313 smi_ctrl_ins.int_cnt_09[3] +.sym 31318 w_rx_09_fifo_pulled_data[14] +.sym 31319 w_rx_09_fifo_pulled_data[30] .sym 31320 smi_ctrl_ins.int_cnt_09[4] -.sym 31321 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_7_O[3] -.sym 31337 w_rx_09_fifo_pulled_data[14] -.sym 31349 w_rx_09_fifo_pulled_data[15] -.sym 31350 lvds_rx_09_inst.r_data[24] -.sym 31358 lvds_rx_09_inst.r_data[21] -.sym 31370 w_rx_09_fifo_pulled_data[19] -.sym 31371 w_rx_09_fifo_pulled_data[27] -.sym 31372 smi_ctrl_ins.int_cnt_09[4] -.sym 31373 smi_ctrl_ins.int_cnt_09[3] -.sym 31374 w_rx_09_fifo_pulled_data[1] -.sym 31375 w_rx_09_fifo_pulled_data[9] -.sym 31376 smi_ctrl_ins.int_cnt_09[4] -.sym 31377 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_13_O[3] -.sym 31382 w_rx_09_fifo_pulled_data[17] -.sym 31383 w_rx_09_fifo_pulled_data[25] +.sym 31321 smi_ctrl_ins.int_cnt_09[3] +.sym 31327 spi_if_ins.r_tx_byte[7] +.sym 31328 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1] +.sym 31329 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 31331 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 31335 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 31336 $PACKER_VCC_NET +.sym 31339 spi_if_ins.spi.r_tx_bit_count[2] +.sym 31340 $PACKER_VCC_NET +.sym 31341 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] +.sym 31345 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E +.sym 31349 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 31351 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0] +.sym 31352 $PACKER_VCC_NET +.sym 31353 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 31361 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 31366 i_sck$SB_IO_IN +.sym 31371 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 31372 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 31373 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2] +.sym 31374 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0] +.sym 31375 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2] +.sym 31376 spi_if_ins.spi.r_tx_bit_count[2] +.sym 31377 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 31378 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1] +.sym 31382 w_rx_09_fifo_pulled_data[12] +.sym 31383 w_rx_09_fifo_pulled_data[28] .sym 31384 smi_ctrl_ins.int_cnt_09[4] .sym 31385 smi_ctrl_ins.int_cnt_09[3] -.sym 31386 w_rx_09_fifo_pulled_data[18] -.sym 31387 w_rx_09_fifo_pulled_data[26] -.sym 31388 smi_ctrl_ins.int_cnt_09[4] -.sym 31389 smi_ctrl_ins.int_cnt_09[3] -.sym 31414 w_rx_09_fifo_pulled_data[3] -.sym 31415 w_rx_09_fifo_pulled_data[11] -.sym 31416 smi_ctrl_ins.int_cnt_09[4] -.sym 31417 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_9_O[3] -.sym 31418 w_rx_09_fifo_pulled_data[2] -.sym 31419 w_rx_09_fifo_pulled_data[10] -.sym 31420 smi_ctrl_ins.int_cnt_09[4] -.sym 31421 smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_11_O[3] -.sym 31450 lvds_rx_09_inst.r_data[26] -.sym 31462 spi_if_ins.spi.SCKr[1] -.sym 31478 i_sck$SB_IO_IN -.sym 31482 spi_if_ins.spi.SCKr[0] -.sym 31491 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31496 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31500 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31501 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] -.sym 31512 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31513 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31517 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31522 i_ss$SB_IO_IN -.sym 31523 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31524 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31525 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31530 spi_if_ins.spi.r_rx_done -.sym 31540 spi_if_ins.spi.r3_rx_done -.sym 31541 spi_if_ins.spi.r2_rx_done -.sym 31546 spi_if_ins.spi.r2_rx_done -.sym 31551 spi_if_ins.spi.r_rx_bit_count[0] -.sym 31552 spi_if_ins.spi.r_rx_bit_count[2] -.sym 31553 spi_if_ins.spi.r_rx_bit_count[1] -.sym 31610 spi_if_ins.w_rx_data[1] -.sym 31638 w_rx_data[1] -.sym 31642 w_rx_data[0] -.sym 31650 io_ctrl_ins.rf_pin_state[3] -.sym 31651 io_ctrl_ins.rf_mode[2] -.sym 31652 io_ctrl_ins.rf_mode[1] -.sym 31653 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 31655 io_ctrl_ins.rf_pin_state[5] -.sym 31656 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 31657 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31663 io_ctrl_ins.rf_pin_state[7] -.sym 31664 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 31665 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31666 io_ctrl_ins.rf_mode[2] -.sym 31667 io_ctrl_ins.rf_mode[0] -.sym 31668 io_ctrl_ins.rf_mode[1] -.sym 31669 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 31670 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 31671 io_ctrl_ins.rf_mode[2] -.sym 31672 io_ctrl_ins.rf_mode[0] -.sym 31673 io_ctrl_ins.rf_mode[1] -.sym 31679 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 31680 io_ctrl_ins.rf_pin_state[6] -.sym 31681 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31687 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2[3] -.sym 31688 io_ctrl_ins.rf_pin_state[4] -.sym 31689 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] -.sym 31697 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E -.sym 32002 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 32006 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 32010 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 32022 i_mosi$SB_IO_IN -.sym 32030 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 31386 spi_if_ins.spi.SCKr[0] +.sym 31390 w_rx_09_fifo_pulled_data[15] +.sym 31391 w_rx_09_fifo_pulled_data[31] +.sym 31392 smi_ctrl_ins.int_cnt_09[4] +.sym 31393 smi_ctrl_ins.int_cnt_09[3] +.sym 31395 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31400 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31404 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31405 spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3[2] +.sym 31409 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31418 i_ss$SB_IO_IN +.sym 31419 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31420 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31421 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31424 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31425 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31434 spi_if_ins.spi.r_temp_rx_byte[3] +.sym 31438 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 31442 spi_if_ins.spi.r_temp_rx_byte[2] +.sym 31455 spi_if_ins.spi.r_rx_bit_count[0] +.sym 31456 spi_if_ins.spi.r_rx_bit_count[2] +.sym 31457 spi_if_ins.spi.r_rx_bit_count[1] +.sym 31458 spi_if_ins.spi.r_rx_byte[3] +.sym 31462 spi_if_ins.spi.r_rx_byte[1] +.sym 31466 spi_if_ins.spi.r_rx_byte[0] +.sym 31470 spi_if_ins.spi.r_rx_byte[4] +.sym 31474 spi_if_ins.spi.r_rx_byte[2] +.sym 31478 spi_if_ins.spi.r_rx_byte[6] +.sym 31484 i_ss$SB_IO_IN +.sym 31485 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 31486 spi_if_ins.spi.r_rx_byte[5] +.sym 31490 spi_if_ins.spi.r_temp_rx_byte[4] +.sym 31494 spi_if_ins.spi.r_temp_rx_byte[0] +.sym 31498 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 31514 i_mosi$SB_IO_IN +.sym 31518 spi_if_ins.spi.r_temp_rx_byte[1] +.sym 31522 lvds_rx_24_inst.r_data[12] +.sym 31526 lvds_rx_24_inst.r_data[29] +.sym 31530 lvds_rx_24_inst.r_data[19] +.sym 31534 w_rx_24_fifo_pulled_data[4] +.sym 31535 w_rx_24_fifo_pulled_data[20] +.sym 31536 smi_ctrl_ins.int_cnt_24[3] +.sym 31537 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 31538 lvds_rx_24_inst.r_data[11] +.sym 31542 lvds_rx_24_inst.r_data[27] +.sym 31546 lvds_rx_24_inst.r_data[18] +.sym 31550 w_rx_24_fifo_pulled_data[7] +.sym 31551 w_rx_24_fifo_pulled_data[23] +.sym 31552 smi_ctrl_ins.int_cnt_24[3] +.sym 31553 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 31558 w_rx_24_fifo_pulled_data[15] +.sym 31559 w_rx_24_fifo_pulled_data[31] +.sym 31560 smi_ctrl_ins.int_cnt_24[3] +.sym 31561 smi_ctrl_ins.int_cnt_24[4] +.sym 31562 w_rx_24_fifo_pulled_data[12] +.sym 31563 w_rx_24_fifo_pulled_data[28] +.sym 31564 smi_ctrl_ins.int_cnt_24[3] +.sym 31565 smi_ctrl_ins.int_cnt_24[4] +.sym 31568 smi_ctrl_ins.int_cnt_24[3] +.sym 31569 smi_ctrl_ins.int_cnt_24[4] +.sym 31570 w_rx_24_fifo_pulled_data[6] +.sym 31571 w_rx_24_fifo_pulled_data[22] +.sym 31572 smi_ctrl_ins.int_cnt_24[3] +.sym 31573 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 31574 w_rx_24_fifo_pulled_data[5] +.sym 31575 w_rx_24_fifo_pulled_data[21] +.sym 31576 smi_ctrl_ins.int_cnt_24[3] +.sym 31577 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] +.sym 31581 smi_ctrl_ins.int_cnt_24[3] +.sym 31586 w_rx_24_fifo_pulled_data[14] +.sym 31587 w_rx_24_fifo_pulled_data[30] +.sym 31588 smi_ctrl_ins.int_cnt_24[3] +.sym 31589 smi_ctrl_ins.int_cnt_24[4] +.sym 31590 w_rx_24_fifo_pulled_data[13] +.sym 31591 w_rx_24_fifo_pulled_data[29] +.sym 31592 smi_ctrl_ins.int_cnt_24[3] +.sym 31593 smi_ctrl_ins.int_cnt_24[4] +.sym 31594 w_tx_data_smi[1] +.sym 31595 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 31596 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 31597 w_tx_data_io[1] +.sym 31604 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 31605 w_tx_data_io[6] +.sym 31608 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 31609 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[1] +.sym 31612 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 31613 w_tx_data_io[4] +.sym 31615 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 31616 w_tx_data_io[5] +.sym 31617 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 31618 w_rx_data[5] +.sym 31626 w_rx_data[0] +.sym 31634 w_rx_data[1] +.sym 31654 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 31655 io_ctrl_ins.debug_mode[0] +.sym 31656 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 31657 io_ctrl_ins.o_pmod[0] +.sym 31658 w_rx_data[0] +.sym 31662 w_rx_data[4] +.sym 31674 w_rx_data[5] +.sym 31678 w_rx_data[3] +.sym 31682 w_rx_data[0] +.sym 31690 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O[1] +.sym 31691 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31692 io_ctrl_ins.led0_state_SB_LUT4_I1_O[1] +.sym 31693 o_tr_vc2$SB_IO_OUT +.sym 31694 i_config_SB_LUT4_I0_I1[0] +.sym 31695 i_config[2]$SB_IO_IN +.sym 31696 io_ctrl_ins.led1_state_SB_LUT4_I1_O[1] +.sym 31697 io_ctrl_ins.o_pmod[5] +.sym 31706 w_rx_data[1] +.sym 31718 io_ctrl_ins.rf_pin_state[0] +.sym 31719 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 31720 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31721 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31723 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31724 io_ctrl_ins.rf_pin_state[4] +.sym 31725 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31730 io_ctrl_ins.rf_pin_state[3] +.sym 31731 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 31732 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31733 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31735 io_ctrl_ins.rf_pin_state[5] +.sym 31736 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31737 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2] +.sym 31742 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0] +.sym 31743 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1] +.sym 31744 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2] +.sym 31745 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3] +.sym 31750 lvds_rx_24_inst.r_data[3] +.sym 31773 i_config[0]$SB_IO_IN +.sym 31918 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] +.sym 31942 spi_if_ins.spi.r2_rx_done +.sym 31946 spi_if_ins.spi.r_rx_done +.sym 31958 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O +.sym 31964 spi_if_ins.spi.r3_rx_done +.sym 31965 spi_if_ins.spi.r2_rx_done +.sym 31982 spi_if_ins.spi.r_temp_rx_byte[5] +.sym 32022 spi_if_ins.state_if_SB_DFFESR_Q_D[0] .sym 32038 spi_if_ins.spi.r_rx_byte[7] -.sym 32044 i_ss$SB_IO_IN -.sym 32045 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1] -.sym 32046 spi_if_ins.spi.r_rx_byte[1] -.sym 32058 spi_if_ins.spi.r_rx_byte[4] -.sym 32062 spi_if_ins.spi.r_rx_byte[6] -.sym 32066 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 32070 spi_if_ins.spi.r_temp_rx_byte[2] -.sym 32074 spi_if_ins.spi.r_temp_rx_byte[1] -.sym 32078 spi_if_ins.spi.r_temp_rx_byte[3] -.sym 32090 i_mosi$SB_IO_IN -.sym 32098 spi_if_ins.spi.r_rx_byte[3] -.sym 32106 spi_if_ins.spi.r_rx_byte[0] -.sym 32114 spi_if_ins.spi.r_rx_byte[5] -.sym 32122 spi_if_ins.spi.r_rx_byte[2] -.sym 32453 i_ss$SB_IO_IN -.sym 32526 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 32538 spi_if_ins.spi.r_temp_rx_byte[4] -.sym 32546 spi_if_ins.spi.r_temp_rx_byte[5] -.sym 32554 spi_if_ins.spi.r_temp_rx_byte[0] -.sym 32566 spi_if_ins.spi.r_temp_rx_byte[6] +.sym 32049 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E +.sym 32053 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[2] +.sym 32057 $PACKER_VCC_NET +.sym 32071 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 32072 w_tx_data_io[7] +.sym 32073 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 32074 w_tx_data_smi[3] +.sym 32075 spi_if_ins.o_cs_SB_LUT4_I2_O[1] +.sym 32076 spi_if_ins.o_cs_SB_LUT4_I2_O[2] +.sym 32077 w_tx_data_io[3] +.sym 32085 $PACKER_VCC_NET +.sym 32118 w_tx_data_sys[0] +.sym 32119 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1] +.sym 32120 smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O[0] +.sym 32121 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3] +.sym 32146 w_rx_24_fifo_full +.sym 32162 lvds_rx_24_inst.r_data[5] +.sym 32185 w_lvds_rx_24_d0 +.sym 32202 lvds_rx_24_inst.o_debug_state[1] +.sym 32203 w_lvds_rx_24_d1 +.sym 32204 w_lvds_rx_24_d0 +.sym 32205 lvds_rx_24_inst.o_debug_state[0] +.sym 32214 lvds_rx_24_inst.o_debug_state[1] +.sym 32215 w_lvds_rx_24_d1 +.sym 32216 w_lvds_rx_24_d0 +.sym 32217 lvds_rx_24_inst.o_debug_state[0] +.sym 32565 r_counter +.sym 32580 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1] +.sym 32581 spi_if_ins.state_if[2] +.sym 32638 r_tx_data[0] diff --git a/firmware/top.bin b/firmware/top.bin index 0db0b8b..e5877f1 100644 Binary files a/firmware/top.bin and b/firmware/top.bin differ diff --git a/firmware/top.json b/firmware/top.json index 95aa5d2..fe3e29f 100644 --- a/firmware/top.json +++ b/firmware/top.json @@ -64,7 +64,7 @@ } }, "cells": { - "$specify$267": { + "$specify$266": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -95,7 +95,7 @@ "SRC": [ 6 ] } }, - "$specify$268": { + "$specify$267": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -126,7 +126,7 @@ "SRC": [ 2 ] } }, - "$specify$269": { + "$specify$268": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -157,7 +157,7 @@ "SRC": [ 2 ] } }, - "$specify$270": { + "$specify$269": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -188,7 +188,7 @@ "SRC": [ 3 ] } }, - "$specify$271": { + "$specify$270": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -219,7 +219,7 @@ "SRC": [ 3 ] } }, - "$specify$272": { + "$specify$271": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -250,7 +250,7 @@ "SRC": [ 3 ] } }, - "$specify$273": { + "$specify$272": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -281,7 +281,7 @@ "SRC": [ 4 ] } }, - "$specify$274": { + "$specify$273": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -312,7 +312,7 @@ "SRC": [ 4 ] } }, - "$specify$275": { + "$specify$274": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -343,7 +343,7 @@ "SRC": [ 4 ] } }, - "$specify$276": { + "$specify$275": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -374,7 +374,7 @@ "SRC": [ 5 ] } }, - "$specify$277": { + "$specify$276": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -405,7 +405,7 @@ "SRC": [ 5 ] } }, - "$specify$278": { + "$specify$277": { "hide_name": 1, "type": "$specify3", "parameters": { @@ -442,7 +442,7 @@ "SRC": [ 7 ] } }, - "$specify$279": { + "$specify$278": { "hide_name": 1, "type": "$specify2", "parameters": { @@ -473,7 +473,7 @@ "SRC": [ 9 ] } }, - "$specify$280": { + "$specify$279": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -508,7 +508,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$281": { + "$specify$280": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -543,7 +543,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$282": { + "$specify$281": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -578,7 +578,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$283": { + "$specify$282": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -613,7 +613,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$284": { + "$specify$283": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -648,7 +648,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$285": { + "$specify$284": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -683,7 +683,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$286": { + "$specify$285": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -718,7 +718,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$287": { + "$specify$286": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -753,7 +753,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$288": { + "$specify$287": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -788,7 +788,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$289": { + "$specify$288": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -823,7 +823,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$290": { + "$specify$289": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -858,7 +858,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$291": { + "$specify$290": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -893,7 +893,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$292": { + "$specify$291": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -928,7 +928,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$293": { + "$specify$292": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -963,7 +963,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$294": { + "$specify$293": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -998,7 +998,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$295": { + "$specify$294": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -1033,7 +1033,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$296": { + "$specify$295": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -1068,7 +1068,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$297": { + "$specify$296": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -1103,7 +1103,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$298": { + "$specify$297": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -1138,7 +1138,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$299": { + "$specify$298": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -1173,7 +1173,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$300": { + "$specify$299": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -1208,7 +1208,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$301": { + "$specify$300": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6390,7 +6390,7 @@ } }, "cells": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1633$386": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1633$385": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -6414,7 +6414,7 @@ "Y": [ 78 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1635$387": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1635$386": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -6438,7 +6438,7 @@ "Y": [ 79 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1641$388": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1641$387": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -6462,7 +6462,7 @@ "Y": [ 80 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1645$389": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1645$388": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -6486,7 +6486,7 @@ "Y": [ 81 ] } }, - "$specify$231": { + "$specify$230": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6521,7 +6521,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$232": { + "$specify$231": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6556,7 +6556,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$233": { + "$specify$232": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6591,7 +6591,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$234": { + "$specify$233": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6626,7 +6626,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$235": { + "$specify$234": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6661,7 +6661,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$236": { + "$specify$235": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6696,7 +6696,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$237": { + "$specify$236": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6731,7 +6731,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$238": { + "$specify$237": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -6766,7 +6766,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$239": { + "$specify$238": { "hide_name": 1, "type": "$specify3", "parameters": { @@ -6805,28 +6805,28 @@ } }, "netnames": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1633$386_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1633$385_Y": { "hide_name": 1, "bits": [ 78 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1633.33-1633.44" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1635$387_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1635$386_Y": { "hide_name": 1, "bits": [ 79 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1635.34-1635.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1641$388_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1641$387_Y": { "hide_name": 1, "bits": [ 80 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1641.34-1641.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1645$389_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1645$388_Y": { "hide_name": 1, "bits": [ 81 ], "attributes": { @@ -6991,7 +6991,7 @@ } }, "cells": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1769$390": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1769$389": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7015,7 +7015,7 @@ "Y": [ 78 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1771$391": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1771$390": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7039,7 +7039,7 @@ "Y": [ 79 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1777$392": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1777$391": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7063,7 +7063,7 @@ "Y": [ 80 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1781$393": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1781$392": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7087,7 +7087,7 @@ "Y": [ 81 ] } }, - "$specify$240": { + "$specify$239": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7122,7 +7122,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$241": { + "$specify$240": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7157,7 +7157,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$242": { + "$specify$241": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7192,7 +7192,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$243": { + "$specify$242": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7227,7 +7227,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$244": { + "$specify$243": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7262,7 +7262,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$245": { + "$specify$244": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7297,7 +7297,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$246": { + "$specify$245": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7332,7 +7332,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$247": { + "$specify$246": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7367,7 +7367,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$248": { + "$specify$247": { "hide_name": 1, "type": "$specify3", "parameters": { @@ -7406,28 +7406,28 @@ } }, "netnames": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1769$390_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1769$389_Y": { "hide_name": 1, "bits": [ 78 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1769.33-1769.44" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1771$391_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1771$390_Y": { "hide_name": 1, "bits": [ 79 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1771.35-1771.46" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1777$392_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1777$391_Y": { "hide_name": 1, "bits": [ 80 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:1777.34-1777.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1781$393_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1781$392_Y": { "hide_name": 1, "bits": [ 81 ], "attributes": { @@ -7592,7 +7592,7 @@ } }, "cells": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2041$398": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2041$397": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7616,7 +7616,7 @@ "Y": [ 78 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2043$399": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2043$398": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7640,7 +7640,7 @@ "Y": [ 79 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2049$400": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2049$399": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7664,7 +7664,7 @@ "Y": [ 80 ] } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2053$401": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2053$400": { "hide_name": 1, "type": "$logic_and", "parameters": { @@ -7688,7 +7688,7 @@ "Y": [ 81 ] } }, - "$specify$258": { + "$specify$257": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7723,7 +7723,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$259": { + "$specify$258": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7758,7 +7758,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$260": { + "$specify$259": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7793,7 +7793,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$261": { + "$specify$260": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7828,7 +7828,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$262": { + "$specify$261": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7863,7 +7863,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$263": { + "$specify$262": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7898,7 +7898,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$264": { + "$specify$263": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7933,7 +7933,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$265": { + "$specify$264": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -7968,7 +7968,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$266": { + "$specify$265": { "hide_name": 1, "type": "$specify3", "parameters": { @@ -8007,28 +8007,28 @@ } }, "netnames": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2041$398_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2041$397_Y": { "hide_name": 1, "bits": [ 78 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:2041.34-2041.45" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2043$399_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2043$398_Y": { "hide_name": 1, "bits": [ 79 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:2043.35-2043.46" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2049$400_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2049$399_Y": { "hide_name": 1, "bits": [ 80 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:2049.35-2049.46" } }, - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2053$401_Y": { + "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:2053$400_Y": { "hide_name": 1, "bits": [ 81 ], "attributes": { @@ -8193,7 +8193,7 @@ } }, "cells": { - "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1905$394": { + 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+8324,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$250": { + "$specify$249": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -8359,7 +8359,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$251": { + "$specify$250": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -8394,7 +8394,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$252": { + "$specify$251": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -8429,7 +8429,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$253": { + "$specify$252": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -8464,7 +8464,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$254": { + "$specify$253": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -8499,7 +8499,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$255": { + "$specify$254": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -8534,7 +8534,7 @@ "SRC_EN": [ "1" ] } }, - "$specify$256": { + "$specify$255": { "hide_name": 1, "type": "$specrule", "parameters": { @@ -8569,7 +8569,7 @@ "SRC_EN": [ "1" ] } }, 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], + "I3": [ 57 ], + "O": [ 58 ] } }, "i_smi_a1_SB_LUT4_I1": { @@ -9835,22 +9910,22 @@ "O": "output" }, "connections": { - "I0": [ 51 ], + "I0": [ 57 ], "I1": [ 28 ], "I2": [ 29 ], "I3": [ 30 ], - "O": [ 52 ] + "O": [ 59 ] } }, - "i_smi_a2_SB_LUT4_I0": { + "i_smi_a2_SB_LUT4_I1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111111101000000" + "LUT_INIT": "0011000000000000" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" }, "port_directions": { "I0": "input", @@ -9860,11 +9935,11 @@ "O": "output" }, "connections": { - "I0": [ 29 ], - "I1": [ 28 ], - "I2": [ 30 ], - "I3": [ 51 ], - "O": [ 53 ] + "I0": [ "0" ], + "I1": [ 29 ], + "I2": [ 28 ], + "I3": [ 30 ], + "O": [ 60 ] } }, "i_ss_SB_LUT4_I3": { @@ -9889,7 +9964,7 @@ "I1": [ "0" ], "I2": [ "0" ], "I3": [ 45 ], - "O": [ 54 ] + "O": [ 61 ] } }, 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{ + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000101110111011" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 79 ], + "I1": [ 67 ], + "I2": [ 52 ], + "I3": [ 80 ], + "O": [ 81 ] } }, "io_ctrl_ins.led1_state_SB_DFFESR_Q": { @@ -10080,11 +10180,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 56 ], - "E": [ 69 ], + "C": [ 62 ], + "D": [ 63 ], + "E": [ 76 ], "Q": [ 27 ], - "R": [ 51 ] + "R": [ 57 ] } }, "io_ctrl_ins.led1_state_SB_DFFESR_Q_E_SB_LUT4_O": { @@ -10106,17 +10206,17 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 73 ], + "I1": [ 82 ], "I2": [ 47 ], - "I3": [ 51 ], - "O": [ 69 ] + "I3": [ 57 ], + "O": [ 76 ] } }, - "io_ctrl_ins.led1_state_SB_LUT4_I0": { + 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], + "I3": [ 163 ], + "O": [ 162 ] } }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3": { + "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "0000011101110111" + "LUT_INIT": "1000111111111111" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -11804,18 +12004,18 @@ "O": "output" }, "connections": { - "I0": [ 48 ], - "I1": [ 146 ], - "I2": [ 81 ], - "I3": [ 6 ], - "O": [ 125 ] + "I0": [ 6 ], + "I1": [ 48 ], + "I2": [ 164 ], + "I3": [ 56 ], + "O": [ 105 ] } }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O_SB_LUT4_O": { + "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1011000010111011" + "LUT_INIT": "0000101110111011" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -11830,10 +12030,10 @@ }, "connections": { "I0": [ 79 ], - "I1": [ 139 ], - "I2": [ 82 ], - "I3": [ 62 ], - "O": [ 124 ] + "I1": [ 69 ], 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"PACKAGE_PIN": [ 11 ] + } + }, "iq_rx_clk": { "hide_name": 0, "type": "SB_IO", @@ -12252,7 +12479,7 @@ }, "connections": { "CLOCK_ENABLE": [ "1" ], - "D_IN_0": [ 171 ], + "D_IN_0": [ 177 ], "PACKAGE_PIN": [ 12 ] } }, @@ -12263,7 +12490,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12272,10 +12499,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 172 ], - "E": [ 173 ], - "Q": [ 174 ] + "C": [ 177 ], + "D": [ 180 ], + "E": [ 181 ], + "Q": [ 182 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_1": { @@ -12285,7 +12512,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12294,10 +12521,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 175 ], - "E": [ 173 ], - "Q": [ 176 ] + "C": [ 177 ], + "D": [ 183 ], + "E": [ 181 ], + "Q": [ 184 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_10": { @@ -12307,7 +12534,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12316,10 +12543,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 177 ], - "E": [ 173 ], - "Q": [ 178 ] + "C": [ 177 ], + "D": [ 185 ], + "E": [ 181 ], + "Q": [ 186 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_11": { @@ -12329,7 +12556,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12338,10 +12565,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 179 ], - "E": [ 173 ], - "Q": [ 180 ] + "C": [ 177 ], + "D": [ 187 ], + "E": [ 181 ], + "Q": [ 188 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_12": { @@ -12351,7 +12578,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": 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"top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12404,10 +12631,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 185 ], - "E": [ 173 ], - "Q": [ 186 ] + "C": [ 177 ], + "D": [ 193 ], + "E": [ 181 ], + "Q": [ 194 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_15": { @@ -12417,7 +12644,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12426,10 +12653,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 187 ], - "E": [ 173 ], - "Q": [ 188 ] + "C": [ 177 ], + "D": [ 195 ], + "E": [ 181 ], + "Q": [ 196 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_16": { @@ -12439,7 +12666,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12448,10 +12675,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 189 ], - "E": [ 173 ], - "Q": [ 190 ] + "C": [ 177 ], + "D": [ 197 ], + "E": [ 181 ], + "Q": [ 198 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_17": { @@ -12461,7 +12688,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": 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"top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12514,10 +12741,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 195 ], - "E": [ 173 ], - "Q": [ 196 ] + "C": [ 177 ], + "D": [ 203 ], + "E": [ 181 ], + "Q": [ 204 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_2": { @@ -12527,7 +12754,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12536,10 +12763,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 197 ], - "E": [ 173 ], - "Q": [ 198 ] + "C": [ 177 ], + "D": [ 205 ], + "E": [ 181 ], + "Q": [ 206 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_20": { @@ -12549,7 +12776,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12558,10 +12785,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 199 ], - "E": [ 173 ], - "Q": [ 200 ] + "C": [ 177 ], + "D": [ 207 ], + "E": [ 181 ], + "Q": [ 208 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_21": { @@ -12571,7 +12798,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": 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"top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12624,10 +12851,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 205 ], - "E": [ 173 ], - "Q": [ 206 ] + "C": [ 177 ], + "D": [ 213 ], + "E": [ 181 ], + "Q": [ 214 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_24": { @@ -12637,7 +12864,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12646,10 +12873,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 207 ], - "E": [ 173 ], - "Q": [ 208 ] + "C": [ 177 ], + "D": [ 215 ], + "E": [ 181 ], + "Q": [ 216 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_25": { @@ -12659,7 +12886,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12668,10 +12895,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 209 ], - "E": [ 173 ], - "Q": [ 210 ] + "C": [ 177 ], + "D": [ 217 ], + "E": [ 181 ], + "Q": [ 218 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_26": { @@ -12681,7 +12908,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12690,10 +12917,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 211 ], - "E": [ 173 ], - "Q": [ 212 ] + "C": [ 177 ], + "D": [ 219 ], + "E": [ 181 ], + "Q": [ 220 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_27": { @@ -12703,7 +12930,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12712,10 +12939,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 213 ], - "E": [ 173 ], - "Q": [ 214 ] + "C": [ 177 ], + "D": [ 221 ], + "E": [ 181 ], + "Q": [ 222 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_28": { @@ -12725,7 +12952,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12734,10 +12961,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 215 ], - "E": [ 173 ], - "Q": [ 216 ] + "C": [ 177 ], + "D": [ 223 ], + "E": [ 181 ], + "Q": [ 224 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_29": { @@ -12747,7 +12974,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12756,10 +12983,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 217 ], - "E": [ 173 ], - "Q": [ 218 ] + "C": [ 177 ], + "D": [ 225 ], + "E": [ 181 ], + "Q": [ 226 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_3": { @@ -12769,7 +12996,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": "input", @@ -12778,10 +13005,10 @@ "Q": "output" }, "connections": { - "C": [ 171 ], - "D": [ 219 ], - "E": [ 173 ], - "Q": [ 220 ] + "C": [ 177 ], + "D": [ 227 ], + "E": [ 181 ], + "Q": [ 228 ] } }, "lvds_rx_09_inst.o_fifo_data_SB_DFFE_Q_30": { @@ -12791,7 +13018,7 @@ }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "top.v:259.12-279.5|lvds_rx.v:48.5-105.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" + "src": "top.v:259.12-279.5|lvds_rx.v:46.5-99.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103" }, "port_directions": { "C": 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"hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ "0" ], + "I2": [ 57 ], + "I3": [ 513 ], + "O": [ 569 ] + } + }, "rx_09_fifo.mem_i.1.0.0": { "hide_name": 0, "type": "SB_RAM40_4K", @@ -16720,15 +20491,15 @@ }, "connections": { "MASK": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], - "RADDR": [ 369, 354, 338, 268, 349, 271, 272, 350, 240, 269, "0" ], - "RCLK": [ 55 ], - "RCLKE": [ 386 ], - "RDATA": [ 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418 ], + "RADDR": [ 568, 535, 533, 280, 277, 278, 274, 246, 538, 275, "0" ], + "RCLK": [ 62 ], + "RCLKE": [ 569 ], + "RDATA": [ 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605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, 616, 617 ], "RE": [ "1" ], - "WADDR": [ 370, 259, 260, 258, 256, 254, 252, 250, 248, 246, "0" ], - "WCLK": [ 171 ], - "WCLKE": [ 243 ], - "WDATA": [ "x", 232, "x", "x", "x", 230, "x", "x", "x", 228, "x", "x", "x", 226, "x", "x" ], + "WADDR": [ 560, 272, 271, 268, 265, 262, 259, 257, 254, 251, "0" ], + "WCLK": [ 177 ], + "WCLKE": [ 249 ], + "WDATA": [ "x", 238, "x", "x", "x", 236, "x", "x", "x", 234, "x", "x", "x", 232, "x", "x" ], "WE": [ "1" ] } }, @@ -16828,15 +20599,15 @@ }, "connections": { "MASK": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], - "RADDR": [ 369, 354, 338, 268, 349, 271, 272, 350, 240, 269, "0" ], - "RCLK": [ 55 ], - "RCLKE": [ 386 ], - "RDATA": [ 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450 ], + "RADDR": [ 568, 535, 533, 280, 277, 278, 274, 246, 538, 275, "0" ], + "RCLK": [ 62 ], + "RCLKE": [ 569 ], + "RDATA": [ 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, 629, 630, 631, 632, 633 ], "RE": [ "1" ], - "WADDR": [ 370, 259, 260, 258, 256, 254, 252, 250, 248, 246, "0" ], - "WCLK": [ 171 ], - "WCLKE": [ 243 ], - "WDATA": [ "x", 220, "x", "x", "x", 198, "x", "x", "x", 176, "x", "x", "x", 174, "x", "x" ], + "WADDR": [ 560, 272, 271, 268, 265, 262, 259, 257, 254, 251, "0" ], + "WCLK": [ 177 ], + "WCLKE": [ 249 ], + "WDATA": [ "x", 228, "x", "x", "x", 206, "x", "x", "x", 184, "x", "x", "x", 182, "x", "x" ], "WE": [ "1" ] } }, @@ -16882,15 +20653,15 @@ }, "connections": { "MASK": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], - "RADDR": [ 369, 354, 338, 268, 349, 271, 272, 350, 240, 269, "0" ], - "RCLK": [ 55 ], - "RCLKE": [ 386 ], - "RDATA": [ 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, 464, 465, 466 ], + "RADDR": [ 568, 535, 533, 280, 277, 278, 274, 246, 538, 275, "0" ], + "RCLK": [ 62 ], + "RCLKE": [ 569 ], + "RDATA": [ 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, 645, 646, 647, 648, 649 ], "RE": [ "1" ], - "WADDR": [ 370, 259, 260, 258, 256, 254, 252, 250, 248, 246, "0" ], - "WCLK": [ 171 ], - "WCLKE": [ 243 ], - "WDATA": [ "x", 224, "x", "x", "x", 222, "x", "x", "x", 218, "x", "x", "x", 216, "x", "x" ], + "WADDR": [ 560, 272, 271, 268, 265, 262, 259, 257, 254, 251, "0" ], + "WCLK": [ 177 ], + "WCLKE": [ 249 ], + "WDATA": [ "x", 230, "x", "x", "x", 229, "x", "x", "x", 226, "x", "x", "x", 224, "x", "x" ], "WE": [ "1" ] } }, @@ -16936,15 +20707,15 @@ }, "connections": { "MASK": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], - "RADDR": [ 369, 354, 338, 268, 349, 271, 272, 350, 240, 269, "0" ], - "RCLK": [ 55 ], - "RCLKE": [ 386 ], - "RDATA": [ 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482 ], + "RADDR": [ 568, 535, 533, 280, 277, 278, 274, 246, 538, 275, "0" ], + "RCLK": [ 62 ], + "RCLKE": [ 569 ], + "RDATA": [ 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665 ], "RE": [ "1" ], - "WADDR": [ 370, 259, 260, 258, 256, 254, 252, 250, 248, 246, "0" ], - "WCLK": [ 171 ], - "WCLKE": [ 243 ], - "WDATA": [ "x", 214, "x", "x", "x", 212, "x", "x", "x", 210, "x", "x", "x", 208, "x", "x" ], + "WADDR": [ 560, 272, 271, 268, 265, 262, 259, 257, 254, 251, "0" ], + "WCLK": [ 177 ], + "WCLKE": [ 249 ], + "WDATA": [ "x", 222, "x", "x", "x", 220, "x", "x", "x", 218, "x", "x", "x", 216, "x", "x" ], "WE": [ "1" ] } }, @@ -16990,15 +20761,15 @@ }, "connections": { "MASK": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], - "RADDR": [ 369, 354, 338, 268, 349, 271, 272, 350, 240, 269, "0" ], - "RCLK": [ 55 ], - "RCLKE": [ 386 ], - "RDATA": [ 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498 ], + "RADDR": [ 568, 535, 533, 280, 277, 278, 274, 246, 538, 275, "0" ], + "RCLK": [ 62 ], + "RCLKE": [ 569 ], + "RDATA": [ 666, 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 678, 679, 680, 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[ 707 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_9": { @@ -17542,8 +21313,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 369 ], - "O": [ 525 ] + "I3": [ 568 ], + "O": [ 708 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO": { @@ -17561,10 +21332,10 @@ "I1": "input" }, "connections": { - "CI": [ 527 ], - "CO": [ 526 ], + "CI": [ 710 ], + "CO": [ 709 ], "I0": [ "0" ], - "I1": [ 240 ] + "I1": [ 538 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_1": { @@ -17582,10 +21353,10 @@ "I1": "input" }, "connections": { - "CI": [ 528 ], - "CO": [ 527 ], + "CI": [ 711 ], + "CO": [ 710 ], "I0": [ "0" ], - "I1": [ 350 ] + "I1": [ 246 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_2": { @@ -17603,10 +21374,10 @@ "I1": "input" }, "connections": { - "CI": [ 529 ], - "CO": [ 528 ], + "CI": [ 712 ], + "CO": [ 711 ], "I0": [ "0" ], - "I1": [ 272 ] + "I1": [ 274 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_3": { @@ -17624,10 +21395,10 @@ "I1": "input" }, "connections": { - "CI": [ 530 ], - "CO": [ 529 ], + "CI": [ 713 ], + "CO": [ 712 ], "I0": [ "0" ], - "I1": [ 271 ] + "I1": [ 278 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_4": { @@ -17645,10 +21416,10 @@ "I1": "input" }, "connections": { - "CI": [ 531 ], - "CO": [ 530 ], + "CI": [ 714 ], + "CO": [ 713 ], "I0": [ "0" ], - "I1": [ 349 ] + "I1": [ 277 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_5": { @@ -17666,10 +21437,10 @@ "I1": "input" }, "connections": { - "CI": [ 532 ], - "CO": [ 531 ], + "CI": [ 715 ], + "CO": [ 714 ], "I0": [ "0" ], - "I1": [ 268 ] + "I1": [ 280 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_6": { @@ -17687,10 +21458,10 @@ "I1": "input" }, "connections": { - "CI": [ 533 ], - "CO": [ 532 ], + "CI": [ 716 ], + "CO": [ 715 ], "I0": [ "0" ], - "I1": [ 338 ] + "I1": [ 533 ] } }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_7": { @@ -17708,10 +21479,35 @@ "I1": "input" }, "connections": { - "CI": [ 369 ], - "CO": [ 533 ], + "CI": [ 568 ], + "CO": [ 716 ], "I0": [ "0" ], - "I1": [ 354 ] + "I1": [ 535 ] + } + }, + "rx_09_fifo.rd_addr_SB_DFFESR_Q_E_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ "0" ], + "I2": [ 513 ], + "I3": [ 57 ], + "O": [ 699 ] } }, "rx_09_fifo.wr_addr_SB_DFFESR_Q": { @@ -17731,11 +21527,11 @@ "R": "input" }, "connections": { - "C": [ 171 ], - "D": [ 373 ], - "E": [ 244 ], - "Q": [ 246 ], - "R": [ 51 ] + "C": [ 177 ], + "D": [ 563 ], + "E": [ 250 ], + "Q": [ 251 ], + "R": [ 57 ] } }, "rx_09_fifo.wr_addr_SB_DFFESR_Q_1": { @@ -17755,11 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"rx_09_fifo.wr_addr_SB_DFFESR_Q_5": { @@ -17851,11 +21647,11 @@ "R": "input" }, "connections": { - "C": [ 171 ], - "D": [ 380 ], - "E": [ 244 ], - "Q": [ 256 ], - "R": [ 51 ] + "C": [ 177 ], + "D": [ 547 ], + "E": [ 250 ], + "Q": [ 265 ], + "R": [ 57 ] } }, "rx_09_fifo.wr_addr_SB_DFFESR_Q_6": { @@ -17875,11 +21671,11 @@ "R": "input" }, "connections": { - "C": [ 171 ], - "D": [ 340 ], - "E": [ 244 ], - "Q": [ 258 ], - "R": [ 51 ] + "C": [ 177 ], + "D": [ 558 ], + "E": [ 250 ], + "Q": [ 268 ], + "R": [ 57 ] } }, "rx_09_fifo.wr_addr_SB_DFFESR_Q_7": { @@ -17899,11 +21695,11 @@ "R": "input" }, "connections": { - "C": [ 171 ], - "D": [ 383 ], - "E": [ 244 ], - "Q": [ 260 ], - "R": [ 51 ] + "C": [ 177 ], + "D": [ 546 ], + "E": [ 250 ], + "Q": [ 271 ], + "R": [ 57 ] } }, "rx_09_fifo.wr_addr_SB_DFFESR_Q_8": { @@ -17923,11 +21719,11 @@ "R": "input" }, "connections": { - "C": [ 171 ], - "D": [ 384 ], - "E": [ 244 ], - "Q": [ 259 ], - "R": [ 51 ] + "C": [ 177 ], + "D": [ 561 ], + "E": [ 250 ], + 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"I1": [ 598 ], - "I2": [ 609 ], - "I3": [ 610 ], - "O": [ 621 ] + "I1": [ 1041 ], + "I2": [ 1046 ], + "I3": [ 1045 ], + "O": [ 1059 ] } }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E_SB_LUT4_O": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111111100110000" + "LUT_INIT": "0011001100110101" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" }, "port_directions": { "I0": "input", @@ -20792,11 +28520,11 @@ "O": "output" }, "connections": { - "I0": [ "0" ], - "I1": [ 607 ], - "I2": [ 608 ], - "I3": [ 66 ], - "O": [ 622 ] + "I0": [ 1046 ], + "I1": [ 1048 ], + "I2": [ 1041 ], + "I3": [ 1045 ], + "O": [ 1060 ] } }, "spi_if_ins.r_tx_data_valid_SB_LUT4_I3": { @@ -20820,33 +28548,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ 45 ], - "I3": [ 623 ], - "O": [ 624 ] - } - }, - "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_I3": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0011000011111111" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ 625 ], - "I2": [ 626 ], - "I3": [ 624 ], - "O": [ 627 ] + "I3": [ 1061 ], + "O": [ 1062 ] } }, "spi_if_ins.spi.SCKr_SB_DFF_Q": { @@ -20864,9 +28567,9 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 628 ], - "Q": [ 629 ] + "C": [ 62 ], + "D": [ 1063 ], + "Q": [ 1064 ] } }, "spi_if_ins.spi.SCKr_SB_DFF_Q_1": { @@ -20884,9 +28587,9 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 630 ], - "Q": [ 628 ] + "C": [ 62 ], + "D": [ 1065 ], + "Q": [ 1063 ] } }, "spi_if_ins.spi.SCKr_SB_DFF_Q_2": { @@ -20904,9 +28607,9 @@ "Q": "output" }, "connections": { - "C": [ 55 ], + "C": [ 62 ], "D": [ 44 ], - "Q": [ 630 ] + "Q": [ 1065 ] } }, "spi_if_ins.spi.SCKr_SB_LUT4_I0": { @@ -20927,11 +28630,11 @@ "O": "output" }, "connections": { - "I0": [ 629 ], - "I1": [ 631 ], - "I2": [ 632 ], - "I3": [ 628 ], - "O": [ 626 ] + "I0": [ 1064 ], + "I1": [ 1066 ], + "I2": [ 1067 ], + "I3": [ 1063 ], + "O": [ 1068 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q": { @@ -20950,10 +28653,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 633 ], - "E": [ 634 ], - "Q": [ 587 ] + "C": [ 62 ], + "D": [ 1069 ], + "E": [ 1070 ], + "Q": [ 1030 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_1": { @@ -20972,10 +28675,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 635 ], - "E": [ 634 ], - "Q": [ 585 ] + "C": [ 62 ], + "D": [ 1071 ], + "E": [ 1070 ], + "Q": [ 1027 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_2": { @@ -20994,10 +28697,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 636 ], - "E": [ 634 ], - "Q": [ 586 ] + "C": [ 62 ], + "D": [ 1072 ], + "E": [ 1070 ], + "Q": [ 1028 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_3": { @@ -21016,10 +28719,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 637 ], - "E": [ 634 ], - "Q": [ 589 ] + "C": [ 62 ], + "D": [ 1073 ], + "E": [ 1070 ], + "Q": [ 1032 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_4": { @@ -21038,10 +28741,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 638 ], - "E": [ 634 ], - "Q": [ 590 ] + "C": [ 62 ], + "D": [ 1074 ], + "E": [ 1070 ], + "Q": [ 1033 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_5": { @@ -21060,10 +28763,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 639 ], - "E": [ 634 ], - "Q": [ 591 ] + "C": [ 62 ], + "D": [ 1075 ], + "E": [ 1070 ], + "Q": [ 1034 ] } }, "spi_if_ins.spi.o_rx_byte_SB_DFFE_Q_6": { @@ -21082,10 +28785,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 640 ], - "E": [ 634 ], - "Q": [ 592 ] + "C": [ 62 ], + "D": [ 1076 ], + "E": [ 1070 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] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_2": { @@ -21940,9 +29668,9 @@ }, "connections": { "C": [ 44 ], - "D": [ 672 ], - "E": [ 54 ], - "Q": [ 671 ] + "D": [ 1108 ], + "E": [ 61 ], + "Q": [ 1107 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_3": { @@ -21962,9 +29690,9 @@ }, "connections": { "C": [ 44 ], - "D": [ 673 ], - "E": [ 54 ], - "Q": [ 672 ] + "D": [ 1109 ], + "E": [ 61 ], + "Q": [ 1108 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_4": { @@ -21984,9 +29712,9 @@ }, "connections": { "C": [ 44 ], - "D": [ 674 ], - "E": [ 54 ], - "Q": [ 673 ] + "D": [ 1110 ], + "E": [ 61 ], + "Q": [ 1109 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_5": { @@ -22006,9 +29734,9 @@ }, "connections": { "C": [ 44 ], - "D": [ 675 ], - "E": [ 54 ], - "Q": [ 674 ] + "D": [ 1111 ], + "E": [ 61 ], + "Q": [ 1110 ] } }, "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q_6": { @@ -22029,8 +29757,8 @@ "connections": { "C": [ 44 ], "D": [ 43 ], - "E": [ 54 ], - "Q": [ 675 ] + "E": [ 61 ], + "Q": [ 1111 ] } }, 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+29971,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 613 ], - "E": [ 627 ], - "Q": [ 651 ], - "R": [ 624 ] + "C": [ 62 ], + "D": [ 1051 ], + "E": [ 1119 ], + "Q": [ 1091 ], + "R": [ 1062 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_1": { @@ -22267,11 +29995,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 614 ], - "E": [ 627 ], - "Q": [ 649 ], - "R": [ 624 ] + "C": [ 62 ], + "D": [ 1052 ], + "E": [ 1119 ], + "Q": [ 1089 ], + "R": [ 1062 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_2": { @@ -22291,11 +30019,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 615 ], - "E": [ 627 ], - "Q": [ 655 ], - "R": [ 624 ] + "C": [ 62 ], + "D": [ 1053 ], + "E": [ 1119 ], + "Q": [ 1093 ], + "R": [ 1062 ] } }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_3": { @@ -22315,11 +30043,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 616 ], - "E": [ 627 ], - "Q": [ 657 ], - "R": [ 624 ] + "C": [ 62 ], + "D": [ 1054 ], + "E": [ 1119 ], + "Q": [ 1086 ], + "R": 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"C": [ 62 ], + "D": [ 1058 ], + "E": [ 1119 ], + "Q": [ 1085 ], + "R": [ 1062 ] + } + }, + "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0011000011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 1084 ], + "I2": [ 1068 ], + "I3": [ 1062 ], + "O": [ 1119 ] } }, "spi_if_ins.state_if_SB_DFFESR_Q": { @@ -22435,11 +30188,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 683 ], - "E": [ 684 ], - "Q": [ 609 ], - "R": [ 596 ] + "C": [ 62 ], + "D": [ 1120 ], + "E": [ 1121 ], + "Q": [ 1046 ], + "R": [ 1039 ] } }, "spi_if_ins.state_if_SB_DFFESR_Q_1": { @@ -22459,11 +30212,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 608 ], - "E": [ 684 ], - "Q": [ 598 ], - "R": [ 607 ] + "C": [ 62 ], + "D": [ 1047 ], + "E": [ 1121 ], + "Q": [ 1041 ], + "R": [ 1048 ] } }, "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O": { @@ -22485,35 +30238,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 598 ], - "I2": [ 609 ], - "I3": [ 610 ], - "O": [ 683 ] - } - }, - "spi_if_ins.state_if_SB_DFFESR_Q_D_SB_LUT4_O_1": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "1111110011111111" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ 598 ], - "I2": [ 610 ], - "I3": [ 609 ], - "O": [ 608 ] + "I1": [ 1041 ], + "I2": [ 1046 ], + "I3": [ 1045 ], + "O": [ 1120 ] } }, "spi_if_ins.state_if_SB_DFFESR_Q_R_SB_LUT4_O": { @@ -22537,8 +30265,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 607 ], - "O": [ 596 ] + "I3": [ 1048 ], + "O": [ 1039 ] } }, "spi_if_ins.state_if_SB_DFFE_Q": { @@ -22557,10 +30285,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 685 ], - "E": [ 684 ], - "Q": [ 610 ] + "C": [ 62 ], + "D": [ 1122 ], + "E": [ 1121 ], + "Q": [ 1045 ] } }, "spi_if_ins.state_if_SB_DFFE_Q_D_SB_LUT4_O": { @@ -22581,11 +30309,11 @@ "O": "output" }, "connections": { - "I0": [ 683 ], - "I1": [ 587 ], - "I2": [ 608 ], - "I3": [ 607 ], - "O": [ 685 ] + "I0": [ 1120 ], + "I1": [ 1030 ], + "I2": [ 1047 ], + "I3": [ 1048 ], + "O": [ 1122 ] } }, "spi_if_ins.state_if_SB_DFFE_Q_E_SB_LUT4_O": { @@ -22606,11 +30334,11 @@ "O": "output" }, "connections": { - "I0": [ 598 ], - "I1": [ 607 ], - "I2": [ 609 ], - "I3": [ 610 ], - "O": [ 684 ] + "I0": [ 1041 ], + "I1": [ 1048 ], + "I2": [ 1046 ], + "I3": [ 1045 ], + "O": [ 1121 ] } }, "sys_ctrl_ins.i_cs_SB_DFFE_Q": { @@ -22629,10 +30357,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 68 ], - "E": [ 66 ], - "Q": [ 564 ] + "C": [ 62 ], + "D": [ 75 ], + "E": [ 73 ], + "Q": [ 1029 ] } }, "sys_ctrl_ins.i_cs_SB_DFFE_Q_D_SB_LUT4_O": { @@ -22655,9 +30383,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 585 ], - "I3": [ 586 ], - "O": [ 68 ] + "I2": [ 1028 ], + "I3": [ 1027 ], + "O": [ 75 ] } }, "sys_ctrl_ins.o_data_out_SB_DFFE_Q": { @@ -22676,35 +30404,10 @@ "Q": "output" }, "connections": { - "C": [ 55 ], - "D": [ 79 ], - "E": [ 686 ], - "Q": [ 687 ] - } - }, - "sys_ctrl_ins.o_data_out_SB_DFFE_Q_D_SB_LUT4_O": { - "hide_name": 0, - "type": "SB_LUT4", - "parameters": { - "LUT_INIT": "0011111111111111" - }, - "attributes": { - "module_not_derived": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" - }, - "port_directions": { - "I0": "input", - "I1": "input", - "I2": "input", - "I3": "input", - "O": "output" - }, - "connections": { - "I0": [ "0" ], - "I1": [ 85 ], - "I2": [ 84 ], - "I3": [ 86 ], - "O": [ 79 ] + "C": [ 62 ], + "D": [ 50 ], + "E": [ 1123 ], + "Q": [ 1124 ] } }, "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O": { @@ -22726,10 +30429,10 @@ }, "connections": { "I0": [ "0" ], - "I1": [ 85 ], - "I2": [ 564 ], - "I3": [ 560 ], - "O": [ 686 ] + "I1": [ 115 ], + "I2": [ 1029 ], + "I3": [ 117 ], + "O": [ 1123 ] } }, "sys_ctrl_ins.o_data_out_SB_LUT4_I0": { @@ -22750,11 +30453,11 @@ "O": "output" }, "connections": { - "I0": [ 687 ], - "I1": [ 312 ], - "I2": [ 563 ], - "I3": [ 562 ], - "O": [ 326 ] + "I0": [ 1124 ], + "I1": [ 491 ], + "I2": [ 958 ], + "I3": [ 957 ], + "O": [ 505 ] } }, "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q": { @@ -22774,11 +30477,11 @@ "S": "input" }, "connections": { - "C": [ 55 ], + "C": [ 62 ], "D": [ "0" ], - "E": [ 688 ], - "Q": [ 51 ], - "S": [ 689 ] + "E": [ 1125 ], + "Q": [ 57 ], + "S": [ 1126 ] } }, "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E_SB_LUT4_O": { @@ -22802,8 +30505,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 690 ], - "O": [ 688 ] + "I3": [ 1127 ], + "O": [ 1125 ] } }, "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S_SB_LUT4_O": { @@ -22824,11 +30527,11 @@ "O": "output" }, "connections": { - "I0": [ 691 ], - "I1": [ 692 ], - "I2": [ 693 ], - "I3": [ 694 ], - "O": [ 689 ] + "I0": [ 1128 ], + "I1": [ 1129 ], + "I2": [ 1130 ], + "I3": [ 1131 ], + "O": [ 1126 ] } }, "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q": { @@ -22848,11 +30551,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], + "C": [ 62 ], "D": [ "1" ], - "E": [ 695 ], - "Q": [ 690 ], - "R": [ 696 ] + "E": [ 1132 ], + "Q": [ 1127 ], + "R": [ 1133 ] } }, "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O": { @@ -22873,11 +30576,11 @@ "O": "output" }, "connections": { - "I0": [ 560 ], - "I1": [ 48 ], - "I2": [ 606 ], - "I3": [ 564 ], - "O": [ 695 ] + "I0": [ 117 ], + "I1": [ 52 ], + "I2": [ 1044 ], + "I3": [ 1029 ], + "O": [ 1132 ] } }, "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R_SB_LUT4_O": { @@ -22901,8 +30604,33 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 564 ], - "O": [ 696 ] + "I3": [ 1029 ], + "O": [ 1133 ] + } + }, + "sys_ctrl_ins.reset_cmd_SB_LUT4_I3": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111111111110000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ "0" ], + "I2": [ 1126 ], + "I3": [ 1127 ], + "O": [ 1134 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q": { @@ -22922,11 +30650,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 697 ], - "E": [ 698 ], - "Q": [ 691 ], - "R": [ 690 ] + "C": [ 62 ], + "D": [ 1135 ], + "E": [ 1134 ], + "Q": [ 1128 ], + "R": [ 1127 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_1": { @@ -22946,11 +30674,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 699 ], - "E": [ 698 ], - "Q": [ 693 ], - "R": [ 690 ] + "C": [ 62 ], + "D": [ 1136 ], + "E": [ 1134 ], + "Q": [ 1130 ], + "R": [ 1127 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_1_D_SB_LUT4_O": { @@ -22971,11 +30699,11 @@ "O": "output" }, "connections": { - "I0": [ 689 ], + "I0": [ 1126 ], "I1": [ "0" ], - "I2": [ 693 ], - "I3": [ 700 ], - "O": [ 699 ] + "I2": [ 1130 ], + "I3": [ 1137 ], + "O": [ 1136 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_2": { @@ -22995,11 +30723,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 701 ], - "E": [ 698 ], - "Q": [ 692 ], - "R": [ 690 ] + "C": [ 62 ], + "D": [ 1138 ], + "E": [ 1134 ], + "Q": [ 1129 ], + "R": [ 1127 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_2_D_SB_LUT4_O": { @@ -23020,11 +30748,11 @@ "O": "output" }, "connections": { - "I0": [ 689 ], + "I0": [ 1126 ], "I1": [ "0" ], - "I2": [ 692 ], - "I3": [ 694 ], - "O": [ 701 ] + "I2": [ 1129 ], + "I3": [ 1131 ], + "O": [ 1138 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_3": { @@ -23044,11 +30772,11 @@ "R": "input" }, "connections": { - "C": [ 55 ], - "D": [ 702 ], - "E": [ 698 ], - "Q": [ 694 ], - "R": [ 690 ] + "C": [ 62 ], + "D": [ 1139 ], + "E": [ 1134 ], + "Q": [ 1131 ], + "R": [ 1127 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_3_D_SB_LUT4_O": { @@ -23072,8 +30800,8 @@ "I0": [ "0" ], "I1": [ "0" ], "I2": [ "0" ], - "I3": [ 694 ], - "O": [ 702 ] + "I3": [ 1131 ], + "O": [ 1139 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O": { @@ -23094,11 +30822,11 @@ "O": "output" }, "connections": { - "I0": [ 689 ], + "I0": [ 1126 ], "I1": [ "0" ], - "I2": [ 691 ], - "I3": [ 703 ], - "O": [ 697 ] + "I2": [ 1128 ], + "I3": [ 1140 ], + "O": [ 1135 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO": { @@ -23116,10 +30844,10 @@ "I1": "input" }, "connections": { - "CI": [ 700 ], - "CO": [ 703 ], + "CI": [ 1137 ], + "CO": [ 1140 ], "I0": [ "0" ], - "I1": [ 693 ] + "I1": [ 1130 ] } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_1": { @@ -23137,17 +30865,117 @@ "I1": "input" }, "connections": { - "CI": [ 694 ], - "CO": [ 700 ], + "CI": [ 1131 ], + "CO": [ 1137 ], "I0": [ "0" ], - "I1": [ 692 ] + "I1": [ 1129 ] } }, - "sys_ctrl_ins.reset_count_SB_DFFESR_Q_E_SB_LUT4_O": { + "w_lvds_rx_09_d1_SB_LUT4_I1": { "hide_name": 0, "type": "SB_LUT4", "parameters": { - "LUT_INIT": "1111111111110000" + "LUT_INIT": "1110111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 322 ], + "I1": [ 175 ], + "I2": [ 176 ], + "I3": [ 323 ], + "O": [ 328 ] + } + }, + "w_lvds_rx_09_d1_SB_LUT4_I1_O_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111110011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 57 ], + "I2": [ 286 ], + "I3": [ 322 ], + "O": [ 283 ] + } + }, + "w_lvds_rx_24_d1_SB_LUT4_I1": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1110111100000000" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ 471 ], + "I1": [ 179 ], + "I2": [ 178 ], + "I3": [ 472 ], + "O": [ 477 ] + } + }, + "w_lvds_rx_24_d1_SB_LUT4_I1_O_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "1111110011111111" + }, + "attributes": { + "module_not_derived": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" + }, + "port_directions": { + "I0": "input", + "I1": "input", + "I2": "input", + "I3": "input", + "O": "output" + }, + "connections": { + "I0": [ "0" ], + "I1": [ 57 ], + "I2": [ 435 ], + "I3": [ 471 ], + "O": [ 432 ] + } + }, + "w_smi_read_req_SB_LUT4_O": { + "hide_name": 0, + "type": "SB_LUT4", + "parameters": { + "LUT_INIT": "0000111111111111" }, "attributes": { "module_not_derived": "00000000000000000000000000000001", @@ -23163,9 +30991,9 @@ "connections": { "I0": [ "0" ], "I1": [ "0" ], - "I2": [ 689 ], - "I3": [ 690 ], - "O": [ 698 ] + "I2": [ 718 ], + "I3": [ 508 ], + "O": [ 486 ] } } }, @@ -23177,9 +31005,9 @@ "src": "top.v:40.13-40.21" } }, - "i_button_SB_LUT4_I1_O": { + "i_button_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 112, 50 ], + "bits": [ 54, 49 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -23192,6 +31020,14 @@ "src": "top.v:39.19-39.27" } }, + "i_config_SB_LUT4_I0_I1": { + "hide_name": 0, + "bits": [ 47, 27, 50, 83 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "i_glob_clock": { "hide_name": 0, "bits": [ 2 ], @@ -23243,7 +31079,7 @@ }, "i_smi_a1_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 52 ], + "bits": [ 59 ], "attributes": { } }, @@ -23254,10 +31090,12 @@ "src": "top.v:47.13-47.21" } }, - "i_smi_a2_SB_LUT4_I0_O": { + "i_smi_a2_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 53 ], + "bits": [ 60, 57 ], "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "i_smi_a3": { @@ -23288,21 +31126,41 @@ "src": "top.v:59.13-59.17" } }, + "i_ss_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 61 ], + "attributes": { + } + }, "int_miso": { "hide_name": 0, - "bits": [ 307 ], + "bits": [ 485 ], "attributes": { "src": "top.v:110.9-110.17" } }, "io_ctrl_ins.debug_mode": { "hide_name": 0, - "bits": [ 60, 58 ], + "bits": [ 67, 65 ], "attributes": { "hdlname": "io_ctrl_ins debug_mode", "src": "top.v:128.12-156.5|io_ctrl.v:67.17-67.27" } }, + "io_ctrl_ins.debug_mode_SB_LUT4_I0_O": { + "hide_name": 0, + "bits": [ 70 ], + "attributes": { + } + }, + "io_ctrl_ins.debug_mode_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 113, 69, 68, 71 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.i_button": { "hide_name": 0, "bits": [ 17 ], @@ -23321,7 +31179,7 @@ }, "io_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 67 ], + "bits": [ 74 ], "attributes": { "hdlname": "io_ctrl_ins i_cs", "src": "top.v:128.12-156.5|io_ctrl.v:9.29-9.33" @@ -23329,7 +31187,7 @@ }, "io_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 59, 56, 142, 140, 138, 136, 134, 131 ], + "bits": [ 66, 63, 148, 146, 145, 143, 141, 139 ], "attributes": { "hdlname": "io_ctrl_ins i_data_in", "src": "top.v:128.12-156.5|io_ctrl.v:7.29-7.38" @@ -23337,7 +31195,7 @@ }, "io_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 560 ], + "bits": [ 117 ], "attributes": { "hdlname": "io_ctrl_ins i_fetch_cmd", "src": "top.v:128.12-156.5|io_ctrl.v:10.29-10.40" @@ -23345,7 +31203,7 @@ }, "io_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 84, 86, 603, 602, 601 ], + "bits": [ 136, 135, 133, 134, 130 ], "attributes": { "hdlname": "io_ctrl_ins i_ioc", "src": "top.v:128.12-156.5|io_ctrl.v:6.29-6.34" @@ -23353,7 +31211,7 @@ }, "io_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 606 ], + "bits": [ 1044 ], "attributes": { "hdlname": "io_ctrl_ins i_load_cmd", "src": "top.v:128.12-156.5|io_ctrl.v:11.29-11.39" @@ -23361,7 +31219,7 @@ }, "io_ctrl_ins.i_reset": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "hdlname": "io_ctrl_ins i_reset", "src": "top.v:128.12-156.5|io_ctrl.v:3.29-3.36" @@ -23369,7 +31227,7 @@ }, "io_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 55 ], + "bits": [ 62 ], "attributes": { "hdlname": "io_ctrl_ins i_sys_clk", "src": "top.v:128.12-156.5|io_ctrl.v:4.29-4.38" @@ -23383,6 +31241,14 @@ "src": "top.v:128.12-156.5|io_ctrl.v:71.17-71.27" } }, + "io_ctrl_ins.led0_state_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 93, 48, 81, 78 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.led1_state": { "hide_name": 0, "bits": [ 27 ], @@ -23393,10 +31259,18 @@ }, "io_ctrl_ins.led1_state_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 69 ], + "bits": [ 76 ], "attributes": { } }, + "io_ctrl_ins.led1_state_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 137, 52, 85, 84 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.lna_rx_shutdown_state": { "hide_name": 0, "bits": [ 8 ], @@ -23407,19 +31281,11 @@ }, "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 77 ], + "bits": [ 86 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, - "io_ctrl_ins.lna_rx_shutdown_state_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 27, 47, 74, 75 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.lna_tx_shutdown_state": { "hide_name": 0, "bits": [ 9 ], @@ -23430,14 +31296,14 @@ }, "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 87 ], + "bits": [ 88 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, "io_ctrl_ins.mixer_en_state": { "hide_name": 0, - "bits": [ 92 ], + "bits": [ 93 ], "attributes": { "hdlname": "io_ctrl_ins mixer_en_state", "src": "top.v:128.12-156.5|io_ctrl.v:76.17-76.31" @@ -23445,22 +31311,14 @@ }, "io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 91 ], + "bits": [ 92 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, - "io_ctrl_ins.mixer_en_state_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 26, 47, 70, 71 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.o_data_out": { "hide_name": 0, - "bits": [ 130, 116, 98, 119, 123, 102, 107, 111 ], + "bits": [ 138, 98, 109, 101, 106, 120, 125, 129 ], "attributes": { "hdlname": "io_ctrl_ins o_data_out", "src": "top.v:128.12-156.5|io_ctrl.v:8.29-8.39" @@ -23476,7 +31334,7 @@ }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 106 ], + "bits": [ 105 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" @@ -23484,27 +31342,49 @@ }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 110 ], + "bits": [ 107 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" } }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2": { + "hide_name": 0, + "bits": [ 111, 50, 112, 91 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E": { "hide_name": 0, - "bits": [ 101 ], + "bits": [ 108 ], "attributes": { } }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 48, 52, 115, 116 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I3_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 97 ], + "attributes": { + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R": { + "hide_name": 0, + "bits": [ 114, 115, 110, 116 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_4_D": { - "hide_name": 0, - "bits": [ 76 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_D": { "hide_name": 0, "bits": [ 118 ], "attributes": { @@ -23512,14 +31392,60 @@ "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" } }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D": { + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_D": { "hide_name": 0, - "bits": [ 122 ], + "bits": [ 124 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" } }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D": { + "hide_name": 0, + "bits": [ 128 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E": { + "hide_name": 0, + "bits": [ 119 ], + "attributes": { + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 130, 114, 131 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3": { + "hide_name": 0, + "bits": [ 131, 132 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_1_I3_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 121, 79 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E_SB_LUT4_O_I0_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 135, 115, 48, 52 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D": { "hide_name": 0, "bits": [ 96 ], @@ -23528,34 +31454,6 @@ "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" } }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 126, 90 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_E": { - "hide_name": 0, - "bits": [ 97 ], - "attributes": { - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 51, 129, 535, 560 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "io_ctrl_ins.o_data_out_SB_DFFESR_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 115 ], - "attributes": { - } - }, "io_ctrl_ins.o_data_out_SB_DFFESR_Q_R": { "hide_name": 0, "bits": [ 99 ], @@ -23564,18 +31462,12 @@ }, "io_ctrl_ins.o_data_out_SB_DFFESS_Q_D": { "hide_name": 0, - "bits": [ 72 ], + "bits": [ 95 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22" } }, - "io_ctrl_ins.o_data_out_SB_DFFESS_Q_S": { - "hide_name": 0, - "bits": [ 117 ], - "attributes": { - } - }, "io_ctrl_ins.o_led0": { "hide_name": 0, "bits": [ 26 ], @@ -23610,7 +31502,7 @@ }, "io_ctrl_ins.o_pmod": { "hide_name": 0, - "bits": [ 95, 83, 128, 147, 146, 145, 144, 49 ], + "bits": [ 80, 137, 90, 102, 152, 151, 150, 53 ], "attributes": { "hdlname": "io_ctrl_ins o_pmod", "src": "top.v:128.12-156.5|io_ctrl.v:18.29-18.35" @@ -23674,7 +31566,7 @@ }, "io_ctrl_ins.pmod_dir_state": { "hide_name": 0, - "bits": [ 94, 80, 89, 141, 139, 137, 135, 133 ], + "bits": [ 77, 83, 111, 147, 55, 144, 142, 51 ], "attributes": { "hdlname": "io_ctrl_ins pmod_dir_state", "src": "top.v:128.12-156.5|io_ctrl.v:73.17-73.31" @@ -23682,7 +31574,7 @@ }, "io_ctrl_ins.pmod_state": { "hide_name": 0, - "bits": [ 95, 83, 128, 147, 146, 145, 144, 49 ], + "bits": [ 80, 137, 90, 102, 152, 151, 150, 53 ], "attributes": { "hdlname": "io_ctrl_ins pmod_state", "src": "top.v:128.12-156.5|io_ctrl.v:74.17-74.27" @@ -23690,7 +31582,7 @@ }, "io_ctrl_ins.rf_mode": { "hide_name": 0, - "bits": [ 127, 61, 62 ], + "bits": [ 113, 68, 69 ], "attributes": { "hdlname": "io_ctrl_ins rf_mode", "src": "top.v:128.12-156.5|io_ctrl.v:68.17-68.24" @@ -23698,7 +31590,7 @@ }, "io_ctrl_ins.rf_pin_state": { "hide_name": 0, - "bits": [ 93, 78, 88, 153, 152, 151, 150, 149 ], + "bits": [ 94, 87, 89, 158, 157, 156, 155, 154 ], "attributes": { "hdlname": "io_ctrl_ins rf_pin_state", "src": "top.v:128.12-156.5|io_ctrl.v:75.17-75.29" @@ -23714,14 +31606,14 @@ }, "io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 154 ], + "bits": [ 159 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, "io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 108, 109 ], + "bits": [ 126, 127 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -23737,33 +31629,19 @@ }, "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 156 ], + "bits": [ 161 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, - "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I2": { - "hide_name": 0, - "bits": [ 62, 127, 61, 64 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 149, 64, 155 ], + "bits": [ 71, 155, 160 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "io_ctrl_ins.rx_h_state_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 63 ], - "attributes": { - } - }, "io_ctrl_ins.tr_vc_1_b_state": { "hide_name": 0, "bits": [ 6 ], @@ -23774,14 +31652,14 @@ }, "io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 157 ], + "bits": [ 162 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, - "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I3_O": { + "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_I2": { "hide_name": 0, - "bits": [ 14, 47, 124, 125 ], + "bits": [ 6, 48, 164, 56 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -23797,14 +31675,14 @@ }, "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 159 ], + "bits": [ 165 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 64, 152, 158 ], + "bits": [ 156, 71, 163 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -23812,7 +31690,7 @@ }, "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 15, 47, 104, 105 ], + "bits": [ 122, 123 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -23828,14 +31706,14 @@ }, "io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 160 ], + "bits": [ 166 ], "attributes": { "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8" } }, "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 13, 47, 120, 121 ], + "bits": [ 102, 52, 103, 104 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -23857,21 +31735,21 @@ }, "lvds_clock": { "hide_name": 0, - "bits": [ 171 ], + "bits": [ 177 ], "attributes": { "src": "top.v:189.9-189.19" } }, "lvds_clock_buf": { "hide_name": 0, - "bits": [ 171 ], + "bits": [ 177 ], "attributes": { "src": "top.v:190.9-190.23" } }, "lvds_rx_09_inst.i_ddr_clk": { "hide_name": 0, - "bits": [ 171 ], + "bits": [ 177 ], "attributes": { "hdlname": "lvds_rx_09_inst i_ddr_clk", "src": "top.v:259.12-279.5|lvds_rx.v:4.29-4.38" @@ -23879,7 +31757,7 @@ }, "lvds_rx_09_inst.i_ddr_data": { "hide_name": 0, - "bits": [ 170, 169 ], + "bits": [ 176, 175 ], "attributes": { "hdlname": "lvds_rx_09_inst i_ddr_data", "src": "top.v:259.12-279.5|lvds_rx.v:5.29-5.39" @@ -23887,7 +31765,7 @@ }, "lvds_rx_09_inst.i_fifo_full": { "hide_name": 0, - "bits": [ 302 ], + "bits": [ 331 ], "attributes": { "hdlname": "lvds_rx_09_inst i_fifo_full", "src": "top.v:259.12-279.5|lvds_rx.v:7.29-7.40" @@ -23895,7 +31773,7 @@ }, "lvds_rx_09_inst.i_reset": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "hdlname": "lvds_rx_09_inst i_reset", "src": "top.v:259.12-279.5|lvds_rx.v:3.29-3.36" @@ -23903,7 +31781,7 @@ }, "lvds_rx_09_inst.o_debug_state": { "hide_name": 0, - "bits": [ 279, 281 ], + "bits": [ 286, 322 ], "attributes": { "hdlname": "lvds_rx_09_inst o_debug_state", "src": "top.v:259.12-279.5|lvds_rx.v:11.29-11.42" @@ -23911,7 +31789,7 @@ }, "lvds_rx_09_inst.o_fifo_data": { "hide_name": 0, - "bits": [ 224, 222, 218, 216, 214, 212, 210, 208, 206, 204, 202, 200, 196, 194, 192, 190, 188, 186, 184, 182, 180, 178, 236, 234, 232, 230, 228, 226, 220, 198, 176, 174 ], + "bits": [ 230, 229, 226, 224, 222, 220, 218, 216, 214, 212, 210, 208, 204, 202, 200, 198, 196, 194, 192, 190, 188, 186, 242, 240, 238, 236, 234, 232, 228, 206, 184, 182 ], "attributes": { "hdlname": "lvds_rx_09_inst o_fifo_data", "src": "top.v:259.12-279.5|lvds_rx.v:10.29-10.40" @@ -23919,7 +31797,7 @@ }, "lvds_rx_09_inst.o_fifo_push": { "hide_name": 0, - "bits": [ 238 ], + "bits": [ 244 ], "attributes": { "hdlname": "lvds_rx_09_inst o_fifo_push", "src": "top.v:259.12-279.5|lvds_rx.v:9.29-9.40" @@ -23927,37 +31805,37 @@ }, "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O": { "hide_name": 0, - "bits": [ 243 ], + "bits": [ 249 ], "attributes": { "src": "top.v:284.17-295.5|complex_fifo.v:23.1-37.4" } }, "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_2_O": { "hide_name": 0, - "bits": [ 244 ], + "bits": [ 250 ], "attributes": { } }, "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I0": { "hide_name": 0, - "bits": [ "0", 259, 257, 255, 253, 251, 249, 247, 245, 239 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "top.v:284.17-295.5|complex_fifo.v:30.24-30.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" - } - }, - "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_I2": { - "hide_name": 0, - "bits": [ 704, 261, 267, 266, 265, 264, 263, 241, 262, 239 ], + "bits": [ 1141, 273, 270, 267, 264, 261, 245, 256, 253, 247 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": 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"bits": [ 299 ], + "attributes": { + } + }, + "lvds_rx_09_inst.r_data_SB_DFFESR_Q_23_D": { + "hide_name": 0, + "bits": [ 300 ], + "attributes": { + } + }, + "lvds_rx_09_inst.r_data_SB_DFFESR_Q_24_D": { + "hide_name": 0, + "bits": [ 301 ], + "attributes": { + } + }, + "lvds_rx_09_inst.r_data_SB_DFFESR_Q_25_D": { + "hide_name": 0, + "bits": [ 302 ], + "attributes": { + } + }, + "lvds_rx_09_inst.r_data_SB_DFFESR_Q_26_D": { + "hide_name": 0, + "bits": [ 303 ], + "attributes": { + } + }, + "lvds_rx_09_inst.r_data_SB_DFFESR_Q_27_D": { + "hide_name": 0, + "bits": [ 304 ], + "attributes": { + } + }, + "lvds_rx_09_inst.r_data_SB_DFFESR_Q_28_D": { + "hide_name": 0, + "bits": [ 305 ], + "attributes": { + } + }, + "lvds_rx_09_inst.r_data_SB_DFFESR_Q_29_D": { + "hide_name": 0, + "bits": [ 306 ], + "attributes": { + } + }, "lvds_rx_09_inst.r_data_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 286 ], + "bits": [ 296 ], "attributes": { } }, "lvds_rx_09_inst.r_data_SB_DFFESR_Q_3_D": { "hide_name": 0, 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"rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ "0", 370, 382, 381, 379, 377, 376, 375, 374, 372 ], + "bits": [ "0", 560, 559, 557, 556, 554, 552, 551, 549, 562 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:284.17-295.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" @@ -24475,15 +32858,29 @@ }, "rx_09_fifo.full_o_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 343, 344, 345, 346 ], + "bits": [ 565, 548, 566, 567 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, + "rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I0_O": { + "hide_name": 0, + "bits": [ 246, 544, 545 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_09_fifo.mem_i.0.0.0_RCLKE": { + "hide_name": 0, + "bits": [ 569 ], + "attributes": { + } + }, "rx_09_fifo.mem_i.0.0.0_RDATA": { "hide_name": 0, - "bits": [ 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, 400, 401, 402 ], + "bits": [ 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24491,7 +32888,7 @@ }, "rx_09_fifo.mem_i.1.0.0_RDATA": { "hide_name": 0, - "bits": [ 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418 ], + "bits": [ 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24499,7 +32896,7 @@ }, "rx_09_fifo.mem_i.2.0.0_RDATA": { "hide_name": 0, - "bits": [ 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 434 ], + "bits": [ 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, 616, 617 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24507,7 +32904,7 @@ }, "rx_09_fifo.mem_i.3.0.0_RDATA": { "hide_name": 0, - "bits": [ 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450 ], + "bits": [ 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, 629, 630, 631, 632, 633 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24515,7 +32912,7 @@ }, "rx_09_fifo.mem_q.0.0.0_RDATA": { "hide_name": 0, - "bits": [ 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, 464, 465, 466 ], + "bits": [ 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, 645, 646, 647, 648, 649 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24523,7 +32920,7 @@ }, "rx_09_fifo.mem_q.1.0.0_RDATA": { "hide_name": 0, - "bits": [ 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482 ], + "bits": [ 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24531,7 +32928,7 @@ }, "rx_09_fifo.mem_q.2.0.0_RDATA": { "hide_name": 0, - "bits": [ 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498 ], + "bits": [ 666, 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 678, 679, 680, 681 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24539,7 +32936,7 @@ }, "rx_09_fifo.mem_q.3.0.0_RDATA": { "hide_name": 0, - "bits": [ 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511, 512, 513, 514 ], + "bits": [ 682, 683, 684, 685, 686, 687, 688, 689, 690, 691, 692, 693, 694, 695, 696, 697 ], "attributes": { "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" @@ -24547,7 +32944,7 @@ }, "rx_09_fifo.rd_addr": { "hide_name": 0, - "bits": [ 369, 354, 338, 268, 349, 271, 272, 350, 240, 269 ], + "bits": [ 568, 535, 533, 280, 277, 278, 274, 246, 538, 275 ], "attributes": { "hdlname": "rx_09_fifo rd_addr", "src": "top.v:284.17-295.5|complex_fifo.v:21.22-21.29" @@ -24555,7 +32952,7 @@ }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 525, 524, 523, 522, 521, 520, 519, 518, 517, 515 ], + "bits": [ 708, 707, 706, 705, 704, 703, 702, 701, 700, 698 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:284.17-295.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" @@ -24563,15 +32960,21 @@ }, "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ "0", 369, 533, 532, 531, 530, 529, 528, 527, 526 ], + "bits": [ "0", 568, 716, 715, 714, 713, 712, 711, 710, 709 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:284.17-295.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" } }, + "rx_09_fifo.rd_addr_SB_DFFESR_Q_E": { + "hide_name": 0, + "bits": [ 699 ], + "attributes": { + } + }, "rx_09_fifo.rd_clk_i": { "hide_name": 0, - "bits": [ 55 ], + "bits": [ 62 ], "attributes": { "hdlname": "rx_09_fifo rd_clk_i", "src": "top.v:284.17-295.5|complex_fifo.v:12.31-12.39" @@ -24579,7 +32982,7 @@ }, "rx_09_fifo.rd_data_o": { "hide_name": 0, - "bits": [ 420, 424, 428, 432, 436, 440, 444, 448, 388, 392, 396, 400, 404, 408, 412, 416, 484, 488, 492, 496, 500, 504, 508, 512, 452, 456, 460, 464, 468, 472, 476, 480 ], + "bits": [ 603, 607, 611, 615, 619, 623, 627, 631, 571, 575, 579, 583, 587, 591, 595, 599, 667, 671, 675, 679, 683, 687, 691, 695, 635, 639, 643, 647, 651, 655, 659, 663 ], "attributes": { "hdlname": "rx_09_fifo rd_data_o", "src": "top.v:284.17-295.5|complex_fifo.v:14.35-14.44" @@ -24587,7 +32990,7 @@ }, "rx_09_fifo.rd_rst_i": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "hdlname": "rx_09_fifo rd_rst_i", "src": "top.v:284.17-295.5|complex_fifo.v:11.31-11.39" @@ -24595,7 +32998,7 @@ }, "rx_09_fifo.wr_addr": { "hide_name": 0, - "bits": [ 370, 259, 260, 258, 256, 254, 252, 250, 248, 246 ], + "bits": [ 560, 272, 271, 268, 265, 262, 259, 257, 254, 251 ], "attributes": { "hdlname": "rx_09_fifo wr_addr", "src": "top.v:284.17-295.5|complex_fifo.v:20.22-20.29" @@ -24603,7 +33006,7 @@ }, "rx_09_fifo.wr_clk_i": { "hide_name": 0, - "bits": [ 171 ], + "bits": [ 177 ], "attributes": { "hdlname": "rx_09_fifo wr_clk_i", "src": "top.v:284.17-295.5|complex_fifo.v:7.31-7.39" @@ -24611,7 +33014,7 @@ }, "rx_09_fifo.wr_data_i": { "hide_name": 0, - "bits": [ 224, 222, 218, 216, 214, 212, 210, 208, 206, 204, 202, 200, 196, 194, 192, 190, 188, 186, 184, 182, 180, 178, 236, 234, 232, 230, 228, 226, 220, 198, 176, 174 ], + "bits": [ 230, 229, 226, 224, 222, 220, 218, 216, 214, 212, 210, 208, 204, 202, 200, 198, 196, 194, 192, 190, 188, 186, 242, 240, 238, 236, 234, 232, 228, 206, 184, 182 ], "attributes": { "hdlname": "rx_09_fifo wr_data_i", "src": "top.v:284.17-295.5|complex_fifo.v:9.35-9.44" @@ -24619,7 +33022,7 @@ }, "rx_09_fifo.wr_en_i": { "hide_name": 0, - "bits": [ 238 ], + "bits": [ 244 ], "attributes": { "hdlname": "rx_09_fifo wr_en_i", "src": "top.v:284.17-295.5|complex_fifo.v:8.31-8.38" @@ -24627,15 +33030,315 @@ }, "rx_09_fifo.wr_rst_i": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "hdlname": "rx_09_fifo wr_rst_i", "src": "top.v:284.17-295.5|complex_fifo.v:6.31-6.39" } }, + "rx_24_fifo.empty_o": { + "hide_name": 0, + "bits": [ 718 ], + "attributes": { + "hdlname": "rx_24_fifo empty_o", + "src": "top.v:320.17-331.5|complex_fifo.v:17.19-17.26" + } + }, + "rx_24_fifo.empty_o_SB_DFFSS_Q_D": { + "hide_name": 0, + "bits": [ 717 ], + "attributes": { + } + }, + "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 719, 720, 721, 722 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.empty_o_SB_LUT4_I0_I1": { + "hide_name": 0, + "bits": [ 718, 727, 728, 729 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.empty_o_SB_LUT4_I0_O": { + "hide_name": 0, + "bits": [ 723, 724, 720, 725 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.empty_o_SB_LUT4_I0_O_SB_LUT4_O_I1": { + "hide_name": 0, + "bits": [ 920, 752, 750, 748, 746, 744, 726, 741, 739, 735, 1016 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "top.v:320.17-331.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" + } + }, + "rx_24_fifo.full_o": { + "hide_name": 0, + "bits": [ 480 ], + "attributes": { + "hdlname": "rx_24_fifo full_o", + "src": "top.v:320.17-331.5|complex_fifo.v:16.19-16.25" + } + }, + "rx_24_fifo.full_o_SB_DFFSR_Q_D": { + "hide_name": 0, + "bits": [ 753 ], + "attributes": { + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_I1": { + "hide_name": 0, + "bits": [ 400, 758, 720, 480 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_I2": { + "hide_name": 0, + "bits": [ 734, 735, 425, 720 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 754, 755, 756, 757 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I2": { + "hide_name": 0, + "bits": [ 734, 766, 767, 768 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2": { + "hide_name": 0, + "bits": [ 732, 773, 774, 775 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2_SB_LUT4_O_1_I0": { + "hide_name": 0, + "bits": [ 776, 777, 429, 778 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 762, 763, 764, 765 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3": { + "hide_name": 0, + "bits": [ 423, 428, 720, 779 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_3_I3": { + "hide_name": 0, + "bits": [ 733, 420, 723, 780 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "rx_24_fifo.mem_i.0.0.0_RDATA": { + "hide_name": 0, + "bits": [ 782, 783, 784, 785, 786, 787, 788, 789, 790, 791, 792, 793, 794, 795, 796, 797 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", + "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" + } + }, + "rx_24_fifo.mem_i.1.0.0_RDATA": { + "hide_name": 0, + "bits": [ 798, 799, 800, 801, 802, 803, 804, 805, 806, 807, 808, 809, 810, 811, 812, 813 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", + "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" + } + }, + "rx_24_fifo.mem_i.2.0.0_RDATA": { + "hide_name": 0, + "bits": [ 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, 824, 825, 826, 827, 828, 829 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", + "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" + } + }, + "rx_24_fifo.mem_i.3.0.0_RDATA": { + "hide_name": 0, + "bits": [ 830, 831, 832, 833, 834, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845 ], + "attributes": { + "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23", + "unused_bits": "0 2 3 4 6 7 8 10 11 12 14 15" + } + }, + "rx_24_fifo.mem_q.0.0.0_RDATA": { + "hide_name": 0, + "bits": [ 846, 847, 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"attributes": { + "hdlname": "rx_24_fifo wr_data_i", + "src": "top.v:320.17-331.5|complex_fifo.v:9.35-9.44" + } + }, + "rx_24_fifo.wr_en_i": { + "hide_name": 0, + "bits": [ 400 ], + "attributes": { + "hdlname": "rx_24_fifo wr_en_i", + "src": "top.v:320.17-331.5|complex_fifo.v:8.31-8.38" + } + }, + "rx_24_fifo.wr_rst_i": { + "hide_name": 0, + "bits": [ 57 ], + "attributes": { + "hdlname": "rx_24_fifo wr_rst_i", + "src": "top.v:320.17-331.5|complex_fifo.v:6.31-6.39" + } + }, "smi_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 535 ], + "bits": [ 939 ], "attributes": { "hdlname": "smi_ctrl_ins i_cs", "src": "top.v:333.13-364.5|smi_ctrl.v:9.29-9.33" @@ -24643,7 +33346,7 @@ }, "smi_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 59, 56, 142, 140, 138, 136, 134, 131 ], + "bits": [ 66, 63, 148, 146, 145, 143, 141, 139 ], "attributes": { "hdlname": "smi_ctrl_ins i_data_in", "src": "top.v:333.13-364.5|smi_ctrl.v:7.29-7.38" @@ -24651,7 +33354,7 @@ }, "smi_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 560 ], + "bits": [ 117 ], "attributes": { "hdlname": "smi_ctrl_ins i_fetch_cmd", "src": "top.v:333.13-364.5|smi_ctrl.v:10.29-10.40" @@ -24659,7 +33362,7 @@ }, "smi_ctrl_ins.i_fifo_09_empty": { "hide_name": 0, - "bits": [ 329 ], + "bits": [ 508 ], "attributes": { "hdlname": "smi_ctrl_ins i_fifo_09_empty", "src": "top.v:333.13-364.5|smi_ctrl.v:17.29-17.44" @@ -24667,7 +33370,7 @@ }, "smi_ctrl_ins.i_fifo_09_full": { "hide_name": 0, - "bits": [ 302 ], + "bits": [ 331 ], "attributes": { "hdlname": "smi_ctrl_ins i_fifo_09_full", "src": "top.v:333.13-364.5|smi_ctrl.v:16.29-16.43" @@ -24675,7 +33378,7 @@ }, "smi_ctrl_ins.i_fifo_09_pulled_data": { "hide_name": 0, - "bits": [ 420, 424, 428, 432, 436, 440, 444, 448, 388, 392, 396, 400, 404, 408, 412, 416, 484, 488, 492, 496, 500, 504, 508, 512, 452, 456, 460, 464, 468, 472, 476, 480 ], + "bits": [ 603, 607, 611, 615, 619, 623, 627, 631, 571, 575, 579, 583, 587, 591, 595, 599, 667, 671, 675, 679, 683, 687, 691, 695, 635, 639, 643, 647, 651, 655, 659, 663 ], "attributes": { "hdlname": "smi_ctrl_ins i_fifo_09_pulled_data", "src": "top.v:333.13-364.5|smi_ctrl.v:15.29-15.50" @@ -24683,7 +33386,7 @@ }, "smi_ctrl_ins.i_fifo_24_empty": { "hide_name": 0, - "bits": [ "x" ], + "bits": [ 718 ], "attributes": { "hdlname": "smi_ctrl_ins i_fifo_24_empty", "src": "top.v:333.13-364.5|smi_ctrl.v:23.29-23.44" @@ -24691,7 +33394,7 @@ }, "smi_ctrl_ins.i_fifo_24_full": { "hide_name": 0, - "bits": [ "x" ], + "bits": [ 480 ], "attributes": { "hdlname": "smi_ctrl_ins i_fifo_24_full", "src": "top.v:333.13-364.5|smi_ctrl.v:22.29-22.43" @@ -24699,7 +33402,7 @@ }, "smi_ctrl_ins.i_fifo_24_pulled_data": { "hide_name": 0, - "bits": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], + "bits": [ 815, 819, 823, 827, 831, 835, 839, 843, 783, 787, 791, 795, 799, 803, 807, 811, 879, 883, 887, 891, 895, 899, 903, 907, 847, 851, 855, 859, 863, 867, 871, 875 ], "attributes": { "hdlname": "smi_ctrl_ins i_fifo_24_pulled_data", "src": "top.v:333.13-364.5|smi_ctrl.v:21.29-21.50" @@ -24707,7 +33410,7 @@ }, "smi_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 84, 86, 603, 602, 601 ], + "bits": [ 136, 135, 133, 134, 130 ], "attributes": { "hdlname": "smi_ctrl_ins i_ioc", "src": "top.v:333.13-364.5|smi_ctrl.v:6.29-6.34" @@ -24715,7 +33418,7 @@ }, "smi_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 606 ], + "bits": [ 1044 ], "attributes": { "hdlname": "smi_ctrl_ins i_load_cmd", "src": "top.v:333.13-364.5|smi_ctrl.v:11.29-11.39" @@ -24723,7 +33426,7 @@ }, "smi_ctrl_ins.i_reset": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "hdlname": "smi_ctrl_ins i_reset", "src": "top.v:333.13-364.5|smi_ctrl.v:3.29-3.36" @@ -24773,7 +33476,7 @@ }, "smi_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 55 ], + "bits": [ 62 ], "attributes": { "hdlname": "smi_ctrl_ins i_sys_clk", "src": "top.v:333.13-364.5|smi_ctrl.v:4.29-4.38" @@ -24781,7 +33484,7 @@ }, "smi_ctrl_ins.int_cnt_09": { "hide_name": 0, - "bits": [ "1", "1", "1", 540, 538 ], + "bits": [ "1", "1", "1", 945, 943 ], "attributes": { "hdlname": "smi_ctrl_ins int_cnt_09", "src": "top.v:333.13-364.5|smi_ctrl.v:97.15-97.25" @@ -24789,87 +33492,43 @@ }, "smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_D": { "hide_name": 0, - "bits": [ 539, 537 ], + "bits": [ 944, 941 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:333.13-364.5|smi_ctrl.v:127.35-127.49|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27" } }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_11_O": { + "smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E": { "hide_name": 0, - "bits": [ 428, 396, 538, 543 ], + "bits": [ 942 ], "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_13_O": { - "hide_name": 0, - "bits": [ 424, 392, 538, 545 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_15_O": { - "hide_name": 0, - "bits": [ 420, 388, 538, 547 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_1_O": { - "hide_name": 0, - "bits": [ 448, 416, 538, 541 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_3_O": { - "hide_name": 0, - "bits": [ 444, 412, 538, 549 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_5_O": { - "hide_name": 0, - "bits": [ 440, 408, 538, 551 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_7_O": { - "hide_name": 0, - "bits": [ 436, 404, 538, 553 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.int_cnt_09_SB_LUT4_I2_9_O": { - "hide_name": 0, - "bits": [ 432, 400, 538, 555 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "smi_ctrl_ins.int_cnt_24": { "hide_name": 0, - "bits": [ "1", "1", "1", "x", "x" ], + "bits": [ "1", "1", "1", 949, 947 ], "attributes": { "hdlname": "smi_ctrl_ins int_cnt_24", "src": "top.v:333.13-364.5|smi_ctrl.v:98.15-98.25" } }, + "smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_D": { + "hide_name": 0, + "bits": [ 948, 946 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "top.v:333.13-364.5|smi_ctrl.v:136.35-136.49|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27" + } + }, + "smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E": { + "hide_name": 0, + "bits": [ 58 ], + "attributes": { + } + }, "smi_ctrl_ins.o_data_out": { "hide_name": 0, - "bits": [ 559, 558, "0", "0", "0", "0", "0", "0" ], + "bits": [ 954, 953, 952, 951, "0", "0", "0", "0" ], "attributes": { "hdlname": "smi_ctrl_ins o_data_out", "src": "top.v:333.13-364.5|smi_ctrl.v:8.29-8.39" @@ -24877,38 +33536,22 @@ }, "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E": { "hide_name": 0, - "bits": [ 557 ], + "bits": [ 950 ], "attributes": { } }, - "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_S": { + "smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O": { "hide_name": 0, - "bits": [ 103, 82 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.o_data_out_SB_LUT4_I0_1_O": { - "hide_name": 0, - "bits": [ 721, 309, 313, 315, 317, 319, 321, 324 ], + "bits": [ 1165, 488, 492, 494, 496, 498, 500, 503 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:0.0-0.0|top.v:176.7-182.14|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22", "unused_bits": "0 " } }, - "smi_ctrl_ins.o_data_out_SB_LUT4_I0_I1": { + "smi_ctrl_ins.o_data_out_SB_LUT4_I0_3_O": { "hide_name": 0, - "bits": [ 559, 561, 323, 130 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "smi_ctrl_ins.o_data_out_SB_LUT4_I0_O": { - "hide_name": 0, - "bits": [ 687, 312, 563, 562 ], + "bits": [ 958, 959 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -24916,23 +33559,191 @@ }, "smi_ctrl_ins.o_smi_data_out": { "hide_name": 0, - "bits": [ 168, 167, 166, 165, 164, 163, 162, 161 ], + "bits": [ 174, 173, 172, 171, 170, 169, 168, 167 ], "attributes": { "hdlname": "smi_ctrl_ins o_smi_data_out", "src": "top.v:333.13-364.5|smi_ctrl.v:29.29-29.43" } }, - "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D": { + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D": { "hide_name": 0, - "bits": [ 548, 546, 544, 556, 554, 552, 550, 542 ], + "bits": [ 961 ], + "attributes": { + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 962, 963, 964, 60 ], "attributes": { "force_downto": "00000000000000000000000000000001", - "src": "top.v:333.13-364.5|smi_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 839, 903, 949, 965 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": 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"00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 819, 883, 949, 990 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D": { + "hide_name": 0, + "bits": [ 991 ], + "attributes": { + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 992, 993, 994, 60 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 815, 879, 949, 995 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D": { + "hide_name": 0, + "bits": [ 960 ], + "attributes": { + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0": { + "hide_name": 0, + "bits": [ 996, 997, 998, 60 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3": { + "hide_name": 0, + "bits": [ 843, 907, 949, 999 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "smi_ctrl_ins.o_smi_read_req": { "hide_name": 0, - "bits": [ "1" ], + "bits": [ 486 ], "attributes": { "hdlname": "smi_ctrl_ins o_smi_read_req", "src": "top.v:333.13-364.5|smi_ctrl.v:31.29-31.43" @@ -24956,7 +33767,7 @@ }, "smi_ctrl_ins.r_fifo_09_pull": { "hide_name": 0, - "bits": [ 566 ], + "bits": [ 1000 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_09_pull", "src": "top.v:333.13-364.5|smi_ctrl.v:99.9-99.23" @@ -24964,51 +33775,99 @@ }, "smi_ctrl_ins.r_fifo_09_pull_1": { "hide_name": 0, - "bits": [ 567 ], + "bits": [ 1001 ], "attributes": { "hdlname": "smi_ctrl_ins r_fifo_09_pull_1", "src": "top.v:333.13-364.5|smi_ctrl.v:100.9-100.25" } }, - "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_1_O": { + "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O": { "hide_name": 0, - "bits": [ 516 ], - "attributes": { - } - }, - "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O": { - "hide_name": 0, - "bits": [ 357, 358, 359, 360 ], + "bits": [ 513, 514, 515, 511 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_1_I0": { + "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I0": { "hide_name": 0, - "bits": [ 525, 572, 580, 579, 573, 578, 577, 576, 575, 574, 357 ], + "bits": [ 708, 516, 523, 524, 526, 527, 528, 530, 525, 529, 1002 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:284.17-295.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" } }, - "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I0_O_SB_LUT4_O_I0": { + "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I2": { "hide_name": 0, - "bits": [ 568, 569, 570, 571 ], + "bits": [ "0", 568, 1011, 1010, 1009, 1008, 1007, 1006, 1005, 1004, 1002 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "top.v:284.17-295.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" + } + }, + "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_1_I3": { + "hide_name": 0, + "bits": [ 527, 262, 1002, 1003 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O": { + "smi_ctrl_ins.r_fifo_24_pull": { "hide_name": 0, - "bits": [ 386 ], + "bits": [ 1013 ], "attributes": { + "hdlname": "smi_ctrl_ins r_fifo_24_pull", + "src": "top.v:333.13-364.5|smi_ctrl.v:102.9-102.23" + } + }, + "smi_ctrl_ins.r_fifo_24_pull_1": { + "hide_name": 0, + "bits": [ 1014 ], + "attributes": { + "hdlname": "smi_ctrl_ins r_fifo_24_pull_1", + "src": "top.v:333.13-364.5|smi_ctrl.v:103.9-103.25" + } + }, + "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 1016, 427, 739, 1015 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 911 ], + "attributes": { + } + }, + "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_1_O": { + "hide_name": 0, + "bits": [ 781 ], + "attributes": { + } + }, + "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_I0": { + "hide_name": 0, + "bits": [ "0", 751, 749, 747, 745, 743, 742, 740, 738, 737, 1016 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "top.v:320.17-331.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" + } + }, + "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 1018, 1019, 1020, 1017 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, "smi_ctrl_ins.soe_and_reset": { "hide_name": 0, - "bits": [ 536 ], + "bits": [ 940 ], "attributes": { "hdlname": "smi_ctrl_ins soe_and_reset", "src": "top.v:333.13-364.5|smi_ctrl.v:108.10-108.23" @@ -25016,7 +33875,7 @@ }, "smi_ctrl_ins.w_fifo_09_pull_trigger": { "hide_name": 0, - "bits": [ 581 ], + "bits": [ 1012 ], "attributes": { "hdlname": "smi_ctrl_ins w_fifo_09_pull_trigger", "src": "top.v:333.13-364.5|smi_ctrl.v:101.10-101.32" @@ -25024,20 +33883,35 @@ }, "smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_D": { "hide_name": 0, - "bits": [ 582 ], + "bits": [ 1022 ], "attributes": { "src": "top.v:333.13-364.5|smi_ctrl.v:119.39-119.79" } }, - "smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_E": { + "smi_ctrl_ins.w_fifo_24_pull_trigger": { "hide_name": 0, - "bits": [ 583 ], + "bits": [ 1021 ], + "attributes": { + "hdlname": "smi_ctrl_ins w_fifo_24_pull_trigger", + "src": "top.v:333.13-364.5|smi_ctrl.v:104.10-104.32" + } + }, + "smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_D": { + "hide_name": 0, + "bits": [ 1024 ], + "attributes": { + "src": "top.v:333.13-364.5|smi_ctrl.v:120.39-120.79" + } + }, + "smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E": { + "hide_name": 0, + "bits": [ 1023 ], "attributes": { } }, "spi_if_ins.i_data_out": { "hide_name": 0, - "bits": [ 327, 311, 314, 316, 318, 320, 322, 325 ], + "bits": [ 506, 490, 493, 495, 497, 499, 501, 504 ], "attributes": { "hdlname": "spi_if_ins i_data_out", "src": "top.v:92.11-108.5|spi_if.v:10.29-10.39" @@ -25045,7 +33919,7 @@ }, "spi_if_ins.i_rst_b": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "hdlname": "spi_if_ins i_rst_b", "src": "top.v:92.11-108.5|spi_if.v:5.29-5.36" @@ -25077,7 +33951,7 @@ }, "spi_if_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 55 ], + "bits": [ 62 ], "attributes": { "hdlname": "spi_if_ins i_sys_clk", "src": "top.v:92.11-108.5|spi_if.v:6.29-6.38" @@ -25085,7 +33959,7 @@ }, "spi_if_ins.o_cs": { "hide_name": 0, - "bits": [ 564, 67, 535, 565 ], + "bits": [ 1029, 74, 939, 1026 ], "attributes": { "hdlname": "spi_if_ins o_cs", "src": "top.v:92.11-108.5|spi_if.v:11.29-11.33" @@ -25093,29 +33967,37 @@ }, "spi_if_ins.o_cs_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ "0", "0", "0", 584, "0", "0", 534, "0", "0", 65, "0", "0" ], + "bits": [ "0", "0", "0", 1025, "0", "0", 938, "0", "0", 72, "0", "0" ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:92.11-108.5|spi_if.v:65.21-70.28|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:583.28-583.35" } }, - "spi_if_ins.o_cs_SB_LUT4_I1_1_O": { + "spi_if_ins.o_cs_SB_LUT4_I2_2_O": { "hide_name": 0, - "bits": [ 310 ], - "attributes": { - } - }, - "spi_if_ins.o_cs_SB_LUT4_I1_O": { - "hide_name": 0, - "bits": [ 323, 107 ], + "bits": [ 1124, 491, 958, 957 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, + "spi_if_ins.o_cs_SB_LUT4_I2_O": { + "hide_name": 0, + "bits": [ 953, 956, 502, 98 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "spi_if_ins.o_cs_SB_LUT4_I3_1_O": { + "hide_name": 0, + "bits": [ 489 ], + "attributes": { + } + }, "spi_if_ins.o_data_in": { "hide_name": 0, - "bits": [ 59, 56, 142, 140, 138, 136, 134, 131 ], + "bits": [ 66, 63, 148, 146, 145, 143, 141, 139 ], "attributes": { "hdlname": "spi_if_ins o_data_in", "src": "top.v:92.11-108.5|spi_if.v:9.29-9.38" @@ -25123,13 +34005,13 @@ }, "spi_if_ins.o_data_in_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 588 ], + "bits": [ 1031 ], "attributes": { } }, "spi_if_ins.o_fetch_cmd": { "hide_name": 0, - "bits": [ 560 ], + "bits": [ 117 ], "attributes": { "hdlname": "spi_if_ins o_fetch_cmd", "src": "top.v:92.11-108.5|spi_if.v:12.29-12.40" @@ -25137,19 +34019,19 @@ }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 594 ], + "bits": [ 1037 ], "attributes": { } }, "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 595 ], + "bits": [ 1038 ], "attributes": { } }, "spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 84, 85, 113, 114 ], + "bits": [ 115, 955 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25157,31 +34039,15 @@ }, "spi_if_ins.o_ioc": { "hide_name": 0, - "bits": [ 84, 86, 603, 602, 601 ], + "bits": [ 136, 135, 133, 134, 130 ], "attributes": { "hdlname": "spi_if_ins o_ioc", "src": "top.v:92.11-108.5|spi_if.v:8.29-8.34" } }, - "spi_if_ins.o_ioc_SB_LUT4_I0_O": { - "hide_name": 0, - "bits": [ 84, 85, 81, 48 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_ioc_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 86, 601, 604, 84 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, "spi_if_ins.o_load_cmd": { "hide_name": 0, - "bits": [ 606 ], + "bits": [ 1044 ], "attributes": { "hdlname": "spi_if_ins o_load_cmd", "src": "top.v:92.11-108.5|spi_if.v:13.29-13.39" @@ -25189,23 +34055,7 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 597, 607 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O": { - "hide_name": 0, - "bits": [ 598, 587, 599, 600 ], - "attributes": { - "force_downto": "00000000000000000000000000000001", - "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" - } - }, - "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O": { - "hide_name": 0, - "bits": [ 607, 608, 66 ], + "bits": [ 1047, 1040, 1048 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25213,13 +34063,13 @@ }, "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 605 ], + "bits": [ 1043 ], "attributes": { } }, "spi_if_ins.o_load_cmd_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 51, 73 ], + "bits": [ 79, 82, 57 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25227,13 +34077,13 @@ }, "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 57 ], + "bits": [ 64 ], "attributes": { } }, "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 81, 611 ], + "bits": [ 50, 1049 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25241,25 +34091,25 @@ }, "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O": { "hide_name": 0, - "bits": [ 143 ], + "bits": [ 140 ], "attributes": { } }, "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O": { "hide_name": 0, - "bits": [ 148 ], + "bits": [ 153 ], "attributes": { } }, "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 132 ], + "bits": [ 149 ], "attributes": { } }, "spi_if_ins.o_spi_miso": { "hide_name": 0, - "bits": [ 307 ], + "bits": [ 485 ], "attributes": { "hdlname": "spi_if_ins o_spi_miso", "src": "top.v:92.11-108.5|spi_if.v:17.29-17.39" @@ -25267,7 +34117,7 @@ }, "spi_if_ins.r_tx_byte": { "hide_name": 0, - "bits": [ 620, 619, 618, 617, 616, 615, 614, 613 ], + "bits": [ 1058, 1057, 1056, 1055, 1054, 1053, 1052, 1051 ], "attributes": { "hdlname": "spi_if_ins r_tx_byte", "src": "top.v:92.11-108.5|spi_if.v:32.17-32.26" @@ -25275,7 +34125,7 @@ }, "spi_if_ins.r_tx_data_valid": { "hide_name": 0, - "bits": [ 623 ], + "bits": [ 1061 ], "attributes": { "hdlname": "spi_if_ins r_tx_data_valid", "src": "top.v:92.11-108.5|spi_if.v:31.17-31.32" @@ -25283,7 +34133,7 @@ }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 607, 621 ], + "bits": [ 1048, 1059 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25291,19 +34141,19 @@ }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 612 ], + "bits": [ 1050 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 622 ], + "bits": [ 1060 ], "attributes": { } }, "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 624 ], + "bits": [ 1064, 1063, 1062 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25311,7 +34161,7 @@ }, "spi_if_ins.spi.SCKr": { "hide_name": 0, - "bits": [ 630, 628, 629 ], + "bits": [ 1065, 1063, 1064 ], "attributes": { "hdlname": "spi_if_ins spi SCKr", "src": "top.v:92.11-108.5|spi_slave.v:80.13-80.17|spi_if.v:42.15-54.6" @@ -25319,7 +34169,7 @@ }, "spi_if_ins.spi.SCKr_SB_LUT4_I0_O": { "hide_name": 0, - "bits": [ 625, 626, 624 ], + "bits": [ 1084, 1068, 1062 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25351,7 +34201,7 @@ }, "spi_if_ins.spi.i_sys_clk": { "hide_name": 0, - "bits": [ 55 ], + "bits": [ 62 ], "attributes": { "hdlname": "spi_if_ins spi i_sys_clk", "src": "top.v:92.11-108.5|spi_slave.v:5.23-5.32|spi_if.v:42.15-54.6" @@ -25359,7 +34209,7 @@ }, "spi_if_ins.spi.i_tx_byte": { "hide_name": 0, - "bits": [ 620, 619, 618, 617, 616, 615, 614, 613 ], + "bits": [ 1058, 1057, 1056, 1055, 1054, 1053, 1052, 1051 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_byte", "src": "top.v:92.11-108.5|spi_slave.v:9.23-9.32|spi_if.v:42.15-54.6" @@ -25367,7 +34217,7 @@ }, "spi_if_ins.spi.i_tx_data_valid": { "hide_name": 0, - "bits": [ 623 ], + "bits": [ 1061 ], "attributes": { "hdlname": "spi_if_ins spi i_tx_data_valid", "src": "top.v:92.11-108.5|spi_slave.v:8.23-8.38|spi_if.v:42.15-54.6" @@ -25375,7 +34225,7 @@ }, "spi_if_ins.spi.o_rx_byte": { "hide_name": 0, - "bits": [ 593, 592, 591, 590, 589, 586, 585, 587 ], + "bits": [ 1036, 1035, 1034, 1033, 1032, 1028, 1027, 1030 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_byte", "src": "top.v:92.11-108.5|spi_slave.v:7.23-7.32|spi_if.v:42.15-54.6" @@ -25383,15 +34233,23 @@ }, "spi_if_ins.spi.o_rx_data_valid": { "hide_name": 0, - "bits": [ 607 ], + "bits": [ 1048 ], "attributes": { "hdlname": "spi_if_ins spi o_rx_data_valid", "src": "top.v:92.11-108.5|spi_slave.v:6.23-6.38|spi_if.v:42.15-54.6" } }, + "spi_if_ins.spi.o_rx_data_valid_SB_LUT4_I3_O": { + "hide_name": 0, + "bits": [ 1030, 73, 1042 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "spi_if_ins.spi.o_spi_miso": { "hide_name": 0, - "bits": [ 307 ], + "bits": [ 485 ], "attributes": { "hdlname": "spi_if_ins spi o_spi_miso", "src": "top.v:92.11-108.5|spi_slave.v:13.23-13.33|spi_if.v:42.15-54.6" @@ -25399,14 +34257,14 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 642 ], + "bits": [ 1078 ], "attributes": { "src": "top.v:92.11-108.5|spi_slave.v:87.3-104.6|spi_if.v:42.15-54.6" } }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2": { "hide_name": 0, - "bits": [ 613, 644, 624 ], + "bits": [ 1051, 1080, 1062 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25414,15 +34272,15 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0": { "hide_name": 0, - "bits": [ 645, 646, 625, 647 ], + "bits": [ 1081, 1082, 1083, 1084 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0": { + "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ 652, 653, 625, 631 ], + "bits": [ 1085, 1086, 1066, 1087 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25430,13 +34288,13 @@ }, "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 643 ], + "bits": [ 1079 ], "attributes": { } }, "spi_if_ins.spi.r2_rx_done": { "hide_name": 0, - "bits": [ 659 ], + "bits": [ 1095 ], "attributes": { "hdlname": "spi_if_ins spi r2_rx_done", "src": "top.v:92.11-108.5|spi_slave.v:22.7-22.17|spi_if.v:42.15-54.6" @@ -25444,7 +34302,7 @@ }, "spi_if_ins.spi.r3_rx_done": { "hide_name": 0, - "bits": [ 660 ], + "bits": [ 1096 ], "attributes": { "hdlname": "spi_if_ins spi r3_rx_done", "src": "top.v:92.11-108.5|spi_slave.v:23.7-23.17|spi_if.v:42.15-54.6" @@ -25452,14 +34310,14 @@ }, "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O": { "hide_name": 0, - "bits": [ 634 ], + "bits": [ 1070 ], "attributes": { "src": "top.v:92.11-108.5|spi_slave.v:66.3-78.6|spi_if.v:42.15-54.6" } }, "spi_if_ins.spi.r_rx_bit_count": { "hide_name": 0, - "bits": [ 666, 664, 662 ], + "bits": [ 1102, 1100, 1098 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_bit_count", "src": "top.v:92.11-108.5|spi_slave.v:17.13-17.27|spi_if.v:42.15-54.6" @@ -25467,7 +34325,7 @@ }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D": { "hide_name": 0, - "bits": [ 665, 664, 662 ], + "bits": [ 1101, 1100, 1098 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.23-33.24" @@ -25475,7 +34333,7 @@ }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D": { "hide_name": 0, - "bits": [ 665, 663, 661 ], + "bits": [ 1101, 1099, 1097 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" @@ -25483,7 +34341,7 @@ }, "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ "0", 666, 667 ], + "bits": [ "0", 1102, 1103 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" @@ -25491,7 +34349,7 @@ }, "spi_if_ins.spi.r_rx_byte": { "hide_name": 0, - "bits": [ 641, 640, 639, 638, 637, 636, 635, 633 ], + "bits": [ 1077, 1076, 1075, 1074, 1073, 1072, 1071, 1069 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_byte", "src": "top.v:92.11-108.5|spi_slave.v:20.13-20.22|spi_if.v:42.15-54.6" @@ -25499,7 +34357,7 @@ }, "spi_if_ins.spi.r_rx_done": { "hide_name": 0, - "bits": [ 658 ], + "bits": [ 1094 ], "attributes": { "hdlname": "spi_if_ins spi r_rx_done", "src": "top.v:92.11-108.5|spi_slave.v:21.7-21.16|spi_if.v:42.15-54.6" @@ -25507,7 +34365,7 @@ }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 45, 676 ], + "bits": [ 45, 1112 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25515,19 +34373,19 @@ }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O": { "hide_name": 0, - "bits": [ 669 ], + "bits": [ 1105 ], "attributes": { } }, "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 677 ], + "bits": [ 1113 ], "attributes": { } }, "spi_if_ins.spi.r_temp_rx_byte": { "hide_name": 0, - "bits": [ 675, 674, 673, 672, 671, 670, 668, "x" ], + "bits": [ 1111, 1110, 1109, 1108, 1107, 1106, 1104, "x" ], "attributes": { "hdlname": "spi_if_ins spi r_temp_rx_byte", "src": "top.v:92.11-108.5|spi_slave.v:19.13-19.27|spi_if.v:42.15-54.6" @@ -25535,7 +34393,7 @@ }, "spi_if_ins.spi.r_tx_bit_count": { "hide_name": 0, - "bits": [ 631, 625, 632 ], + "bits": [ 1066, 1084, 1067 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_bit_count", "src": "top.v:92.11-108.5|spi_slave.v:18.13-18.27|spi_if.v:42.15-54.6" @@ -25543,7 +34401,7 @@ }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 678, 682, 681 ], + "bits": [ 1114, 1118, 1117 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:92.11-108.5|spi_slave.v:95.27-95.45|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" @@ -25551,7 +34409,7 @@ }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ "1", 631, 680 ], + "bits": [ "1", 1066, 1116 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:92.11-108.5|spi_slave.v:95.27-95.45|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" @@ -25559,13 +34417,13 @@ }, "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 679 ], + "bits": [ 1115 ], "attributes": { } }, "spi_if_ins.spi.r_tx_byte": { "hide_name": 0, - "bits": [ 656, 654, 648, 650, 657, 655, 649, 651 ], + "bits": [ 1085, 1092, 1088, 1090, 1086, 1093, 1089, 1091 ], "attributes": { "hdlname": "spi_if_ins spi r_tx_byte", "src": "top.v:92.11-108.5|spi_slave.v:24.13-24.22|spi_if.v:42.15-54.6" @@ -25573,13 +34431,13 @@ }, "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 627 ], + "bits": [ 1119 ], "attributes": { } }, "spi_if_ins.state_if": { "hide_name": 0, - "bits": [ 609, 610, 598 ], + "bits": [ 1046, 1045, 1041 ], "attributes": { "hdlname": "spi_if_ins state_if", "src": "top.v:92.11-108.5|spi_if.v:28.17-28.25" @@ -25587,7 +34445,7 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 683, 587, 608, 607 ], + "bits": [ 1120, 1030, 1047, 1048 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" @@ -25595,26 +34453,26 @@ }, "spi_if_ins.state_if_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 596 ], + "bits": [ 1039 ], "attributes": { } }, "spi_if_ins.state_if_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 685 ], + "bits": [ 1122 ], "attributes": { "src": "top.v:92.11-108.5|spi_if.v:56.5-111.8" } }, "spi_if_ins.state_if_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 684 ], + "bits": [ 1121 ], "attributes": { } }, "spi_if_ins.w_rx_data": { "hide_name": 0, - "bits": [ 593, 592, 591, 590, 589, 586, 585, 587 ], + "bits": [ 1036, 1035, 1034, 1033, 1032, 1028, 1027, 1030 ], "attributes": { "hdlname": "spi_if_ins w_rx_data", "src": "top.v:92.11-108.5|spi_if.v:30.17-30.26" @@ -25622,7 +34480,7 @@ }, "spi_if_ins.w_rx_data_valid": { "hide_name": 0, - "bits": [ 607 ], + "bits": [ 1048 ], "attributes": { "hdlname": "spi_if_ins w_rx_data_valid", "src": "top.v:92.11-108.5|spi_if.v:29.17-29.32" @@ -25630,7 +34488,7 @@ }, "sys_ctrl_ins.i_cs": { "hide_name": 0, - "bits": [ 564 ], + "bits": [ 1029 ], "attributes": { "hdlname": "sys_ctrl_ins i_cs", "src": "top.v:113.13-126.5|sys_ctrl.v:9.29-9.33" @@ -25638,7 +34496,7 @@ }, "sys_ctrl_ins.i_cs_SB_DFFE_Q_D": { "hide_name": 0, - "bits": [ 68, 722, 723, 724 ], + "bits": [ 75, 1166, 1167, 1168 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:92.11-108.5|spi_if.v:65.21-70.28|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22", @@ -25647,7 +34505,7 @@ }, "sys_ctrl_ins.i_data_in": { "hide_name": 0, - "bits": [ 59, 56, 142, 140, 138, 136, 134, 131 ], + "bits": [ 66, 63, 148, 146, 145, 143, 141, 139 ], "attributes": { "hdlname": "sys_ctrl_ins i_data_in", "src": "top.v:113.13-126.5|sys_ctrl.v:7.29-7.38" @@ -25663,7 +34521,7 @@ }, "sys_ctrl_ins.i_fetch_cmd": { "hide_name": 0, - "bits": [ 560 ], + "bits": [ 117 ], "attributes": { "hdlname": "sys_ctrl_ins i_fetch_cmd", "src": "top.v:113.13-126.5|sys_ctrl.v:10.29-10.40" @@ -25671,7 +34529,7 @@ }, "sys_ctrl_ins.i_ioc": { "hide_name": 0, - "bits": [ 84, 86, 603, 602, 601 ], + "bits": [ 136, 135, 133, 134, 130 ], "attributes": { "hdlname": "sys_ctrl_ins i_ioc", "src": "top.v:113.13-126.5|sys_ctrl.v:6.29-6.34" @@ -25679,7 +34537,7 @@ }, "sys_ctrl_ins.i_load_cmd": { "hide_name": 0, - "bits": [ 606 ], + "bits": [ 1044 ], "attributes": { "hdlname": "sys_ctrl_ins i_load_cmd", "src": "top.v:113.13-126.5|sys_ctrl.v:11.29-11.39" @@ -25695,7 +34553,7 @@ }, "sys_ctrl_ins.i_sys_clk": { "hide_name": 0, - "bits": [ 55 ], + "bits": [ 62 ], "attributes": { "hdlname": "sys_ctrl_ins i_sys_clk", "src": "top.v:113.13-126.5|sys_ctrl.v:4.29-4.38" @@ -25703,29 +34561,29 @@ }, "sys_ctrl_ins.o_data_out": { "hide_name": 0, - "bits": [ 687, "0", "0", "0", "0", "0", "0", "0" ], + "bits": [ 1124, "0", "0", "0", "0", "0", "0", "0" ], "attributes": { "hdlname": "sys_ctrl_ins o_data_out", "src": "top.v:113.13-126.5|sys_ctrl.v:8.29-8.39" } }, - "sys_ctrl_ins.o_data_out_SB_DFFE_Q_D": { + "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E": { "hide_name": 0, - "bits": [ 81, 48, 79 ], + "bits": [ 1123 ], + "attributes": { + } + }, + "sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2": { + "hide_name": 0, + "bits": [ 502, 129, 958 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" } }, - "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E": { - "hide_name": 0, - "bits": [ 686 ], - "attributes": { - } - }, "sys_ctrl_ins.o_soft_reset": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "hdlname": "sys_ctrl_ins o_soft_reset", "src": "top.v:113.13-126.5|sys_ctrl.v:13.29-13.41" @@ -25733,13 +34591,13 @@ }, "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E": { "hide_name": 0, - "bits": [ 688 ], + "bits": [ 1125 ], "attributes": { } }, "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S": { "hide_name": 0, - "bits": [ 689 ], + "bits": [ 1126 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:113.13-126.5|sys_ctrl.v:72.17-72.36|/usr/local/bin/../share/yosys/cmp2lut.v:24.22-24.23" @@ -25747,7 +34605,7 @@ }, "sys_ctrl_ins.reset_cmd": { "hide_name": 0, - "bits": [ 690 ], + "bits": [ 1127 ], "attributes": { "hdlname": "sys_ctrl_ins reset_cmd", "src": "top.v:113.13-126.5|sys_ctrl.v:35.9-35.18" @@ -25755,19 +34613,19 @@ }, "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 695 ], + "bits": [ 1132 ], "attributes": { } }, "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R": { "hide_name": 0, - "bits": [ 696 ], + "bits": [ 1133 ], "attributes": { } }, "sys_ctrl_ins.reset_count": { "hide_name": 0, - "bits": [ 694, 692, 693, 691 ], + "bits": [ 1131, 1129, 1130, 1128 ], "attributes": { "hdlname": "sys_ctrl_ins reset_count", "src": "top.v:113.13-126.5|sys_ctrl.v:34.15-34.26" @@ -25775,31 +34633,31 @@ }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_1_D": { "hide_name": 0, - "bits": [ 699 ], + "bits": [ 1136 ], "attributes": { } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_2_D": { "hide_name": 0, - "bits": [ 701 ], + "bits": [ 1138 ], "attributes": { } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_3_D": { "hide_name": 0, - "bits": [ 702 ], + "bits": [ 1139 ], "attributes": { } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D": { "hide_name": 0, - "bits": [ 697 ], + "bits": [ 1135 ], "attributes": { } }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": { "hide_name": 0, - "bits": [ "0", 694, 700, 703 ], + "bits": [ "0", 1131, 1137, 1140 ], "attributes": { "force_downto": "00000000000000000000000000000001", "src": "top.v:113.13-126.5|sys_ctrl.v:73.32-73.50|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" @@ -25807,125 +34665,176 @@ }, "sys_ctrl_ins.reset_count_SB_DFFESR_Q_E": { "hide_name": 0, - "bits": [ 698 ], + "bits": [ 1134 ], "attributes": { } }, "w_clock_sys": { "hide_name": 0, - "bits": [ 55 ], + "bits": [ 62 ], "attributes": { "src": "top.v:67.16-67.27" } }, "w_cs": { "hide_name": 0, - "bits": [ 564, 67, 535, 565 ], + "bits": [ 1029, 74, 939, 1026 ], "attributes": { "src": "top.v:71.16-71.20" } }, "w_fetch": { "hide_name": 0, - "bits": [ 560 ], + "bits": [ 117 ], "attributes": { "src": "top.v:72.16-72.23" } }, "w_ioc": { "hide_name": 0, - "bits": [ 84, 86, 603, 602, 601 ], + "bits": [ 136, 135, 133, 134, 130 ], "attributes": { "src": "top.v:68.16-68.21" } }, "w_load": { "hide_name": 0, - "bits": [ 606 ], + "bits": [ 1044 ], "attributes": { "src": "top.v:73.16-73.22" } }, "w_lvds_rx_09_d0": { "hide_name": 0, - "bits": [ 170 ], + "bits": [ 176 ], "attributes": { "src": "top.v:238.9-238.24" } }, "w_lvds_rx_09_d1": { "hide_name": 0, - "bits": [ 169 ], + "bits": [ 175 ], "attributes": { "src": "top.v:239.9-239.24" } }, + "w_lvds_rx_09_d1_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 57, 328, 283 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, + "w_lvds_rx_24_d0": { + "hide_name": 0, + "bits": [ 178 ], + "attributes": { + "src": "top.v:240.9-240.24" + } + }, + "w_lvds_rx_24_d1": { + "hide_name": 0, + "bits": [ 179 ], + "attributes": { + "src": "top.v:241.9-241.24" + } + }, + "w_lvds_rx_24_d1_SB_LUT4_I1_O": { + "hide_name": 0, + "bits": [ 57, 477, 432 ], + "attributes": { + "force_downto": "00000000000000000000000000000001", + "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" + } + }, "w_rx_09_fifo_data": { "hide_name": 0, - "bits": [ 224, 222, 218, 216, 214, 212, 210, 208, 206, 204, 202, 200, 196, 194, 192, 190, 188, 186, 184, 182, 180, 178, 236, 234, 232, 230, 228, 226, 220, 198, 176, 174 ], + "bits": [ 230, 229, 226, 224, 222, 220, 218, 216, 214, 212, 210, 208, 204, 202, 200, 198, 196, 194, 192, 190, 188, 186, 242, 240, 238, 236, 234, 232, 228, 206, 184, 182 ], "attributes": { "src": "top.v:247.16-247.33" } }, "w_rx_09_fifo_empty": { "hide_name": 0, - "bits": [ 329 ], + "bits": [ 508 ], "attributes": { "src": "top.v:244.9-244.27" } }, "w_rx_09_fifo_full": { "hide_name": 0, - "bits": [ 302 ], + "bits": [ 331 ], "attributes": { "src": "top.v:243.9-243.26" } }, "w_rx_09_fifo_pulled_data": { "hide_name": 0, - "bits": [ 420, 424, 428, 432, 436, 440, 444, 448, 388, 392, 396, 400, 404, 408, 412, 416, 484, 488, 492, 496, 500, 504, 508, 512, 452, 456, 460, 464, 468, 472, 476, 480 ], + "bits": [ 603, 607, 611, 615, 619, 623, 627, 631, 571, 575, 579, 583, 587, 591, 595, 599, 667, 671, 675, 679, 683, 687, 691, 695, 635, 639, 643, 647, 651, 655, 659, 663 ], "attributes": { "src": "top.v:249.16-249.40" } }, "w_rx_09_fifo_push": { "hide_name": 0, - "bits": [ 238 ], + "bits": [ 244 ], "attributes": { "src": "top.v:246.9-246.26" } }, "w_rx_09_fifo_write_clk": { "hide_name": 0, - "bits": [ 171 ], + "bits": [ 177 ], "attributes": { "src": "top.v:245.9-245.31" } }, + "w_rx_24_fifo_data": { + "hide_name": 0, + "bits": [ 386, 385, 382, 380, 378, 376, 374, 372, 370, 368, 366, 364, 360, 358, 356, 354, 352, 350, 348, 346, 344, 342, 398, 396, 394, 392, 390, 388, 384, 362, 340, 338 ], + "attributes": { + "src": "top.v:255.16-255.33" + } + }, "w_rx_24_fifo_empty": { "hide_name": 0, - "bits": [ "x" ], + "bits": [ 718 ], "attributes": { "src": "top.v:252.9-252.27" } }, "w_rx_24_fifo_full": { "hide_name": 0, - "bits": [ "x" ], + "bits": [ 480 ], "attributes": { "src": "top.v:251.9-251.26" } }, "w_rx_24_fifo_pulled_data": { "hide_name": 0, - "bits": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], + "bits": [ 815, 819, 823, 827, 831, 835, 839, 843, 783, 787, 791, 795, 799, 803, 807, 811, 879, 883, 887, 891, 895, 899, 903, 907, 847, 851, 855, 859, 863, 867, 871, 875 ], "attributes": { "src": "top.v:257.16-257.40" } }, + "w_rx_24_fifo_push": { + "hide_name": 0, + "bits": [ 400 ], + "attributes": { + "src": "top.v:254.9-254.26" + } + }, + "w_rx_24_fifo_write_clk": { + "hide_name": 0, + "bits": [ 177 ], + "attributes": { + "src": "top.v:253.9-253.31" + } + }, "w_rx_data": { "hide_name": 0, - "bits": [ 59, 56, 142, 140, 138, 136, 134, 131 ], + "bits": [ 66, 63, 148, 146, 145, 143, 141, 139 ], "attributes": { "src": "top.v:69.16-69.25" } @@ -25947,14 +34856,14 @@ }, "w_smi_data_output": { "hide_name": 0, - "bits": [ 168, 167, 166, 165, 164, 163, 162, 161 ], + "bits": [ 174, 173, 172, 171, 170, 169, 168, 167 ], "attributes": { "src": "top.v:367.15-367.32" } }, "w_smi_read_req": { "hide_name": 0, - "bits": [ "1" ], + "bits": [ 486 ], "attributes": { "src": "top.v:369.9-369.23" } @@ -25982,27 +34891,27 @@ }, "w_soft_reset": { "hide_name": 0, - "bits": [ 51 ], + "bits": [ 57 ], "attributes": { "src": "top.v:75.16-75.28" } }, "w_tx_data_io": { "hide_name": 0, - "bits": [ 130, 116, 98, 119, 123, 102, 107, 111 ], + "bits": [ 138, 98, 109, 101, 106, 120, 125, 129 ], "attributes": { "src": "top.v:78.16-78.28" } }, "w_tx_data_smi": { "hide_name": 0, - "bits": [ 559, 558, "0", "0" ], + "bits": [ 954, 953, 952, 951 ], "attributes": { } }, "w_tx_data_sys": { "hide_name": 0, - "bits": [ 687, "0", "0", "0", "0", "0", "0", "0" ], + "bits": [ 1124, "0", "0", "0", "0", "0", "0", "0" ], "attributes": { "src": "top.v:77.16-77.29" } diff --git a/software/libcariboulite/src/caribou_smi/caribou_smi.c b/software/libcariboulite/src/caribou_smi/caribou_smi.c index 199ecce..483e274 100644 --- a/software/libcariboulite/src/caribou_smi/caribou_smi.c +++ b/software/libcariboulite/src/caribou_smi/caribou_smi.c @@ -45,6 +45,87 @@ static void caribou_smi_print_smi_settings(caribou_smi_st* dev, struct smi_setti static void caribou_smi_setup_settings (caribou_smi_st* dev, struct smi_settings *settings); static void caribou_smi_init_stream(caribou_smi_st* dev, caribou_smi_stream_type_en type, caribou_smi_channel_en ch); + +#define TIMING_PERF_SYNC (0) + +#if (TIMING_PERF_SYNC) + #define TIMING_PERF_SYNC_VARS \ + struct timeval tv_pre = {0}; \ + struct timeval tv_post = {0}; \ + long long total_samples = 0,last_total_samples = 0; \ + double time_pre = 0, batch_time = 0, sample_rate = 0; \ + double time_post = 0, process_time = 0; \ + double temp_pre; \ + double num_samples = 0, num_samples_avg = 0; + + #define TIMING_PERF_SYNC_TICK \ + gettimeofday(&tv_pre, NULL); + + #define TIMING_PERF_SYNC_TOCK \ + gettimeofday(&tv_post, NULL); \ + num_samples = (double)(st->read_ret_value) / 4.0; \ + num_samples_avg = num_samples_avg*0.1 + num_samples*0.9; \ + temp_pre = tv_pre.tv_sec + ((double)(tv_pre.tv_usec)) / 1e6; \ + time_post = tv_post.tv_sec + ((double)(tv_post.tv_usec)) / 1e6; \ + batch_time = temp_pre - time_pre; \ + sample_rate = sample_rate*0.1 + (num_samples / batch_time) * 0.9; \ + process_time = process_time*0.1 + (time_post - temp_pre)*0.9; \ + time_pre = temp_pre; \ + total_samples += st->read_ret_value; \ + if ((total_samples - last_total_samples) > 4000000*4) \ + { \ + last_total_samples = total_samples; \ + ZF_LOGD("sample_rate = %.2f SPS, process_time = %.2f usec" \ + ", num_samples_avg = %.1f", \ + sample_rate, process_time * 1e6, num_samples_avg); \ + } +#else + #define TIMING_PERF_SYNC_VARS + #define TIMING_PERF_SYNC_TICK + #define TIMING_PERF_SYNC_TOCK +#endif + +//========================================================================= +void dump_hex(const void* data, size_t size) +{ + char ascii[17]; + size_t i, j; + ascii[16] = '\0'; + + for (i = 0; i < size; ++i) { + printf("%02X ", ((unsigned char*)data)[i]); + if (((unsigned char*)data)[i] >= ' ' && ((unsigned char*)data)[i] <= '~') + { + ascii[i % 16] = ((unsigned char*)data)[i]; + } + else + { + ascii[i % 16] = '.'; + } + if ((i+1) % 8 == 0 || i+1 == size) + { + printf(" "); + if ((i+1) % 16 == 0) + { + printf("| %s \n", ascii); + } + else if (i+1 == size) + { + ascii[(i+1) % 16] = '\0'; + if ((i+1) % 16 <= 8) + { + printf(" "); + } + for (j = (i+1) % 16; j < 16; ++j) + { + printf(" "); + } + printf("| %s \n", ascii); + } + } + } +} + //========================================================================= char* caribou_smi_get_error_string(caribou_smi_error_en err) { @@ -131,49 +212,6 @@ int caribou_smi_close (caribou_smi_st* dev) return 0; } -//========================================================================= -int caribou_smi_read_async( - caribou_smi_st* dev, - caribou_smi_address_en source, - char* buffer, - int size_of_buf, - struct aiocb *read_aiocb) -{ - // set the address - if (source > 0 && CARIBOU_SMI_READ_ADDR(source)) - { - if (source != dev->current_address) - { - int ret = ioctl(dev->filedesc, BCM2835_SMI_IOC_ADDRESS, source); - if (ret != 0) - { - ZF_LOGE("failed setting smi address (idle / %d) to device", source); - return -1; - } - printf("Set address to %d\n", source); - dev->current_address = source; - } - } - else - { - ZF_LOGE("the specified address is not a read address (%d)", source); - return -1; - } - - bzero((char *)read_aiocb, sizeof(struct aiocb)); - read_aiocb->aio_buf = buffer; - read_aiocb->aio_fildes = dev->filedesc; - read_aiocb->aio_nbytes = size_of_buf; - read_aiocb->aio_offset = 0; - int ret = aio_read(read_aiocb); - if (ret < 0) - { - printf("aio_read failed!!\n"); - return -1; - } - return 0; -} - //========================================================================= int caribou_smi_timeout_read(caribou_smi_st* dev, caribou_smi_address_en source, @@ -348,6 +386,7 @@ static void set_realtime_priority(int priority_deter) ZF_LOGI("Thread priority is %d", params.sched_priority); } +//========================================================================= int caribou_smi_search_offset(uint8_t *buff, int len) { bool succ = false; @@ -365,24 +404,131 @@ int caribou_smi_search_offset(uint8_t *buff, int len) } //========================================================================= -#define TIMING_PERF_SYNC (0) +/*void caribou_smi_convert_data(uint8_t *buffer, + size_t length_bytes, + caribou_smi_sample_complex_int16* cmplx_vec, + caribou_smi_sample_meta* meta_vec) +{ + static bool ptr = true; + + // the verilog struct looks as follows: + // [ 31:30 ] [ 29:28 ] [ 27:15 ] [ 14 ] [ 13:1 ] [ 0 ] + // [always "11"] [ CNT 2Bits ] [ I sample ] [ SYNC1 ] [ Q sample ] [ SYNC2 ] + + uint32_t *samples = (uint32_t*)buffer; + //uint32_t cnt_gaps = 0; + int num_sync_errors = 0; + + if (ptr) + { + dump_hex(buffer, 64); + for (int k = 0; k < 8; k ++) + { + + printf("0x%08X, \n", __builtin_bswap32(samples[k])); + } + //ptr = false; + } + + for (unsigned int i = 0; i < length_bytes/4; i++) + { + uint32_t s = __builtin_bswap32(samples[i]); + + meta_vec[i].sync2 = s & 0x00000001; s >>= 1; + cmplx_vec[i].q = s & 0x00001FFF; s >>= 13; + meta_vec[i].sync1 = s & 0x00000001; s >>= 1; + cmplx_vec[i].i = s & 0x00001FFF; s >>= 13; + meta_vec[i].cnt = s & 0x00000003; s >>= 2; + if (s != 0x3) + { + num_sync_errors++; + } + + if (cmplx_vec[i].i >= (int16_t)0x1000) cmplx_vec[i].i -= (int16_t)0x2000; + if (cmplx_vec[i].q >= (int16_t)0x1000) cmplx_vec[i].q -= (int16_t)0x2000; + + // TODO: calculate the cnt gaps + } + + if (ptr) + { + for (int k = 0; k < 64; k ++) + { + printf("(%d, %d), sync = [%d,%d]\n", cmplx_vec[k].i, cmplx_vec[k].q, meta_vec[k].sync1, meta_vec[k].sync2); + } + ptr = false; + } + + //if (num_sync_errors) printf("caribou_smi_convert_data: sync errors @ %d samples\n", num_sync_errors); +}*/ + +void caribou_smi_convert_data(uint8_t *buffer, + size_t length_bytes, + caribou_smi_sample_complex_int16* cmplx_vec, + caribou_smi_sample_meta* meta_vec) +{ + static bool ptr = true; + + // the verilog struct looks as follows: + // [31:30] [ 29:17 ] [ 16 ] [ 15:14 ] [ 13:1 ] [ 0 ] + // [ '00'] [ I sample ] [ '0' ] [ '01' ] [ Q sample ] [ '0' ] + + uint32_t *samples = (uint32_t*)buffer; + //uint32_t cnt_gaps = 0; + int num_sync_errors = 0; + + if (ptr) + { + printf("got byte array with %d bytes\n", length_bytes); + dump_hex(buffer, 64); + for (int k = 0; k < 8; k ++) + { + + printf("0x%08X, \n", (samples[k])); + } + //ptr = false; + } + + for (unsigned int i = 0; i < length_bytes/4; i++) + { + uint32_t s = (samples[i]); + + /*meta_vec[i].sync2 = s & 0x00000001; */s >>= 1; + cmplx_vec[i].q = s & 0x00001FFF; s >>= 13; + s >>= 2; + /*meta_vec[i].sync1 = s & 0x00000001; */s >>= 1; + cmplx_vec[i].i = s & 0x00001FFF; s >>= 13; + //meta_vec[i].cnt = s & 0x00000003; s >>= 2; + if (s != 0x0) + { + num_sync_errors++; + } + + if (cmplx_vec[i].i >= (int16_t)0x1000) cmplx_vec[i].i -= (int16_t)0x2000; + if (cmplx_vec[i].q >= (int16_t)0x1000) cmplx_vec[i].q -= (int16_t)0x2000; + + // TODO: calculate the cnt gaps + } + + if (ptr) + { + for (int k = 0; k < 64; k ++) + { + printf("(%d, %d), sync = [%d,%d]\n", cmplx_vec[k].i, cmplx_vec[k].q, meta_vec[k].sync1, meta_vec[k].sync2); + } + ptr = false; + } + + //if (num_sync_errors) printf("caribou_smi_convert_data: sync errors @ %d samples\n", num_sync_errors); +} + +//========================================================================= void* caribou_smi_analyze_thread(void* arg) { //static int a = 0; int current_data_size = 0; pthread_t tid = pthread_self(); - - // -------------------------------------------- - // TIMING PERF VARIABLES - #if (TIMING_PERF_SYNC) - struct timeval tv_pre = {0}; - struct timeval tv_post = {0}; - long long total_samples = 0; - double time_pre = 0, batch_time = 0, sample_rate = 0; - double time_post = 0, process_time = 0; - double temp_pre; - double num_samples = 0, num_samples_avg = 0; - #endif // TIMING_PERF_SYNC + TIMING_PERF_SYNC_VARS; caribou_smi_stream_st* st = (caribou_smi_stream_st*)arg; caribou_smi_st* dev = (caribou_smi_st*)st->parent_dev; @@ -393,56 +539,36 @@ void* caribou_smi_analyze_thread(void* arg) set_realtime_priority(2); int offset = 0; + // **************************************** + // MAIN LOOP + // **************************************** while (st->read_analysis_thread_running) { pthread_mutex_lock(&st->read_analysis_lock); - - #if (TIMING_PERF_SYNC) - gettimeofday(&tv_pre, NULL); - #endif - + TIMING_PERF_SYNC_TICK; if (!st->read_analysis_thread_running) break; - offset = caribou_smi_search_offset(st->current_app_buffer, 16); + /*offset = caribou_smi_search_offset(st->current_app_buffer, 16); if (offset == -1) { ZF_LOGE("Offset error!"); - for (int i = 0; i < 60; i+=4) - { - printf("%08X\n", *((uint32_t*)(st->current_app_buffer + i))); - } - } + dump_hex(st->current_app_buffer, 60); + }*/ current_data_size = st->read_ret_value; - if (offset != 0) current_data_size -= 4; + //if (offset != 0) current_data_size -= 4; - if (st->data_cb) st->data_cb(dev->cb_context, - st->service_context, - type, - ch, - current_data_size, - st->current_app_buffer + offset, - st->batch_length); + caribou_smi_convert_data(st->current_app_buffer + offset, + current_data_size, + st->app_cmplx_vec, + st->app_meta_vec); + + if (st->data_cb) st->data_cb(dev->cb_context, st->service_context, type, ch, + current_data_size / 4, + st->app_cmplx_vec, + st->app_meta_vec, + st->batch_length / 4); - #if (TIMING_PERF_SYNC) - gettimeofday(&tv_post, NULL); - - // benchmarking - num_samples = (double)(st->read_ret_value) / 4.0; - num_samples_avg = num_samples_avg*0.1 + num_samples*0.9; - temp_pre = tv_pre.tv_sec + ((double)(tv_pre.tv_usec)) / 1e6; - time_post = tv_post.tv_sec + ((double)(tv_post.tv_usec)) / 1e6; - - batch_time = temp_pre - time_pre; - sample_rate = sample_rate*0.1 + (num_samples / batch_time) * 0.9; - process_time = process_time*0.1 + (time_post - temp_pre)*0.9; - - time_pre = temp_pre; - total_samples += st->read_ret_value; - if (total_samples % (4*4000000) == 0) - { - printf("sample_rate = %.2f SPS, process_time = %.2f usec, num_samples_avg = %.1f\n", sample_rate, process_time * 1e6, num_samples_avg); - } - #endif + TIMING_PERF_SYNC_TOCK; } ZF_LOGD("Leaving SMI analysis thread id %lu, running = %d", tid, st->read_analysis_thread_running); @@ -452,24 +578,11 @@ void* caribou_smi_analyze_thread(void* arg) //========================================================================= void* caribou_smi_thread(void *arg) { - // -------------------------------------------- - // TIMING PERF VARIABLES - #if (TIMING_PERF_SYNC) - struct timeval tv_pre = {0}; - struct timeval tv_post = {0}; - long long total_samples = 0; - long long last_total_samples = 0; - double time_pre = 0, batch_time = 0, sample_rate = 0; - double time_post = 0, process_time = 0; - double temp_pre; - double num_samples = 0, num_samples_avg = 0; - #endif // TIMING_PERF_SYNC - // -------------------------------------------- + TIMING_PERF_SYNC_VARS; pthread_t tid = pthread_self(); caribou_smi_stream_st* st = (caribou_smi_stream_st*)arg; caribou_smi_st* dev = (caribou_smi_st*)st->parent_dev; - //caribou_smi_stream_type_en type = (caribou_smi_stream_type_en)(st->stream_id>>1 & 0x1); caribou_smi_channel_en ch = (caribou_smi_channel_en)(st->stream_id & 0x1); ZF_LOGD("Entered thread id %lu, running = %d, Perf-Verbosity = %d", tid, st->running, TIMING_PERF_SYNC); @@ -498,13 +611,11 @@ void* caribou_smi_thread(void *arg) // start thread notification if (st->data_cb != NULL) st->data_cb(dev->cb_context, st->service_context, - caribou_smi_stream_start, - ch, - 0, - st->current_app_buffer, - st->batch_length); + caribou_smi_stream_start, ch, 0, NULL, NULL, 0); - // thread main loop + // **************************************** + // MAIN LOOP + // **************************************** while (st->active) { if (!st->running) @@ -513,12 +624,7 @@ void* caribou_smi_thread(void *arg) continue; } - // -------------------------------------------- - // TIMING PERF - #if (TIMING_PERF_SYNC) - gettimeofday(&tv_pre, NULL); - #endif // TIMING_PERF_SYNC - // -------------------------------------------- + TIMING_PERF_SYNC_TICK; int ret = caribou_smi_timeout_read(dev, st->addr, (char*)st->current_smi_buffer, st->batch_length, 200); if (ret < 0) @@ -546,30 +652,7 @@ void* caribou_smi_thread(void *arg) if (st->current_smi_buffer_index >= (int)(st->num_of_buffers)) st->current_smi_buffer_index = 0; st->current_smi_buffer = st->buffers[st->current_smi_buffer_index]; - // -------------------------------------------- - // TIMING PERF - #if (TIMING_PERF_SYNC) - gettimeofday(&tv_post, NULL); - num_samples = (double)(st->read_ret_value) / 4.0; - num_samples_avg = num_samples_avg*0.1 + num_samples*0.9; - temp_pre = tv_pre.tv_sec + ((double)(tv_pre.tv_usec)) / 1e6; - time_post = tv_post.tv_sec + ((double)(tv_post.tv_usec)) / 1e6; - - batch_time = temp_pre - time_pre; - sample_rate = sample_rate*0.1 + (num_samples / batch_time) * 0.9; - process_time = process_time*0.1 + (time_post - temp_pre)*0.9; - - time_pre = temp_pre; - total_samples += st->read_ret_value; - if ((total_samples - last_total_samples) > 4000000*4) - { - last_total_samples = total_samples; - ZF_LOGD("sample_rate = %.2f SPS, process_time = %.2f usec" - ", num_samples_avg = %.1f", - sample_rate, process_time * 1e6, num_samples_avg); - } - #endif // TIMING_PERF_SYNC - // -------------------------------------------- + TIMING_PERF_SYNC_TOCK; } st->read_analysis_thread_running = 0; @@ -578,153 +661,14 @@ void* caribou_smi_thread(void *arg) pthread_mutex_destroy(&st->read_analysis_lock); // exit thread notification - if (st->data_cb != NULL) st->data_cb(dev->cb_context, - st->service_context, - caribou_smi_stream_end, - (caribou_smi_channel_en)(st->stream_id>>1), - 0, - st->current_app_buffer, - st->batch_length); + if (st->data_cb != NULL) st->data_cb(dev->cb_context, st->service_context, + caribou_smi_stream_end, (caribou_smi_channel_en)(st->stream_id>>1), + 0, NULL, NULL, 0); ZF_LOGD("Leaving thread id %lu", tid); return NULL; } -/*#define TIMING_PERF_ASYNC (1) -//========================================================================= -void* caribou_smi_thread_async(void *arg) -{ - // -------------------------------------------- - // TIMING PERF VARIABLES - #if (TIMING_PERF_ASYNC) - struct timeval tv_pre = {0}; - struct timeval tv_post = {0}; - long long total_samples = 0; - double time_pre = 0, batch_time = 0, sample_rate = 0; - double time_post = 0, process_time = 0; - double temp_pre; - double num_samples = 0, num_samples_avg = 0; - #endif // TIMING_PERF_ASYNC - // -------------------------------------------- - - pthread_t tid = pthread_self(); - struct aiocb read_aiocb = {0}; - caribou_smi_stream_st* st = (caribou_smi_stream_st*)arg; - caribou_smi_st* dev = (caribou_smi_st*)st->parent_dev; - caribou_smi_stream_type_en type = (caribou_smi_stream_type_en)(st->stream_id>>1 & 0x1); - caribou_smi_channel_en ch = (caribou_smi_channel_en)(st->stream_id & 0x1); - - ZF_LOGD("Entered thread id %lu, running = %d", tid, st->running); - set_realtime_priority(0); - - st->active = 1; - - // start thread notification - if (st->data_cb != NULL) st->data_cb(dev->cb_context, st->service_context, - caribou_smi_stream_start, - ch, - 0, - st->current_app_buffer, - st->batch_length); - - // ------------------------------- - // THREAD MAIN LOOP - // ------------------------------- - while (st->active) - { - if (!st->running) - { - usleep(1000); - continue; - } - - // -------------------------------------------- - // TIMING PERF - #if (TIMING_PERF_ASYNC) - gettimeofday(&tv_pre, NULL); - #endif // TIMING_PERF_ASYNC - // -------------------------------------------- - - // Run the async read - // This operation doesn't block and returns immediatelly - // in the meantime we do other stuff and some back - // to get the results later. - int ret = caribou_smi_read_async(dev, st->addr, - (char*)st->current_smi_buffer, - st->batch_length, - &read_aiocb); - - if (ret < 0) - { - ZF_LOGE("async read failed"); - if (dev->error_cb) dev->error_cb(dev->cb_context, st->stream_id & 0x1, caribou_smi_error_read_failed); - break; - } - - // analyze the last buffer that was accepted - if (st->current_app_buffer) - { - if (st->data_cb) st->data_cb(dev->cb_context, - st->service_context, - type, - ch, - st->read_ret_value, - st->current_app_buffer, - st->batch_length); - } - - // -------------------------------------------- - // TIMING PERF - #if (TIMING_PERF_ASYNC) - gettimeofday(&tv_post, NULL); - num_samples = (double)(st->read_ret_value) / 4.0; - num_samples_avg = num_samples_avg*0.1 + num_samples*0.9; - temp_pre = tv_pre.tv_sec + ((double)(tv_pre.tv_usec)) / 1e6; - time_post = tv_post.tv_sec + ((double)(tv_post.tv_usec)) / 1e6; - - batch_time = temp_pre - time_pre; - sample_rate = sample_rate*0.1 + (num_samples / batch_time) * 0.9; - process_time = process_time*0.1 + (time_post - temp_pre)*0.9; - - time_pre = temp_pre; - total_samples += st->read_ret_value; - if (total_samples % (4*4000000) == 0) - { - printf("sample_rate = %.2f SPS, process_time = %.2f usec" - ", num_samples_avg = %.1f\n", - sample_rate, process_time * 1e6, num_samples_avg); - } - #endif // TIMING_PERF_ASYNC - // -------------------------------------------- - - // wait for the async to complete - struct aiocb* read_aiocb_vec[1]; - read_aiocb_vec[0] = &read_aiocb; - ret = aio_suspend(read_aiocb_vec, 1, NULL); - if (ret >= 0) - { - st->read_ret_value = st->batch_length; - st->current_app_buffer = st->current_smi_buffer; - } - - st->current_smi_buffer_index ++; - if (st->current_smi_buffer_index >= (int)(st->num_of_buffers)) st->current_smi_buffer_index = 0; - st->current_smi_buffer = st->buffers[st->current_smi_buffer_index]; - } - - // exit thread notification - if (st->data_cb != NULL) st->data_cb(dev->cb_context, - st->service_context, - caribou_smi_stream_end, - (caribou_smi_channel_en)(st->stream_id>>1), - 0, - st->current_app_buffer, - st->batch_length); - - ZF_LOGD("Leaving thread id %lu", tid); - return NULL; -}*/ - //========================================================================= static int caribou_smi_set_driver_streaming_state(caribou_smi_st* dev, int state) { @@ -753,8 +697,10 @@ int caribou_smi_setup_stream(caribou_smi_st* dev, return 1; } + st->app_meta_vec = NULL; + st->app_cmplx_vec = NULL; st->batch_length = dev->native_batch_length_bytes; - st->num_of_buffers = 3; + st->num_of_buffers = 2; st->data_cb = cb; caribou_smi_set_driver_streaming_state(dev, 0); @@ -766,6 +712,26 @@ int caribou_smi_setup_stream(caribou_smi_st* dev, return -1; } + // Allocate the complex vector and metadata vector + st->app_cmplx_vec = + (caribou_smi_sample_complex_int16*)malloc(sizeof(caribou_smi_sample_complex_int16) * st->batch_length / 4); + if (st->app_cmplx_vec == NULL) + { + ZF_LOGE("application complex buffer allocation failed"); + release_buffer_vec(st->buffers, st->num_of_buffers, st->batch_length); + return -1; + } + + st->app_meta_vec = + (caribou_smi_sample_meta*)malloc(sizeof(caribou_smi_sample_meta) * st->batch_length / 4); + if (st->app_meta_vec == NULL) + { + ZF_LOGE("application meta-data buffer allocation failed"); + release_buffer_vec(st->buffers, st->num_of_buffers, st->batch_length); + free(st->app_cmplx_vec); + return -1; + } + st->current_smi_buffer_index = 0; st->current_smi_buffer = st->buffers[0]; st->current_app_buffer = st->buffers[st->num_of_buffers-1]; @@ -779,6 +745,8 @@ int caribou_smi_setup_stream(caribou_smi_st* dev, { ZF_LOGE("read stream thread creation failed"); release_buffer_vec(st->buffers, st->num_of_buffers, st->batch_length); + free(st->app_cmplx_vec); + free(st->app_meta_vec); st->buffers = NULL; st->active = 0; st->running = 0; @@ -869,7 +837,11 @@ int caribou_smi_destroy_stream(caribou_smi_st* dev, int id) } release_buffer_vec(dev->streams[id].buffers, dev->streams[id].num_of_buffers, dev->streams[id].batch_length); - + free(dev->streams[id].app_cmplx_vec); + free(dev->streams[id].app_meta_vec); + + dev->streams[id].app_cmplx_vec = NULL; + dev->streams[id].app_meta_vec = NULL; dev->streams[id].buffers = NULL; dev->streams[id].current_smi_buffer = NULL; dev->streams[id].current_app_buffer = NULL; @@ -934,50 +906,7 @@ static void caribou_smi_setup_settings (caribou_smi_st* dev, struct smi_settings settings->dma_enable = 1; settings->pack_data = 1; settings->dma_passthrough_enable = 1; - - //settings->dma_read_thresh = 1; - //settings->dma_write_thresh = 1; - //settings->dma_panic_read_thresh = 1; - //settings->dma_panic_write_thresh = 1; } -//========================================================================= -void dump_hex(const void* data, size_t size) -{ - char ascii[17]; - size_t i, j; - ascii[16] = '\0'; - for (i = 0; i < size; ++i) { - printf("%02X ", ((unsigned char*)data)[i]); - if (((unsigned char*)data)[i] >= ' ' && ((unsigned char*)data)[i] <= '~') - { - ascii[i % 16] = ((unsigned char*)data)[i]; - } - else - { - ascii[i % 16] = '.'; - } - if ((i+1) % 8 == 0 || i+1 == size) - { - printf(" "); - if ((i+1) % 16 == 0) - { - printf("| %s \n", ascii); - } - else if (i+1 == size) - { - ascii[(i+1) % 16] = '\0'; - if ((i+1) % 16 <= 8) - { - printf(" "); - } - for (j = (i+1) % 16; j < 16; ++j) - { - printf(" "); - } - printf("| %s \n", ascii); - } - } - } -} + diff --git a/software/libcariboulite/src/caribou_smi/caribou_smi.h b/software/libcariboulite/src/caribou_smi/caribou_smi.h index 69a71c8..53bfd00 100644 --- a/software/libcariboulite/src/caribou_smi/caribou_smi.h +++ b/software/libcariboulite/src/caribou_smi/caribou_smi.h @@ -41,18 +41,37 @@ typedef enum caribou_smi_error_read_failed = 0, } caribou_smi_error_en; +#pragma pack(1) +// associated with CS16 - total 4 bytes / element +typedef struct +{ + int16_t i; // LSB + int16_t q; // MSB +} caribou_smi_sample_complex_int16; + +typedef struct +{ + uint8_t cnt : 2; + uint8_t sync1 : 1; + uint8_t sync2 : 1; + uint8_t res : 4; +} caribou_smi_sample_meta; +#pragma pack() + #define CARIBOU_SMI_ERROR_STRS { \ "reading from SMI source failed", \ } -typedef void (*caribou_smi_data_callback)( void *ctx, // The context of the requesting application - void *serviced_context, // the context of the session within the app - caribou_smi_stream_type_en type, // which type of stream is it? read / write? - caribou_smi_channel_en ch, // which channel (900 / 2400) - uint32_t byte_count, // for "read stream only" - number of read data bytes in buffer - uint8_t *buffer, // for "read" - data buffer to be analyzed - // for "write" - the data buffer to be filled with information - uint32_t buffer_len_bytes); // the total size of the buffer +typedef void (*caribou_smi_data_callback)( void *ctx, // The context of the requesting application + void *serviced_context, // the context of the session within the app + caribou_smi_stream_type_en type, // which type of stream is it? read / write? + caribou_smi_channel_en ch, // which channel (900 / 2400) + size_t num_samples, // for "read stream only" - number of read data bytes in buffer + caribou_smi_sample_complex_int16 *cplx_vec, // for "read" - complex vector of samples to be analyzed + // for "write" - complex vector of samples to be written into + caribou_smi_sample_meta *metadat_vec, // for "read" - the metadata send by the receiver for each sample + // for "write" - the metadata to be written by app for each sample + size_t total_length_samples); // The capacity (in terms of samples) in the above vectors typedef void (*caribou_smi_error_callback)( void *ctx, caribou_smi_channel_en ch, @@ -73,6 +92,9 @@ typedef struct uint8_t *current_smi_buffer; // the buffer that is currently in the SMI DMA uint8_t *current_app_buffer; // the buffer that is currently analyzed / written by the application callback + caribou_smi_sample_complex_int16* app_cmplx_vec; + caribou_smi_sample_meta* app_meta_vec; + int active; // the thread is active int running; // the stream state - is it running and fetching / pushing information int stream_id; // the stream id for the application - may be deleted later diff --git a/software/libcariboulite/src/cariboulite_fpga_firmware.h b/software/libcariboulite/src/cariboulite_fpga_firmware.h index 1bf4849..7497543 100644 --- a/software/libcariboulite/src/cariboulite_fpga_firmware.h +++ b/software/libcariboulite/src/cariboulite_fpga_firmware.h @@ -17,16 +17,16 @@ extern "C" { /* * Time tagging of the module through the 'struct tm' structure - * Date: 2021-12-27 - * Time: 23:29:22 + * Date: 2022-01-03 + * Time: 16:23:23 */ struct tm cariboulite_firmware_date_time = { - .tm_sec = 22, - .tm_min = 29, - .tm_hour = 23, - .tm_mday = 27, - .tm_mon = 11, /* +1 */ - .tm_year = 121, /* +1900 */ + .tm_sec = 23, + .tm_min = 23, + .tm_hour = 16, + .tm_mday = 3, + .tm_mon = 0, /* +1 */ + .tm_year = 122, /* +1900 */ }; /* @@ -44,392 +44,392 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x40, 0x05, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 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0x30, + 0x0A, 0x14, 0xCB, 0xB0, 0x00, 0x00, 0x80, 0x00, 0x40, 0x00, 0x00, 0x30, 0x01, 0x3A, 0xDC, 0x18, + 0xA0, 0x00, 0xC1, 0x24, 0x08, 0x00, 0x03, 0xC0, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x13, 0xEC, 0xF0, 0x0D, 0x10, 0x10, + 0x05, 0x32, 0xE3, 0x00, 0x00, 0x00, 0x29, 0x37, 0x81, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x42, 0x00, 0x00, 0x10, 0x03, 0x4E, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x50, 0x2A, 0x3C, 0x61, 0x00, 0x10, 0x01, 0x00, 0x83, 0x2E, 0x7C, 0x08, 0x50, 0x02, + 0xBA, 0x6A, 0x81, 0x82, 0x01, 0x41, 0x20, 0x83, 0x80, 0x06, 0x90, 0x05, 0x80, 0x10, 0x3E, 0xC0, + 0x0E, 0x00, 0x14, 0x10, 0x02, 0x09, 0x0A, 0x50, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x00, 0x00, 0x01, 0x27, 0xC3, 0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x40, 0x00, + 0x00, 0x08, 0x02, 0x28, 0x00, 0x00, 0x00, 0x28, 0x0B, 0x00, 0x01, 0x40, 0x00, 0x00, 0x00, 0x02, + 0xFF, 0x03, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x40, 0x41, 0x20, 0x87, 0x01, 0xE0, 0x40, 0x00, 0x00, + 0x81, 0x46, 0x17, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x05, 0x40, 0x00, 0x36, 0xC3, 0x80, 0x03, 0x04, 0x09, 0x4E, 0xF9, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x06, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA1, 0x80, 0x00, + 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, + 0x00, 0x20, 0x68, 0x00, 0x30, 0x01, 0xD6, 0x6B, 0x00, 0x00, 0x00, 0x00, 0x2A, 0x50, 0x64, 0x00, + 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x04, + 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x42, 0x92, 0x80, 0x00, 0x80, 0x00, 0x20, 0x08, 0x6C, 0x10, + 0x80, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x08, 0x08, 0x00, 0x01, 0x01, 0xA0, 0x00, 0x00, 0x28, + 0x18, 0x04, 0x00, 0x00, 0x00, 0x80, 0x00, 0x3C, 0xF0, 0x1A, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x2C, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x02, 0xC0, + 0x00, 0x80, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x05, 0x08, 0x00, 0x00, 0x00, 0x00, 0x60, + 0x61, 0xCF, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x06, 0x40, 0x04, 0x00, 0x00, 0x09, 0x02, 0x00, 0x00, 0xA0, + 0x00, 0x00, 0x20, 0x51, 0xE0, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x01, 0x40, 0x00, + 0x02, 0x00, 0x0A, 0x50, 0x30, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x02, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x2C, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xA0, 0x40, 0x00, 0x50, 0x0A, 0x9C, 0x00, + 0x04, 0x00, 0x10, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x5A, 0x00, 0x40, 0x00, + 0x00, 0x02, 0x03, 0xC1, 0x60, 0x01, 0xE0, 0x00, 0x00, 0x00, 0x0E, 0x01, 0x00, 0x00, 0x08, 0x21, + 0x60, 0x01, 0xE0, 0x08, 0x20, 0x0A, 0x05, 0x00, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0xC0, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x30, 0x75, 0x85, 0x0D, 0x00, 0x00, 0x00, 0x4E, + 0xDA, 0x2C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x38, 0x00, + 0x00, 0x43, 0x65, 0xD8, 0x80, 0x10, 0x00, 0x00, 0x08, 0xD1, 0x02, 0x06, 0x05, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x80, 0x01, 0x4C, 0x00, 0x28, 0x24, 0x08, 0x02, 0x80, 0x00, 0x00, 0x0D, 0x10, 0x01, + 0x40, 0x04, 0x50, 0x06, 0xDC, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xC0, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x08, 0x80, 0x00, + 0x5E, 0x78, 0x00, 0x20, 0x08, 0x20, 0xC0, 0x00, 0xA1, 0x90, 0x80, 0x05, 0xA1, 0xB0, 0x42, 0x80, + 0x03, 0x00, 0x02, 0x1E, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x22, 0x04, 0x00, 0x80, 0x10, 0x10, 0x00, 0x09, 0x39, 0xC6, 0x80, 0x00, 0x02, 0x00, 0x34, + 0x0D, 0x00, 0x00, 0x00, 0x04, 0xFF, 0x06, 0x9C, 0x38, 0x00, 0x00, 0x01, 0x77, 0xCE, 0x00, 0x90, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x08, 0x00, 0x01, 0x01, 0xE0, + 0x01, 0x40, 0x82, 0xFE, 0x7C, 0x00, 0x70, 0x09, 0x02, 0x00, 0x01, 0xA0, 0x01, 0xC0, 0x0A, 0x50, + 0x34, 0x06, 0x88, 0x07, 0x01, 0x1D, 0x07, 0xC0, 0x01, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x09, 0x31, 0xC0, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x00, 0x90, 0xA0, 0x00, 0x88, 0x81, 0x94, 0x14, 0x00, 0x00, 0x00, 0x00, 0x40, + 0x0E, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x50, 0x00, 0x00, 0x00, 0x80, 0x40, 0x00, 0x00, 0x00, 0x08, 0x20, 0x40, 0x78, 0x80, 0x00, + 0x00, 0x28, 0x18, 0x70, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x00, 0x3F, 0x72, 0x00, 0x80, 0x11, 0x00, 0x82, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -2048,7 +2048,7 @@ uint8_t cariboulite_firmware[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x99, 0xA5, 0x01, 0x06, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x74, 0x9B, 0x01, 0x06, 0x00, }; #ifdef __cplusplus diff --git a/software/libcariboulite/src/cariboulite_setup.c b/software/libcariboulite/src/cariboulite_setup.c index dea48f1..f65f37b 100644 --- a/software/libcariboulite/src/cariboulite_setup.c +++ b/software/libcariboulite/src/cariboulite_setup.c @@ -348,7 +348,7 @@ int cariboulite_init_submodules (cariboulite_st* sys) at86rf215_iq_interface_config_st modem_iq_config = { .loopback_enable = 0, - .drv_strength = at86rf215_iq_drive_current_2ma, + .drv_strength = at86rf215_iq_drive_current_4ma, .common_mode_voltage = at86rf215_iq_common_mode_v_ieee1596_1v2, .tx_control_with_iq_if = false, .radio09_mode = at86rf215_iq_if_mode, diff --git a/software/libcariboulite/src/datatypes/circular_buffer.h b/software/libcariboulite/src/datatypes/circular_buffer.h index 054dc34..ac3a052 100644 --- a/software/libcariboulite/src/datatypes/circular_buffer.h +++ b/software/libcariboulite/src/datatypes/circular_buffer.h @@ -10,15 +10,6 @@ #define IS_POWER_OF_2(x) (!((x) == 0) && !((x) & ((x) - 1))) #define MIN(x,y) ((x)>(y)?(y):(x)) -uint32_t next_power_of_2 (uint32_t x) -{ - uint32_t power = 1; - while(power < x) - { - power <<= 1; - } - return power; -} template class circular_buffer { @@ -142,6 +133,17 @@ public: } } +private: + uint32_t next_power_of_2 (uint32_t x) + { + uint32_t power = 1; + while(power < x) + { + power <<= 1; + } + return power; + } + private: std::mutex mutex_; std::condition_variable cond_var_; diff --git a/software/libcariboulite/src/soapy_api/Cariboulite.hpp b/software/libcariboulite/src/soapy_api/Cariboulite.hpp index 8f77c9f..ce41f05 100644 --- a/software/libcariboulite/src/soapy_api/Cariboulite.hpp +++ b/software/libcariboulite/src/soapy_api/Cariboulite.hpp @@ -30,11 +30,8 @@ enum Cariboulite_Format CARIBOULITE_FORMAT_FLOAT64 = 3, }; -//#define BUFFER_SIZE_MS ( 10 ) #define NUM_SAMPLEQUEUE_BUFS ( 3 ) #define NUM_BYTES_PER_CPLX_ELEM ( 4 ) -//#define GET_MTU_MS(ms) ( 4000*(ms) ) -//#define GET_MTU_MS_BYTES(ms) ( GET_MTU_MS(ms) * NUM_BYTES_PER_CPLX_ELEM ) #pragma pack(1) // associated with CS8 - total 2 bytes / element @@ -51,13 +48,6 @@ typedef struct int16_t q :12; // MSB } sample_complex_int12; -// associated with CS16 - total 4 bytes / element -typedef struct -{ - int16_t i; // LSB - int16_t q; // MSB -} sample_complex_int16; - // associated with CS32 - total 8 bytes / element typedef struct { @@ -99,10 +89,10 @@ public: SampleQueue(int mtu_bytes, int num_buffers); ~SampleQueue(); int AttachStreamId(int id, int dir, int channel); - int Write(uint8_t *buffer, size_t length, uint32_t meta, long timeout_us); - int Read(uint8_t *buffer, size_t length, uint32_t *meta, long timeout_us); + int Write(caribou_smi_sample_complex_int16 *buffer, size_t num_samples, uint8_t* meta, long timeout_us); + int Read(caribou_smi_sample_complex_int16 *buffer, size_t num_samples, uint8_t *meta, long timeout_us); - int ReadSamples(sample_complex_int16* buffer, size_t num_elements, long timeout_us); + int ReadSamples(caribou_smi_sample_complex_int16* buffer, size_t num_elements, long timeout_us); int ReadSamples(sample_complex_float* buffer, size_t num_elements, long timeout_us); int ReadSamples(sample_complex_double* buffer, size_t num_elements, long timeout_us); int ReadSamples(sample_complex_int8* buffer, size_t num_elements, long timeout_us); @@ -114,13 +104,13 @@ public: Cariboulite_Format chosen_format; int dig_filt; private: - circular_buffer *queue; + circular_buffer *queue; size_t mtu_size_bytes; uint8_t *partial_buffer; int partial_buffer_start; int partial_buffer_length; - sample_complex_int16 *interm_native_buffer; + caribou_smi_sample_complex_int16 *interm_native_buffer; #define FILT_ORDER 6 #define FILT_ORDER1 8 Iir::Butterworth::LowPass filt20_i; diff --git a/software/libcariboulite/src/soapy_api/CaribouliteSampleQueue.cpp b/software/libcariboulite/src/soapy_api/CaribouliteSampleQueue.cpp index ec7f7c8..0a882b0 100644 --- a/software/libcariboulite/src/soapy_api/CaribouliteSampleQueue.cpp +++ b/software/libcariboulite/src/soapy_api/CaribouliteSampleQueue.cpp @@ -2,34 +2,11 @@ #include #include - - -//============================================== -void print_iq(uint32_t* array, int len) -{ - //printf("Values I/Q:\n"); - for (int i=0; i> 1) & (0x1FFF); - int16_t i_val = (v>>17) & (0x1FFF); - if (q_val >= 0x1000) q_val-=0x2000; - if (i_val >= 0x1000) i_val-=0x2000; - float fi = i_val, fq = q_val; - float mod = sqrt(fi*fi + fq*fq); - float arg = atan2(fq, fi); - printf("(%d, %d), ", i_val, q_val); - if ((i % 32) == 0) printf("\n"); - } -} - //================================================================= SampleQueue::SampleQueue(int mtu_bytes, int num_buffers) { SoapySDR_logf(SOAPY_SDR_INFO, "Creating SampleQueue MTU: %d bytes, NumBuffers: %d", mtu_bytes, num_buffers); - queue = new circular_buffer(mtu_bytes / 4 * num_buffers) + queue = new circular_buffer(mtu_bytes / 4 * num_buffers*10); mtu_size_bytes = mtu_bytes; stream_id = -1; stream_dir = -1; @@ -42,7 +19,7 @@ SampleQueue::SampleQueue(int mtu_bytes, int num_buffers) // a buffer for conversion betwen native and emulated formats // the maximal size is the 2*(mtu_size in bytes) - interm_native_buffer = new sample_complex_int16[2*mtu_size_bytes]; + interm_native_buffer = new caribou_smi_sample_complex_int16[2*mtu_size_bytes]; is_cw = 0; filt20_i.setup(4e6, 20e3/2); @@ -61,9 +38,6 @@ SampleQueue::SampleQueue(int mtu_bytes, int num_buffers) //================================================================= SampleQueue::~SampleQueue() { - //printf("~SampleQueue streamID: %d, dir: %d, channel: %d\n", stream_id, stream_dir, stream_channel); - //SoapySDR_logf(SOAPY_SDR_INFO, "~SampleQueue streamID: %d, dir: %d, channel: %d", stream_id, stream_dir, stream_channel); - stream_id = -1; stream_dir = -1; stream_channel = -1; @@ -88,131 +62,35 @@ int SampleQueue::AttachStreamId(int id, int dir, int channel) } //================================================================= -int SampleQueue::Write(sample_complex_int16 *buffer, size_t num_samples, uint8_t* meta, long timeout_us) +int SampleQueue::Write(caribou_smi_sample_complex_int16 *buffer, size_t num_samples, uint8_t* meta, long timeout_us) { - return queue->put(buffer, elements) + return queue->put(buffer, num_samples); } //================================================================= -int SampleQueue::Read(uint8_t *buffer, size_t length, uint32_t *meta, long timeout_us) +int SampleQueue::Read(caribou_smi_sample_complex_int16 *buffer, size_t num_samples, uint8_t *meta, long timeout_us) { - tsqueue_item_st* item_ptr = NULL; - int left_to_read = length; - int read_so_far = 0; - int chunk = 0; - - // first read out from partial buffer - int amount_to_read_from_partial = (left_to_read <= partial_buffer_length) ? - left_to_read : partial_buffer_length; - memcpy (buffer, partial_buffer + partial_buffer_start, amount_to_read_from_partial); - left_to_read -= amount_to_read_from_partial; - partial_buffer_length -= amount_to_read_from_partial; - partial_buffer_start += amount_to_read_from_partial; - read_so_far += amount_to_read_from_partial; - - // read from the queue - while (left_to_read) - { - int res = tsqueue_pop_item(&queue, &item_ptr, timeout_us); - switch (res) - { - case TSQUEUE_NOT_INITIALIZED: - case TSQUEUE_SEM_FAILED: - { - SoapySDR_logf(SOAPY_SDR_ERROR, "popping buffer %d failed", chunk); - return -1; - } break; - case TSQUEUE_TIMEOUT: - case TSQUEUE_FAILED_EMPTY: return read_so_far; break; - default: break; - } - if (meta) *meta = item_ptr->metadata; - - // if we need more or exactly the mtu size - if (left_to_read >= item_ptr->length) - { - memcpy(&buffer[read_so_far], item_ptr->data, item_ptr->length); - left_to_read -= item_ptr->length; - read_so_far += item_ptr->length; - } - // if we need less than the mtu size - store the residue for next time - else - { - // copy out only the amount that is needed - memcpy(&buffer[read_so_far], item_ptr->data, left_to_read); - - // we are left with "item_ptr->length - left_to_read" bytes - // which will be stored for future requests - - // store the residue in the partial buffer - for the next time - partial_buffer_length = item_ptr->length - left_to_read; - partial_buffer_start = (int)mtu_size_bytes - partial_buffer_length; - memcpy (partial_buffer + partial_buffer_start, - item_ptr->data + left_to_read, - partial_buffer_length); - - read_so_far += left_to_read; - left_to_read = 0; - } - chunk ++; - } - - return read_so_far; + return queue->get(buffer, num_samples); } //================================================================= -int SampleQueue::ReadSamples(sample_complex_int16* buffer, size_t num_elements, long timeout_us) +int SampleQueue::ReadSamples(caribou_smi_sample_complex_int16* buffer, size_t num_elements, long timeout_us) { static int once = 100; static uint16_t last_q = 0; - // this is the native method - int tot_length = num_elements * sizeof(sample_complex_int16); - int res = Read((uint8_t *)buffer, tot_length, NULL, timeout_us); + + int res = Read(buffer, num_elements, NULL, timeout_us); if (res < 0) { // todo!! return res; } - int tot_read_elements = res / sizeof(sample_complex_int16); - - // shift q - //buffer[0].q = last_q; - /*for (int i = 1; i < tot_read_elements; i++) - { - buffer[i-1].q = buffer[i].q; - }*/ - - /*for (int i = 1; i < tot_read_elements; i+=2) - { - short t = buffer[i].i; - buffer[i].i = buffer[i+1].i; - buffer[i+1].i = t; - t = buffer[i].q; - buffer[i].q = buffer[i+1].q; - buffer[i+1].q = t; - }*/ - - /*for (int i = tot_read_elements-1; i >= 0; i--) - { - buffer[i].q = buffer[i-1].q; - }*/ - - for (int i = 0; i < tot_read_elements; i++) - { - - buffer[i].i >>= 1; - buffer[i].q >>= 1; - - buffer[i].i = buffer[i].i & 0x1FFF; - buffer[i].q = buffer[i].q & 0x1FFF; - - if (buffer[i].i >= (int16_t)0x1000) buffer[i].i -= (int16_t)0x2000; - if (buffer[i].q >= (int16_t)0x1000) buffer[i].q -= (int16_t)0x2000; - } + int tot_read_elements = res; return tot_read_elements; + // digital filters - TBD if (dig_filt == 0) { for (int i = 0; i < res; i++) @@ -260,7 +138,7 @@ int SampleQueue::ReadSamples(sample_complex_int16* buffer, size_t num_elements, //================================================================= int SampleQueue::ReadSamples(sample_complex_float* buffer, size_t num_elements, long timeout_us) { - uint32_t max_native_samples = 2*(mtu_size_bytes / sizeof(sample_complex_int16)); + uint32_t max_native_samples = 2*(mtu_size_bytes / sizeof(caribou_smi_sample_complex_int16)); // do not allow to store more than is possible in the intermediate buffer if (num_elements > max_native_samples) @@ -332,7 +210,7 @@ int SampleQueue::ReadSamples(sample_complex_float* buffer, size_t num_elements, //================================================================= int SampleQueue::ReadSamples(sample_complex_double* buffer, size_t num_elements, long timeout_us) { - uint32_t max_native_samples = 2*(mtu_size_bytes / sizeof(sample_complex_int16)); + uint32_t max_native_samples = 2*(mtu_size_bytes / sizeof(caribou_smi_sample_complex_int16)); // do not allow to store more than is possible in the intermediate buffer if (num_elements > max_native_samples) @@ -362,7 +240,7 @@ int SampleQueue::ReadSamples(sample_complex_double* buffer, size_t num_elements, //================================================================= int SampleQueue::ReadSamples(sample_complex_int8* buffer, size_t num_elements, long timeout_us) { - uint32_t max_native_samples = 2*(mtu_size_bytes / sizeof(sample_complex_int16)); + uint32_t max_native_samples = 2*(mtu_size_bytes / sizeof(caribou_smi_sample_complex_int16)); // do not allow to store more than is possible in the intermediate buffer if (num_elements > max_native_samples) diff --git a/software/libcariboulite/src/soapy_api/CaribouliteStream.cpp b/software/libcariboulite/src/soapy_api/CaribouliteStream.cpp index 7895ab7..9479ad2 100644 --- a/software/libcariboulite/src/soapy_api/CaribouliteStream.cpp +++ b/software/libcariboulite/src/soapy_api/CaribouliteStream.cpp @@ -1,15 +1,15 @@ #include "Cariboulite.hpp" #include "cariboulite_config/cariboulite_config_default.h" - //================================================================= static void caribou_stream_data_event( void *ctx, void *service_context, caribou_smi_stream_type_en type, caribou_smi_channel_en ch, - uint32_t byte_count, - uint8_t *buffer, - uint32_t buffer_len_bytes) + size_t sample_count, + caribou_smi_sample_complex_int16 *cmplx_vec, + caribou_smi_sample_meta *meta_vec, + size_t buffers_capacity_samples) { cariboulite_st* sys = (cariboulite_st*)ctx; Cariboulite *obj = (Cariboulite*)service_context; @@ -23,7 +23,7 @@ static void caribou_stream_data_event( void *ctx, case caribou_smi_stream_type_read: { int sample_queue_index = CARIBOU_SMI_GET_STREAM_ID(type, ch); - obj->sample_queues[sample_queue_index]->Write(buffer, buffer_len_bytes, 0, 10000L); + obj->sample_queues[sample_queue_index]->Write(cmplx_vec, sample_count, 0, 10000L); } break; @@ -38,16 +38,16 @@ static void caribou_stream_data_event( void *ctx, //------------------------------------------------------- case caribou_smi_stream_start: { - SoapySDR_logf(SOAPY_SDR_DEBUG, "start event: stream channel %d, batch length: %d bytes", - ch, buffer_len_bytes); + SoapySDR_logf(SOAPY_SDR_DEBUG, "start event: stream channel %d, batch length: %d samples", + ch, buffers_capacity_samples); } break; //------------------------------------------------------- case caribou_smi_stream_end: { - SoapySDR_logf(SOAPY_SDR_DEBUG, "end event: stream channel %d, batch length: %d bytes", - ch, buffer_len_bytes); + SoapySDR_logf(SOAPY_SDR_DEBUG, "end event: stream channel %d, batch length: %d sample", + ch, buffers_capacity_samples); } break; @@ -278,7 +278,7 @@ void Cariboulite::closeStream(SoapySDR::Stream *stream) size_t Cariboulite::getStreamMTU(SoapySDR::Stream *stream) const { //printf("getStreamMTU\n"); - return 1024 * 1024 / 2 / 4; // # milliseconds of buffer + return 1024 * 1024 / 2 / 4; } //======================================================== @@ -399,7 +399,7 @@ int Cariboulite::readStream( } break; case CARIBOULITE_FORMAT_INT16: - res = sample_queues[stream_id]->ReadSamples((sample_complex_int16*)buffs[0], numElems, timeoutUs); + res = sample_queues[stream_id]->ReadSamples((caribou_smi_sample_complex_int16*)buffs[0], numElems, timeoutUs); break; case CARIBOULITE_FORMAT_INT8: res = sample_queues[stream_id]->ReadSamples((sample_complex_int8*)buffs[0], numElems, timeoutUs);