Update README.md

hardware/README.md

@@ -22,7 +22,23 @@ The usage of LDOs provides high level of voltage isolation, low emitted noise, a
 
 The power distribution provides high frequency isolation of the RF components from the digital components (memory, RPI and FPGA) at frequencies lower than 10 MHz. Above 100 MHz additional isolation is provided by using ferrite beads with high impedance (>500 Ohms) at 100MHz. A set of filterring bypass capacitors have been chosen to further suppress noise generated by components on their power lines at mid-range frequencies (10 to 100 MHz) - the set contains 1nF, 100 nF and 4.7uF capacitors bypassing power and data lines effective at the said frequency ranges.
 
+## RPI HAT EEPROM
+TBD
 
+## Clocking
+TBD
+
+## PMOD Connector
+TBD
+
+## FPGA and LVDS
+TBD
+
+## SPI
+TBD
+
+## RF PATH
+TBD
 
 
 # License