kopia lustrzana https://github.com/cariboulabs/cariboulite
fixed driver lockup at channel 0 RX. The fpga firmware
was using the smi address pins to determine which channel can write the complex_fifo. The read side of the complex fifo is connected to the DREQ pin of the SMI interface on the raspberry. The address pins on the smi interface are at logic 1 when no transfer is in progress. This caused a deadlock condition: the SMI address pin is at 1, so the fifo cannot be filled, so the DREQ cannot be asserted and the SMI cannot start reading data.pull/192/head
rodzic
baccfb4805
commit
26fe48f53d
|
@ -346,7 +346,7 @@ module top (
|
|||
wire w_rx_fifo_empty;
|
||||
wire channel;
|
||||
|
||||
assign channel = i_smi_a3;
|
||||
//assign channel = i_smi_a3;
|
||||
|
||||
complex_fifo #(
|
||||
.ADDR_WIDTH(10), // 1024 samples
|
||||
|
@ -445,7 +445,7 @@ module top (
|
|||
.i_smi_data_in(w_smi_data_input),
|
||||
.o_smi_read_req(w_smi_read_req),
|
||||
.o_smi_write_req(w_smi_write_req),
|
||||
.o_channel(/*channel*/),
|
||||
.o_channel(channel),
|
||||
.o_dir (/*w_smi_data_direction*/),
|
||||
.i_smi_test(1'b0/*w_debug_smi_test*/),
|
||||
.o_cond_tx(),
|
||||
|
|
Plik diff jest za duży
Load Diff
Ładowanie…
Reference in New Issue